Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/CodeGen/GlobalISel/Utils.cpp
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//===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file This file implements the utility functions used by the GlobalISel
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/// pipeline.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define DEBUG_TYPE "globalisel-utils"
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using namespace llvm;
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unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,
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                                   const TargetInstrInfo &TII,
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                                   const RegisterBankInfo &RBI,
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                                   MachineInstr &InsertPt, unsigned Reg,
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3.11M
                                   const TargetRegisterClass &RegClass) {
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3.11M
  if (
!RBI.constrainGenericRegister(Reg, RegClass, MRI)3.11M
) {
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0
    unsigned NewReg = MRI.createVirtualRegister(&RegClass);
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    BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
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            TII.get(TargetOpcode::COPY), NewReg)
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        .addReg(Reg);
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    return NewReg;
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  }
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3.11M
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3.11M
  return Reg;
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3.11M
}
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unsigned llvm::constrainOperandRegClass(
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    const MachineFunction &MF, const TargetRegisterInfo &TRI,
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    MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
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    const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
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3.06M
    unsigned Reg, unsigned OpIdx) {
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  // Assume physical registers are properly constrained.
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  assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
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3.06M
         "PhysReg not implemented");
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  const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
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  return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass);
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3.06M
}
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bool llvm::isTriviallyDead(const MachineInstr &MI,
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7.25M
                           const MachineRegisterInfo &MRI) {
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  // If we can move an instruction, we can remove it.  Otherwise, it has
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  // a side-effect of some sort.
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  bool SawStore = false;
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  if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore))
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    return false;
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  // Instructions without side-effects are dead iff they only define dead vregs.
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4.75M
  
for (auto &MO : MI.operands()) 4.75M
{
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    if (
!MO.isReg() || 5.95M
!MO.isDef()5.64M
)
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1.20M
      continue;
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    unsigned Reg = MO.getReg();
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    if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
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        !MRI.use_nodbg_empty(Reg))
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      return false;
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  }
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  return true;
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}
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void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
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                              MachineOptimizationRemarkEmitter &MORE,
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                              MachineOptimizationRemarkMissed &R) {
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  MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
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  // Print the function name explicitly if we don't have a debug location (which
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  // makes the diagnostic less useful) or if we're going to emit a raw error.
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  if (
!R.getLocation().isValid() || 62.1k
TPC.isGlobalISelAbortEnabled()0
)
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    R << (" (in function: " + MF.getName() + ")").str();
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  if (TPC.isGlobalISelAbortEnabled())
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    report_fatal_error(R.getMsg());
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  else
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    MORE.emit(R);
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}
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void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
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                              MachineOptimizationRemarkEmitter &MORE,
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                              const char *PassName, StringRef Msg,
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                              const MachineInstr &MI) {
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  MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
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                                    MI.getDebugLoc(), MI.getParent());
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  R << Msg;
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  // Printing MI is expensive;  only do it if expensive remarks are enabled.
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  if (MORE.allowExtraAnalysis(PassName))
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    R << ": " << ore::MNV("Inst", MI);
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  reportGISelFailure(MF, TPC, MORE, R);
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}
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Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
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1.11M
                                           const MachineRegisterInfo &MRI) {
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  MachineInstr *MI = MRI.getVRegDef(VReg);
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  if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
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    return None;
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if (544k
MI->getOperand(1).isImm()544k
)
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    return MI->getOperand(1).getImm();
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if (544k
MI->getOperand(1).isCImm() &&
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      MI->getOperand(1).getCImm()->getBitWidth() <= 64)
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    return MI->getOperand(1).getCImm()->getSExtValue();
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0
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  return None;
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}
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const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,
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                                       const MachineRegisterInfo &MRI) {
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  MachineInstr *MI = MRI.getVRegDef(VReg);
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  if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
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    return nullptr;
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  return MI->getOperand(1).getFPImm();
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}