/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/CodeGen/GlobalISel/Utils.cpp
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1 | | //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | /// \file This file implements the utility functions used by the GlobalISel |
10 | | /// pipeline. |
11 | | //===----------------------------------------------------------------------===// |
12 | | |
13 | | #include "llvm/CodeGen/GlobalISel/Utils.h" |
14 | | #include "llvm/ADT/Twine.h" |
15 | | #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" |
16 | | #include "llvm/CodeGen/MachineInstr.h" |
17 | | #include "llvm/CodeGen/MachineInstrBuilder.h" |
18 | | #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" |
19 | | #include "llvm/CodeGen/MachineRegisterInfo.h" |
20 | | #include "llvm/CodeGen/TargetPassConfig.h" |
21 | | #include "llvm/IR/Constants.h" |
22 | | #include "llvm/Target/TargetInstrInfo.h" |
23 | | #include "llvm/Target/TargetRegisterInfo.h" |
24 | | |
25 | | #define DEBUG_TYPE "globalisel-utils" |
26 | | |
27 | | using namespace llvm; |
28 | | |
29 | | unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI, |
30 | | const TargetInstrInfo &TII, |
31 | | const RegisterBankInfo &RBI, |
32 | | MachineInstr &InsertPt, unsigned Reg, |
33 | 3.11M | const TargetRegisterClass &RegClass) { |
34 | 3.11M | if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)3.11M ) { |
35 | 0 | unsigned NewReg = MRI.createVirtualRegister(&RegClass); |
36 | 0 | BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(), |
37 | 0 | TII.get(TargetOpcode::COPY), NewReg) |
38 | 0 | .addReg(Reg); |
39 | 0 | return NewReg; |
40 | 0 | } |
41 | 3.11M | |
42 | 3.11M | return Reg; |
43 | 3.11M | } |
44 | | |
45 | | |
46 | | unsigned llvm::constrainOperandRegClass( |
47 | | const MachineFunction &MF, const TargetRegisterInfo &TRI, |
48 | | MachineRegisterInfo &MRI, const TargetInstrInfo &TII, |
49 | | const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, |
50 | 3.06M | unsigned Reg, unsigned OpIdx) { |
51 | 3.06M | // Assume physical registers are properly constrained. |
52 | 3.06M | assert(TargetRegisterInfo::isVirtualRegister(Reg) && |
53 | 3.06M | "PhysReg not implemented"); |
54 | 3.06M | |
55 | 3.06M | const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); |
56 | 3.06M | return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass); |
57 | 3.06M | } |
58 | | |
59 | | bool llvm::isTriviallyDead(const MachineInstr &MI, |
60 | 7.25M | const MachineRegisterInfo &MRI) { |
61 | 7.25M | // If we can move an instruction, we can remove it. Otherwise, it has |
62 | 7.25M | // a side-effect of some sort. |
63 | 7.25M | bool SawStore = false; |
64 | 7.25M | if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore)) |
65 | 2.49M | return false; |
66 | 4.75M | |
67 | 4.75M | // Instructions without side-effects are dead iff they only define dead vregs. |
68 | 4.75M | for (auto &MO : MI.operands()) 4.75M { |
69 | 5.95M | if (!MO.isReg() || 5.95M !MO.isDef()5.64M ) |
70 | 1.20M | continue; |
71 | 4.75M | |
72 | 4.75M | unsigned Reg = MO.getReg(); |
73 | 4.75M | if (TargetRegisterInfo::isPhysicalRegister(Reg) || |
74 | 3.27M | !MRI.use_nodbg_empty(Reg)) |
75 | 3.98M | return false; |
76 | 769k | } |
77 | 769k | return true; |
78 | 769k | } |
79 | | |
80 | | void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, |
81 | | MachineOptimizationRemarkEmitter &MORE, |
82 | 62.1k | MachineOptimizationRemarkMissed &R) { |
83 | 62.1k | MF.getProperties().set(MachineFunctionProperties::Property::FailedISel); |
84 | 62.1k | |
85 | 62.1k | // Print the function name explicitly if we don't have a debug location (which |
86 | 62.1k | // makes the diagnostic less useful) or if we're going to emit a raw error. |
87 | 62.1k | if (!R.getLocation().isValid() || 62.1k TPC.isGlobalISelAbortEnabled()0 ) |
88 | 62.1k | R << (" (in function: " + MF.getName() + ")").str(); |
89 | 62.1k | |
90 | 62.1k | if (TPC.isGlobalISelAbortEnabled()) |
91 | 0 | report_fatal_error(R.getMsg()); |
92 | 62.1k | else |
93 | 62.1k | MORE.emit(R); |
94 | 62.1k | } |
95 | | |
96 | | void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, |
97 | | MachineOptimizationRemarkEmitter &MORE, |
98 | | const char *PassName, StringRef Msg, |
99 | 62.1k | const MachineInstr &MI) { |
100 | 62.1k | MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ", |
101 | 62.1k | MI.getDebugLoc(), MI.getParent()); |
102 | 62.1k | R << Msg; |
103 | 62.1k | // Printing MI is expensive; only do it if expensive remarks are enabled. |
104 | 62.1k | if (MORE.allowExtraAnalysis(PassName)) |
105 | 13 | R << ": " << ore::MNV("Inst", MI); |
106 | 62.1k | reportGISelFailure(MF, TPC, MORE, R); |
107 | 62.1k | } |
108 | | |
109 | | Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg, |
110 | 1.11M | const MachineRegisterInfo &MRI) { |
111 | 1.11M | MachineInstr *MI = MRI.getVRegDef(VReg); |
112 | 1.11M | if (MI->getOpcode() != TargetOpcode::G_CONSTANT) |
113 | 567k | return None; |
114 | 544k | |
115 | 544k | if (544k MI->getOperand(1).isImm()544k ) |
116 | 0 | return MI->getOperand(1).getImm(); |
117 | 544k | |
118 | 544k | if (544k MI->getOperand(1).isCImm() && |
119 | 544k | MI->getOperand(1).getCImm()->getBitWidth() <= 64) |
120 | 544k | return MI->getOperand(1).getCImm()->getSExtValue(); |
121 | 0 |
|
122 | 0 | return None; |
123 | 0 | } |
124 | | |
125 | | const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg, |
126 | 0 | const MachineRegisterInfo &MRI) { |
127 | 0 | MachineInstr *MI = MRI.getVRegDef(VReg); |
128 | 0 | if (TargetOpcode::G_FCONSTANT != MI->getOpcode()) |
129 | 0 | return nullptr; |
130 | 0 | return MI->getOperand(1).getFPImm(); |
131 | 0 | } |