/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
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1 | | //===- TargetSubtargetInfo.cpp - General Target Information ----------------==// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | /// \file This file describes the general parts of a Subtarget. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "llvm/Target/TargetSubtargetInfo.h" |
15 | | #include "llvm/ADT/Optional.h" |
16 | | #include "llvm/CodeGen/MachineInstr.h" |
17 | | #include "llvm/CodeGen/TargetSchedule.h" |
18 | | #include "llvm/MC/MCInst.h" |
19 | | #include "llvm/Support/Format.h" |
20 | | #include "llvm/Support/raw_ostream.h" |
21 | | #include "llvm/Target/TargetInstrInfo.h" |
22 | | #include <string> |
23 | | |
24 | | using namespace llvm; |
25 | | |
26 | | TargetSubtargetInfo::TargetSubtargetInfo( |
27 | | const Triple &TT, StringRef CPU, StringRef FS, |
28 | | ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, |
29 | | const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, |
30 | | const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, |
31 | | const InstrStage *IS, const unsigned *OC, const unsigned *FP) |
32 | 44.6k | : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) { |
33 | 44.6k | } |
34 | | |
35 | 28.0k | TargetSubtargetInfo::~TargetSubtargetInfo() = default; |
36 | | |
37 | 553k | bool TargetSubtargetInfo::enableAtomicExpand() const { |
38 | 553k | return true; |
39 | 553k | } |
40 | | |
41 | 63.0k | bool TargetSubtargetInfo::enableMachineScheduler() const { |
42 | 63.0k | return false; |
43 | 63.0k | } |
44 | | |
45 | 588k | bool TargetSubtargetInfo::enableJoinGlobalCopies() const { |
46 | 588k | return enableMachineScheduler(); |
47 | 588k | } |
48 | | |
49 | | bool TargetSubtargetInfo::enableRALocalReassignment( |
50 | 587k | CodeGenOpt::Level OptLevel) const { |
51 | 587k | return true; |
52 | 587k | } |
53 | | |
54 | 95.5k | bool TargetSubtargetInfo::enablePostRAScheduler() const { |
55 | 95.5k | return getSchedModel().PostRAScheduler; |
56 | 95.5k | } |
57 | | |
58 | 971k | bool TargetSubtargetInfo::useAA() const { |
59 | 971k | return false; |
60 | 971k | } |
61 | | |
62 | | static std::string createSchedInfoStr(unsigned Latency, |
63 | 17.0k | Optional<double> RThroughput) { |
64 | 17.0k | static const char *SchedPrefix = " sched: ["; |
65 | 17.0k | std::string Comment; |
66 | 17.0k | raw_string_ostream CS(Comment); |
67 | 17.0k | if (Latency > 0 && 17.0k RThroughput.hasValue()16.6k ) |
68 | 16.5k | CS << SchedPrefix << Latency << format(":%2.2f", RThroughput.getValue()) |
69 | 16.5k | << "]"; |
70 | 482 | else if (482 Latency > 0482 ) |
71 | 137 | CS << SchedPrefix << Latency << ":?]"; |
72 | 345 | else if (345 RThroughput.hasValue()345 ) |
73 | 0 | CS << SchedPrefix << "?:" << RThroughput.getValue() << "]"; |
74 | 17.0k | CS.flush(); |
75 | 17.0k | return Comment; |
76 | 17.0k | } |
77 | | |
78 | | /// Returns string representation of scheduler comment |
79 | 0 | std::string TargetSubtargetInfo::getSchedInfoStr(const MachineInstr &MI) const { |
80 | 0 | if (MI.isPseudo() || 0 MI.isTerminator()0 ) |
81 | 0 | return std::string(); |
82 | 0 | // We don't cache TSchedModel because it depends on TargetInstrInfo |
83 | 0 | // that could be changed during the compilation |
84 | 0 | TargetSchedModel TSchedModel; |
85 | 0 | TSchedModel.init(getSchedModel(), this, getInstrInfo()); |
86 | 0 | unsigned Latency = TSchedModel.computeInstrLatency(&MI); |
87 | 0 | Optional<double> RThroughput = TSchedModel.computeInstrRThroughput(&MI); |
88 | 0 | return createSchedInfoStr(Latency, RThroughput); |
89 | 0 | } |
90 | | |
91 | | /// Returns string representation of scheduler comment |
92 | 17.3k | std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const { |
93 | 17.3k | // We don't cache TSchedModel because it depends on TargetInstrInfo |
94 | 17.3k | // that could be changed during the compilation |
95 | 17.3k | TargetSchedModel TSchedModel; |
96 | 17.3k | TSchedModel.init(getSchedModel(), this, getInstrInfo()); |
97 | 17.3k | unsigned Latency; |
98 | 17.3k | if (TSchedModel.hasInstrSchedModel()) |
99 | 15.8k | Latency = TSchedModel.computeInstrLatency(MCI.getOpcode()); |
100 | 1.51k | else if (1.51k TSchedModel.hasInstrItineraries()1.51k ) { |
101 | 1.20k | auto *ItinData = TSchedModel.getInstrItineraries(); |
102 | 1.20k | Latency = ItinData->getStageLatency( |
103 | 1.20k | getInstrInfo()->get(MCI.getOpcode()).getSchedClass()); |
104 | 1.20k | } else |
105 | 307 | return std::string(); |
106 | 17.0k | Optional<double> RThroughput = |
107 | 17.0k | TSchedModel.computeInstrRThroughput(MCI.getOpcode()); |
108 | 17.0k | return createSchedInfoStr(Latency, RThroughput); |
109 | 17.0k | } |