Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
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//===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file defines all the static objects used by AArch64RegisterBankInfo.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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namespace llvm {
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RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
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    /* StartIdx, Length, RegBank */
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    // 0: FPR 32-bit value.
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    {0, 32, AArch64::FPRRegBank},
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    // 1: FPR 64-bit value.
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    {0, 64, AArch64::FPRRegBank},
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    // 2: FPR 128-bit value.
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    {0, 128, AArch64::FPRRegBank},
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    // 3: FPR 256-bit value.
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    {0, 256, AArch64::FPRRegBank},
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    // 4: FPR 512-bit value.
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    {0, 512, AArch64::FPRRegBank},
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    // 5: GPR 32-bit value.
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    {0, 32, AArch64::GPRRegBank},
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    // 6: GPR 64-bit value.
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    {0, 64, AArch64::GPRRegBank},
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};
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// ValueMappings.
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RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
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    /* BreakDown, NumBreakDowns */
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    // 0: invalid
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    {nullptr, 0},
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    // 3-operands instructions (all binary operations should end up with one of
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    // those mapping).
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    // 1: FPR 32-bit value. <-- This must match First3OpsIdx.
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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    // 4: FPR 64-bit value.
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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    // 7: FPR 128-bit value.
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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    // 10: FPR 256-bit value.
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
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    // 13: FPR 512-bit value.
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
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    // 16: GPR 32-bit value.
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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    // 19: GPR 64-bit value. <-- This must match Last3OpsIdx.
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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    // Cross register bank copies.
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    // 22: FPR 32-bit value to GPR 32-bit value. <-- This must match
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    //                                               FirstCrossRegCpyIdx.
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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    // 24: FPR 64-bit value to GPR 64-bit value.
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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    // 26: FPR 128-bit value to GPR 128-bit value (invalid)
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    {nullptr, 1},
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    {nullptr, 1},
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    // 28: FPR 256-bit value to GPR 256-bit value (invalid)
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    {nullptr, 1},
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    {nullptr, 1},
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    // 30: FPR 512-bit value to GPR 512-bit value (invalid)
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    {nullptr, 1},
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    {nullptr, 1},
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    // 32: GPR 32-bit value to FPR 32-bit value.
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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    // 34: GPR 64-bit value to FPR 64-bit value. <-- This must match
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    //                                               LastCrossRegCpyIdx.
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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};
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bool AArch64GenRegisterBankInfo::checkPartialMap(unsigned Idx,
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                                                 unsigned ValStartIdx,
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                                                 unsigned ValLength,
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0
                                                 const RegisterBank &RB) {
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  const PartialMapping &Map = PartMappings[Idx - PartialMappingIdx::PMI_Min];
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  return Map.StartIdx == ValStartIdx && Map.Length == ValLength &&
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0
         Map.RegBank == &RB;
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0
}
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bool AArch64GenRegisterBankInfo::checkValueMapImpl(unsigned Idx,
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                                                   unsigned FirstInBank,
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                                                   unsigned Size,
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0
                                                   unsigned Offset) {
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  unsigned PartialMapBaseIdx = Idx - PartialMappingIdx::PMI_Min;
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  const ValueMapping &Map =
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      AArch64GenRegisterBankInfo::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset];
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  return Map.BreakDown == &PartMappings[PartialMapBaseIdx] &&
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         Map.NumBreakDowns == 1;
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0
}
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bool AArch64GenRegisterBankInfo::checkPartialMappingIdx(
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    PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias,
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0
    ArrayRef<PartialMappingIdx> Order) {
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  if (Order.front() != FirstAlias)
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    return false;
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0
  
if (0
Order.back() != LastAlias0
)
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    return false;
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0
  
if (0
Order.front() > Order.back()0
)
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    return false;
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0
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  PartialMappingIdx Previous = Order.front();
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  bool First = true;
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  for (const auto &Current : Order) {
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    if (
First0
) {
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      First = false;
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      continue;
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0
    }
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0
    
if (0
Previous + 1 != Current0
)
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      return false;
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    Previous = Current;
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0
  }
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0
  return true;
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0
}
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unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
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6.40M
                                                             unsigned Size) {
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6.40M
  if (
RBIdx == PMI_FirstGPR6.40M
) {
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6.30M
    if (Size <= 32)
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3.21M
      return 0;
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3.09M
    
if (3.09M
Size <= 643.09M
)
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3.09M
      return 1;
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0
    return -1;
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6.30M
  }
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101k
  
if (101k
RBIdx == PMI_FirstFPR101k
) {
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101k
    if (Size <= 32)
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34.4k
      return 0;
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66.7k
    
if (66.7k
Size <= 6466.7k
)
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65.7k
      return 1;
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1.00k
    
if (1.00k
Size <= 1281.00k
)
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935
      return 2;
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74
    
if (74
Size <= 25674
)
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      return 3;
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0
    
if (0
Size <= 5120
)
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0
      return 4;
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0
    return -1;
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101k
  }
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0
  return -1;
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6.40M
}
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const RegisterBankInfo::ValueMapping *
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AArch64GenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx,
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6.35M
                                            unsigned Size) {
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6.35M
  assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
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6.35M
  unsigned BaseIdxOffset = getRegBankBaseIdxOffset(RBIdx, Size);
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6.35M
  if (BaseIdxOffset == -1u)
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0
    return &ValMappings[InvalidIdx];
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6.35M
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6.35M
  unsigned ValMappingIdx =
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6.35M
      First3OpsIdx + (RBIdx - PartialMappingIdx::PMI_Min + BaseIdxOffset) *
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6.35M
                         ValueMappingIdx::DistanceBetweenRegBanks;
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6.35M
  assert(ValMappingIdx >= First3OpsIdx && ValMappingIdx <= Last3OpsIdx &&
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6.35M
         "Mapping out of bound");
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6.35M
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6.35M
  return &ValMappings[ValMappingIdx];
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6.35M
}
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AArch64GenRegisterBankInfo::PartialMappingIdx
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    AArch64GenRegisterBankInfo::BankIDToCopyMapIdx[]{
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        PMI_None,     // CCR
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        PMI_FirstFPR, // FPR
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        PMI_FirstGPR, // GPR
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    };
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const RegisterBankInfo::ValueMapping *
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AArch64GenRegisterBankInfo::getCopyMapping(unsigned DstBankID,
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111k
                                           unsigned SrcBankID, unsigned Size) {
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111k
  assert(DstBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
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111k
  assert(SrcBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
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111k
  PartialMappingIdx DstRBIdx = BankIDToCopyMapIdx[DstBankID];
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111k
  PartialMappingIdx SrcRBIdx = BankIDToCopyMapIdx[SrcBankID];
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111k
  assert(DstRBIdx != PMI_None && "No such mapping");
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111k
  assert(SrcRBIdx != PMI_None && "No such mapping");
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111k
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111k
  if (DstRBIdx == SrcRBIdx)
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55.8k
    return getValueMapping(DstRBIdx, Size);
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111k
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56.1k
  assert(Size <= 64 && "GPR cannot handle that size");
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56.1k
  unsigned ValMappingIdx =
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56.1k
      FirstCrossRegCpyIdx +
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56.1k
      (DstRBIdx - PMI_Min + getRegBankBaseIdxOffset(DstRBIdx, Size)) *
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56.1k
          ValueMappingIdx::DistanceBetweenCrossRegCpy;
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56.1k
  assert(ValMappingIdx >= FirstCrossRegCpyIdx &&
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56.1k
         ValMappingIdx <= LastCrossRegCpyIdx && "Mapping out of bound");
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56.1k
  return &ValMappings[ValMappingIdx];
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111k
}
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} // End llvm namespace.