/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
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1 | | //===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | /// \file |
10 | | /// This file defines all the static objects used by AArch64RegisterBankInfo. |
11 | | /// \todo This should be generated by TableGen. |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | namespace llvm { |
15 | | RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{ |
16 | | /* StartIdx, Length, RegBank */ |
17 | | // 0: FPR 32-bit value. |
18 | | {0, 32, AArch64::FPRRegBank}, |
19 | | // 1: FPR 64-bit value. |
20 | | {0, 64, AArch64::FPRRegBank}, |
21 | | // 2: FPR 128-bit value. |
22 | | {0, 128, AArch64::FPRRegBank}, |
23 | | // 3: FPR 256-bit value. |
24 | | {0, 256, AArch64::FPRRegBank}, |
25 | | // 4: FPR 512-bit value. |
26 | | {0, 512, AArch64::FPRRegBank}, |
27 | | // 5: GPR 32-bit value. |
28 | | {0, 32, AArch64::GPRRegBank}, |
29 | | // 6: GPR 64-bit value. |
30 | | {0, 64, AArch64::GPRRegBank}, |
31 | | }; |
32 | | |
33 | | // ValueMappings. |
34 | | RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{ |
35 | | /* BreakDown, NumBreakDowns */ |
36 | | // 0: invalid |
37 | | {nullptr, 0}, |
38 | | // 3-operands instructions (all binary operations should end up with one of |
39 | | // those mapping). |
40 | | // 1: FPR 32-bit value. <-- This must match First3OpsIdx. |
41 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1}, |
42 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1}, |
43 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1}, |
44 | | // 4: FPR 64-bit value. |
45 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1}, |
46 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1}, |
47 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1}, |
48 | | // 7: FPR 128-bit value. |
49 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1}, |
50 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1}, |
51 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1}, |
52 | | // 10: FPR 256-bit value. |
53 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1}, |
54 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1}, |
55 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1}, |
56 | | // 13: FPR 512-bit value. |
57 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1}, |
58 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1}, |
59 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1}, |
60 | | // 16: GPR 32-bit value. |
61 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1}, |
62 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1}, |
63 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1}, |
64 | | // 19: GPR 64-bit value. <-- This must match Last3OpsIdx. |
65 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1}, |
66 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1}, |
67 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1}, |
68 | | // Cross register bank copies. |
69 | | // 22: FPR 32-bit value to GPR 32-bit value. <-- This must match |
70 | | // FirstCrossRegCpyIdx. |
71 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1}, |
72 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1}, |
73 | | // 24: FPR 64-bit value to GPR 64-bit value. |
74 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1}, |
75 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1}, |
76 | | // 26: FPR 128-bit value to GPR 128-bit value (invalid) |
77 | | {nullptr, 1}, |
78 | | {nullptr, 1}, |
79 | | // 28: FPR 256-bit value to GPR 256-bit value (invalid) |
80 | | {nullptr, 1}, |
81 | | {nullptr, 1}, |
82 | | // 30: FPR 512-bit value to GPR 512-bit value (invalid) |
83 | | {nullptr, 1}, |
84 | | {nullptr, 1}, |
85 | | // 32: GPR 32-bit value to FPR 32-bit value. |
86 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1}, |
87 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1}, |
88 | | // 34: GPR 64-bit value to FPR 64-bit value. <-- This must match |
89 | | // LastCrossRegCpyIdx. |
90 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1}, |
91 | | {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1}, |
92 | | }; |
93 | | |
94 | | bool AArch64GenRegisterBankInfo::checkPartialMap(unsigned Idx, |
95 | | unsigned ValStartIdx, |
96 | | unsigned ValLength, |
97 | 0 | const RegisterBank &RB) { |
98 | 0 | const PartialMapping &Map = PartMappings[Idx - PartialMappingIdx::PMI_Min]; |
99 | 0 | return Map.StartIdx == ValStartIdx && Map.Length == ValLength && |
100 | 0 | Map.RegBank == &RB; |
101 | 0 | } |
102 | | |
103 | | bool AArch64GenRegisterBankInfo::checkValueMapImpl(unsigned Idx, |
104 | | unsigned FirstInBank, |
105 | | unsigned Size, |
106 | 0 | unsigned Offset) { |
107 | 0 | unsigned PartialMapBaseIdx = Idx - PartialMappingIdx::PMI_Min; |
108 | 0 | const ValueMapping &Map = |
109 | 0 | AArch64GenRegisterBankInfo::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset]; |
110 | 0 | return Map.BreakDown == &PartMappings[PartialMapBaseIdx] && |
111 | 0 | Map.NumBreakDowns == 1; |
112 | 0 | } |
113 | | |
114 | | bool AArch64GenRegisterBankInfo::checkPartialMappingIdx( |
115 | | PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, |
116 | 0 | ArrayRef<PartialMappingIdx> Order) { |
117 | 0 | if (Order.front() != FirstAlias) |
118 | 0 | return false; |
119 | 0 | if (0 Order.back() != LastAlias0 ) |
120 | 0 | return false; |
121 | 0 | if (0 Order.front() > Order.back()0 ) |
122 | 0 | return false; |
123 | 0 |
|
124 | 0 | PartialMappingIdx Previous = Order.front(); |
125 | 0 | bool First = true; |
126 | 0 | for (const auto &Current : Order) { |
127 | 0 | if (First0 ) { |
128 | 0 | First = false; |
129 | 0 | continue; |
130 | 0 | } |
131 | 0 | if (0 Previous + 1 != Current0 ) |
132 | 0 | return false; |
133 | 0 | Previous = Current; |
134 | 0 | } |
135 | 0 | return true; |
136 | 0 | } |
137 | | |
138 | | unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx, |
139 | 6.40M | unsigned Size) { |
140 | 6.40M | if (RBIdx == PMI_FirstGPR6.40M ) { |
141 | 6.30M | if (Size <= 32) |
142 | 3.21M | return 0; |
143 | 3.09M | if (3.09M Size <= 643.09M ) |
144 | 3.09M | return 1; |
145 | 0 | return -1; |
146 | 6.30M | } |
147 | 101k | if (101k RBIdx == PMI_FirstFPR101k ) { |
148 | 101k | if (Size <= 32) |
149 | 34.4k | return 0; |
150 | 66.7k | if (66.7k Size <= 6466.7k ) |
151 | 65.7k | return 1; |
152 | 1.00k | if (1.00k Size <= 1281.00k ) |
153 | 935 | return 2; |
154 | 74 | if (74 Size <= 25674 ) |
155 | 74 | return 3; |
156 | 0 | if (0 Size <= 5120 ) |
157 | 0 | return 4; |
158 | 0 | return -1; |
159 | 101k | } |
160 | 0 | return -1; |
161 | 6.40M | } |
162 | | |
163 | | const RegisterBankInfo::ValueMapping * |
164 | | AArch64GenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx, |
165 | 6.35M | unsigned Size) { |
166 | 6.35M | assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that"); |
167 | 6.35M | unsigned BaseIdxOffset = getRegBankBaseIdxOffset(RBIdx, Size); |
168 | 6.35M | if (BaseIdxOffset == -1u) |
169 | 0 | return &ValMappings[InvalidIdx]; |
170 | 6.35M | |
171 | 6.35M | unsigned ValMappingIdx = |
172 | 6.35M | First3OpsIdx + (RBIdx - PartialMappingIdx::PMI_Min + BaseIdxOffset) * |
173 | 6.35M | ValueMappingIdx::DistanceBetweenRegBanks; |
174 | 6.35M | assert(ValMappingIdx >= First3OpsIdx && ValMappingIdx <= Last3OpsIdx && |
175 | 6.35M | "Mapping out of bound"); |
176 | 6.35M | |
177 | 6.35M | return &ValMappings[ValMappingIdx]; |
178 | 6.35M | } |
179 | | |
180 | | AArch64GenRegisterBankInfo::PartialMappingIdx |
181 | | AArch64GenRegisterBankInfo::BankIDToCopyMapIdx[]{ |
182 | | PMI_None, // CCR |
183 | | PMI_FirstFPR, // FPR |
184 | | PMI_FirstGPR, // GPR |
185 | | }; |
186 | | |
187 | | const RegisterBankInfo::ValueMapping * |
188 | | AArch64GenRegisterBankInfo::getCopyMapping(unsigned DstBankID, |
189 | 111k | unsigned SrcBankID, unsigned Size) { |
190 | 111k | assert(DstBankID < AArch64::NumRegisterBanks && "Invalid bank ID"); |
191 | 111k | assert(SrcBankID < AArch64::NumRegisterBanks && "Invalid bank ID"); |
192 | 111k | PartialMappingIdx DstRBIdx = BankIDToCopyMapIdx[DstBankID]; |
193 | 111k | PartialMappingIdx SrcRBIdx = BankIDToCopyMapIdx[SrcBankID]; |
194 | 111k | assert(DstRBIdx != PMI_None && "No such mapping"); |
195 | 111k | assert(SrcRBIdx != PMI_None && "No such mapping"); |
196 | 111k | |
197 | 111k | if (DstRBIdx == SrcRBIdx) |
198 | 55.8k | return getValueMapping(DstRBIdx, Size); |
199 | 111k | |
200 | 56.1k | assert(Size <= 64 && "GPR cannot handle that size"); |
201 | 56.1k | unsigned ValMappingIdx = |
202 | 56.1k | FirstCrossRegCpyIdx + |
203 | 56.1k | (DstRBIdx - PMI_Min + getRegBankBaseIdxOffset(DstRBIdx, Size)) * |
204 | 56.1k | ValueMappingIdx::DistanceBetweenCrossRegCpy; |
205 | 56.1k | assert(ValMappingIdx >= FirstCrossRegCpyIdx && |
206 | 56.1k | ValMappingIdx <= LastCrossRegCpyIdx && "Mapping out of bound"); |
207 | 56.1k | return &ValMappings[ValMappingIdx]; |
208 | 111k | } |
209 | | } // End llvm namespace. |