Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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//==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that AArch64 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
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#include "AArch64.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace AArch64ISD {
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enum NodeType : unsigned {
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  FIRST_NUMBER = ISD::BUILTIN_OP_END,
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  WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
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  CALL,         // Function call.
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  // Produces the full sequence of instructions for getting the thread pointer
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  // offset of a variable into X0, using the TLSDesc model.
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  TLSDESC_CALLSEQ,
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  ADRP,     // Page address of a TargetGlobalAddress operand.
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  ADDlow,   // Add the low 12 bits of a TargetGlobalAddress operand.
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  LOADgot,  // Load from automatically generated descriptor (e.g. Global
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            // Offset Table, TLS record).
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  RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
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  BRCOND,   // Conditional branch instruction; "b.cond".
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  CSEL,
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  FCSEL, // Conditional move instruction.
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  CSINV, // Conditional select invert.
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  CSNEG, // Conditional select negate.
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  CSINC, // Conditional select increment.
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  // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
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  // ELF.
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  THREAD_POINTER,
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  ADC,
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  SBC, // adc, sbc instructions
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  // Arithmetic instructions which write flags.
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  ADDS,
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  SUBS,
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  ADCS,
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  SBCS,
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  ANDS,
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  // Conditional compares. Operands: left,right,falsecc,cc,flags
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  CCMP,
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  CCMN,
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  FCCMP,
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  // Floating point comparison
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  FCMP,
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  // Scalar extract
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  EXTR,
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  // Scalar-to-vector duplication
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  DUP,
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  DUPLANE8,
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  DUPLANE16,
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  DUPLANE32,
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  DUPLANE64,
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  // Vector immedate moves
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  MOVI,
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  MOVIshift,
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  MOVIedit,
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  MOVImsl,
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  FMOV,
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  MVNIshift,
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  MVNImsl,
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  // Vector immediate ops
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  BICi,
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  ORRi,
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  // Vector bit select: similar to ISD::VSELECT but not all bits within an
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  // element must be identical.
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  BSL,
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  // Vector arithmetic negation
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  NEG,
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  // Vector shuffles
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  ZIP1,
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  ZIP2,
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  UZP1,
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  UZP2,
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  TRN1,
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  TRN2,
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  REV16,
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  REV32,
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  REV64,
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  EXT,
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  // Vector shift by scalar
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  VSHL,
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  VLSHR,
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  VASHR,
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  // Vector shift by scalar (again)
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  SQSHL_I,
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  UQSHL_I,
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  SQSHLU_I,
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  SRSHR_I,
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  URSHR_I,
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  // Vector comparisons
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  CMEQ,
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  CMGE,
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  CMGT,
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  CMHI,
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  CMHS,
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  FCMEQ,
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  FCMGE,
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  FCMGT,
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  // Vector zero comparisons
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  CMEQz,
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  CMGEz,
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  CMGTz,
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  CMLEz,
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  CMLTz,
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  FCMEQz,
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  FCMGEz,
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  FCMGTz,
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  FCMLEz,
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  FCMLTz,
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  // Vector across-lanes addition
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  // Only the lower result lane is defined.
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  SADDV,
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  UADDV,
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  // Vector across-lanes min/max
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  // Only the lower result lane is defined.
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  SMINV,
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  UMINV,
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  SMAXV,
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  UMAXV,
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  // Vector bitwise negation
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  NOT,
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  // Vector bitwise selection
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  BIT,
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  // Compare-and-branch
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  CBZ,
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  CBNZ,
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  TBZ,
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  TBNZ,
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  // Tail calls
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  TC_RETURN,
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  // Custom prefetch handling
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  PREFETCH,
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  // {s|u}int to FP within a FP register.
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  SITOF,
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  UITOF,
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  /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
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  /// world w.r.t vectors; which causes additional REV instructions to be
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  /// generated to compensate for the byte-swapping. But sometimes we do
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  /// need to re-interpret the data in SIMD vector registers in big-endian
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  /// mode without emitting such REV instructions.
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  NVCAST,
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  SMULL,
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  UMULL,
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  // Reciprocal estimates and steps.
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  FRECPE, FRECPS,
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  FRSQRTE, FRSQRTS,
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  // NEON Load/Store with post-increment base updates
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  LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
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  LD3post,
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  LD4post,
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  ST2post,
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  ST3post,
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  ST4post,
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  LD1x2post,
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  LD1x3post,
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  LD1x4post,
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  ST1x2post,
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  ST1x3post,
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  ST1x4post,
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  LD1DUPpost,
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  LD2DUPpost,
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  LD3DUPpost,
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  LD4DUPpost,
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  LD1LANEpost,
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  LD2LANEpost,
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  LD3LANEpost,
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  LD4LANEpost,
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  ST2LANEpost,
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  ST3LANEpost,
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  ST4LANEpost
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};
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} // end namespace AArch64ISD
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namespace {
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// Any instruction that defines a 32-bit result zeros out the high half of the
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// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
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// be copying from a truncate. But any other 32-bit operation will zero-extend
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// up to 64 bits.
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// FIXME: X86 also checks for CMOV here. Do we need something similar?
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static inline bool isDef32(const SDNode &N) {
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  unsigned Opc = N.getOpcode();
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  return Opc != ISD::TRUNCATE && Opc != TargetOpcode::EXTRACT_SUBREG &&
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         Opc != ISD::CopyFromReg;
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}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64AsmPrinter.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
AArch64ISelDAGToDAG.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
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static inline bool isDef32(const SDNode &N) {
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  unsigned Opc = N.getOpcode();
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  return Opc != ISD::TRUNCATE && Opc != TargetOpcode::EXTRACT_SUBREG &&
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         Opc != ISD::CopyFromReg;
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}
Unexecuted instantiation: AArch64ISelLowering.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64InstrInfo.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
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} // end anonymous namespace
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class AArch64Subtarget;
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class AArch64TargetMachine;
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class AArch64TargetLowering : public TargetLowering {
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public:
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  explicit AArch64TargetLowering(const TargetMachine &TM,
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                                 const AArch64Subtarget &STI);
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  /// Selects the correct CCAssignFn for a given CallingConvention value.
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  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
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  /// Selects the correct CCAssignFn for a given CallingConvention value.
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  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const;
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  /// Determine which of the bits specified in Mask are known to be either zero
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  /// or one and return them in the KnownZero/KnownOne bitsets.
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  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
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                                     const APInt &DemandedElts,
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                                     const SelectionDAG &DAG,
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                                     unsigned Depth = 0) const override;
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  bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
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                                    TargetLoweringOpt &TLO) const override;
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  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
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  /// Returns true if the target allows unaligned memory accesses of the
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  /// specified type.
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  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
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                                      unsigned Align = 1,
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                                      bool *Fast = nullptr) const override;
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  /// Provide custom lowering hooks for some operations.
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  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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  const char *getTargetNodeName(unsigned Opcode) const override;
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  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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  /// Returns true if a cast between SrcAS and DestAS is a noop.
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0
  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
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0
    // Addrspacecasts are always noops.
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0
    return true;
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0
  }
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  /// This method returns a target specific FastISel object, or null if the
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  /// target does not support "fast" ISel.
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  FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
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                           const TargetLibraryInfo *libInfo) const override;
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  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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  /// Return true if the given shuffle mask can be codegen'd directly, or if it
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  /// should be stack expanded.
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  bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
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  /// Return the ISD::SETCC ValueType.
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  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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                         EVT VT) const override;
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  SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
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  MachineBasicBlock *EmitF128CSEL(MachineInstr &MI,
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                                  MachineBasicBlock *BB) const;
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  MachineBasicBlock *
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  EmitInstrWithCustomInserter(MachineInstr &MI,
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                              MachineBasicBlock *MBB) const override;
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  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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                          unsigned Intrinsic) const override;
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  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
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  bool isTruncateFree(EVT VT1, EVT VT2) const override;
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  bool isProfitableToHoist(Instruction *I) const override;
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  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
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  bool isZExtFree(EVT VT1, EVT VT2) const override;
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  bool isZExtFree(SDValue Val, EVT VT2) const override;
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  bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
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458k
  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
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  bool lowerInterleavedLoad(LoadInst *LI,
325
                            ArrayRef<ShuffleVectorInst *> Shuffles,
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                            ArrayRef<unsigned> Indices,
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                            unsigned Factor) const override;
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  bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
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                             unsigned Factor) const override;
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  bool isLegalAddImmediate(int64_t) const override;
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  bool isLegalICmpImmediate(int64_t) const override;
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  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
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                          bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
336
                          MachineFunction &MF) const override;
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  /// Return true if the addressing mode represented by AM is legal for this
339
  /// target, for a load/store of the specified type.
340
  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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                             unsigned AS,
342
                             Instruction *I = nullptr) const override;
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344
  /// \brief Return the cost of the scaling factor used in the addressing
345
  /// mode represented by AM for this target, for a load/store
346
  /// of the specified type.
347
  /// If the AM is supported, the return value must be >= 0.
348
  /// If the AM is not supported, it returns a negative value.
349
  int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
350
                           unsigned AS) const override;
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352
  /// Return true if an FMA operation is faster than a pair of fmul and fadd
353
  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
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  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
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  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
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357
  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
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359
  /// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask.
360
  bool isDesirableToCommuteWithShift(const SDNode *N) const override;
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  /// \brief Returns true if it is beneficial to convert a load of a constant
363
  /// to just the constant itself.
364
  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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                                         Type *Ty) const override;
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367
  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
368
                        AtomicOrdering Ord) const override;
369
  Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
370
                              Value *Addr, AtomicOrdering Ord) const override;
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372
  void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
373
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  TargetLoweringBase::AtomicExpansionKind
375
  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
376
  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
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  TargetLoweringBase::AtomicExpansionKind
378
  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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380
  bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
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  bool useLoadStackGuardNode() const override;
383
  TargetLoweringBase::LegalizeTypeAction
384
  getPreferredVectorAction(EVT VT) const override;
385
386
  /// If the target has a standard location for the stack protector cookie,
387
  /// returns the address of that location. Otherwise, returns nullptr.
388
  Value *getIRStackGuard(IRBuilder<> &IRB) const override;
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390
  /// If the target has a standard location for the unsafe stack pointer,
391
  /// returns the address of that location. Otherwise, returns nullptr.
392
  Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
393
394
  /// If a physical register, this returns the register that receives the
395
  /// exception address on entry to an EH pad.
396
  unsigned
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36.1k
  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
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36.1k
    // FIXME: This is a guess. Has this been defined yet?
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36.1k
    return AArch64::X0;
400
36.1k
  }
401
402
  /// If a physical register, this returns the register that receives the
403
  /// exception typeid on entry to a landing pad.
404
  unsigned
405
18.0k
  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
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18.0k
    // FIXME: This is a guess. Has this been defined yet?
407
18.0k
    return AArch64::X1;
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18.0k
  }
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  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
411
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  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
413
1.67M
                        const SelectionDAG &DAG) const override {
414
1.67M
    // Do not merge to float value size (128 bytes) if no implicit
415
1.67M
    // float attribute is set.
416
1.67M
417
1.67M
    bool NoFloat = DAG.getMachineFunction().getFunction()->hasFnAttribute(
418
1.67M
        Attribute::NoImplicitFloat);
419
1.67M
420
1.67M
    if (NoFloat)
421
4
      return (MemVT.getSizeInBits() <= 64);
422
1.67M
    return true;
423
1.67M
  }
424
425
440
  bool isCheapToSpeculateCttz() const override {
426
440
    return true;
427
440
  }
428
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1.60k
  bool isCheapToSpeculateCtlz() const override {
430
1.60k
    return true;
431
1.60k
  }
432
433
  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
434
435
7.23k
  bool hasAndNotCompare(SDValue) const override {
436
7.23k
    // 'bics'
437
7.23k
    return true;
438
7.23k
  }
439
440
33.9k
  bool hasBitPreservingFPLogic(EVT VT) const override {
441
33.9k
    // FIXME: Is this always true? It should be true for vectors at least.
442
27.9k
    return VT == MVT::f32 || VT == MVT::f64;
443
33.9k
  }
444
445
299k
  bool supportSplitCSR(MachineFunction *MF) const override {
446
299k
    return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
447
12
           MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
448
299k
  }
449
  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
450
  void insertCopiesSplitCSR(
451
      MachineBasicBlock *Entry,
452
      const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
453
454
19.7M
  bool supportSwiftError() const override {
455
19.7M
    return true;
456
19.7M
  }
457
458
  /// Returns the size of the platform's va_list object.
459
  unsigned getVaListSizeInBits(const DataLayout &DL) const override;
460
461
  /// Returns true if \p VecTy is a legal interleaved access type. This
462
  /// function checks the vector element type and the overall width of the
463
  /// vector.
464
  bool isLegalInterleavedAccessType(VectorType *VecTy,
465
                                    const DataLayout &DL) const;
466
467
  /// Returns the number of interleaved accesses that will be generated when
468
  /// lowering accesses of the given type.
469
  unsigned getNumInterleavedAccesses(VectorType *VecTy,
470
                                     const DataLayout &DL) const;
471
472
  MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override;
473
474
  bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
475
                                                 CallingConv::ID CallConv,
476
                                                 bool isVarArg) const override;
477
private:
478
  bool isExtFreeImpl(const Instruction *Ext) const override;
479
480
  /// Keep a pointer to the AArch64Subtarget around so that we can
481
  /// make the right decision when generating code for different targets.
482
  const AArch64Subtarget *Subtarget;
483
484
  void addTypeForNEON(MVT VT, MVT PromotedBitwiseVT);
485
  void addDRTypeForNEON(MVT VT);
486
  void addQRTypeForNEON(MVT VT);
487
488
  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
489
                               bool isVarArg,
490
                               const SmallVectorImpl<ISD::InputArg> &Ins,
491
                               const SDLoc &DL, SelectionDAG &DAG,
492
                               SmallVectorImpl<SDValue> &InVals) const override;
493
494
  SDValue LowerCall(CallLoweringInfo & /*CLI*/,
495
                    SmallVectorImpl<SDValue> &InVals) const override;
496
497
  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
498
                          CallingConv::ID CallConv, bool isVarArg,
499
                          const SmallVectorImpl<ISD::InputArg> &Ins,
500
                          const SDLoc &DL, SelectionDAG &DAG,
501
                          SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
502
                          SDValue ThisVal) const;
503
504
  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
505
506
  bool isEligibleForTailCallOptimization(
507
      SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
508
      const SmallVectorImpl<ISD::OutputArg> &Outs,
509
      const SmallVectorImpl<SDValue> &OutVals,
510
      const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
511
512
  /// Finds the incoming stack arguments which overlap the given fixed stack
513
  /// object and incorporates their load into the current chain. This prevents
514
  /// an upcoming store from clobbering the stack argument before it's used.
515
  SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
516
                              MachineFrameInfo &MFI, int ClobberedFI) const;
517
518
  bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
519
520
  void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
521
                           SDValue &Chain) const;
522
523
  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
524
                      bool isVarArg,
525
                      const SmallVectorImpl<ISD::OutputArg> &Outs,
526
                      LLVMContext &Context) const override;
527
528
  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
529
                      const SmallVectorImpl<ISD::OutputArg> &Outs,
530
                      const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
531
                      SelectionDAG &DAG) const override;
532
533
  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
534
                        unsigned Flag) const;
535
  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
536
                        unsigned Flag) const;
537
  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
538
                        unsigned Flag) const;
539
  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
540
                        unsigned Flag) const;
541
  template <class NodeTy> SDValue getGOT(NodeTy *N, SelectionDAG &DAG) const;
542
  template <class NodeTy>
543
  SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG) const;
544
  template <class NodeTy> SDValue getAddr(NodeTy *N, SelectionDAG &DAG) const;
545
  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
546
  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
547
  SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
548
  SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
549
  SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
550
                                 SelectionDAG &DAG) const;
551
  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
552
  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
553
  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
554
  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
555
  SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
556
                         SDValue TVal, SDValue FVal, const SDLoc &dl,
557
                         SelectionDAG &DAG) const;
558
  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
559
  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
560
  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
561
  SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
562
  SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
563
  SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
564
  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
565
  SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
566
  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
567
  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
568
  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
569
  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
570
  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
571
  SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
572
  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
573
  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
574
  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
575
  SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
576
  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
577
  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
578
  SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
579
  SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
580
  SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
581
                        RTLIB::Libcall Call) const;
582
  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
583
  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
584
  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
585
  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
586
  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
587
  SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const;
588
  SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
589
  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
590
  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
591
  SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
592
593
  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
594
                        std::vector<SDNode *> *Created) const override;
595
  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
596
                          int &ExtraSteps, bool &UseOneConst,
597
                          bool Reciprocal) const override;
598
  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
599
                           int &ExtraSteps) const override;
600
  unsigned combineRepeatedFPDivisors() const override;
601
602
  ConstraintType getConstraintType(StringRef Constraint) const override;
603
  unsigned getRegisterByName(const char* RegName, EVT VT,
604
                             SelectionDAG &DAG) const override;
605
606
  /// Examine constraint string and operand type and determine a weight value.
607
  /// The operand object must already have been set up with the operand type.
608
  ConstraintWeight
609
  getSingleConstraintMatchWeight(AsmOperandInfo &info,
610
                                 const char *constraint) const override;
611
612
  std::pair<unsigned, const TargetRegisterClass *>
613
  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
614
                               StringRef Constraint, MVT VT) const override;
615
616
  const char *LowerXConstraint(EVT ConstraintVT) const override;
617
618
  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
619
                                    std::vector<SDValue> &Ops,
620
                                    SelectionDAG &DAG) const override;
621
622
2
  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
623
2
    if (ConstraintCode == "Q")
624
2
      return InlineAsm::Constraint_Q;
625
2
    // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
626
2
    //        followed by llvm_unreachable so we'll leave them unimplemented in
627
2
    //        the backend for now.
628
0
    return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
629
2
  }
630
631
  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
632
  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
633
  bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
634
                              ISD::MemIndexedMode &AM, bool &IsInc,
635
                              SelectionDAG &DAG) const;
636
  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
637
                                 ISD::MemIndexedMode &AM,
638
                                 SelectionDAG &DAG) const override;
639
  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
640
                                  SDValue &Offset, ISD::MemIndexedMode &AM,
641
                                  SelectionDAG &DAG) const override;
642
643
  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
644
                          SelectionDAG &DAG) const override;
645
646
  bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
647
};
648
649
namespace AArch64 {
650
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
651
                         const TargetLibraryInfo *libInfo);
652
} // end namespace AArch64
653
654
} // end namespace llvm
655
656
#endif