Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
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//===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides AArch64 specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64MCTargetDesc.h"
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#include "AArch64ELFStreamer.h"
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#include "AArch64MCAsmInfo.h"
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#include "AArch64WinCOFFStreamer.h"
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#include "InstPrinter/AArch64InstPrinter.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "AArch64GenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "AArch64GenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "AArch64GenRegisterInfo.inc"
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static MCInstrInfo *createAArch64MCInstrInfo() {
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  MCInstrInfo *X = new MCInstrInfo();
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  InitAArch64MCInstrInfo(X);
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  return X;
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}
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static MCSubtargetInfo *
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createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
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  if (CPU.empty())
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    CPU = "generic";
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  return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
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}
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void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
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  for (unsigned Reg = AArch64::NoRegister + 1;
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Reg < AArch64::NUM_TARGET_REGS13.9M
;
++Reg13.9M
) {
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    unsigned CV = MRI->getEncodingValue(Reg);
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    MRI->mapLLVMRegToCVReg(Reg, CV);
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  }
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}
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static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
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  MCRegisterInfo *X = new MCRegisterInfo();
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  InitAArch64MCRegisterInfo(X, AArch64::LR);
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  AArch64_MC::initLLVMToCVRegMapping(X);
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  return X;
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}
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static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
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                                         const Triple &TheTriple) {
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  MCAsmInfo *MAI;
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  if (TheTriple.isOSBinFormatMachO())
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    MAI = new AArch64MCAsmInfoDarwin();
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  else 
if (1.50k
TheTriple.isWindowsMSVCEnvironment()1.50k
)
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    MAI = new AArch64MCAsmInfoMicrosoftCOFF();
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  else 
if (1.49k
TheTriple.isOSBinFormatCOFF()1.49k
)
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    MAI = new AArch64MCAsmInfoGNUCOFF();
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  else {
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    assert(TheTriple.isOSBinFormatELF() && "Invalid target");
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    MAI = new AArch64MCAsmInfoELF(TheTriple);
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  }
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  // Initial state of the frame pointer is SP.
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  unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
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  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
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  MAI->addInitialFrameState(Inst);
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  return MAI;
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}
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static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
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                                                 unsigned SyntaxVariant,
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                                                 const MCAsmInfo &MAI,
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                                                 const MCInstrInfo &MII,
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                                                 const MCRegisterInfo &MRI) {
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  if (SyntaxVariant == 0)
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    return new AArch64InstPrinter(MAI, MII, MRI);
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if (397
SyntaxVariant == 1397
)
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    return new AArch64AppleInstPrinter(MAI, MII, MRI);
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  return nullptr;
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}
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static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
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                                     MCAsmBackend &TAB, raw_pwrite_stream &OS,
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                                     MCCodeEmitter *Emitter, bool RelaxAll) {
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  return createAArch64ELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
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}
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static MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,
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                                       raw_pwrite_stream &OS,
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                                       MCCodeEmitter *Emitter, bool RelaxAll,
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                                       bool DWARFMustBeAtTheEnd) {
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  return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
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                             DWARFMustBeAtTheEnd,
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                             /*LabelSections*/ true);
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}
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static MCStreamer *createWinCOFFStreamer(MCContext &Ctx, MCAsmBackend &TAB,
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                                         raw_pwrite_stream &OS,
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                                         MCCodeEmitter *Emitter, bool RelaxAll,
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                                         bool IncrementalLinkerCompatible) {
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  return createAArch64WinCOFFStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
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                                      IncrementalLinkerCompatible);
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}
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static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {
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  return new MCInstrAnalysis(Info);
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}
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// Force static initialization.
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extern "C" void LLVMInitializeAArch64TargetMC() {
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  for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
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                    &getTheARM64Target()}) {
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    // Register the MC asm info.
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    RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
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    // Register the MC instruction info.
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    TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
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    // Register the MC register info.
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    TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);
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    // Register the MC subtarget info.
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    TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo);
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    // Register the MC instruction analyzer.
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    TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis);
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    // Register the MC Code Emitter
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    TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter);
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    // Register the obj streamers.
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    TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
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    TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer);
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    TargetRegistry::RegisterCOFFStreamer(*T, createWinCOFFStreamer);
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    // Register the obj target streamer.
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    TargetRegistry::RegisterObjectTargetStreamer(
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        *T, createAArch64ObjectTargetStreamer);
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    // Register the asm streamer.
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    TargetRegistry::RegisterAsmTargetStreamer(*T,
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                                              createAArch64AsmTargetStreamer);
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    // Register the MCInstPrinter.
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    TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);
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  }
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  // Register the asm backend.
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  for (Target *T : {&getTheAArch64leTarget(), &getTheARM64Target()})
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    TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);
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  TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(),
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                                       createAArch64beAsmBackend);
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}