/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
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1 | | //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file provides AArch64 specific target descriptions. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "AArch64MCTargetDesc.h" |
15 | | #include "AArch64ELFStreamer.h" |
16 | | #include "AArch64MCAsmInfo.h" |
17 | | #include "AArch64WinCOFFStreamer.h" |
18 | | #include "InstPrinter/AArch64InstPrinter.h" |
19 | | #include "llvm/MC/MCInstrAnalysis.h" |
20 | | #include "llvm/MC/MCInstrInfo.h" |
21 | | #include "llvm/MC/MCRegisterInfo.h" |
22 | | #include "llvm/MC/MCStreamer.h" |
23 | | #include "llvm/MC/MCSubtargetInfo.h" |
24 | | #include "llvm/Support/ErrorHandling.h" |
25 | | #include "llvm/Support/TargetRegistry.h" |
26 | | |
27 | | using namespace llvm; |
28 | | |
29 | | #define GET_INSTRINFO_MC_DESC |
30 | | #include "AArch64GenInstrInfo.inc" |
31 | | |
32 | | #define GET_SUBTARGETINFO_MC_DESC |
33 | | #include "AArch64GenSubtargetInfo.inc" |
34 | | |
35 | | #define GET_REGINFO_MC_DESC |
36 | | #include "AArch64GenRegisterInfo.inc" |
37 | | |
38 | 14.9k | static MCInstrInfo *createAArch64MCInstrInfo() { |
39 | 14.9k | MCInstrInfo *X = new MCInstrInfo(); |
40 | 14.9k | InitAArch64MCInstrInfo(X); |
41 | 14.9k | return X; |
42 | 14.9k | } |
43 | | |
44 | | static MCSubtargetInfo * |
45 | 14.8k | createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { |
46 | 14.8k | if (CPU.empty()) |
47 | 1.64k | CPU = "generic"; |
48 | 14.8k | |
49 | 14.8k | return createAArch64MCSubtargetInfoImpl(TT, CPU, FS); |
50 | 14.8k | } |
51 | | |
52 | 28.8k | void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { |
53 | 28.8k | for (unsigned Reg = AArch64::NoRegister + 1; |
54 | 13.9M | Reg < AArch64::NUM_TARGET_REGS13.9M ; ++Reg13.9M ) { |
55 | 13.9M | unsigned CV = MRI->getEncodingValue(Reg); |
56 | 13.9M | MRI->mapLLVMRegToCVReg(Reg, CV); |
57 | 13.9M | } |
58 | 28.8k | } |
59 | | |
60 | 14.9k | static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) { |
61 | 14.9k | MCRegisterInfo *X = new MCRegisterInfo(); |
62 | 14.9k | InitAArch64MCRegisterInfo(X, AArch64::LR); |
63 | 14.9k | AArch64_MC::initLLVMToCVRegMapping(X); |
64 | 14.9k | return X; |
65 | 14.9k | } |
66 | | |
67 | | static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, |
68 | 14.9k | const Triple &TheTriple) { |
69 | 14.9k | MCAsmInfo *MAI; |
70 | 14.9k | if (TheTriple.isOSBinFormatMachO()) |
71 | 13.3k | MAI = new AArch64MCAsmInfoDarwin(); |
72 | 1.50k | else if (1.50k TheTriple.isWindowsMSVCEnvironment()1.50k ) |
73 | 12 | MAI = new AArch64MCAsmInfoMicrosoftCOFF(); |
74 | 1.49k | else if (1.49k TheTriple.isOSBinFormatCOFF()1.49k ) |
75 | 3 | MAI = new AArch64MCAsmInfoGNUCOFF(); |
76 | 1.48k | else { |
77 | 1.48k | assert(TheTriple.isOSBinFormatELF() && "Invalid target"); |
78 | 1.48k | MAI = new AArch64MCAsmInfoELF(TheTriple); |
79 | 1.48k | } |
80 | 14.9k | |
81 | 14.9k | // Initial state of the frame pointer is SP. |
82 | 14.9k | unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true); |
83 | 14.9k | MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); |
84 | 14.9k | MAI->addInitialFrameState(Inst); |
85 | 14.9k | |
86 | 14.9k | return MAI; |
87 | 14.9k | } |
88 | | |
89 | | static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T, |
90 | | unsigned SyntaxVariant, |
91 | | const MCAsmInfo &MAI, |
92 | | const MCInstrInfo &MII, |
93 | 1.28k | const MCRegisterInfo &MRI) { |
94 | 1.28k | if (SyntaxVariant == 0) |
95 | 883 | return new AArch64InstPrinter(MAI, MII, MRI); |
96 | 397 | if (397 SyntaxVariant == 1397 ) |
97 | 397 | return new AArch64AppleInstPrinter(MAI, MII, MRI); |
98 | 0 |
|
99 | 0 | return nullptr; |
100 | 0 | } |
101 | | |
102 | | static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, |
103 | | MCAsmBackend &TAB, raw_pwrite_stream &OS, |
104 | 159 | MCCodeEmitter *Emitter, bool RelaxAll) { |
105 | 159 | return createAArch64ELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll); |
106 | 159 | } |
107 | | |
108 | | static MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB, |
109 | | raw_pwrite_stream &OS, |
110 | | MCCodeEmitter *Emitter, bool RelaxAll, |
111 | 12.9k | bool DWARFMustBeAtTheEnd) { |
112 | 12.9k | return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll, |
113 | 12.9k | DWARFMustBeAtTheEnd, |
114 | 12.9k | /*LabelSections*/ true); |
115 | 12.9k | } |
116 | | |
117 | | static MCStreamer *createWinCOFFStreamer(MCContext &Ctx, MCAsmBackend &TAB, |
118 | | raw_pwrite_stream &OS, |
119 | | MCCodeEmitter *Emitter, bool RelaxAll, |
120 | 5 | bool IncrementalLinkerCompatible) { |
121 | 5 | return createAArch64WinCOFFStreamer(Ctx, TAB, OS, Emitter, RelaxAll, |
122 | 5 | IncrementalLinkerCompatible); |
123 | 5 | } |
124 | | |
125 | 43 | static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) { |
126 | 43 | return new MCInstrAnalysis(Info); |
127 | 43 | } |
128 | | |
129 | | // Force static initialization. |
130 | 70.1k | extern "C" void LLVMInitializeAArch64TargetMC() { |
131 | 70.1k | for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(), |
132 | 210k | &getTheARM64Target()}) { |
133 | 210k | // Register the MC asm info. |
134 | 210k | RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); |
135 | 210k | |
136 | 210k | // Register the MC instruction info. |
137 | 210k | TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo); |
138 | 210k | |
139 | 210k | // Register the MC register info. |
140 | 210k | TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo); |
141 | 210k | |
142 | 210k | // Register the MC subtarget info. |
143 | 210k | TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo); |
144 | 210k | |
145 | 210k | // Register the MC instruction analyzer. |
146 | 210k | TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis); |
147 | 210k | |
148 | 210k | // Register the MC Code Emitter |
149 | 210k | TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter); |
150 | 210k | |
151 | 210k | // Register the obj streamers. |
152 | 210k | TargetRegistry::RegisterELFStreamer(*T, createELFStreamer); |
153 | 210k | TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer); |
154 | 210k | TargetRegistry::RegisterCOFFStreamer(*T, createWinCOFFStreamer); |
155 | 210k | |
156 | 210k | // Register the obj target streamer. |
157 | 210k | TargetRegistry::RegisterObjectTargetStreamer( |
158 | 210k | *T, createAArch64ObjectTargetStreamer); |
159 | 210k | |
160 | 210k | // Register the asm streamer. |
161 | 210k | TargetRegistry::RegisterAsmTargetStreamer(*T, |
162 | 210k | createAArch64AsmTargetStreamer); |
163 | 210k | // Register the MCInstPrinter. |
164 | 210k | TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter); |
165 | 210k | } |
166 | 70.1k | |
167 | 70.1k | // Register the asm backend. |
168 | 70.1k | for (Target *T : {&getTheAArch64leTarget(), &getTheARM64Target()}) |
169 | 140k | TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend); |
170 | 70.1k | TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(), |
171 | 70.1k | createAArch64beAsmBackend); |
172 | 70.1k | } |