Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/ARM/ARMFastISel.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- ARMFastISel.cpp - ARM FastISel implementation ----------------------===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This file defines the ARM-specific support for the FastISel class. Some
11
// of the target-specific code is generated by tablegen in the file
12
// ARMGenFastISel.inc, which is #included here.
13
//
14
//===----------------------------------------------------------------------===//
15
16
#include "ARM.h"
17
#include "ARMBaseInstrInfo.h"
18
#include "ARMBaseRegisterInfo.h"
19
#include "ARMCallingConv.h"
20
#include "ARMConstantPoolValue.h"
21
#include "ARMISelLowering.h"
22
#include "ARMMachineFunctionInfo.h"
23
#include "ARMSubtarget.h"
24
#include "MCTargetDesc/ARMAddressingModes.h"
25
#include "MCTargetDesc/ARMBaseInfo.h"
26
#include "Utils/ARMBaseInfo.h"
27
#include "llvm/ADT/APFloat.h"
28
#include "llvm/ADT/APInt.h"
29
#include "llvm/ADT/DenseMap.h"
30
#include "llvm/ADT/SmallVector.h"
31
#include "llvm/CodeGen/CallingConvLower.h"
32
#include "llvm/CodeGen/FastISel.h"
33
#include "llvm/CodeGen/FunctionLoweringInfo.h"
34
#include "llvm/CodeGen/ISDOpcodes.h"
35
#include "llvm/CodeGen/MachineBasicBlock.h"
36
#include "llvm/CodeGen/MachineConstantPool.h"
37
#include "llvm/CodeGen/MachineFrameInfo.h"
38
#include "llvm/CodeGen/MachineFunction.h"
39
#include "llvm/CodeGen/MachineInstr.h"
40
#include "llvm/CodeGen/MachineInstrBuilder.h"
41
#include "llvm/CodeGen/MachineMemOperand.h"
42
#include "llvm/CodeGen/MachineOperand.h"
43
#include "llvm/CodeGen/MachineRegisterInfo.h"
44
#include "llvm/CodeGen/MachineValueType.h"
45
#include "llvm/CodeGen/RuntimeLibcalls.h"
46
#include "llvm/CodeGen/ValueTypes.h"
47
#include "llvm/IR/Argument.h"
48
#include "llvm/IR/Attributes.h"
49
#include "llvm/IR/CallSite.h"
50
#include "llvm/IR/CallingConv.h"
51
#include "llvm/IR/Constant.h"
52
#include "llvm/IR/Constants.h"
53
#include "llvm/IR/DataLayout.h"
54
#include "llvm/IR/DerivedTypes.h"
55
#include "llvm/IR/Function.h"
56
#include "llvm/IR/GetElementPtrTypeIterator.h"
57
#include "llvm/IR/GlobalValue.h"
58
#include "llvm/IR/GlobalVariable.h"
59
#include "llvm/IR/InstrTypes.h"
60
#include "llvm/IR/Instruction.h"
61
#include "llvm/IR/Instructions.h"
62
#include "llvm/IR/IntrinsicInst.h"
63
#include "llvm/IR/Intrinsics.h"
64
#include "llvm/IR/Module.h"
65
#include "llvm/IR/Operator.h"
66
#include "llvm/IR/Type.h"
67
#include "llvm/IR/User.h"
68
#include "llvm/IR/Value.h"
69
#include "llvm/MC/MCInstrDesc.h"
70
#include "llvm/MC/MCRegisterInfo.h"
71
#include "llvm/Support/Casting.h"
72
#include "llvm/Support/Compiler.h"
73
#include "llvm/Support/ErrorHandling.h"
74
#include "llvm/Support/MathExtras.h"
75
#include "llvm/Target/TargetInstrInfo.h"
76
#include "llvm/Target/TargetLowering.h"
77
#include "llvm/Target/TargetMachine.h"
78
#include "llvm/Target/TargetOpcodes.h"
79
#include "llvm/Target/TargetOptions.h"
80
#include "llvm/Target/TargetRegisterInfo.h"
81
#include <cassert>
82
#include <cstdint>
83
#include <utility>
84
85
using namespace llvm;
86
87
namespace {
88
89
  // All possible address modes, plus some.
90
  struct Address {
91
    enum {
92
      RegBase,
93
      FrameIndexBase
94
    } BaseType = RegBase;
95
96
    union {
97
      unsigned Reg;
98
      int FI;
99
    } Base;
100
101
    int Offset = 0;
102
103
    // Innocuous defaults for our address.
104
1.55k
    Address() {
105
1.55k
      Base.Reg = 0;
106
1.55k
    }
107
  };
108
109
class ARMFastISel final : public FastISel {
110
  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
111
  /// make the right decision when generating code for different targets.
112
  const ARMSubtarget *Subtarget;
113
  Module &M;
114
  const TargetMachine &TM;
115
  const TargetInstrInfo &TII;
116
  const TargetLowering &TLI;
117
  ARMFunctionInfo *AFI;
118
119
  // Convenience variables to avoid some queries.
120
  bool isThumb2;
121
  LLVMContext *Context;
122
123
  public:
124
    explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
125
                         const TargetLibraryInfo *libInfo)
126
        : FastISel(funcInfo, libInfo),
127
          Subtarget(
128
              &static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget())),
129
          M(const_cast<Module &>(*funcInfo.Fn->getParent())),
130
          TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
131
907
          TLI(*Subtarget->getTargetLowering()) {
132
907
      AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
133
907
      isThumb2 = AFI->isThumbFunction();
134
907
      Context = &funcInfo.Fn->getContext();
135
907
    }
136
137
  private:
138
    // Code from FastISel.cpp.
139
140
    unsigned fastEmitInst_r(unsigned MachineInstOpcode,
141
                            const TargetRegisterClass *RC,
142
                            unsigned Op0, bool Op0IsKill);
143
    unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
144
                             const TargetRegisterClass *RC,
145
                             unsigned Op0, bool Op0IsKill,
146
                             unsigned Op1, bool Op1IsKill);
147
    unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
148
                             const TargetRegisterClass *RC,
149
                             unsigned Op0, bool Op0IsKill,
150
                             uint64_t Imm);
151
    unsigned fastEmitInst_i(unsigned MachineInstOpcode,
152
                            const TargetRegisterClass *RC,
153
                            uint64_t Imm);
154
155
    // Backend specific FastISel code.
156
157
    bool fastSelectInstruction(const Instruction *I) override;
158
    unsigned fastMaterializeConstant(const Constant *C) override;
159
    unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
160
    bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
161
                             const LoadInst *LI) override;
162
    bool fastLowerArguments() override;
163
164
  #include "ARMGenFastISel.inc"
165
166
    // Instruction selection routines.
167
168
    bool SelectLoad(const Instruction *I);
169
    bool SelectStore(const Instruction *I);
170
    bool SelectBranch(const Instruction *I);
171
    bool SelectIndirectBr(const Instruction *I);
172
    bool SelectCmp(const Instruction *I);
173
    bool SelectFPExt(const Instruction *I);
174
    bool SelectFPTrunc(const Instruction *I);
175
    bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
176
    bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
177
    bool SelectIToFP(const Instruction *I, bool isSigned);
178
    bool SelectFPToI(const Instruction *I, bool isSigned);
179
    bool SelectDiv(const Instruction *I, bool isSigned);
180
    bool SelectRem(const Instruction *I, bool isSigned);
181
    bool SelectCall(const Instruction *I, const char *IntrMemName);
182
    bool SelectIntrinsicCall(const IntrinsicInst &I);
183
    bool SelectSelect(const Instruction *I);
184
    bool SelectRet(const Instruction *I);
185
    bool SelectTrunc(const Instruction *I);
186
    bool SelectIntExt(const Instruction *I);
187
    bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
188
189
    // Utility routines.
190
191
    bool isPositionIndependent() const;
192
    bool isTypeLegal(Type *Ty, MVT &VT);
193
    bool isLoadTypeLegal(Type *Ty, MVT &VT);
194
    bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
195
                    bool isZExt, bool isEquality);
196
    bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
197
                     unsigned Alignment = 0, bool isZExt = true,
198
                     bool allocReg = true);
199
    bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
200
                      unsigned Alignment = 0);
201
    bool ARMComputeAddress(const Value *Obj, Address &Addr);
202
    void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
203
    bool ARMIsMemCpySmall(uint64_t Len);
204
    bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
205
                               unsigned Alignment);
206
    unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
207
    unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
208
    unsigned ARMMaterializeInt(const Constant *C, MVT VT);
209
    unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
210
    unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
211
    unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
212
    unsigned ARMSelectCallOp(bool UseReg);
213
    unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
214
215
0
    const TargetLowering *getTargetLowering() { return &TLI; }
216
217
    // Call handling routines.
218
219
    CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
220
                                  bool Return,
221
                                  bool isVarArg);
222
    bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
223
                         SmallVectorImpl<unsigned> &ArgRegs,
224
                         SmallVectorImpl<MVT> &ArgVTs,
225
                         SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
226
                         SmallVectorImpl<unsigned> &RegArgs,
227
                         CallingConv::ID CC,
228
                         unsigned &NumBytes,
229
                         bool isVarArg);
230
    unsigned getLibcallReg(const Twine &Name);
231
    bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
232
                    const Instruction *I, CallingConv::ID CC,
233
                    unsigned &NumBytes, bool isVarArg);
234
    bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
235
236
    // OptionalDef handling routines.
237
238
    bool isARMNEONPred(const MachineInstr *MI);
239
    bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
240
    const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
241
    void AddLoadStoreOperands(MVT VT, Address &Addr,
242
                              const MachineInstrBuilder &MIB,
243
                              MachineMemOperand::Flags Flags, bool useAM3);
244
};
245
246
} // end anonymous namespace
247
248
#include "ARMGenCallingConv.inc"
249
250
// DefinesOptionalPredicate - This is different from DefinesPredicate in that
251
// we don't care about implicit defs here, just places we'll need to add a
252
// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
253
5.94k
bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
254
5.94k
  if (!MI->hasOptionalDef())
255
5.09k
    return false;
256
848
257
848
  // Look to see if our OptionalDef is defining CPSR or CCR.
258
848
  
for (const MachineOperand &MO : MI->operands()) 848
{
259
4.05k
    if (
!MO.isReg() || 4.05k
!MO.isDef()2.30k
)
continue3.20k
;
260
848
    
if (848
MO.getReg() == ARM::CPSR848
)
261
0
      *CPSR = true;
262
4.05k
  }
263
5.94k
  return true;
264
5.94k
}
265
266
5.94k
bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
267
5.94k
  const MCInstrDesc &MCID = MI->getDesc();
268
5.94k
269
5.94k
  // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
270
5.94k
  if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
271
2
       AFI->isThumb2Function())
272
5.94k
    return MI->isPredicable();
273
2
274
2
  for (const MCOperandInfo &opInfo : MCID.operands())
275
6
    
if (6
opInfo.isPredicate()6
)
276
2
      return true;
277
0
278
0
  return false;
279
0
}
280
281
// If the machine is predicable go ahead and add the predicate operands, if
282
// it needs default CC operands add those.
283
// TODO: If we want to support thumb1 then we'll need to deal with optional
284
// CPSR defs that need to be added before the remaining operands. See s_cc_out
285
// for descriptions why.
286
const MachineInstrBuilder &
287
5.94k
ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
288
5.94k
  MachineInstr *MI = &*MIB;
289
5.94k
290
5.94k
  // Do we use a predicate? or...
291
5.94k
  // Are we NEON in ARM mode and have a predicate operand? If so, I know
292
5.94k
  // we're not predicable but add it anyways.
293
5.94k
  if (isARMNEONPred(MI))
294
5.67k
    MIB.add(predOps(ARMCC::AL));
295
5.94k
296
5.94k
  // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
297
5.94k
  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
298
5.94k
  bool CPSR = false;
299
5.94k
  if (DefinesOptionalPredicate(MI, &CPSR))
300
848
    
MIB.add(CPSR ? 848
t1CondCodeOp()0
:
condCodeOp()848
);
301
5.94k
  return MIB;
302
5.94k
}
303
304
unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
305
                                     const TargetRegisterClass *RC,
306
83
                                     unsigned Op0, bool Op0IsKill) {
307
83
  unsigned ResultReg = createResultReg(RC);
308
83
  const MCInstrDesc &II = TII.get(MachineInstOpcode);
309
83
310
83
  // Make sure the input operand is sufficiently constrained to be legal
311
83
  // for this instruction.
312
83
  Op0 = constrainOperandRegClass(II, Op0, 1);
313
83
  if (
II.getNumDefs() >= 183
) {
314
83
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
315
83
                            ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
316
83
  } else {
317
0
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
318
0
                   .addReg(Op0, Op0IsKill * RegState::Kill));
319
0
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
320
0
                   TII.get(TargetOpcode::COPY), ResultReg)
321
0
                   .addReg(II.ImplicitDefs[0]));
322
0
  }
323
83
  return ResultReg;
324
83
}
325
326
unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
327
                                      const TargetRegisterClass *RC,
328
                                      unsigned Op0, bool Op0IsKill,
329
150
                                      unsigned Op1, bool Op1IsKill) {
330
150
  unsigned ResultReg = createResultReg(RC);
331
150
  const MCInstrDesc &II = TII.get(MachineInstOpcode);
332
150
333
150
  // Make sure the input operands are sufficiently constrained to be legal
334
150
  // for this instruction.
335
150
  Op0 = constrainOperandRegClass(II, Op0, 1);
336
150
  Op1 = constrainOperandRegClass(II, Op1, 2);
337
150
338
150
  if (
II.getNumDefs() >= 1150
) {
339
150
    AddOptionalDefs(
340
150
        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
341
150
            .addReg(Op0, Op0IsKill * RegState::Kill)
342
150
            .addReg(Op1, Op1IsKill * RegState::Kill));
343
150
  } else {
344
0
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
345
0
                   .addReg(Op0, Op0IsKill * RegState::Kill)
346
0
                   .addReg(Op1, Op1IsKill * RegState::Kill));
347
0
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
348
0
                           TII.get(TargetOpcode::COPY), ResultReg)
349
0
                   .addReg(II.ImplicitDefs[0]));
350
0
  }
351
150
  return ResultReg;
352
150
}
353
354
unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
355
                                      const TargetRegisterClass *RC,
356
                                      unsigned Op0, bool Op0IsKill,
357
465
                                      uint64_t Imm) {
358
465
  unsigned ResultReg = createResultReg(RC);
359
465
  const MCInstrDesc &II = TII.get(MachineInstOpcode);
360
465
361
465
  // Make sure the input operand is sufficiently constrained to be legal
362
465
  // for this instruction.
363
465
  Op0 = constrainOperandRegClass(II, Op0, 1);
364
465
  if (
II.getNumDefs() >= 1465
) {
365
465
    AddOptionalDefs(
366
465
        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
367
465
            .addReg(Op0, Op0IsKill * RegState::Kill)
368
465
            .addImm(Imm));
369
465
  } else {
370
0
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
371
0
                   .addReg(Op0, Op0IsKill * RegState::Kill)
372
0
                   .addImm(Imm));
373
0
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
374
0
                           TII.get(TargetOpcode::COPY), ResultReg)
375
0
                   .addReg(II.ImplicitDefs[0]));
376
0
  }
377
465
  return ResultReg;
378
465
}
379
380
unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
381
                                     const TargetRegisterClass *RC,
382
15
                                     uint64_t Imm) {
383
15
  unsigned ResultReg = createResultReg(RC);
384
15
  const MCInstrDesc &II = TII.get(MachineInstOpcode);
385
15
386
15
  if (
II.getNumDefs() >= 115
) {
387
15
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
388
15
                            ResultReg).addImm(Imm));
389
15
  } else {
390
0
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
391
0
                   .addImm(Imm));
392
0
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
393
0
                           TII.get(TargetOpcode::COPY), ResultReg)
394
0
                   .addReg(II.ImplicitDefs[0]));
395
0
  }
396
15
  return ResultReg;
397
15
}
398
399
// TODO: Don't worry about 64-bit now, but when this is fixed remove the
400
// checks from the various callers.
401
37
unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
402
37
  if (
VT == MVT::f6437
)
return 00
;
403
37
404
37
  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
405
37
  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
406
37
                          TII.get(ARM::VMOVSR), MoveReg)
407
37
                  .addReg(SrcReg));
408
37
  return MoveReg;
409
37
}
410
411
12
unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
412
12
  if (
VT == MVT::i6412
)
return 00
;
413
12
414
12
  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
415
12
  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
416
12
                          TII.get(ARM::VMOVRS), MoveReg)
417
12
                  .addReg(SrcReg));
418
12
  return MoveReg;
419
12
}
420
421
// For double width floating point we need to materialize two constants
422
// (the high and the low) into integer registers then use a move to get
423
// the combined constant into an FP reg.
424
309
unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
425
309
  const APFloat Val = CFP->getValueAPF();
426
309
  bool is64bit = VT == MVT::f64;
427
309
428
309
  // This checks to see if we can use VFP3 instructions to materialize
429
309
  // a constant, otherwise we have to go through the constant pool.
430
309
  if (
TLI.isFPImmLegal(Val, VT)309
) {
431
47
    int Imm;
432
47
    unsigned Opc;
433
47
    if (
is64bit47
) {
434
1
      Imm = ARM_AM::getFP64Imm(Val);
435
1
      Opc = ARM::FCONSTD;
436
47
    } else {
437
46
      Imm = ARM_AM::getFP32Imm(Val);
438
46
      Opc = ARM::FCONSTS;
439
46
    }
440
47
    unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
441
47
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
442
47
                            TII.get(Opc), DestReg).addImm(Imm));
443
47
    return DestReg;
444
47
  }
445
262
446
262
  // Require VFP2 for loading fp constants.
447
262
  
if (262
!Subtarget->hasVFP2()262
)
return false0
;
448
262
449
262
  // MachineConstantPool wants an explicit alignment.
450
262
  unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
451
262
  if (
Align == 0262
) {
452
0
    // TODO: Figure out if this is correct.
453
0
    Align = DL.getTypeAllocSize(CFP->getType());
454
0
  }
455
262
  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
456
262
  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
457
262
  unsigned Opc = is64bit ? 
ARM::VLDRD149
:
ARM::VLDRS113
;
458
309
459
309
  // The extra reg is for addrmode5.
460
309
  AddOptionalDefs(
461
309
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
462
309
          .addConstantPoolIndex(Idx)
463
309
          .addReg(0));
464
309
  return DestReg;
465
309
}
466
467
531
unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
468
531
  if (
VT != MVT::i32 && 531
VT != MVT::i16122
&&
VT != MVT::i896
&&
VT != MVT::i116
)
469
0
    return 0;
470
531
471
531
  // If we can do this in a single instruction without a constant pool entry
472
531
  // do so now.
473
531
  const ConstantInt *CI = cast<ConstantInt>(C);
474
531
  if (
Subtarget->hasV6T2Ops() && 531
isUInt<16>(CI->getZExtValue())525
) {
475
316
    unsigned Opc = isThumb2 ? 
ARM::t2MOVi16125
:
ARM::MOVi16191
;
476
125
    const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
477
191
      &ARM::GPRRegClass;
478
316
    unsigned ImmReg = createResultReg(RC);
479
316
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
480
316
                            TII.get(Opc), ImmReg)
481
316
                    .addImm(CI->getZExtValue()));
482
316
    return ImmReg;
483
316
  }
484
215
485
215
  // Use MVN to emit negative constants.
486
215
  
if (215
VT == MVT::i32 && 215
Subtarget->hasV6T2Ops()215
&&
CI->isNegative()209
) {
487
207
    unsigned Imm = (unsigned)~(CI->getSExtValue());
488
96
    bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
489
111
      (ARM_AM::getSOImmVal(Imm) != -1);
490
207
    if (
UseImm207
) {
491
192
      unsigned Opc = isThumb2 ? 
ARM::t2MVNi87
:
ARM::MVNi105
;
492
87
      const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
493
105
                                                 &ARM::GPRRegClass;
494
192
      unsigned ImmReg = createResultReg(RC);
495
192
      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
496
192
                              TII.get(Opc), ImmReg)
497
192
                      .addImm(Imm));
498
192
      return ImmReg;
499
192
    }
500
23
  }
501
23
502
23
  unsigned ResultReg = 0;
503
23
  if (Subtarget->useMovt(*FuncInfo.MF))
504
6
    ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
505
23
506
23
  if (ResultReg)
507
4
    return ResultReg;
508
19
509
19
  // Load from constant pool.  For now 32-bit only.
510
19
  
if (19
VT != MVT::i3219
)
511
0
    return 0;
512
19
513
19
  // MachineConstantPool wants an explicit alignment.
514
19
  unsigned Align = DL.getPrefTypeAlignment(C->getType());
515
19
  if (
Align == 019
) {
516
0
    // TODO: Figure out if this is correct.
517
0
    Align = DL.getTypeAllocSize(C->getType());
518
0
  }
519
19
  unsigned Idx = MCP.getConstantPoolIndex(C, Align);
520
19
  ResultReg = createResultReg(TLI.getRegClassFor(VT));
521
19
  if (isThumb2)
522
7
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
523
7
                            TII.get(ARM::t2LDRpci), ResultReg)
524
7
                      .addConstantPoolIndex(Idx));
525
12
  else {
526
12
    // The extra immediate is for addrmode2.
527
12
    ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
528
12
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
529
12
                            TII.get(ARM::LDRcp), ResultReg)
530
12
                      .addConstantPoolIndex(Idx)
531
12
                      .addImm(0));
532
12
  }
533
531
  return ResultReg;
534
531
}
535
536
257
bool ARMFastISel::isPositionIndependent() const {
537
257
  return TLI.isPositionIndependent();
538
257
}
539
540
268
unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
541
268
  // For now 32-bit only.
542
268
  if (
VT != MVT::i32 || 268
GV->isThreadLocal()268
)
return 011
;
543
257
544
257
  // ROPI/RWPI not currently supported.
545
257
  
if (257
Subtarget->isROPI() || 257
Subtarget->isRWPI()257
)
546
0
    return 0;
547
257
548
257
  bool IsIndirect = Subtarget->isGVIndirectSymbol(GV);
549
123
  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
550
134
                                           : &ARM::GPRRegClass;
551
257
  unsigned DestReg = createResultReg(RC);
552
257
553
257
  // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
554
257
  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
555
189
  bool IsThreadLocal = GVar && GVar->isThreadLocal();
556
257
  if (
!Subtarget->isTargetMachO() && 257
IsThreadLocal71
)
return 00
;
557
257
558
257
  bool IsPositionIndependent = isPositionIndependent();
559
257
  // Use movw+movt when possible, it avoids constant pool entries.
560
257
  // Non-darwin targets only support static movt relocations in FastISel.
561
257
  if (Subtarget->useMovt(*FuncInfo.MF) &&
562
257
      
(Subtarget->isTargetMachO() || 251
!IsPositionIndependent71
)) {
563
246
    unsigned Opc;
564
246
    unsigned char TF = 0;
565
246
    if (Subtarget->isTargetMachO())
566
180
      TF = ARMII::MO_NONLAZY;
567
246
568
246
    if (IsPositionIndependent)
569
65
      
Opc = isThumb2 ? 65
ARM::t2MOV_ga_pcrel63
:
ARM::MOV_ga_pcrel2
;
570
246
    else
571
181
      
Opc = isThumb2 ? 181
ARM::t2MOVi32imm55
:
ARM::MOVi32imm126
;
572
246
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
573
246
                            TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
574
257
  } else {
575
11
    // MachineConstantPool wants an explicit alignment.
576
11
    unsigned Align = DL.getPrefTypeAlignment(GV->getType());
577
11
    if (
Align == 011
) {
578
0
      // TODO: Figure out if this is correct.
579
0
      Align = DL.getTypeAllocSize(GV->getType());
580
0
    }
581
11
582
11
    if (
Subtarget->isTargetELF() && 11
IsPositionIndependent5
)
583
5
      return ARMLowerPICELF(GV, Align, VT);
584
6
585
6
    // Grab index.
586
6
    
unsigned PCAdj = IsPositionIndependent ? 6
(Subtarget->isThumb() ? 6
43
:
83
) :
00
;
587
6
    unsigned Id = AFI->createPICLabelUId();
588
6
    ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
589
6
                                                                ARMCP::CPValue,
590
6
                                                                PCAdj);
591
6
    unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
592
6
593
6
    // Load value.
594
6
    MachineInstrBuilder MIB;
595
6
    if (
isThumb26
) {
596
3
      unsigned Opc = IsPositionIndependent ? 
ARM::t2LDRpci_pic3
:
ARM::t2LDRpci0
;
597
3
      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
598
3
                    DestReg).addConstantPoolIndex(Idx);
599
3
      if (IsPositionIndependent)
600
3
        MIB.addImm(Id);
601
3
      AddOptionalDefs(MIB);
602
6
    } else {
603
3
      // The extra immediate is for addrmode2.
604
3
      DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
605
3
      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
606
3
                    TII.get(ARM::LDRcp), DestReg)
607
3
                .addConstantPoolIndex(Idx)
608
3
                .addImm(0);
609
3
      AddOptionalDefs(MIB);
610
3
611
3
      if (
IsPositionIndependent3
) {
612
3
        unsigned Opc = IsIndirect ? 
ARM::PICLDR1
:
ARM::PICADD2
;
613
3
        unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
614
3
615
3
        MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
616
3
                                          DbgLoc, TII.get(Opc), NewDestReg)
617
3
                                  .addReg(DestReg)
618
3
                                  .addImm(Id);
619
3
        AddOptionalDefs(MIB);
620
3
        return NewDestReg;
621
3
      }
622
249
    }
623
11
  }
624
249
625
249
  
if (249
IsIndirect249
) {
626
86
    MachineInstrBuilder MIB;
627
86
    unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
628
86
    if (isThumb2)
629
51
      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
630
51
                    TII.get(ARM::t2LDRi12), NewDestReg)
631
51
            .addReg(DestReg)
632
51
            .addImm(0);
633
86
    else
634
35
      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
635
35
                    TII.get(ARM::LDRi12), NewDestReg)
636
35
                .addReg(DestReg)
637
35
                .addImm(0);
638
86
    DestReg = NewDestReg;
639
86
    AddOptionalDefs(MIB);
640
86
  }
641
268
642
268
  return DestReg;
643
268
}
644
645
1.21k
unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) {
646
1.21k
  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
647
1.21k
648
1.21k
  // Only handle simple types.
649
1.21k
  if (
!CEVT.isSimple()1.21k
)
return 00
;
650
1.21k
  MVT VT = CEVT.getSimpleVT();
651
1.21k
652
1.21k
  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
653
309
    return ARMMaterializeFP(CFP, VT);
654
905
  else 
if (const GlobalValue *905
GV905
= dyn_cast<GlobalValue>(C))
655
256
    return ARMMaterializeGV(GV, VT);
656
649
  else 
if (649
isa<ConstantInt>(C)649
)
657
531
    return ARMMaterializeInt(C, VT);
658
118
659
118
  return 0;
660
118
}
661
662
// TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
663
664
206
unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
665
206
  // Don't handle dynamic allocas.
666
206
  if (
!FuncInfo.StaticAllocaMap.count(AI)206
)
return 00
;
667
206
668
206
  MVT VT;
669
206
  if (
!isLoadTypeLegal(AI->getType(), VT)206
)
return 00
;
670
206
671
206
  DenseMap<const AllocaInst*, int>::iterator SI =
672
206
    FuncInfo.StaticAllocaMap.find(AI);
673
206
674
206
  // This will get lowered later into the correct offsets and registers
675
206
  // via rewriteXFrameIndex.
676
206
  if (
SI != FuncInfo.StaticAllocaMap.end()206
) {
677
206
    unsigned Opc = isThumb2 ? 
ARM::t2ADDri102
:
ARM::ADDri104
;
678
206
    const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
679
206
    unsigned ResultReg = createResultReg(RC);
680
206
    ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
681
206
682
206
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
683
206
                            TII.get(Opc), ResultReg)
684
206
                            .addFrameIndex(SI->second)
685
206
                            .addImm(0));
686
206
    return ResultReg;
687
206
  }
688
0
689
0
  return 0;
690
0
}
691
692
3.04k
bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
693
3.04k
  EVT evt = TLI.getValueType(DL, Ty, true);
694
3.04k
695
3.04k
  // Only handle simple types.
696
3.04k
  if (
evt == MVT::Other || 3.04k
!evt.isSimple()3.03k
)
return false11
;
697
3.03k
  VT = evt.getSimpleVT();
698
3.03k
699
3.03k
  // Handle all legal types, i.e. a register that will directly hold this
700
3.03k
  // value.
701
3.03k
  return TLI.isTypeLegal(VT);
702
3.03k
}
703
704
1.32k
bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
705
1.32k
  if (
isTypeLegal(Ty, VT)1.32k
)
return true1.14k
;
706
175
707
175
  // If this is a type than can be sign or zero-extended to a basic operation
708
175
  // go ahead and accept it now.
709
175
  
if (175
VT == MVT::i1 || 175
VT == MVT::i8158
||
VT == MVT::i1697
)
710
167
    return true;
711
8
712
8
  return false;
713
8
}
714
715
// Computes the address to get to an object.
716
1.56k
bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
717
1.56k
  // Some boilerplate from the X86 FastISel.
718
1.56k
  const User *U = nullptr;
719
1.56k
  unsigned Opcode = Instruction::UserOp1;
720
1.56k
  if (const Instruction *
I1.56k
= dyn_cast<Instruction>(Obj)) {
721
1.12k
    // Don't walk into other basic blocks unless the object is an alloca from
722
1.12k
    // another block, otherwise it may not have a virtual register assigned.
723
1.12k
    if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
724
1.12k
        
FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB557
) {
725
1.06k
      Opcode = I->getOpcode();
726
1.06k
      U = I;
727
1.06k
    }
728
1.56k
  } else 
if (const ConstantExpr *437
C437
= dyn_cast<ConstantExpr>(Obj)) {
729
106
    Opcode = C->getOpcode();
730
106
    U = C;
731
106
  }
732
1.56k
733
1.56k
  if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
734
1.55k
    
if (1.55k
Ty->getAddressSpace() > 2551.55k
)
735
1.55k
      // Fast instruction selection doesn't support the special
736
1.55k
      // address spaces.
737
0
      return false;
738
1.56k
739
1.56k
  switch (Opcode) {
740
427
    default:
741
427
    break;
742
22
    case Instruction::BitCast:
743
22
      // Look through bitcasts.
744
22
      return ARMComputeAddress(U->getOperand(0), Addr);
745
3
    case Instruction::IntToPtr:
746
3
      // Look past no-op inttoptrs.
747
3
      if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
748
3
          TLI.getPointerTy(DL))
749
3
        return ARMComputeAddress(U->getOperand(0), Addr);
750
0
      break;
751
0
    case Instruction::PtrToInt:
752
0
      // Look past no-op ptrtoints.
753
0
      if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
754
0
        return ARMComputeAddress(U->getOperand(0), Addr);
755
0
      break;
756
542
    case Instruction::GetElementPtr: {
757
542
      Address SavedAddr = Addr;
758
542
      int TmpOffset = Addr.Offset;
759
542
760
542
      // Iterate through the GEP folding the constants into offsets where
761
542
      // we can.
762
542
      gep_type_iterator GTI = gep_type_begin(U);
763
542
      for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
764
1.57k
           
i != e1.57k
;
++i, ++GTI1.02k
) {
765
1.03k
        const Value *Op = *i;
766
1.03k
        if (StructType *
STy1.03k
= GTI.getStructTypeOrNull()) {
767
305
          const StructLayout *SL = DL.getStructLayout(STy);
768
305
          unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
769
305
          TmpOffset += SL->getElementOffset(Idx);
770
1.03k
        } else {
771
733
          uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
772
733
          while (
true733
) {
773
733
            if (const ConstantInt *
CI733
= dyn_cast<ConstantInt>(Op)) {
774
723
              // Constant-offset addressing.
775
723
              TmpOffset += CI->getSExtValue() * S;
776
723
              break;
777
723
            }
778
10
            
if (10
canFoldAddIntoGEP(U, Op)10
) {
779
0
              // A compatible add with a constant operand. Fold the constant.
780
0
              ConstantInt *CI =
781
0
              cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
782
0
              TmpOffset += CI->getSExtValue() * S;
783
0
              // Iterate on the other operand.
784
0
              Op = cast<AddOperator>(Op)->getOperand(0);
785
0
              continue;
786
0
            }
787
10
            // Unsupported
788
10
            goto unsupported_gep;
789
10
          }
790
733
        }
791
1.03k
      }
792
542
793
542
      // Try to grab the base operand now.
794
532
      Addr.Offset = TmpOffset;
795
532
      if (
ARMComputeAddress(U->getOperand(0), Addr)532
)
return true530
;
796
2
797
2
      // We failed, restore everything and try the other options.
798
2
      Addr = SavedAddr;
799
2
800
12
      unsupported_gep:
801
12
      break;
802
2
    }
803
568
    case Instruction::Alloca: {
804
568
      const AllocaInst *AI = cast<AllocaInst>(Obj);
805
568
      DenseMap<const AllocaInst*, int>::iterator SI =
806
568
        FuncInfo.StaticAllocaMap.find(AI);
807
568
      if (
SI != FuncInfo.StaticAllocaMap.end()568
) {
808
568
        Addr.BaseType = Address::FrameIndexBase;
809
568
        Addr.Base.FI = SI->second;
810
568
        return true;
811
568
      }
812
0
      break;
813
0
    }
814
439
  }
815
439
816
439
  // Try to get this in a register if nothing else has worked.
817
439
  
if (439
Addr.Base.Reg == 0439
)
Addr.Base.Reg = getRegForValue(Obj)439
;
818
1.56k
  return Addr.Base.Reg != 0;
819
1.56k
}
820
821
1.72k
void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
822
1.72k
  bool needsLowering = false;
823
1.72k
  switch (VT.SimpleTy) {
824
0
    
default: 0
llvm_unreachable0
("Unhandled load/store type!");
825
1.15k
    case MVT::i1:
826
1.15k
    case MVT::i8:
827
1.15k
    case MVT::i16:
828
1.15k
    case MVT::i32:
829
1.15k
      if (
!useAM31.15k
) {
830
1.03k
        // Integer loads/stores handle 12-bit offsets.
831
1.03k
        needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
832
1.03k
        // Handle negative offsets.
833
1.03k
        if (
needsLowering && 1.03k
isThumb219
)
834
19
          
needsLowering = !(Subtarget->hasV6T2Ops() && 19
Addr.Offset < 019
&&
835
19
                            Addr.Offset > -256);
836
1.15k
      } else {
837
116
        // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
838
112
        needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
839
116
      }
840
1.15k
      break;
841
572
    case MVT::f32:
842
572
    case MVT::f64:
843
572
      // Floating point operands handle 8-bit offsets.
844
572
      needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
845
572
      break;
846
1.72k
  }
847
1.72k
848
1.72k
  // If this is a stack pointer and the offset needs to be simplified then
849
1.72k
  // put the alloca address into a register, set the base type back to
850
1.72k
  // register and continue. This should almost never happen.
851
1.72k
  
if (1.72k
needsLowering && 1.72k
Addr.BaseType == Address::FrameIndexBase404
) {
852
0
    const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
853
0
                                             : &ARM::GPRRegClass;
854
0
    unsigned ResultReg = createResultReg(RC);
855
0
    unsigned Opc = isThumb2 ? 
ARM::t2ADDri0
:
ARM::ADDri0
;
856
0
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
857
0
                            TII.get(Opc), ResultReg)
858
0
                            .addFrameIndex(Addr.Base.FI)
859
0
                            .addImm(0));
860
0
    Addr.Base.Reg = ResultReg;
861
0
    Addr.BaseType = Address::RegBase;
862
0
  }
863
1.72k
864
1.72k
  // Since the offset is too large for the load/store instruction
865
1.72k
  // get the reg+offset into a register.
866
1.72k
  if (
needsLowering1.72k
) {
867
404
    Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
868
404
                                 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
869
404
    Addr.Offset = 0;
870
404
  }
871
1.72k
}
872
873
void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
874
                                       const MachineInstrBuilder &MIB,
875
                                       MachineMemOperand::Flags Flags,
876
1.72k
                                       bool useAM3) {
877
1.72k
  // addrmode5 output depends on the selection dag addressing dividing the
878
1.72k
  // offset by 4 that it then later multiplies. Do this here as well.
879
1.72k
  if (
VT.SimpleTy == MVT::f32 || 1.72k
VT.SimpleTy == MVT::f641.60k
)
880
572
    Addr.Offset /= 4;
881
1.72k
882
1.72k
  // Frame base works a bit differently. Handle it separately.
883
1.72k
  if (
Addr.BaseType == Address::FrameIndexBase1.72k
) {
884
571
    int FI = Addr.Base.FI;
885
571
    int Offset = Addr.Offset;
886
571
    MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
887
571
        MachinePointerInfo::getFixedStack(*FuncInfo.MF, FI, Offset), Flags,
888
571
        MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
889
571
    // Now add the rest of the operands.
890
571
    MIB.addFrameIndex(FI);
891
571
892
571
    // ARM halfword load/stores and signed byte loads need an additional
893
571
    // operand.
894
571
    if (
useAM3571
) {
895
6
      int Imm = (Addr.Offset < 0) ? 
(0x100 | -Addr.Offset)0
:
Addr.Offset6
;
896
6
      MIB.addReg(0);
897
6
      MIB.addImm(Imm);
898
571
    } else {
899
565
      MIB.addImm(Addr.Offset);
900
565
    }
901
571
    MIB.addMemOperand(MMO);
902
1.72k
  } else {
903
1.15k
    // Now add the rest of the operands.
904
1.15k
    MIB.addReg(Addr.Base.Reg);
905
1.15k
906
1.15k
    // ARM halfword load/stores and signed byte loads need an additional
907
1.15k
    // operand.
908
1.15k
    if (
useAM31.15k
) {
909
110
      int Imm = (Addr.Offset < 0) ? 
(0x100 | -Addr.Offset)12
:
Addr.Offset98
;
910
110
      MIB.addReg(0);
911
110
      MIB.addImm(Imm);
912
1.15k
    } else {
913
1.04k
      MIB.addImm(Addr.Offset);
914
1.04k
    }
915
1.15k
  }
916
1.72k
  AddOptionalDefs(MIB);
917
1.72k
}
918
919
bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
920
489
                              unsigned Alignment, bool isZExt, bool allocReg) {
921
489
  unsigned Opc;
922
489
  bool useAM3 = false;
923
489
  bool needVMOV = false;
924
489
  const TargetRegisterClass *RC;
925
489
  switch (VT.SimpleTy) {
926
489
    // This is mostly going to be Neon/vector support.
927
4
    default: return false;
928
96
    case MVT::i1:
929
96
    case MVT::i8:
930
96
      if (
isThumb296
) {
931
31
        if (
Addr.Offset < 0 && 31
Addr.Offset > -2563
&&
Subtarget->hasV6T2Ops()2
)
932
2
          
Opc = isZExt ? 2
ARM::t2LDRBi82
:
ARM::t2LDRSBi80
;
933
31
        else
934
29
          
Opc = isZExt ? 29
ARM::t2LDRBi1228
:
ARM::t2LDRSBi121
;
935
96
      } else {
936
65
        if (
isZExt65
) {
937
57
          Opc = ARM::LDRBi12;
938
65
        } else {
939
8
          Opc = ARM::LDRSB;
940
8
          useAM3 = true;
941
8
        }
942
65
      }
943
96
      RC = isThumb2 ? 
&ARM::rGPRRegClass31
:
&ARM::GPRnopcRegClass65
;
944
96
      break;
945
85
    case MVT::i16:
946
85
      if (
Alignment && 85
Alignment < 240
&&
!Subtarget->allowsUnalignedMem()8
)
947
4
        return false;
948
81
949
81
      
if (81
isThumb281
) {
950
24
        if (
Addr.Offset < 0 && 24
Addr.Offset > -2563
&&
Subtarget->hasV6T2Ops()2
)
951
2
          
Opc = isZExt ? 2
ARM::t2LDRHi82
:
ARM::t2LDRSHi80
;
952
24
        else
953
22
          
Opc = isZExt ? 22
ARM::t2LDRHi1221
:
ARM::t2LDRSHi121
;
954
81
      } else {
955
57
        Opc = isZExt ? 
ARM::LDRH55
:
ARM::LDRSH2
;
956
57
        useAM3 = true;
957
57
      }
958
81
      RC = isThumb2 ? 
&ARM::rGPRRegClass24
:
&ARM::GPRnopcRegClass57
;
959
81
      break;
960
284
    case MVT::i32:
961
284
      if (
Alignment && 284
Alignment < 4147
&&
!Subtarget->allowsUnalignedMem()8
)
962
4
        return false;
963
280
964
280
      
if (280
isThumb2280
) {
965
141
        if (
Addr.Offset < 0 && 141
Addr.Offset > -2563
&&
Subtarget->hasV6T2Ops()2
)
966
2
          Opc = ARM::t2LDRi8;
967
141
        else
968
139
          Opc = ARM::t2LDRi12;
969
280
      } else {
970
139
        Opc = ARM::LDRi12;
971
139
      }
972
280
      RC = isThumb2 ? 
&ARM::rGPRRegClass141
:
&ARM::GPRnopcRegClass139
;
973
280
      break;
974
18
    case MVT::f32:
975
18
      if (
!Subtarget->hasVFP2()18
)
return false0
;
976
18
      // Unaligned loads need special handling. Floats require word-alignment.
977
18
      
if (18
Alignment && 18
Alignment < 410
) {
978
8
        needVMOV = true;
979
8
        VT = MVT::i32;
980
8
        Opc = isThumb2 ? 
ARM::t2LDRi122
:
ARM::LDRi126
;
981
8
        RC = isThumb2 ? 
&ARM::rGPRRegClass2
:
&ARM::GPRnopcRegClass6
;
982
18
      } else {
983
10
        Opc = ARM::VLDRS;
984
10
        RC = TLI.getRegClassFor(VT);
985
10
      }
986
18
      break;
987
2
    case MVT::f64:
988
2
      if (
!Subtarget->hasVFP2()2
)
return false0
;
989
2
      // FIXME: Unaligned loads need special handling.  Doublewords require
990
2
      // word-alignment.
991
2
      
if (2
Alignment && 2
Alignment < 41
)
992
0
        return false;
993
2
994
2
      Opc = ARM::VLDRD;
995
2
      RC = TLI.getRegClassFor(VT);
996
2
      break;
997
477
  }
998
477
  // Simplify this down to something we can handle.
999
477
  ARMSimplifyAddress(Addr, VT, useAM3);
1000
477
1001
477
  // Create the base instruction, then add the operands.
1002
477
  if (allocReg)
1003
426
    ResultReg = createResultReg(RC);
1004
477
  assert(ResultReg > 255 && "Expected an allocated virtual register.");
1005
477
  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1006
477
                                    TII.get(Opc), ResultReg);
1007
477
  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1008
477
1009
477
  // If we had an unaligned load of a float we've converted it to an regular
1010
477
  // load.  Now we must move from the GRP to the FP register.
1011
477
  if (
needVMOV477
) {
1012
8
    unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1013
8
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1014
8
                            TII.get(ARM::VMOVSR), MoveReg)
1015
8
                    .addReg(ResultReg));
1016
8
    ResultReg = MoveReg;
1017
8
  }
1018
489
  return true;
1019
489
}
1020
1021
322
bool ARMFastISel::SelectLoad(const Instruction *I) {
1022
322
  // Atomic loads need special handling.
1023
322
  if (cast<LoadInst>(I)->isAtomic())
1024
1
    return false;
1025
321
1026
321
  const Value *SV = I->getOperand(0);
1027
321
  if (
TLI.supportSwiftError()321
) {
1028
321
    // Swifterror values can come from either a function parameter with
1029
321
    // swifterror attribute or an alloca with swifterror attribute.
1030
321
    if (const Argument *
Arg321
= dyn_cast<Argument>(SV)) {
1031
28
      if (Arg->hasSwiftErrorAttr())
1032
0
        return false;
1033
321
    }
1034
321
1035
321
    
if (const AllocaInst *321
Alloca321
= dyn_cast<AllocaInst>(SV)) {
1036
126
      if (Alloca->isSwiftError())
1037
5
        return false;
1038
316
    }
1039
321
  }
1040
316
1041
316
  // Verify we have a legal type before going any further.
1042
316
  MVT VT;
1043
316
  if (!isLoadTypeLegal(I->getType(), VT))
1044
1
    return false;
1045
315
1046
315
  // See if we can handle this address.
1047
315
  Address Addr;
1048
315
  if (
!ARMComputeAddress(I->getOperand(0), Addr)315
)
return false5
;
1049
310
1050
310
  unsigned ResultReg;
1051
310
  if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1052
12
    return false;
1053
298
  updateValueMap(I, ResultReg);
1054
298
  return true;
1055
298
}
1056
1057
bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1058
1.26k
                               unsigned Alignment) {
1059
1.26k
  unsigned StrOpc;
1060
1.26k
  bool useAM3 = false;
1061
1.26k
  switch (VT.SimpleTy) {
1062
1.26k
    // This is mostly going to be Neon/vector support.
1063
5
    default: return false;
1064
11
    case MVT::i1: {
1065
5
      unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass
1066
6
                                              : &ARM::GPRRegClass);
1067
11
      unsigned Opc = isThumb2 ? 
ARM::t2ANDri5
:
ARM::ANDri6
;
1068
11
      SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1069
11
      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1070
11
                              TII.get(Opc), Res)
1071
11
                      .addReg(SrcReg).addImm(1));
1072
11
      SrcReg = Res;
1073
11
      LLVM_FALLTHROUGH;
1074
11
    }
1075
102
    case MVT::i8:
1076
102
      if (
isThumb2102
) {
1077
35
        if (
Addr.Offset < 0 && 35
Addr.Offset > -2563
&&
Subtarget->hasV6T2Ops()2
)
1078
2
          StrOpc = ARM::t2STRBi8;
1079
35
        else
1080
33
          StrOpc = ARM::t2STRBi12;
1081
102
      } else {
1082
67
        StrOpc = ARM::STRBi12;
1083
67
      }
1084
102
      break;
1085
78
    case MVT::i16:
1086
78
      if (
Alignment && 78
Alignment < 230
&&
!Subtarget->allowsUnalignedMem()8
)
1087
4
        return false;
1088
74
1089
74
      
if (74
isThumb274
) {
1090
23
        if (
Addr.Offset < 0 && 23
Addr.Offset > -2563
&&
Subtarget->hasV6T2Ops()2
)
1091
2
          StrOpc = ARM::t2STRHi8;
1092
23
        else
1093
21
          StrOpc = ARM::t2STRHi12;
1094
74
      } else {
1095
51
        StrOpc = ARM::STRH;
1096
51
        useAM3 = true;
1097
51
      }
1098
74
      break;
1099
508
    case MVT::i32:
1100
508
      if (
Alignment && 508
Alignment < 4152
&&
!Subtarget->allowsUnalignedMem()8
)
1101
4
        return false;
1102
504
1103
504
      
if (504
isThumb2504
) {
1104
307
        if (
Addr.Offset < 0 && 307
Addr.Offset > -2563
&&
Subtarget->hasV6T2Ops()2
)
1105
2
          StrOpc = ARM::t2STRi8;
1106
307
        else
1107
305
          StrOpc = ARM::t2STRi12;
1108
504
      } else {
1109
197
        StrOpc = ARM::STRi12;
1110
197
      }
1111
504
      break;
1112
119
    case MVT::f32:
1113
119
      if (
!Subtarget->hasVFP2()119
)
return false0
;
1114
119
      // Unaligned stores need special handling. Floats require word-alignment.
1115
119
      
if (119
Alignment && 119
Alignment < 4114
) {
1116
8
        unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1117
8
        AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1118
8
                                TII.get(ARM::VMOVRS), MoveReg)
1119
8
                        .addReg(SrcReg));
1120
8
        SrcReg = MoveReg;
1121
8
        VT = MVT::i32;
1122
8
        StrOpc = isThumb2 ? 
ARM::t2STRi122
:
ARM::STRi126
;
1123
119
      } else {
1124
111
        StrOpc = ARM::VSTRS;
1125
111
      }
1126
119
      break;
1127
449
    case MVT::f64:
1128
449
      if (
!Subtarget->hasVFP2()449
)
return false0
;
1129
449
      // FIXME: Unaligned stores need special handling.  Doublewords require
1130
449
      // word-alignment.
1131
449
      
if (449
Alignment && 449
Alignment < 428
)
1132
0
          return false;
1133
449
1134
449
      StrOpc = ARM::VSTRD;
1135
449
      break;
1136
1.24k
  }
1137
1.24k
  // Simplify this down to something we can handle.
1138
1.24k
  ARMSimplifyAddress(Addr, VT, useAM3);
1139
1.24k
1140
1.24k
  // Create the base instruction, then add the operands.
1141
1.24k
  SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1142
1.24k
  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1143
1.24k
                                    TII.get(StrOpc))
1144
1.24k
                            .addReg(SrcReg);
1145
1.24k
  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1146
1.24k
  return true;
1147
1.24k
}
1148
1149
599
bool ARMFastISel::SelectStore(const Instruction *I) {
1150
599
  Value *Op0 = I->getOperand(0);
1151
599
  unsigned SrcReg = 0;
1152
599
1153
599
  // Atomic stores need special handling.
1154
599
  if (cast<StoreInst>(I)->isAtomic())
1155
3
    return false;
1156
596
1157
596
  const Value *PtrV = I->getOperand(1);
1158
596
  if (
TLI.supportSwiftError()596
) {
1159
596
    // Swifterror values can come from either a function parameter with
1160
596
    // swifterror attribute or an alloca with swifterror attribute.
1161
596
    if (const Argument *
Arg596
= dyn_cast<Argument>(PtrV)) {
1162
63
      if (Arg->hasSwiftErrorAttr())
1163
1
        return false;
1164
595
    }
1165
595
1166
595
    
if (const AllocaInst *595
Alloca595
= dyn_cast<AllocaInst>(PtrV)) {
1167
260
      if (Alloca->isSwiftError())
1168
1
        return false;
1169
594
    }
1170
596
  }
1171
594
1172
594
  // Verify we have a legal type before going any further.
1173
594
  MVT VT;
1174
594
  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1175
7
    return false;
1176
587
1177
587
  // Get the value to be stored into a register.
1178
587
  SrcReg = getRegForValue(Op0);
1179
587
  if (
SrcReg == 0587
)
return false0
;
1180
587
1181
587
  // See if we can handle this address.
1182
587
  Address Addr;
1183
587
  if (!ARMComputeAddress(I->getOperand(1), Addr))
1184
4
    return false;
1185
583
1186
583
  
if (583
!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment())583
)
1187
13
    return false;
1188
570
  return true;
1189
570
}
1190
1191
84
static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1192
84
  switch (Pred) {
1193
84
    // Needs two compares...
1194
0
    case CmpInst::FCMP_ONE:
1195
0
    case CmpInst::FCMP_UEQ:
1196
0
    default:
1197
0
      // AL is our "false" for now. The other two need more compares.
1198
0
      return ARMCC::AL;
1199
6
    case CmpInst::ICMP_EQ:
1200
6
    case CmpInst::FCMP_OEQ:
1201
6
      return ARMCC::EQ;
1202
3
    case CmpInst::ICMP_SGT:
1203
3
    case CmpInst::FCMP_OGT:
1204
3
      return ARMCC::GT;
1205
5
    case CmpInst::ICMP_SGE:
1206
5
    case CmpInst::FCMP_OGE:
1207
5
      return ARMCC::GE;
1208
3
    case CmpInst::ICMP_UGT:
1209
3
    case CmpInst::FCMP_UGT:
1210
3
      return ARMCC::HI;
1211
0
    case CmpInst::FCMP_OLT:
1212
0
      return ARMCC::MI;
1213
3
    case CmpInst::ICMP_ULE:
1214
3
    case CmpInst::FCMP_OLE:
1215
3
      return ARMCC::LS;
1216
0
    case CmpInst::FCMP_ORD:
1217
0
      return ARMCC::VC;
1218
0
    case CmpInst::FCMP_UNO:
1219
0
      return ARMCC::VS;
1220
0
    case CmpInst::FCMP_UGE:
1221
0
      return ARMCC::PL;
1222
3
    case CmpInst::ICMP_SLT:
1223
3
    case CmpInst::FCMP_ULT:
1224
3
      return ARMCC::LT;
1225
2
    case CmpInst::ICMP_SLE:
1226
2
    case CmpInst::FCMP_ULE:
1227
2
      return ARMCC::LE;
1228
53
    case CmpInst::FCMP_UNE:
1229
53
    case CmpInst::ICMP_NE:
1230
53
      return ARMCC::NE;
1231
0
    case CmpInst::ICMP_UGE:
1232
0
      return ARMCC::HS;
1233
6
    case CmpInst::ICMP_ULT:
1234
6
      return ARMCC::LO;
1235
0
  }
1236
0
}
1237
1238
79
bool ARMFastISel::SelectBranch(const Instruction *I) {
1239
79
  const BranchInst *BI = cast<BranchInst>(I);
1240
79
  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1241
79
  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1242
79
1243
79
  // Simple branch support.
1244
79
1245
79
  // If we can, avoid recomputing the compare - redoing it could lead to wonky
1246
79
  // behavior.
1247
79
  if (const CmpInst *
CI79
= dyn_cast<CmpInst>(BI->getCondition())) {
1248
58
    if (
CI->hasOneUse() && 58
(CI->getParent() == I->getParent())58
) {
1249
58
      // Get the compare predicate.
1250
58
      // Try to take advantage of fallthrough opportunities.
1251
58
      CmpInst::Predicate Predicate = CI->getPredicate();
1252
58
      if (
FuncInfo.MBB->isLayoutSuccessor(TBB)58
) {
1253
52
        std::swap(TBB, FBB);
1254
52
        Predicate = CmpInst::getInversePredicate(Predicate);
1255
52
      }
1256
58
1257
58
      ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1258
58
1259
58
      // We may not handle every CC for now.
1260
58
      if (
ARMPred == ARMCC::AL58
)
return false0
;
1261
58
1262
58
      // Emit the compare.
1263
58
      
if (58
!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
1264
58
                      CI->isEquality()))
1265
0
        return false;
1266
58
1267
58
      
unsigned BrOpc = isThumb2 ? 58
ARM::t2Bcc19
:
ARM::Bcc39
;
1268
58
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1269
58
      .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1270
58
      finishCondBranch(BI->getParent(), TBB, FBB);
1271
58
      return true;
1272
58
    }
1273
21
  } else 
if (TruncInst *21
TI21
= dyn_cast<TruncInst>(BI->getCondition())) {
1274
3
    MVT SourceVT;
1275
3
    if (
TI->hasOneUse() && 3
TI->getParent() == I->getParent()3
&&
1276
3
        
(isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))3
) {
1277
3
      unsigned TstOpc = isThumb2 ? 
ARM::t2TSTri1
:
ARM::TSTri2
;
1278
3
      unsigned OpReg = getRegForValue(TI->getOperand(0));
1279
3
      OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1280
3
      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1281
3
                              TII.get(TstOpc))
1282
3
                      .addReg(OpReg).addImm(1));
1283
3
1284
3
      unsigned CCMode = ARMCC::NE;
1285
3
      if (
FuncInfo.MBB->isLayoutSuccessor(TBB)3
) {
1286
3
        std::swap(TBB, FBB);
1287
3
        CCMode = ARMCC::EQ;
1288
3
      }
1289
3
1290
3
      unsigned BrOpc = isThumb2 ? 
ARM::t2Bcc1
:
ARM::Bcc2
;
1291
3
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1292
3
      .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1293
3
1294
3
      finishCondBranch(BI->getParent(), TBB, FBB);
1295
3
      return true;
1296
3
    }
1297
18
  } else 
if (const ConstantInt *18
CI18
=
1298
12
             dyn_cast<ConstantInt>(BI->getCondition())) {
1299
12
    uint64_t Imm = CI->getZExtValue();
1300
12
    MachineBasicBlock *Target = (Imm == 0) ? 
FBB4
:
TBB8
;
1301
21
    fastEmitBranch(Target, DbgLoc);
1302
21
    return true;
1303
21
  }
1304
6
1305
6
  unsigned CmpReg = getRegForValue(BI->getCondition());
1306
6
  if (
CmpReg == 06
)
return false0
;
1307
6
1308
6
  // We've been divorced from our compare!  Our block was split, and
1309
6
  // now our compare lives in a predecessor block.  We musn't
1310
6
  // re-compare here, as the children of the compare aren't guaranteed
1311
6
  // live across the block boundary (we *could* check for this).
1312
6
  // Regardless, the compare has been done in the predecessor block,
1313
6
  // and it left a value for us in a virtual register.  Ergo, we test
1314
6
  // the one-bit value left in the virtual register.
1315
6
  
unsigned TstOpc = isThumb2 ? 6
ARM::t2TSTri2
:
ARM::TSTri4
;
1316
6
  CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1317
6
  AddOptionalDefs(
1318
6
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1319
6
          .addReg(CmpReg)
1320
6
          .addImm(1));
1321
6
1322
6
  unsigned CCMode = ARMCC::NE;
1323
6
  if (
FuncInfo.MBB->isLayoutSuccessor(TBB)6
) {
1324
3
    std::swap(TBB, FBB);
1325
3
    CCMode = ARMCC::EQ;
1326
3
  }
1327
6
1328
6
  unsigned BrOpc = isThumb2 ? 
ARM::t2Bcc2
:
ARM::Bcc4
;
1329
79
  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1330
79
                  .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1331
79
  finishCondBranch(BI->getParent(), TBB, FBB);
1332
79
  return true;
1333
79
}
1334
1335
4
bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1336
4
  unsigned AddrReg = getRegForValue(I->getOperand(0));
1337
4
  if (
AddrReg == 04
)
return false0
;
1338
4
1339
4
  
unsigned Opc = isThumb2 ? 4
ARM::tBRIND2
:
ARM::BX2
;
1340
4
  assert(isThumb2 || Subtarget->hasV4TOps());
1341
4
1342
4
  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1343
4
                          TII.get(Opc)).addReg(AddrReg));
1344
4
1345
4
  const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1346
4
  for (const BasicBlock *SuccBB : IB->successors())
1347
8
    FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
1348
4
1349
4
  return true;
1350
4
}
1351
1352
bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1353
84
                             bool isZExt, bool isEquality) {
1354
84
  Type *Ty = Src1Value->getType();
1355
84
  EVT SrcEVT = TLI.getValueType(DL, Ty, true);
1356
84
  if (
!SrcEVT.isSimple()84
)
return false0
;
1357
84
  MVT SrcVT = SrcEVT.getSimpleVT();
1358
84
1359
84
  if (
Ty->isFloatTy() && 84
!Subtarget->hasVFP2()16
)
1360
0
    return false;
1361
84
1362
84
  
if (84
Ty->isDoubleTy() && 84
(!Subtarget->hasVFP2() || 7
Subtarget->isFPOnlySP()7
))
1363
1
    return false;
1364
83
1365
83
  // Check to see if the 2nd operand is a constant that we can encode directly
1366
83
  // in the compare.
1367
83
  int Imm = 0;
1368
83
  bool UseImm = false;
1369
83
  bool isNegativeImm = false;
1370
83
  // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1371
83
  // Thus, Src1Value may be a ConstantInt, but we're missing it.
1372
83
  if (const ConstantInt *
ConstInt83
= dyn_cast<ConstantInt>(Src2Value)) {
1373
40
    if (
SrcVT == MVT::i32 || 40
SrcVT == MVT::i1615
||
SrcVT == MVT::i89
||
1374
40
        
SrcVT == MVT::i10
) {
1375
40
      const APInt &CIVal = ConstInt->getValue();
1376
40
      Imm = (isZExt) ? 
(int)CIVal.getZExtValue()3
:
(int)CIVal.getSExtValue()37
;
1377
40
      // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1378
40
      // then a cmn, because there is no way to represent 2147483648 as a
1379
40
      // signed 32-bit int.
1380
40
      if (
Imm < 0 && 40
Imm != (int)0x8000000012
) {
1381
9
        isNegativeImm = true;
1382
9
        Imm = -Imm;
1383
9
      }
1384
16
      UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1385
24
        (ARM_AM::getSOImmVal(Imm) != -1);
1386
40
    }
1387
83
  } else 
if (const ConstantFP *43
ConstFP43
= dyn_cast<ConstantFP>(Src2Value)) {
1388
22
    if (
SrcVT == MVT::f32 || 22
SrcVT == MVT::f646
)
1389
22
      
if (22
ConstFP->isZero() && 22
!ConstFP->isNegative()20
)
1390
14
        UseImm = true;
1391
43
  }
1392
83
1393
83
  unsigned CmpOpc;
1394
83
  bool isICmp = true;
1395
83
  bool needsExt = false;
1396
83
  switch (SrcVT.SimpleTy) {
1397
0
    default: return false;
1398
83
    // TODO: Verify compares.
1399
16
    case MVT::f32:
1400
16
      isICmp = false;
1401
16
      // Equality comparisons shouldn't raise Invalid on uordered inputs.
1402
16
      if (isEquality)
1403
14
        
CmpOpc = UseImm ? 14
ARM::VCMPZS11
:
ARM::VCMPS3
;
1404
16
      else
1405
2
        
CmpOpc = UseImm ? 2
ARM::VCMPEZS0
:
ARM::VCMPES2
;
1406
16
      break;
1407
6
    case MVT::f64:
1408
6
      isICmp = false;
1409
6
      // Equality comparisons shouldn't raise Invalid on uordered inputs.
1410
6
      if (isEquality)
1411
6
        
CmpOpc = UseImm ? 6
ARM::VCMPZD3
:
ARM::VCMPD3
;
1412
6
      else
1413
0
      
CmpOpc = UseImm ? 0
ARM::VCMPEZD0
:
ARM::VCMPED0
;
1414
6
      break;
1415
30
    case MVT::i1:
1416
30
    case MVT::i8:
1417
30
    case MVT::i16:
1418
30
      needsExt = true;
1419
30
    // Intentional fall-through.
1420
61
    case MVT::i32:
1421
61
      if (
isThumb261
) {
1422
22
        if (!UseImm)
1423
7
          CmpOpc = ARM::t2CMPrr;
1424
22
        else
1425
15
          
CmpOpc = isNegativeImm ? 15
ARM::t2CMNri3
:
ARM::t2CMPri12
;
1426
61
      } else {
1427
39
        if (!UseImm)
1428
15
          CmpOpc = ARM::CMPrr;
1429
39
        else
1430
24
          
CmpOpc = isNegativeImm ? 24
ARM::CMNri6
:
ARM::CMPri18
;
1431
39
      }
1432
30
      break;
1433
83
  }
1434
83
1435
83
  unsigned SrcReg1 = getRegForValue(Src1Value);
1436
83
  if (
SrcReg1 == 083
)
return false0
;
1437
83
1438
83
  unsigned SrcReg2 = 0;
1439
83
  if (
!UseImm83
) {
1440
30
    SrcReg2 = getRegForValue(Src2Value);
1441
30
    if (
SrcReg2 == 030
)
return false0
;
1442
83
  }
1443
83
1444
83
  // We have i1, i8, or i16, we need to either zero extend or sign extend.
1445
83
  
if (83
needsExt83
) {
1446
30
    SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1447
30
    if (
SrcReg1 == 030
)
return false0
;
1448
30
    
if (30
!UseImm30
) {
1449
15
      SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1450
15
      if (
SrcReg2 == 015
)
return false0
;
1451
83
    }
1452
30
  }
1453
83
1454
83
  const MCInstrDesc &II = TII.get(CmpOpc);
1455
83
  SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1456
83
  if (
!UseImm83
) {
1457
30
    SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1458
30
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1459
30
                    .addReg(SrcReg1).addReg(SrcReg2));
1460
83
  } else {
1461
53
    MachineInstrBuilder MIB;
1462
53
    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1463
53
      .addReg(SrcReg1);
1464
53
1465
53
    // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1466
53
    if (isICmp)
1467
39
      MIB.addImm(Imm);
1468
53
    AddOptionalDefs(MIB);
1469
53
  }
1470
83
1471
83
  // For floating point we need to move the result to a comparison register
1472
83
  // that we can then use for branches.
1473
83
  if (
Ty->isFloatTy() || 83
Ty->isDoubleTy()67
)
1474
22
    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1475
22
                            TII.get(ARM::FMSTAT)));
1476
84
  return true;
1477
84
}
1478
1479
26
bool ARMFastISel::SelectCmp(const Instruction *I) {
1480
26
  const CmpInst *CI = cast<CmpInst>(I);
1481
26
1482
26
  // Get the compare predicate.
1483
26
  ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1484
26
1485
26
  // We may not handle every CC for now.
1486
26
  if (
ARMPred == ARMCC::AL26
)
return false0
;
1487
26
1488
26
  // Emit the compare.
1489
26
  
if (26
!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
1490
26
                  CI->isEquality()))
1491
1
    return false;
1492
25
1493
25
  // Now set a register based on the comparison. Explicitly set the predicates
1494
25
  // here.
1495
25
  
unsigned MovCCOpc = isThumb2 ? 25
ARM::t2MOVCCi9
:
ARM::MOVCCi16
;
1496
9
  const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
1497
16
                                           : &ARM::GPRRegClass;
1498
26
  unsigned DestReg = createResultReg(RC);
1499
26
  Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1500
26
  unsigned ZeroReg = fastMaterializeConstant(Zero);
1501
26
  // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1502
26
  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
1503
26
          .addReg(ZeroReg).addImm(1)
1504
26
          .addImm(ARMPred).addReg(ARM::CPSR);
1505
26
1506
26
  updateValueMap(I, DestReg);
1507
26
  return true;
1508
26
}
1509
1510
1
bool ARMFastISel::SelectFPExt(const Instruction *I) {
1511
1
  // Make sure we have VFP and that we're extending float to double.
1512
1
  if (
!Subtarget->hasVFP2() || 1
Subtarget->isFPOnlySP()1
)
return false1
;
1513
0
1514
0
  Value *V = I->getOperand(0);
1515
0
  if (!I->getType()->isDoubleTy() ||
1516
0
      
!V->getType()->isFloatTy()0
)
return false0
;
1517
0
1518
0
  unsigned Op = getRegForValue(V);
1519
0
  if (
Op == 00
)
return false0
;
1520
0
1521
0
  unsigned Result = createResultReg(&ARM::DPRRegClass);
1522
0
  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1523
0
                          TII.get(ARM::VCVTDS), Result)
1524
0
                  .addReg(Op));
1525
0
  updateValueMap(I, Result);
1526
0
  return true;
1527
0
}
1528
1529
1
bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1530
1
  // Make sure we have VFP and that we're truncating double to float.
1531
1
  if (
!Subtarget->hasVFP2() || 1
Subtarget->isFPOnlySP()1
)
return false1
;
1532
0
1533
0
  Value *V = I->getOperand(0);
1534
0
  if (!(I->getType()->isFloatTy() &&
1535
0
        
V->getType()->isDoubleTy()0
))
return false0
;
1536
0
1537
0
  unsigned Op = getRegForValue(V);
1538
0
  if (
Op == 00
)
return false0
;
1539
0
1540
0
  unsigned Result = createResultReg(&ARM::SPRRegClass);
1541
0
  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1542
0
                          TII.get(ARM::VCVTSD), Result)
1543
0
                  .addReg(Op));
1544
0
  updateValueMap(I, Result);
1545
0
  return true;
1546
0
}
1547
1548
37
bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1549
37
  // Make sure we have VFP.
1550
37
  if (
!Subtarget->hasVFP2()37
)
return false0
;
1551
37
1552
37
  MVT DstVT;
1553
37
  Type *Ty = I->getType();
1554
37
  if (!isTypeLegal(Ty, DstVT))
1555
0
    return false;
1556
37
1557
37
  Value *Src = I->getOperand(0);
1558
37
  EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
1559
37
  if (!SrcEVT.isSimple())
1560
0
    return false;
1561
37
  MVT SrcVT = SrcEVT.getSimpleVT();
1562
37
  if (
SrcVT != MVT::i32 && 37
SrcVT != MVT::i1624
&&
SrcVT != MVT::i812
)
1563
0
    return false;
1564
37
1565
37
  unsigned SrcReg = getRegForValue(Src);
1566
37
  if (
SrcReg == 037
)
return false0
;
1567
37
1568
37
  // Handle sign-extension.
1569
37
  
if (37
SrcVT == MVT::i16 || 37
SrcVT == MVT::i825
) {
1570
24
    SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1571
24
                                       /*isZExt*/!isSigned);
1572
24
    if (
SrcReg == 024
)
return false0
;
1573
37
  }
1574
37
1575
37
  // The conversion routine works on fp-reg to fp-reg and the operand above
1576
37
  // was an integer, move it to the fp registers if possible.
1577
37
  unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1578
37
  if (
FP == 037
)
return false0
;
1579
37
1580
37
  unsigned Opc;
1581
37
  if (
Ty->isFloatTy()37
)
Opc = isSigned ? 18
ARM::VSITOS9
:
ARM::VUITOS9
;
1582
19
  else 
if (19
Ty->isDoubleTy() && 19
!Subtarget->isFPOnlySP()19
)
1583
18
    
Opc = isSigned ? 18
ARM::VSITOD9
:
ARM::VUITOD9
;
1584
1
  else return false;
1585
36
1586
36
  unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1587
36
  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1588
36
                          TII.get(Opc), ResultReg).addReg(FP));
1589
36
  updateValueMap(I, ResultReg);
1590
36
  return true;
1591
36
}
1592
1593
13
bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1594
13
  // Make sure we have VFP.
1595
13
  if (
!Subtarget->hasVFP2()13
)
return false0
;
1596
13
1597
13
  MVT DstVT;
1598
13
  Type *RetTy = I->getType();
1599
13
  if (!isTypeLegal(RetTy, DstVT))
1600
0
    return false;
1601
13
1602
13
  unsigned Op = getRegForValue(I->getOperand(0));
1603
13
  if (
Op == 013
)
return false0
;
1604
13
1605
13
  unsigned Opc;
1606
13
  Type *OpTy = I->getOperand(0)->getType();
1607
13
  if (
OpTy->isFloatTy()13
)
Opc = isSigned ? 6
ARM::VTOSIZS3
:
ARM::VTOUIZS3
;
1608
7
  else 
if (7
OpTy->isDoubleTy() && 7
!Subtarget->isFPOnlySP()7
)
1609
6
    
Opc = isSigned ? 6
ARM::VTOSIZD3
:
ARM::VTOUIZD3
;
1610
1
  else return false;
1611
12
1612
12
  // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1613
12
  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1614
12
  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1615
12
                          TII.get(Opc), ResultReg).addReg(Op));
1616
12
1617
12
  // This result needs to be in an integer register, but the conversion only
1618
12
  // takes place in fp-regs.
1619
12
  unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1620
12
  if (
IntReg == 012
)
return false0
;
1621
12
1622
12
  updateValueMap(I, IntReg);
1623
12
  return true;
1624
12
}
1625
1626
24
bool ARMFastISel::SelectSelect(const Instruction *I) {
1627
24
  MVT VT;
1628
24
  if (!isTypeLegal(I->getType(), VT))
1629
0
    return false;
1630
24
1631
24
  // Things need to be register sized for register moves.
1632
24
  
if (24
VT != MVT::i3224
)
return false0
;
1633
24
1634
24
  unsigned CondReg = getRegForValue(I->getOperand(0));
1635
24
  if (
CondReg == 024
)
return false0
;
1636
24
  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1637
24
  if (
Op1Reg == 024
)
return false0
;
1638
24
1639
24
  // Check to see if we can use an immediate in the conditional move.
1640
24
  int Imm = 0;
1641
24
  bool UseImm = false;
1642
24
  bool isNegativeImm = false;
1643
24
  if (const ConstantInt *
ConstInt24
= dyn_cast<ConstantInt>(I->getOperand(2))) {
1644
20
    assert(VT == MVT::i32 && "Expecting an i32.");
1645
20
    Imm = (int)ConstInt->getValue().getZExtValue();
1646
20
    if (
Imm < 020
) {
1647
12
      isNegativeImm = true;
1648
12
      Imm = ~Imm;
1649
12
    }
1650
10
    UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1651
10
      (ARM_AM::getSOImmVal(Imm) != -1);
1652
20
  }
1653
24
1654
24
  unsigned Op2Reg = 0;
1655
24
  if (
!UseImm24
) {
1656
4
    Op2Reg = getRegForValue(I->getOperand(2));
1657
4
    if (
Op2Reg == 04
)
return false0
;
1658
24
  }
1659
24
1660
24
  
unsigned TstOpc = isThumb2 ? 24
ARM::t2TSTri12
:
ARM::TSTri12
;
1661
24
  CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);
1662
24
  AddOptionalDefs(
1663
24
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1664
24
          .addReg(CondReg)
1665
24
          .addImm(1));
1666
24
1667
24
  unsigned MovCCOpc;
1668
24
  const TargetRegisterClass *RC;
1669
24
  if (
!UseImm24
) {
1670
4
    RC = isThumb2 ? 
&ARM::tGPRRegClass2
:
&ARM::GPRRegClass2
;
1671
4
    MovCCOpc = isThumb2 ? 
ARM::t2MOVCCr2
:
ARM::MOVCCr2
;
1672
24
  } else {
1673
20
    RC = isThumb2 ? 
&ARM::rGPRRegClass10
:
&ARM::GPRRegClass10
;
1674
20
    if (!isNegativeImm)
1675
8
      
MovCCOpc = isThumb2 ? 8
ARM::t2MOVCCi4
:
ARM::MOVCCi4
;
1676
20
    else
1677
12
      
MovCCOpc = isThumb2 ? 12
ARM::t2MVNCCi6
:
ARM::MVNCCi6
;
1678
20
  }
1679
24
  unsigned ResultReg = createResultReg(RC);
1680
24
  if (
!UseImm24
) {
1681
4
    Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1682
4
    Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1683
4
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1684
4
            ResultReg)
1685
4
        .addReg(Op2Reg)
1686
4
        .addReg(Op1Reg)
1687
4
        .addImm(ARMCC::NE)
1688
4
        .addReg(ARM::CPSR);
1689
24
  } else {
1690
20
    Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1691
20
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1692
20
            ResultReg)
1693
20
        .addReg(Op1Reg)
1694
20
        .addImm(Imm)
1695
20
        .addImm(ARMCC::EQ)
1696
20
        .addReg(ARM::CPSR);
1697
20
  }
1698
24
  updateValueMap(I, ResultReg);
1699
24
  return true;
1700
24
}
1701
1702
14
bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1703
14
  MVT VT;
1704
14
  Type *Ty = I->getType();
1705
14
  if (!isTypeLegal(Ty, VT))
1706
0
    return false;
1707
14
1708
14
  // If we have integer div support we should have selected this automagically.
1709
14
  // In case we have a real miss go ahead and return false and we'll pick
1710
14
  // it up later.
1711
14
  
if (14
Subtarget->hasDivideInThumbMode()14
)
1712
0
    return false;
1713
14
1714
14
  // Otherwise emit a libcall.
1715
14
  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1716
14
  if (VT == MVT::i8)
1717
0
    
LC = isSigned ? 0
RTLIB::SDIV_I80
:
RTLIB::UDIV_I80
;
1718
14
  else 
if (14
VT == MVT::i1614
)
1719
0
    
LC = isSigned ? 0
RTLIB::SDIV_I160
:
RTLIB::UDIV_I160
;
1720
14
  else 
if (14
VT == MVT::i3214
)
1721
14
    
LC = isSigned ? 14
RTLIB::SDIV_I324
:
RTLIB::UDIV_I3210
;
1722
0
  else 
if (0
VT == MVT::i640
)
1723
0
    
LC = isSigned ? 0
RTLIB::SDIV_I640
:
RTLIB::UDIV_I640
;
1724
0
  else 
if (0
VT == MVT::i1280
)
1725
0
    
LC = isSigned ? 0
RTLIB::SDIV_I1280
:
RTLIB::UDIV_I1280
;
1726
14
  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1727
14
1728
14
  return ARMEmitLibcall(I, LC);
1729
14
}
1730
1731
36
bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1732
36
  MVT VT;
1733
36
  Type *Ty = I->getType();
1734
36
  if (!isTypeLegal(Ty, VT))
1735
4
    return false;
1736
32
1737
32
  // Many ABIs do not provide a libcall for standalone remainder, so we need to
1738
32
  // use divrem (see the RTABI 4.3.1). Since FastISel can't handle non-double
1739
32
  // multi-reg returns, we'll have to bail out.
1740
32
  
if (32
!TLI.hasStandaloneRem(VT)32
) {
1741
21
    return false;
1742
21
  }
1743
11
1744
11
  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1745
11
  if (VT == MVT::i8)
1746
0
    
LC = isSigned ? 0
RTLIB::SREM_I80
:
RTLIB::UREM_I80
;
1747
11
  else 
if (11
VT == MVT::i1611
)
1748
0
    
LC = isSigned ? 0
RTLIB::SREM_I160
:
RTLIB::UREM_I160
;
1749
11
  else 
if (11
VT == MVT::i3211
)
1750
11
    
LC = isSigned ? 11
RTLIB::SREM_I329
:
RTLIB::UREM_I322
;
1751
0
  else 
if (0
VT == MVT::i640
)
1752
0
    
LC = isSigned ? 0
RTLIB::SREM_I640
:
RTLIB::UREM_I640
;
1753
0
  else 
if (0
VT == MVT::i1280
)
1754
0
    
LC = isSigned ? 0
RTLIB::SREM_I1280
:
RTLIB::UREM_I1280
;
1755
36
  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1756
36
1757
36
  return ARMEmitLibcall(I, LC);
1758
36
}
1759
1760
37
bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1761
37
  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1762
37
1763
37
  // We can get here in the case when we have a binary operation on a non-legal
1764
37
  // type and the target independent selector doesn't know how to handle it.
1765
37
  if (
DestVT != MVT::i16 && 37
DestVT != MVT::i820
&&
DestVT != MVT::i17
)
1766
1
    return false;
1767
36
1768
36
  unsigned Opc;
1769
36
  switch (ISDOpcode) {
1770
0
    default: return false;
1771
21
    case ISD::ADD:
1772
21
      Opc = isThumb2 ? 
ARM::t2ADDrr3
:
ARM::ADDrr18
;
1773
21
      break;
1774
6
    case ISD::OR:
1775
6
      Opc = isThumb2 ? 
ARM::t2ORRrr2
:
ARM::ORRrr4
;
1776
6
      break;
1777
9
    case ISD::SUB:
1778
9
      Opc = isThumb2 ? 
ARM::t2SUBrr3
:
ARM::SUBrr6
;
1779
9
      break;
1780
36
  }
1781
36
1782
36
  unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1783
36
  if (
SrcReg1 == 036
)
return false0
;
1784
36
1785
36
  // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1786
36
  // in the instruction, rather then materializing the value in a register.
1787
36
  unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1788
36
  if (
SrcReg2 == 036
)
return false0
;
1789
36
1790
36
  unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1791
36
  SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1792
36
  SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1793
36
  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1794
36
                          TII.get(Opc), ResultReg)
1795
36
                  .addReg(SrcReg1).addReg(SrcReg2));
1796
36
  updateValueMap(I, ResultReg);
1797
36
  return true;
1798
36
}
1799
1800
2
bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1801
2
  EVT FPVT = TLI.getValueType(DL, I->getType(), true);
1802
2
  if (
!FPVT.isSimple()2
)
return false0
;
1803
2
  MVT VT = FPVT.getSimpleVT();
1804
2
1805
2
  // FIXME: Support vector types where possible.
1806
2
  if (VT.isVector())
1807
1
    return false;
1808
1
1809
1
  // We can get here in the case when we want to use NEON for our fp
1810
1
  // operations, but can't figure out how to. Just use the vfp instructions
1811
1
  // if we have them.
1812
1
  // FIXME: It'd be nice to use NEON instructions.
1813
1
  Type *Ty = I->getType();
1814
1
  if (
Ty->isFloatTy() && 1
!Subtarget->hasVFP2()0
)
1815
0
    return false;
1816
1
  
if (1
Ty->isDoubleTy() && 1
(!Subtarget->hasVFP2() || 1
Subtarget->isFPOnlySP()1
))
1817
1
    return false;
1818
0
1819
0
  unsigned Opc;
1820
0
  bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1821
0
  switch (ISDOpcode) {
1822
0
    default: return false;
1823
0
    case ISD::FADD:
1824
0
      Opc = is64bit ? 
ARM::VADDD0
:
ARM::VADDS0
;
1825
0
      break;
1826
0
    case ISD::FSUB:
1827
0
      Opc = is64bit ? 
ARM::VSUBD0
:
ARM::VSUBS0
;
1828
0
      break;
1829
0
    case ISD::FMUL:
1830
0
      Opc = is64bit ? 
ARM::VMULD0
:
ARM::VMULS0
;
1831
0
      break;
1832
0
  }
1833
0
  unsigned Op1 = getRegForValue(I->getOperand(0));
1834
0
  if (
Op1 == 00
)
return false0
;
1835
0
1836
0
  unsigned Op2 = getRegForValue(I->getOperand(1));
1837
0
  if (
Op2 == 00
)
return false0
;
1838
0
1839
0
  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1840
0
  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1841
0
                          TII.get(Opc), ResultReg)
1842
0
                  .addReg(Op1).addReg(Op2));
1843
0
  updateValueMap(I, ResultReg);
1844
0
  return true;
1845
0
}
1846
1847
// Call Handling Code
1848
1849
// This is largely taken directly from CCAssignFnForNode
1850
// TODO: We may not support all of this.
1851
CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1852
                                           bool Return,
1853
1.17k
                                           bool isVarArg) {
1854
1.17k
  switch (CC) {
1855
0
  default:
1856
0
    report_fatal_error("Unsupported calling convention");
1857
7
  case CallingConv::Fast:
1858
7
    if (
Subtarget->hasVFP2() && 7
!isVarArg7
) {
1859
7
      if (!Subtarget->isAAPCS_ABI())
1860
5
        
return (Return ? 5
RetFastCC_ARM_APCS0
:
FastCC_ARM_APCS5
);
1861
2
      // For AAPCS ABI targets, just use VFP variant of the calling convention.
1862
2
      
return (Return ? 2
RetCC_ARM_AAPCS_VFP0
:
CC_ARM_AAPCS_VFP2
);
1863
7
    }
1864
0
    
LLVM_FALLTHROUGH0
;
1865
1.12k
  case CallingConv::C:
1866
1.12k
  case CallingConv::CXX_FAST_TLS:
1867
1.12k
    // Use target triple & subtarget features to do actual dispatch.
1868
1.12k
    if (
Subtarget->isAAPCS_ABI()1.12k
) {
1869
300
      if (Subtarget->hasVFP2() &&
1870
300
          
TM.Options.FloatABIType == FloatABI::Hard257
&&
!isVarArg13
)
1871
11
        
return (Return ? 11
RetCC_ARM_AAPCS_VFP11
:
CC_ARM_AAPCS_VFP0
);
1872
300
      else
1873
289
        
return (Return ? 289
RetCC_ARM_AAPCS199
:
CC_ARM_AAPCS90
);
1874
821
    } else {
1875
821
      return (Return ? 
RetCC_ARM_APCS449
:
CC_ARM_APCS372
);
1876
821
    }
1877
33
  case CallingConv::ARM_AAPCS_VFP:
1878
33
  case CallingConv::Swift:
1879
33
    if (!isVarArg)
1880
31
      
return (Return ? 31
RetCC_ARM_AAPCS_VFP23
:
CC_ARM_AAPCS_VFP8
);
1881
2
    // Fall through to soft float variant, variadic functions don't
1882
2
    // use hard floating point ABI.
1883
2
    
LLVM_FALLTHROUGH2
;
1884
11
  case CallingConv::ARM_AAPCS:
1885
11
    return (Return ? 
RetCC_ARM_AAPCS6
:
CC_ARM_AAPCS5
);
1886
1
  case CallingConv::ARM_APCS:
1887
1
    return (Return ? 
RetCC_ARM_APCS1
:
CC_ARM_APCS0
);
1888
0
  case CallingConv::GHC:
1889
0
    if (Return)
1890
0
      report_fatal_error("Can't return in GHC call convention");
1891
0
    else
1892
0
      return CC_ARM_APCS_GHC;
1893
0
  }
1894
0
}
1895
1896
bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1897
                                  SmallVectorImpl<unsigned> &ArgRegs,
1898
                                  SmallVectorImpl<MVT> &ArgVTs,
1899
                                  SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1900
                                  SmallVectorImpl<unsigned> &RegArgs,
1901
                                  CallingConv::ID CC,
1902
                                  unsigned &NumBytes,
1903
482
                                  bool isVarArg) {
1904
482
  SmallVector<CCValAssign, 16> ArgLocs;
1905
482
  CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
1906
482
  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1907
482
                             CCAssignFnForCall(CC, false, isVarArg));
1908
482
1909
482
  // Check that we can handle all of the arguments. If we can't, then bail out
1910
482
  // now before we add code to the MBB.
1911
1.79k
  for (unsigned i = 0, e = ArgLocs.size(); 
i != e1.79k
;
++i1.31k
) {
1912
1.32k
    CCValAssign &VA = ArgLocs[i];
1913
1.32k
    MVT ArgVT = ArgVTs[VA.getValNo()];
1914
1.32k
1915
1.32k
    // We don't handle NEON/vector parameters yet.
1916
1.32k
    if (
ArgVT.isVector() || 1.32k
ArgVT.getSizeInBits() > 641.31k
)
1917
5
      return false;
1918
1.31k
1919
1.31k
    // Now copy/store arg to correct locations.
1920
1.31k
    
if (1.31k
VA.isRegLoc() && 1.31k
!VA.needsCustom()753
) {
1921
752
      continue;
1922
564
    } else 
if (564
VA.needsCustom()564
) {
1923
1
      // TODO: We need custom lowering for vector (v2f64) args.
1924
1
      if (VA.getLocVT() != MVT::f64 ||
1925
1
          // TODO: Only handle register args for now.
1926
1
          
!VA.isRegLoc()1
||
!ArgLocs[++i].isRegLoc()1
)
1927
1
        return false;
1928
563
    } else {
1929
563
      switch (ArgVT.SimpleTy) {
1930
0
      default:
1931
0
        return false;
1932
142
      case MVT::i1:
1933
142
      case MVT::i8:
1934
142
      case MVT::i16:
1935
142
      case MVT::i32:
1936
142
        break;
1937
4
      case MVT::f32:
1938
4
        if (!Subtarget->hasVFP2())
1939
0
          return false;
1940
4
        break;
1941
417
      case MVT::f64:
1942
417
        if (!Subtarget->hasVFP2())
1943
0
          return false;
1944
417
        break;
1945
564
      }
1946
564
    }
1947
1.32k
  }
1948
482
1949
482
  // At the point, we are able to handle the call's arguments in fast isel.
1950
482
1951
482
  // Get a count of how many bytes are to be pushed on the stack.
1952
476
  NumBytes = CCInfo.getNextStackOffset();
1953
476
1954
476
  // Issue CALLSEQ_START
1955
476
  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1956
476
  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1957
476
                          TII.get(AdjStackDown))
1958
476
                  .addImm(NumBytes).addImm(0));
1959
476
1960
476
  // Process the args.
1961
1.78k
  for (unsigned i = 0, e = ArgLocs.size(); 
i != e1.78k
;
++i1.30k
) {
1962
1.30k
    CCValAssign &VA = ArgLocs[i];
1963
1.30k
    const Value *ArgVal = Args[VA.getValNo()];
1964
1.30k
    unsigned Arg = ArgRegs[VA.getValNo()];
1965
1.30k
    MVT ArgVT = ArgVTs[VA.getValNo()];
1966
1.30k
1967
1.30k
    assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1968
1.30k
           "We don't handle NEON/vector parameters yet.");
1969
1.30k
1970
1.30k
    // Handle arg promotion, etc.
1971
1.30k
    switch (VA.getLocInfo()) {
1972
1.09k
      case CCValAssign::Full: break;
1973
18
      case CCValAssign::SExt: {
1974
18
        MVT DestVT = VA.getLocVT();
1975
18
        Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1976
18
        assert(Arg != 0 && "Failed to emit a sext");
1977
18
        ArgVT = DestVT;
1978
18
        break;
1979
1.30k
      }
1980
115
      case CCValAssign::AExt:
1981
115
      // Intentional fall-through.  Handle AExt and ZExt.
1982
115
      case CCValAssign::ZExt: {
1983
115
        MVT DestVT = VA.getLocVT();
1984
115
        Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1985
115
        assert(Arg != 0 && "Failed to emit a zext");
1986
115
        ArgVT = DestVT;
1987
115
        break;
1988
115
      }
1989
81
      case CCValAssign::BCvt: {
1990
81
        unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1991
81
                                 /*TODO: Kill=*/false);
1992
81
        assert(BC != 0 && "Failed to emit a bitcast!");
1993
81
        Arg = BC;
1994
81
        ArgVT = VA.getLocVT();
1995
81
        break;
1996
115
      }
1997
0
      
default: 0
llvm_unreachable0
("Unknown arg promotion!");
1998
1.30k
    }
1999
1.30k
2000
1.30k
    // Now copy/store arg to correct locations.
2001
1.30k
    
if (1.30k
VA.isRegLoc() && 1.30k
!VA.needsCustom()745
) {
2002
745
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2003
745
              TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
2004
745
      RegArgs.push_back(VA.getLocReg());
2005
1.30k
    } else 
if (561
VA.needsCustom()561
) {
2006
0
      // TODO: We need custom lowering for vector (v2f64) args.
2007
0
      assert(VA.getLocVT() == MVT::f64 &&
2008
0
             "Custom lowering for v2f64 args not available");
2009
0
2010
0
      // FIXME: ArgLocs[++i] may extend beyond ArgLocs.size()
2011
0
      CCValAssign &NextVA = ArgLocs[++i];
2012
0
2013
0
      assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2014
0
             "We only handle register args!");
2015
0
2016
0
      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2017
0
                              TII.get(ARM::VMOVRRD), VA.getLocReg())
2018
0
                      .addReg(NextVA.getLocReg(), RegState::Define)
2019
0
                      .addReg(Arg));
2020
0
      RegArgs.push_back(VA.getLocReg());
2021
0
      RegArgs.push_back(NextVA.getLocReg());
2022
561
    } else {
2023
561
      assert(VA.isMemLoc());
2024
561
      // Need to store on the stack.
2025
561
2026
561
      // Don't emit stores for undef values.
2027
561
      if (isa<UndefValue>(ArgVal))
2028
11
        continue;
2029
550
2030
550
      Address Addr;
2031
550
      Addr.BaseType = Address::RegBase;
2032
550
      Addr.Base.Reg = ARM::SP;
2033
550
      Addr.Offset = VA.getLocMemOffset();
2034
550
2035
550
      bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2036
550
      assert(EmitRet && "Could not emit a store for argument!");
2037
550
    }
2038
1.30k
  }
2039
476
2040
476
  return true;
2041
482
}
2042
2043
bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2044
                             const Instruction *I, CallingConv::ID CC,
2045
476
                             unsigned &NumBytes, bool isVarArg) {
2046
476
  // Issue CALLSEQ_END
2047
476
  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2048
476
  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2049
476
                          TII.get(AdjStackUp))
2050
476
                  .addImm(NumBytes).addImm(0));
2051
476
2052
476
  // Now the return value.
2053
476
  if (
RetVT != MVT::isVoid476
) {
2054
235
    SmallVector<CCValAssign, 16> RVLocs;
2055
235
    CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2056
235
    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2057
235
2058
235
    // Copy all of the result registers out of their specified physreg.
2059
235
    if (
RVLocs.size() == 2 && 235
RetVT == MVT::f640
) {
2060
0
      // For this move we copy into two registers and then move into the
2061
0
      // double fp reg we want.
2062
0
      MVT DestVT = RVLocs[0].getValVT();
2063
0
      const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2064
0
      unsigned ResultReg = createResultReg(DstRC);
2065
0
      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2066
0
                              TII.get(ARM::VMOVDRR), ResultReg)
2067
0
                      .addReg(RVLocs[0].getLocReg())
2068
0
                      .addReg(RVLocs[1].getLocReg()));
2069
0
2070
0
      UsedRegs.push_back(RVLocs[0].getLocReg());
2071
0
      UsedRegs.push_back(RVLocs[1].getLocReg());
2072
0
2073
0
      // Finally update the result.
2074
0
      updateValueMap(I, ResultReg);
2075
235
    } else {
2076
235
      assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2077
235
      MVT CopyVT = RVLocs[0].getValVT();
2078
235
2079
235
      // Special handling for extended integers.
2080
235
      if (
RetVT == MVT::i1 || 235
RetVT == MVT::i8226
||
RetVT == MVT::i16208
)
2081
45
        CopyVT = MVT::i32;
2082
235
2083
235
      const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2084
235
2085
235
      unsigned ResultReg = createResultReg(DstRC);
2086
235
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2087
235
              TII.get(TargetOpcode::COPY),
2088
235
              ResultReg).addReg(RVLocs[0].getLocReg());
2089
235
      UsedRegs.push_back(RVLocs[0].getLocReg());
2090
235
2091
235
      // Finally update the result.
2092
235
      updateValueMap(I, ResultReg);
2093
235
    }
2094
235
  }
2095
476
2096
476
  return true;
2097
476
}
2098
2099
895
bool ARMFastISel::SelectRet(const Instruction *I) {
2100
895
  const ReturnInst *Ret = cast<ReturnInst>(I);
2101
895
  const Function &F = *I->getParent()->getParent();
2102
895
2103
895
  if (!FuncInfo.CanLowerReturn)
2104
2
    return false;
2105
893
2106
893
  
if (893
TLI.supportSwiftError() &&
2107
893
      F.getAttributes().hasAttrSomewhere(Attribute::SwiftError))
2108
12
    return false;
2109
881
2110
881
  
if (881
TLI.supportSplitCSR(FuncInfo.MF)881
)
2111
6
    return false;
2112
875
2113
875
  // Build a list of return value registers.
2114
875
  SmallVector<unsigned, 4> RetRegs;
2115
875
2116
875
  CallingConv::ID CC = F.getCallingConv();
2117
875
  if (
Ret->getNumOperands() > 0875
) {
2118
451
    SmallVector<ISD::OutputArg, 4> Outs;
2119
451
    GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
2120
451
2121
451
    // Analyze operands of the call, assigning locations to each operand.
2122
451
    SmallVector<CCValAssign, 16> ValLocs;
2123
451
    CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2124
451
    CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2125
451
                                                 F.isVarArg()));
2126
451
2127
451
    const Value *RV = Ret->getOperand(0);
2128
451
    unsigned Reg = getRegForValue(RV);
2129
451
    if (Reg == 0)
2130
26
      return false;
2131
425
2132
425
    // Only handle a single return value for now.
2133
425
    
if (425
ValLocs.size() != 1425
)
2134
1
      return false;
2135
424
2136
424
    CCValAssign &VA = ValLocs[0];
2137
424
2138
424
    // Don't bother handling odd stuff for now.
2139
424
    if (VA.getLocInfo() != CCValAssign::Full)
2140
7
      return false;
2141
417
    // Only handle register returns for now.
2142
417
    
if (417
!VA.isRegLoc()417
)
2143
0
      return false;
2144
417
2145
417
    unsigned SrcReg = Reg + VA.getValNo();
2146
417
    EVT RVEVT = TLI.getValueType(DL, RV->getType());
2147
417
    if (
!RVEVT.isSimple()417
)
return false0
;
2148
417
    MVT RVVT = RVEVT.getSimpleVT();
2149
417
    MVT DestVT = VA.getValVT();
2150
417
    // Special handling for extended integers.
2151
417
    if (
RVVT != DestVT417
) {
2152
99
      if (
RVVT != MVT::i1 && 99
RVVT != MVT::i888
&&
RVVT != MVT::i1662
)
2153
0
        return false;
2154
99
2155
99
      assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2156
99
2157
99
      // Perform extension if flagged as either zext or sext.  Otherwise, do
2158
99
      // nothing.
2159
99
      if (
Outs[0].Flags.isZExt() || 99
Outs[0].Flags.isSExt()55
) {
2160
60
        SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2161
60
        if (
SrcReg == 060
)
return false0
;
2162
417
      }
2163
99
    }
2164
417
2165
417
    // Make the copy.
2166
417
    unsigned DstReg = VA.getLocReg();
2167
417
    const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2168
417
    // Avoid a cross-class copy. This is very unlikely.
2169
417
    if (!SrcRC->contains(DstReg))
2170
0
      return false;
2171
417
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2172
417
            TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
2173
417
2174
417
    // Add register to return instruction.
2175
417
    RetRegs.push_back(VA.getLocReg());
2176
417
  }
2177
875
2178
841
  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2179
841
                                    TII.get(Subtarget->getReturnOpcode()));
2180
841
  AddOptionalDefs(MIB);
2181
841
  for (unsigned R : RetRegs)
2182
417
    MIB.addReg(R, RegState::Implicit);
2183
841
  return true;
2184
895
}
2185
2186
476
unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2187
476
  if (UseReg)
2188
82
    
return isThumb2 ? 82
ARM::tBLXr30
:
ARM::BLX52
;
2189
476
  else
2190
394
    
return isThumb2 ? 394
ARM::tBL160
:
ARM::BL234
;
2191
0
}
2192
2193
12
unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2194
12
  // Manually compute the global's type to avoid building it when unnecessary.
2195
12
  Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2196
12
  EVT LCREVT = TLI.getValueType(DL, GVTy);
2197
12
  if (
!LCREVT.isSimple()12
)
return 00
;
2198
12
2199
12
  GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false,
2200
12
                                       GlobalValue::ExternalLinkage, nullptr,
2201
12
                                       Name);
2202
12
  assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2203
12
  return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2204
12
}
2205
2206
// A quick function that will emit a call for a named libcall in F with the
2207
// vector of passed arguments for the Instruction in I. We can assume that we
2208
// can emit a call for any libcall we can produce. This is an abridged version
2209
// of the full call infrastructure since we won't need to worry about things
2210
// like computed function pointers or strange arguments at call sites.
2211
// TODO: Try to unify this and the normal call bits for ARM, then try to unify
2212
// with X86.
2213
25
bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2214
25
  CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2215
25
2216
25
  // Handle *simple* calls for now.
2217
25
  Type *RetTy = I->getType();
2218
25
  MVT RetVT;
2219
25
  if (RetTy->isVoidTy())
2220
0
    RetVT = MVT::isVoid;
2221
25
  else 
if (25
!isTypeLegal(RetTy, RetVT)25
)
2222
0
    return false;
2223
25
2224
25
  // Can't handle non-double multi-reg retvals.
2225
25
  
if (25
RetVT != MVT::isVoid && 25
RetVT != MVT::i3225
) {
2226
0
    SmallVector<CCValAssign, 16> RVLocs;
2227
0
    CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2228
0
    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2229
0
    if (
RVLocs.size() >= 2 && 0
RetVT != MVT::f640
)
2230
0
      return false;
2231
25
  }
2232
25
2233
25
  // Set up the argument vectors.
2234
25
  SmallVector<Value*, 8> Args;
2235
25
  SmallVector<unsigned, 8> ArgRegs;
2236
25
  SmallVector<MVT, 8> ArgVTs;
2237
25
  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2238
25
  Args.reserve(I->getNumOperands());
2239
25
  ArgRegs.reserve(I->getNumOperands());
2240
25
  ArgVTs.reserve(I->getNumOperands());
2241
25
  ArgFlags.reserve(I->getNumOperands());
2242
50
  for (Value *Op :  I->operands()) {
2243
50
    unsigned Arg = getRegForValue(Op);
2244
50
    if (
Arg == 050
)
return false0
;
2245
50
2246
50
    Type *ArgTy = Op->getType();
2247
50
    MVT ArgVT;
2248
50
    if (
!isTypeLegal(ArgTy, ArgVT)50
)
return false0
;
2249
50
2250
50
    ISD::ArgFlagsTy Flags;
2251
50
    unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2252
50
    Flags.setOrigAlign(OriginalAlignment);
2253
50
2254
50
    Args.push_back(Op);
2255
50
    ArgRegs.push_back(Arg);
2256
50
    ArgVTs.push_back(ArgVT);
2257
50
    ArgFlags.push_back(Flags);
2258
50
  }
2259
25
2260
25
  // Handle the arguments now that we've gotten them.
2261
25
  SmallVector<unsigned, 4> RegArgs;
2262
25
  unsigned NumBytes;
2263
25
  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2264
25
                       RegArgs, CC, NumBytes, false))
2265
0
    return false;
2266
25
2267
25
  unsigned CalleeReg = 0;
2268
25
  if (
Subtarget->genLongCalls()25
) {
2269
3
    CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2270
3
    if (
CalleeReg == 03
)
return false0
;
2271
25
  }
2272
25
2273
25
  // Issue the call.
2274
25
  unsigned CallOpc = ARMSelectCallOp(Subtarget->genLongCalls());
2275
25
  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2276
25
                                    DbgLoc, TII.get(CallOpc));
2277
25
  // BL / BLX don't take a predicate, but tBL / tBLX do.
2278
25
  if (isThumb2)
2279
3
    MIB.add(predOps(ARMCC::AL));
2280
25
  if (Subtarget->genLongCalls())
2281
3
    MIB.addReg(CalleeReg);
2282
25
  else
2283
22
    MIB.addExternalSymbol(TLI.getLibcallName(Call));
2284
25
2285
25
  // Add implicit physical register uses to the call.
2286
25
  for (unsigned R : RegArgs)
2287
50
    MIB.addReg(R, RegState::Implicit);
2288
25
2289
25
  // Add a register mask with the call-preserved registers.
2290
25
  // Proper defs for return values will be added by setPhysRegsDeadExcept().
2291
25
  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2292
25
2293
25
  // Finish off the call including any return values.
2294
25
  SmallVector<unsigned, 4> UsedRegs;
2295
25
  if (
!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)25
)
return false0
;
2296
25
2297
25
  // Set all unused physreg defs as dead.
2298
25
  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2299
25
2300
25
  return true;
2301
25
}
2302
2303
bool ARMFastISel::SelectCall(const Instruction *I,
2304
633
                             const char *IntrMemName = nullptr) {
2305
633
  const CallInst *CI = cast<CallInst>(I);
2306
633
  const Value *Callee = CI->getCalledValue();
2307
633
2308
633
  // Can't handle inline asm.
2309
633
  if (
isa<InlineAsm>(Callee)633
)
return false11
;
2310
622
2311
622
  // Allow SelectionDAG isel to handle tail calls.
2312
622
  
if (622
CI->isTailCall()622
)
return false91
;
2313
531
2314
531
  // Check the calling convention.
2315
531
  ImmutableCallSite CS(CI);
2316
531
  CallingConv::ID CC = CS.getCallingConv();
2317
531
2318
531
  // TODO: Avoid some calling conventions?
2319
531
2320
531
  FunctionType *FTy = CS.getFunctionType();
2321
531
  bool isVarArg = FTy->isVarArg();
2322
531
2323
531
  // Handle *simple* calls for now.
2324
531
  Type *RetTy = I->getType();
2325
531
  MVT RetVT;
2326
531
  if (RetTy->isVoidTy())
2327
305
    RetVT = MVT::isVoid;
2328
226
  else 
if (226
!isTypeLegal(RetTy, RetVT) && 226
RetVT != MVT::i1652
&&
2329
226
           
RetVT != MVT::i834
&&
RetVT != MVT::i116
)
2330
7
    return false;
2331
524
2332
524
  // Can't handle non-double multi-reg retvals.
2333
524
  
if (524
RetVT != MVT::isVoid && 524
RetVT != MVT::i1219
&&
RetVT != MVT::i8210
&&
2334
524
      
RetVT != MVT::i16192
&&
RetVT != MVT::i32174
) {
2335
3
    SmallVector<CCValAssign, 16> RVLocs;
2336
3
    CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2337
3
    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2338
3
    if (
RVLocs.size() >= 2 && 3
RetVT != MVT::f643
)
2339
3
      return false;
2340
521
  }
2341
521
2342
521
  // Set up the argument vectors.
2343
521
  SmallVector<Value*, 8> Args;
2344
521
  SmallVector<unsigned, 8> ArgRegs;
2345
521
  SmallVector<MVT, 8> ArgVTs;
2346
521
  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2347
521
  unsigned arg_size = CS.arg_size();
2348
521
  Args.reserve(arg_size);
2349
521
  ArgRegs.reserve(arg_size);
2350
521
  ArgVTs.reserve(arg_size);
2351
521
  ArgFlags.reserve(arg_size);
2352
521
  for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2353
1.80k
       
i != e1.80k
;
++i1.28k
) {
2354
1.36k
    // If we're lowering a memory intrinsic instead of a regular call, skip the
2355
1.36k
    // last two arguments, which shouldn't be passed to the underlying function.
2356
1.36k
    if (
IntrMemName && 1.36k
e-i <= 280
)
2357
20
      break;
2358
1.34k
2359
1.34k
    ISD::ArgFlagsTy Flags;
2360
1.34k
    unsigned ArgIdx = i - CS.arg_begin();
2361
1.34k
    if (CS.paramHasAttr(ArgIdx, Attribute::SExt))
2362
19
      Flags.setSExt();
2363
1.34k
    if (CS.paramHasAttr(ArgIdx, Attribute::ZExt))
2364
107
      Flags.setZExt();
2365
1.34k
2366
1.34k
    // FIXME: Only handle *easy* calls for now.
2367
1.34k
    if (CS.paramHasAttr(ArgIdx, Attribute::InReg) ||
2368
1.34k
        CS.paramHasAttr(ArgIdx, Attribute::StructRet) ||
2369
1.30k
        CS.paramHasAttr(ArgIdx, Attribute::SwiftSelf) ||
2370
1.29k
        CS.paramHasAttr(ArgIdx, Attribute::SwiftError) ||
2371
1.29k
        CS.paramHasAttr(ArgIdx, Attribute::Nest) ||
2372
1.29k
        CS.paramHasAttr(ArgIdx, Attribute::ByVal))
2373
51
      return false;
2374
1.29k
2375
1.29k
    Type *ArgTy = (*i)->getType();
2376
1.29k
    MVT ArgVT;
2377
1.29k
    if (
!isTypeLegal(ArgTy, ArgVT) && 1.29k
ArgVT != MVT::i16147
&&
ArgVT != MVT::i8116
&&
2378
24
        ArgVT != MVT::i1)
2379
13
      return false;
2380
1.28k
2381
1.28k
    unsigned Arg = getRegForValue(*i);
2382
1.28k
    if (Arg == 0)
2383
0
      return false;
2384
1.28k
2385
1.28k
    unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2386
1.28k
    Flags.setOrigAlign(OriginalAlignment);
2387
1.28k
2388
1.28k
    Args.push_back(*i);
2389
1.28k
    ArgRegs.push_back(Arg);
2390
1.28k
    ArgVTs.push_back(ArgVT);
2391
1.28k
    ArgFlags.push_back(Flags);
2392
1.28k
  }
2393
521
2394
521
  // Handle the arguments now that we've gotten them.
2395
457
  SmallVector<unsigned, 4> RegArgs;
2396
457
  unsigned NumBytes;
2397
457
  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2398
457
                       RegArgs, CC, NumBytes, isVarArg))
2399
6
    return false;
2400
451
2401
451
  bool UseReg = false;
2402
451
  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2403
451
  if (
!GV || 451
Subtarget->genLongCalls()437
)
UseReg = true79
;
2404
451
2405
451
  unsigned CalleeReg = 0;
2406
451
  if (
UseReg451
) {
2407
79
    if (IntrMemName)
2408
9
      CalleeReg = getLibcallReg(IntrMemName);
2409
79
    else
2410
70
      CalleeReg = getRegForValue(Callee);
2411
79
2412
79
    if (
CalleeReg == 079
)
return false0
;
2413
451
  }
2414
451
2415
451
  // Issue the call.
2416
451
  unsigned CallOpc = ARMSelectCallOp(UseReg);
2417
451
  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2418
451
                                    DbgLoc, TII.get(CallOpc));
2419
451
2420
451
  // ARM calls don't take a predicate, but tBL / tBLX do.
2421
451
  if(isThumb2)
2422
187
    MIB.add(predOps(ARMCC::AL));
2423
451
  if (UseReg)
2424
79
    MIB.addReg(CalleeReg);
2425
372
  else 
if (372
!IntrMemName372
)
2426
361
    MIB.addGlobalAddress(GV, 0, 0);
2427
372
  else
2428
11
    MIB.addExternalSymbol(IntrMemName, 0);
2429
451
2430
451
  // Add implicit physical register uses to the call.
2431
451
  for (unsigned R : RegArgs)
2432
695
    MIB.addReg(R, RegState::Implicit);
2433
451
2434
451
  // Add a register mask with the call-preserved registers.
2435
451
  // Proper defs for return values will be added by setPhysRegsDeadExcept().
2436
451
  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2437
451
2438
451
  // Finish off the call including any return values.
2439
451
  SmallVector<unsigned, 4> UsedRegs;
2440
451
  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2441
0
    return false;
2442
451
2443
451
  // Set all unused physreg defs as dead.
2444
451
  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2445
451
2446
451
  return true;
2447
451
}
2448
2449
60
bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2450
60
  return Len <= 16;
2451
60
}
2452
2453
bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2454
26
                                        uint64_t Len, unsigned Alignment) {
2455
26
  // Make sure we don't bloat code by inlining very large memcpy's.
2456
26
  if (!ARMIsMemCpySmall(Len))
2457
0
    return false;
2458
26
2459
154
  
while (26
Len154
) {
2460
128
    MVT VT;
2461
128
    if (
!Alignment || 128
Alignment >= 4128
) {
2462
26
      if (Len >= 4)
2463
20
        VT = MVT::i32;
2464
6
      else 
if (6
Len >= 26
)
2465
6
        VT = MVT::i16;
2466
0
      else {
2467
0
        assert(Len == 1 && "Expected a length of 1!");
2468
0
        VT = MVT::i8;
2469
0
      }
2470
128
    } else {
2471
102
      // Bound based on alignment.
2472
102
      if (
Len >= 2 && 102
Alignment == 290
)
2473
36
        VT = MVT::i16;
2474
66
      else {
2475
66
        VT = MVT::i8;
2476
66
      }
2477
102
    }
2478
128
2479
128
    bool RV;
2480
128
    unsigned ResultReg;
2481
128
    RV = ARMEmitLoad(VT, ResultReg, Src);
2482
128
    assert(RV && "Should be able to handle this load.");
2483
128
    RV = ARMEmitStore(VT, ResultReg, Dest);
2484
128
    assert(RV && "Should be able to handle this store.");
2485
128
    (void)RV;
2486
128
2487
128
    unsigned Size = VT.getSizeInBits()/8;
2488
128
    Len -= Size;
2489
128
    Dest.Offset += Size;
2490
128
    Src.Offset += Size;
2491
128
  }
2492
26
2493
26
  return true;
2494
26
}
2495
2496
73
bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2497
73
  // FIXME: Handle more intrinsics.
2498
73
  switch (I.getIntrinsicID()) {
2499
14
  default: return false;
2500
9
  case Intrinsic::frameaddress: {
2501
9
    MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo();
2502
9
    MFI.setFrameAddressIsTaken(true);
2503
9
2504
9
    unsigned LdrOpc = isThumb2 ? 
ARM::t2LDRi123
:
ARM::LDRi126
;
2505
3
    const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
2506
6
                                             : &ARM::GPRRegClass;
2507
9
2508
9
    const ARMBaseRegisterInfo *RegInfo =
2509
9
        static_cast<const ARMBaseRegisterInfo *>(Subtarget->getRegisterInfo());
2510
9
    unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2511
9
    unsigned SrcReg = FramePtr;
2512
9
2513
9
    // Recursively load frame address
2514
9
    // ldr r0 [fp]
2515
9
    // ldr r0 [r0]
2516
9
    // ldr r0 [r0]
2517
9
    // ...
2518
9
    unsigned DestReg;
2519
9
    unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2520
21
    while (
Depth--21
) {
2521
12
      DestReg = createResultReg(RC);
2522
12
      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2523
12
                              TII.get(LdrOpc), DestReg)
2524
12
                      .addReg(SrcReg).addImm(0));
2525
12
      SrcReg = DestReg;
2526
12
    }
2527
9
    updateValueMap(&I, SrcReg);
2528
9
    return true;
2529
73
  }
2530
40
  case Intrinsic::memcpy:
2531
40
  case Intrinsic::memmove: {
2532
40
    const MemTransferInst &MTI = cast<MemTransferInst>(I);
2533
40
    // Don't handle volatile.
2534
40
    if (MTI.isVolatile())
2535
0
      return false;
2536
40
2537
40
    // Disable inlining for memmove before calls to ComputeAddress.  Otherwise,
2538
40
    // we would emit dead code because we don't currently handle memmoves.
2539
40
    bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2540
40
    if (
isa<ConstantInt>(MTI.getLength()) && 40
isMemCpy40
) {
2541
34
      // Small memcpy's are common enough that we want to do them without a call
2542
34
      // if possible.
2543
34
      uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2544
34
      if (
ARMIsMemCpySmall(Len)34
) {
2545
26
        Address Dest, Src;
2546
26
        if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2547
26
            !ARMComputeAddress(MTI.getRawSource(), Src))
2548
0
          return false;
2549
26
        unsigned Alignment = MTI.getAlignment();
2550
26
        if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2551
26
          return true;
2552
14
      }
2553
34
    }
2554
14
2555
14
    
if (14
!MTI.getLength()->getType()->isIntegerTy(32)14
)
2556
0
      return false;
2557
14
2558
14
    
if (14
MTI.getSourceAddressSpace() > 255 || 14
MTI.getDestAddressSpace() > 25514
)
2559
0
      return false;
2560
14
2561
14
    
const char *IntrMemName = isa<MemCpyInst>(I) ? 14
"memcpy"8
:
"memmove"6
;
2562
14
    return SelectCall(&I, IntrMemName);
2563
14
  }
2564
6
  case Intrinsic::memset: {
2565
6
    const MemSetInst &MSI = cast<MemSetInst>(I);
2566
6
    // Don't handle volatile.
2567
6
    if (MSI.isVolatile())
2568
0
      return false;
2569
6
2570
6
    
if (6
!MSI.getLength()->getType()->isIntegerTy(32)6
)
2571
0
      return false;
2572
6
2573
6
    
if (6
MSI.getDestAddressSpace() > 2556
)
2574
0
      return false;
2575
6
2576
6
    return SelectCall(&I, "memset");
2577
6
  }
2578
4
  case Intrinsic::trap: {
2579
4
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
2580
4
      Subtarget->useNaClTrap() ? 
ARM::TRAPNaCl0
:
ARM::TRAP4
));
2581
4
    return true;
2582
0
  }
2583
73
  }
2584
73
}
2585
2586
22
bool ARMFastISel::SelectTrunc(const Instruction *I) {
2587
22
  // The high bits for a type smaller than the register size are assumed to be
2588
22
  // undefined.
2589
22
  Value *Op = I->getOperand(0);
2590
22
2591
22
  EVT SrcVT, DestVT;
2592
22
  SrcVT = TLI.getValueType(DL, Op->getType(), true);
2593
22
  DestVT = TLI.getValueType(DL, I->getType(), true);
2594
22
2595
22
  if (
SrcVT != MVT::i32 && 22
SrcVT != MVT::i1610
&&
SrcVT != MVT::i84
)
2596
1
    return false;
2597
21
  
if (21
DestVT != MVT::i16 && 21
DestVT != MVT::i89
&&
DestVT != MVT::i13
)
2598
0
    return false;
2599
21
2600
21
  unsigned SrcReg = getRegForValue(Op);
2601
21
  if (
!SrcReg21
)
return false0
;
2602
21
2603
21
  // Because the high bits are undefined, a truncate doesn't generate
2604
21
  // any code.
2605
21
  updateValueMap(I, SrcReg);
2606
21
  return true;
2607
21
}
2608
2609
unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2610
396
                                    bool isZExt) {
2611
396
  if (
DestVT != MVT::i32 && 396
DestVT != MVT::i1627
&&
DestVT != MVT::i89
)
2612
0
    return 0;
2613
396
  
if (396
SrcVT != MVT::i16 && 396
SrcVT != MVT::i8263
&&
SrcVT != MVT::i174
)
2614
0
    return 0;
2615
396
2616
396
  // Table of which combinations can be emitted as a single instruction,
2617
396
  // and which will require two.
2618
396
  static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2619
396
    //            ARM                     Thumb
2620
396
    //           !hasV6Ops  hasV6Ops     !hasV6Ops  hasV6Ops
2621
396
    //    ext:     s  z      s  z          s  z      s  z
2622
396
    /*  1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2623
396
    /*  8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2624
396
    /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2625
396
  };
2626
396
2627
396
  // Target registers for:
2628
396
  //  - For ARM can never be PC.
2629
396
  //  - For 16-bit Thumb are restricted to lower 8 registers.
2630
396
  //  - For 32-bit Thumb are restricted to non-SP and non-PC.
2631
396
  static const TargetRegisterClass *RCTbl[2][2] = {
2632
396
    // Instructions: Two                     Single
2633
396
    /* ARM      */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2634
396
    /* Thumb    */ { &ARM::tGPRRegClass,    &ARM::rGPRRegClass    }
2635
396
  };
2636
396
2637
396
  // Table governing the instruction(s) to be emitted.
2638
396
  static const struct InstructionTable {
2639
396
    uint32_t Opc   : 16;
2640
396
    uint32_t hasS  :  1; // Some instructions have an S bit, always set it to 0.
2641
396
    uint32_t Shift :  7; // For shift operand addressing mode, used by MOVsi.
2642
396
    uint32_t Imm   :  8; // All instructions have either a shift or a mask.
2643
396
  } IT[2][2][3][2] = {
2644
396
    { // Two instructions (first is left shift, second is in this table).
2645
396
      { // ARM                Opc           S  Shift             Imm
2646
396
        /*  1 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  31 },
2647
396
        /*  1 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  31 } },
2648
396
        /*  8 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  24 },
2649
396
        /*  8 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  24 } },
2650
396
        /* 16 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  16 },
2651
396
        /* 16 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  16 } }
2652
396
      },
2653
396
      { // Thumb              Opc           S  Shift             Imm
2654
396
        /*  1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  31 },
2655
396
        /*  1 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  31 } },
2656
396
        /*  8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  24 },
2657
396
        /*  8 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  24 } },
2658
396
        /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  16 },
2659
396
        /* 16 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  16 } }
2660
396
      }
2661
396
    },
2662
396
    { // Single instruction.
2663
396
      { // ARM                Opc           S  Shift             Imm
2664
396
        /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },
2665
396
        /*  1 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift,   1 } },
2666
396
        /*  8 bit sext */ { { ARM::SXTB   , 0, ARM_AM::no_shift,   0 },
2667
396
        /*  8 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift, 255 } },
2668
396
        /* 16 bit sext */ { { ARM::SXTH   , 0, ARM_AM::no_shift,   0 },
2669
396
        /* 16 bit zext */   { ARM::UXTH   , 0, ARM_AM::no_shift,   0 } }
2670
396
      },
2671
396
      { // Thumb              Opc           S  Shift             Imm
2672
396
        /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },
2673
396
        /*  1 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift,   1 } },
2674
396
        /*  8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift,   0 },
2675
396
        /*  8 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2676
396
        /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift,   0 },
2677
396
        /* 16 bit zext */   { ARM::t2UXTH , 0, ARM_AM::no_shift,   0 } }
2678
396
      }
2679
396
    }
2680
396
  };
2681
396
2682
396
  unsigned SrcBits = SrcVT.getSizeInBits();
2683
396
  unsigned DestBits = DestVT.getSizeInBits();
2684
396
  (void) DestBits;
2685
396
  assert((SrcBits < DestBits) && "can only extend to larger types");
2686
396
  assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2687
396
         "other sizes unimplemented");
2688
396
  assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2689
396
         "other sizes unimplemented");
2690
396
2691
396
  bool hasV6Ops = Subtarget->hasV6Ops();
2692
396
  unsigned Bitness = SrcBits / 8;  // {1,8,16}=>{0,1,2}
2693
396
  assert((Bitness < 3) && "sanity-check table bounds");
2694
396
2695
396
  bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2696
396
  const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2697
396
  const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2698
396
  unsigned Opc = ITP->Opc;
2699
396
  assert(ARM::KILL != Opc && "Invalid table entry");
2700
396
  unsigned hasS = ITP->hasS;
2701
396
  ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2702
396
  assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2703
396
         "only MOVsi has shift operand addressing mode");
2704
396
  unsigned Imm = ITP->Imm;
2705
396
2706
396
  // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2707
396
  bool setsCPSR = &ARM::tGPRRegClass == RC;
2708
396
  unsigned LSLOpc = isThumb2 ? 
ARM::tLSLri130
:
ARM::MOVsi266
;
2709
396
  unsigned ResultReg;
2710
396
  // MOVsi encodes shift and immediate in shift operand addressing mode.
2711
396
  // The following condition has the same value when emitting two
2712
396
  // instruction sequences: both are shifts.
2713
396
  bool ImmIsSO = (Shift != ARM_AM::no_shift);
2714
396
2715
396
  // Either one or two instructions are emitted.
2716
396
  // They're always of the form:
2717
396
  //   dst = in OP imm
2718
396
  // CPSR is set only by 16-bit Thumb instructions.
2719
396
  // Predicate, if any, is AL.
2720
396
  // S bit, if available, is always 0.
2721
396
  // When two are emitted the first's result will feed as the second's input,
2722
396
  // that value is then dead.
2723
396
  unsigned NumInstrsEmitted = isSingleInstr ? 
1387
:
29
;
2724
801
  for (unsigned Instr = 0; 
Instr != NumInstrsEmitted801
;
++Instr405
) {
2725
405
    ResultReg = createResultReg(RC);
2726
396
    bool isLsl = (0 == Instr) && !isSingleInstr;
2727
405
    unsigned Opcode = isLsl ? 
LSLOpc9
:
Opc396
;
2728
405
    ARM_AM::ShiftOpc ShiftAM = isLsl ? 
ARM_AM::lsl9
:
Shift396
;
2729
405
    unsigned ImmEnc = ImmIsSO ? 
ARM_AM::getSORegOpc(ShiftAM, Imm)12
:
Imm393
;
2730
405
    bool isKill = 1 == Instr;
2731
405
    MachineInstrBuilder MIB = BuildMI(
2732
405
        *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
2733
405
    if (setsCPSR)
2734
6
      MIB.addReg(ARM::CPSR, RegState::Define);
2735
405
    SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2736
405
    MIB.addReg(SrcReg, isKill * RegState::Kill)
2737
405
        .addImm(ImmEnc)
2738
405
        .add(predOps(ARMCC::AL));
2739
405
    if (hasS)
2740
207
      MIB.add(condCodeOp());
2741
405
    // Second instruction consumes the first's result.
2742
405
    SrcReg = ResultReg;
2743
405
  }
2744
396
2745
396
  return ResultReg;
2746
396
}
2747
2748
136
bool ARMFastISel::SelectIntExt(const Instruction *I) {
2749
136
  // On ARM, in general, integer casts don't involve legal types; this code
2750
136
  // handles promotable integers.
2751
136
  Type *DestTy = I->getType();
2752
136
  Value *Src = I->getOperand(0);
2753
136
  Type *SrcTy = Src->getType();
2754
136
2755
136
  bool isZExt = isa<ZExtInst>(I);
2756
136
  unsigned SrcReg = getRegForValue(Src);
2757
136
  if (
!SrcReg136
)
return false2
;
2758
134
2759
134
  EVT SrcEVT, DestEVT;
2760
134
  SrcEVT = TLI.getValueType(DL, SrcTy, true);
2761
134
  DestEVT = TLI.getValueType(DL, DestTy, true);
2762
134
  if (
!SrcEVT.isSimple()134
)
return false0
;
2763
134
  
if (134
!DestEVT.isSimple()134
)
return false0
;
2764
134
2765
134
  MVT SrcVT = SrcEVT.getSimpleVT();
2766
134
  MVT DestVT = DestEVT.getSimpleVT();
2767
134
  unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2768
134
  if (
ResultReg == 0134
)
return false0
;
2769
134
  updateValueMap(I, ResultReg);
2770
134
  return true;
2771
134
}
2772
2773
bool ARMFastISel::SelectShift(const Instruction *I,
2774
12
                              ARM_AM::ShiftOpc ShiftTy) {
2775
12
  // We handle thumb2 mode by target independent selector
2776
12
  // or SelectionDAG ISel.
2777
12
  if (isThumb2)
2778
0
    return false;
2779
12
2780
12
  // Only handle i32 now.
2781
12
  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
2782
12
  if (DestVT != MVT::i32)
2783
0
    return false;
2784
12
2785
12
  unsigned Opc = ARM::MOVsr;
2786
12
  unsigned ShiftImm;
2787
12
  Value *Src2Value = I->getOperand(1);
2788
12
  if (const ConstantInt *
CI12
= dyn_cast<ConstantInt>(Src2Value)) {
2789
6
    ShiftImm = CI->getZExtValue();
2790
6
2791
6
    // Fall back to selection DAG isel if the shift amount
2792
6
    // is zero or greater than the width of the value type.
2793
6
    if (
ShiftImm == 0 || 6
ShiftImm >=326
)
2794
0
      return false;
2795
6
2796
6
    Opc = ARM::MOVsi;
2797
6
  }
2798
12
2799
12
  Value *Src1Value = I->getOperand(0);
2800
12
  unsigned Reg1 = getRegForValue(Src1Value);
2801
12
  if (
Reg1 == 012
)
return false0
;
2802
12
2803
12
  unsigned Reg2 = 0;
2804
12
  if (
Opc == ARM::MOVsr12
) {
2805
6
    Reg2 = getRegForValue(Src2Value);
2806
6
    if (
Reg2 == 06
)
return false0
;
2807
12
  }
2808
12
2809
12
  unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2810
12
  if(
ResultReg == 012
)
return false0
;
2811
12
2812
12
  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2813
12
                                    TII.get(Opc), ResultReg)
2814
12
                            .addReg(Reg1);
2815
12
2816
12
  if (Opc == ARM::MOVsi)
2817
6
    MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2818
6
  else 
if (6
Opc == ARM::MOVsr6
) {
2819
6
    MIB.addReg(Reg2);
2820
6
    MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2821
6
  }
2822
12
2823
12
  AddOptionalDefs(MIB);
2824
12
  updateValueMap(I, ResultReg);
2825
12
  return true;
2826
12
}
2827
2828
// TODO: SoftFP support.
2829
3.04k
bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
2830
3.04k
  switch (I->getOpcode()) {
2831
322
    case Instruction::Load:
2832
322
      return SelectLoad(I);
2833
599
    case Instruction::Store:
2834
599
      return SelectStore(I);
2835
79
    case Instruction::Br:
2836
79
      return SelectBranch(I);
2837
4
    case Instruction::IndirectBr:
2838
4
      return SelectIndirectBr(I);
2839
26
    case Instruction::ICmp:
2840
26
    case Instruction::FCmp:
2841
26
      return SelectCmp(I);
2842
1
    case Instruction::FPExt:
2843
1
      return SelectFPExt(I);
2844
1
    case Instruction::FPTrunc:
2845
1
      return SelectFPTrunc(I);
2846
19
    case Instruction::SIToFP:
2847
19
      return SelectIToFP(I, /*isSigned*/ true);
2848
18
    case Instruction::UIToFP:
2849
18
      return SelectIToFP(I, /*isSigned*/ false);
2850
6
    case Instruction::FPToSI:
2851
6
      return SelectFPToI(I, /*isSigned*/ true);
2852
7
    case Instruction::FPToUI:
2853
7
      return SelectFPToI(I, /*isSigned*/ false);
2854
22
    case Instruction::Add:
2855
22
      return SelectBinaryIntOp(I, ISD::ADD);
2856
6
    case Instruction::Or:
2857
6
      return SelectBinaryIntOp(I, ISD::OR);
2858
9
    case Instruction::Sub:
2859
9
      return SelectBinaryIntOp(I, ISD::SUB);
2860
2
    case Instruction::FAdd:
2861
2
      return SelectBinaryFPOp(I, ISD::FADD);
2862
0
    case Instruction::FSub:
2863
0
      return SelectBinaryFPOp(I, ISD::FSUB);
2864
0
    case Instruction::FMul:
2865
0
      return SelectBinaryFPOp(I, ISD::FMUL);
2866
4
    case Instruction::SDiv:
2867
4
      return SelectDiv(I, /*isSigned*/ true);
2868
10
    case Instruction::UDiv:
2869
10
      return SelectDiv(I, /*isSigned*/ false);
2870
31
    case Instruction::SRem:
2871
31
      return SelectRem(I, /*isSigned*/ true);
2872
5
    case Instruction::URem:
2873
5
      return SelectRem(I, /*isSigned*/ false);
2874
686
    case Instruction::Call:
2875
686
      if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2876
73
        return SelectIntrinsicCall(*II);
2877
613
      return SelectCall(I);
2878
24
    case Instruction::Select:
2879
24
      return SelectSelect(I);
2880
895
    case Instruction::Ret:
2881
895
      return SelectRet(I);
2882
22
    case Instruction::Trunc:
2883
22
      return SelectTrunc(I);
2884
136
    case Instruction::ZExt:
2885
136
    case Instruction::SExt:
2886
136
      return SelectIntExt(I);
2887
4
    case Instruction::Shl:
2888
4
      return SelectShift(I, ARM_AM::lsl);
2889
4
    case Instruction::LShr:
2890
4
      return SelectShift(I, ARM_AM::lsr);
2891
4
    case Instruction::AShr:
2892
4
      return SelectShift(I, ARM_AM::asr);
2893
100
    default: break;
2894
100
  }
2895
100
  return false;
2896
100
}
2897
2898
// This table describes sign- and zero-extend instructions which can be
2899
// folded into a preceding load. All of these extends have an immediate
2900
// (sometimes a mask and sometimes a shift) that's applied after
2901
// extension.
2902
static const struct FoldableLoadExtendsStruct {
2903
  uint16_t Opc[2];  // ARM, Thumb.
2904
  uint8_t ExpectedImm;
2905
  uint8_t isZExt     : 1;
2906
  uint8_t ExpectedVT : 7;
2907
} FoldableLoadExtends[] = {
2908
  { { ARM::SXTH,  ARM::t2SXTH  },   0, 0, MVT::i16 },
2909
  { { ARM::UXTH,  ARM::t2UXTH  },   0, 1, MVT::i16 },
2910
  { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8  },
2911
  { { ARM::SXTB,  ARM::t2SXTB  },   0, 0, MVT::i8  },
2912
  { { ARM::UXTB,  ARM::t2UXTB  },   0, 1, MVT::i8  }
2913
};
2914
2915
/// \brief The specified machine instr operand is a vreg, and that
2916
/// vreg is being provided by the specified load instruction.  If possible,
2917
/// try to fold the load as an operand to the instruction, returning true if
2918
/// successful.
2919
bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2920
201
                                      const LoadInst *LI) {
2921
201
  // Verify we have a legal type before going any further.
2922
201
  MVT VT;
2923
201
  if (!isLoadTypeLegal(LI->getType(), VT))
2924
0
    return false;
2925
201
2926
201
  // Combine load followed by zero- or sign-extend.
2927
201
  // ldrb r1, [r0]       ldrb r1, [r0]
2928
201
  // uxtb r2, r1     =>
2929
201
  // mov  r3, r2         mov  r3, r1
2930
201
  
if (201
MI->getNumOperands() < 3 || 201
!MI->getOperand(2).isImm()138
)
2931
94
    return false;
2932
107
  const uint64_t Imm = MI->getOperand(2).getImm();
2933
107
2934
107
  bool Found = false;
2935
107
  bool isZExt;
2936
535
  for (const FoldableLoadExtendsStruct &FLE : FoldableLoadExtends) {
2937
535
    if (FLE.Opc[isThumb2] == MI->getOpcode() &&
2938
51
        (uint64_t)FLE.ExpectedImm == Imm &&
2939
535
        
MVT((MVT::SimpleValueType)FLE.ExpectedVT) == VT51
) {
2940
51
      Found = true;
2941
51
      isZExt = FLE.isZExt;
2942
51
    }
2943
535
  }
2944
107
  if (
!Found107
)
return false56
;
2945
51
2946
51
  // See if we can handle this address.
2947
51
  Address Addr;
2948
51
  if (
!ARMComputeAddress(LI->getOperand(0), Addr)51
)
return false0
;
2949
51
2950
51
  unsigned ResultReg = MI->getOperand(0).getReg();
2951
51
  if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2952
0
    return false;
2953
51
  MI->eraseFromParent();
2954
51
  return true;
2955
51
}
2956
2957
unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2958
5
                                     unsigned Align, MVT VT) {
2959
5
  bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
2960
5
2961
5
  LLVMContext *Context = &MF->getFunction()->getContext();
2962
5
  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2963
5
  unsigned PCAdj = Subtarget->isThumb() ? 
42
:
83
;
2964
5
  ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(
2965
5
      GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj,
2966
5
      UseGOT_PREL ? 
ARMCP::GOT_PREL4
:
ARMCP::no_modifier1
,
2967
5
      /*AddCurrentAddress=*/UseGOT_PREL);
2968
5
2969
5
  unsigned ConstAlign =
2970
5
      MF->getDataLayout().getPrefTypeAlignment(Type::getInt32PtrTy(*Context));
2971
5
  unsigned Idx = MF->getConstantPool()->getConstantPoolIndex(CPV, ConstAlign);
2972
5
2973
5
  unsigned TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
2974
5
  unsigned Opc = isThumb2 ? 
ARM::t2LDRpci2
:
ARM::LDRcp3
;
2975
5
  MachineInstrBuilder MIB =
2976
5
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg)
2977
5
          .addConstantPoolIndex(Idx);
2978
5
  if (Opc == ARM::LDRcp)
2979
3
    MIB.addImm(0);
2980
5
  MIB.add(predOps(ARMCC::AL));
2981
5
2982
5
  // Fix the address by adding pc.
2983
5
  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
2984
5
  Opc = Subtarget->isThumb() ? 
ARM::tPICADD2
:
UseGOT_PREL ? 3
ARM::PICLDR2
2985
1
                                                          : ARM::PICADD;
2986
5
  DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0);
2987
5
  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2988
5
            .addReg(TempReg)
2989
5
            .addImm(ARMPCLabelIndex);
2990
5
  if (!Subtarget->isThumb())
2991
3
    MIB.add(predOps(ARMCC::AL));
2992
5
2993
5
  if (
UseGOT_PREL && 5
Subtarget->isThumb()4
) {
2994
2
    unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
2995
2
    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2996
2
                  TII.get(ARM::t2LDRi12), NewDestReg)
2997
2
              .addReg(DestReg)
2998
2
              .addImm(0);
2999
2
    DestReg = NewDestReg;
3000
2
    AddOptionalDefs(MIB);
3001
2
  }
3002
5
  return DestReg;
3003
5
}
3004
3005
905
bool ARMFastISel::fastLowerArguments() {
3006
905
  if (!FuncInfo.CanLowerReturn)
3007
0
    return false;
3008
905
3009
905
  const Function *F = FuncInfo.Fn;
3010
905
  if (F->isVarArg())
3011
1
    return false;
3012
904
3013
904
  CallingConv::ID CC = F->getCallingConv();
3014
904
  switch (CC) {
3015
10
  default:
3016
10
    return false;
3017
894
  case CallingConv::Fast:
3018
894
  case CallingConv::C:
3019
894
  case CallingConv::ARM_AAPCS_VFP:
3020
894
  case CallingConv::ARM_AAPCS:
3021
894
  case CallingConv::ARM_APCS:
3022
894
  case CallingConv::Swift:
3023
894
    break;
3024
894
  }
3025
894
3026
894
  // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3027
894
  // which are passed in r0 - r3.
3028
894
  
for (const Argument &Arg : F->args()) 894
{
3029
822
    if (Arg.getArgNo() >= 4)
3030
7
      return false;
3031
815
3032
815
    
if (815
Arg.hasAttribute(Attribute::InReg) ||
3033
815
        Arg.hasAttribute(Attribute::StructRet) ||
3034
810
        Arg.hasAttribute(Attribute::SwiftSelf) ||
3035
800
        Arg.hasAttribute(Attribute::SwiftError) ||
3036
793
        Arg.hasAttribute(Attribute::ByVal))
3037
22
      return false;
3038
793
3039
793
    Type *ArgTy = Arg.getType();
3040
793
    if (
ArgTy->isStructTy() || 793
ArgTy->isArrayTy()792
||
ArgTy->isVectorTy()789
)
3041
10
      return false;
3042
783
3043
783
    EVT ArgVT = TLI.getValueType(DL, ArgTy);
3044
783
    if (
!ArgVT.isSimple()783
)
return false0
;
3045
783
    switch (ArgVT.getSimpleVT().SimpleTy) {
3046
611
    case MVT::i8:
3047
611
    case MVT::i16:
3048
611
    case MVT::i32:
3049
611
      break;
3050
172
    default:
3051
172
      return false;
3052
683
    }
3053
683
  }
3054
683
3055
683
  static const MCPhysReg GPRArgRegs[] = {
3056
683
    ARM::R0, ARM::R1, ARM::R2, ARM::R3
3057
683
  };
3058
683
3059
683
  const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3060
539
  for (const Argument &Arg : F->args()) {
3061
539
    unsigned ArgNo = Arg.getArgNo();
3062
539
    unsigned SrcReg = GPRArgRegs[ArgNo];
3063
539
    unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3064
539
    // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3065
539
    // Without this, EmitLiveInCopies may eliminate the livein if its only
3066
539
    // use is a bitcast (which isn't turned into an instruction).
3067
539
    unsigned ResultReg = createResultReg(RC);
3068
539
    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3069
539
            TII.get(TargetOpcode::COPY),
3070
539
            ResultReg).addReg(DstReg, getKillRegState(true));
3071
539
    updateValueMap(&Arg, ResultReg);
3072
539
  }
3073
905
3074
905
  return true;
3075
905
}
3076
3077
namespace llvm {
3078
3079
  FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3080
1.13k
                                const TargetLibraryInfo *libInfo) {
3081
1.13k
    if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
3082
907
      return new ARMFastISel(funcInfo, libInfo);
3083
231
3084
231
    return nullptr;
3085
231
  }
3086
3087
} // end namespace llvm