Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
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//===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMHazardRecognizer.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
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1.27k
                         const TargetRegisterInfo &TRI) {
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  // FIXME: Detect integer instructions properly.
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  const MCInstrDesc &MCID = MI->getDesc();
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  unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
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  if (MI->mayStore())
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    return false;
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  unsigned Opcode = MCID.getOpcode();
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  if (
Opcode == ARM::VMOVRS || 1.26k
Opcode == ARM::VMOVRRD1.13k
)
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    return false;
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1.12k
  
if (1.12k
(Domain & ARMII::DomainVFP) || 1.12k
(Domain & ARMII::DomainNEON)21
)
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    return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
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  return false;
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}
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ScheduleHazardRecognizer::HazardType
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ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
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  assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
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  MachineInstr *MI = SU->getInstr();
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  if (
!MI->isDebugValue()213k
) {
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    // Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
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    // a VMLA / VMLS will cause 4 cycle stall.
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    const MCInstrDesc &MCID = MI->getDesc();
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    if (
LastMI && 213k
(MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral167k
) {
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      MachineInstr *DefMI = LastMI;
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      const MCInstrDesc &LastMCID = LastMI->getDesc();
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      const MachineFunction *MF = MI->getParent()->getParent();
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      const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
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                                        MF->getSubtarget().getInstrInfo());
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      // Skip over one non-VFP / NEON instruction.
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      if (!LastMI->isBarrier() &&
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!(TII.getSubtarget().hasMuxedUnits() && 49.1k
LastMI->mayLoadOrStore()1.26k
) &&
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(LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral48.7k
) {
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        MachineBasicBlock::iterator I = LastMI;
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        if (
I != LastMI->getParent()->begin()4.95k
) {
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          I = std::prev(I);
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          DefMI = &*I;
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        }
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      }
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      if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
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          (TII.canCauseFpMLxStall(MI->getOpcode()) ||
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hasRAWHazard(DefMI, MI, TII.getRegisterInfo())1.27k
)) {
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        // Try to schedule another instruction for the next 4 cycles.
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        if (FpMLxStalls == 0)
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          FpMLxStalls = 4;
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        return Hazard;
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      }
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    }
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  }
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  return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
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}
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void ARMHazardRecognizer::Reset() {
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  LastMI = nullptr;
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  FpMLxStalls = 0;
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  ScoreboardHazardRecognizer::Reset();
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}
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void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
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  MachineInstr *MI = SU->getInstr();
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  if (
!MI->isDebugValue()172k
) {
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    LastMI = MI;
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    FpMLxStalls = 0;
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  }
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  ScoreboardHazardRecognizer::EmitInstruction(SU);
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}
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void ARMHazardRecognizer::AdvanceCycle() {
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  if (
FpMLxStalls && 153k
--FpMLxStalls == 0363
)
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    // Stalled for 4 cycles but still can't schedule any other instructions.
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    LastMI = nullptr;
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  ScoreboardHazardRecognizer::AdvanceCycle();
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}
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void ARMHazardRecognizer::RecedeCycle() {
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  llvm_unreachable("reverse ARM hazard checking unsupported");
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}