/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Lanai/LanaiInstrInfo.h
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1 | | //===- LanaiInstrInfo.h - Lanai Instruction Information ---------*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file contains the Lanai implementation of the TargetInstrInfo class. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #ifndef LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H |
15 | | #define LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H |
16 | | |
17 | | #include "LanaiRegisterInfo.h" |
18 | | #include "llvm/Target/TargetInstrInfo.h" |
19 | | |
20 | | #define GET_INSTRINFO_HEADER |
21 | | #include "LanaiGenInstrInfo.inc" |
22 | | |
23 | | namespace llvm { |
24 | | |
25 | | class LanaiInstrInfo : public LanaiGenInstrInfo { |
26 | | const LanaiRegisterInfo RegisterInfo; |
27 | | |
28 | | public: |
29 | | LanaiInstrInfo(); |
30 | | |
31 | | // getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As |
32 | | // such, whenever a client has an instance of instruction info, it should |
33 | | // always be able to get register info as well (through this method). |
34 | 9.77k | virtual const LanaiRegisterInfo &getRegisterInfo() const { |
35 | 9.77k | return RegisterInfo; |
36 | 9.77k | } |
37 | | |
38 | | bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, |
39 | | AliasAnalysis *AA) const override; |
40 | | |
41 | | unsigned isLoadFromStackSlot(const MachineInstr &MI, |
42 | | int &FrameIndex) const override; |
43 | | |
44 | | unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, |
45 | | int &FrameIndex) const override; |
46 | | |
47 | | unsigned isStoreToStackSlot(const MachineInstr &MI, |
48 | | int &FrameIndex) const override; |
49 | | |
50 | | void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, |
51 | | const DebugLoc &DL, unsigned DestinationRegister, |
52 | | unsigned SourceRegister, bool KillSource) const override; |
53 | | |
54 | | void |
55 | | storeRegToStackSlot(MachineBasicBlock &MBB, |
56 | | MachineBasicBlock::iterator Position, |
57 | | unsigned SourceRegister, bool IsKill, int FrameIndex, |
58 | | const TargetRegisterClass *RegisterClass, |
59 | | const TargetRegisterInfo *RegisterInfo) const override; |
60 | | |
61 | | void |
62 | | loadRegFromStackSlot(MachineBasicBlock &MBB, |
63 | | MachineBasicBlock::iterator Position, |
64 | | unsigned DestinationRegister, int FrameIndex, |
65 | | const TargetRegisterClass *RegisterClass, |
66 | | const TargetRegisterInfo *RegisterInfo) const override; |
67 | | |
68 | | bool expandPostRAPseudo(MachineInstr &MI) const override; |
69 | | |
70 | | bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, |
71 | | int64_t &Offset, |
72 | | const TargetRegisterInfo *TRI) const override; |
73 | | |
74 | | bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg, |
75 | | int64_t &Offset, unsigned &Width, |
76 | | const TargetRegisterInfo *TRI) const; |
77 | | |
78 | | std::pair<unsigned, unsigned> |
79 | | decomposeMachineOperandsTargetFlags(unsigned TF) const override; |
80 | | |
81 | | ArrayRef<std::pair<unsigned, const char *>> |
82 | | getSerializableDirectMachineOperandTargetFlags() const override; |
83 | | |
84 | | bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, |
85 | | MachineBasicBlock *&FalseBlock, |
86 | | SmallVectorImpl<MachineOperand> &Condition, |
87 | | bool AllowModify) const override; |
88 | | |
89 | | unsigned removeBranch(MachineBasicBlock &MBB, |
90 | | int *BytesRemoved = nullptr) const override; |
91 | | |
92 | | // For a comparison instruction, return the source registers in SrcReg and |
93 | | // SrcReg2 if having two register operands, and the value it compares against |
94 | | // in CmpValue. Return true if the comparison instruction can be analyzed. |
95 | | bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, |
96 | | unsigned &SrcReg2, int &CmpMask, |
97 | | int &CmpValue) const override; |
98 | | |
99 | | // See if the comparison instruction can be converted into something more |
100 | | // efficient. E.g., on Lanai register-register instructions can set the flag |
101 | | // register, obviating the need for a separate compare. |
102 | | bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, |
103 | | unsigned SrcReg2, int CmpMask, int CmpValue, |
104 | | const MachineRegisterInfo *MRI) const override; |
105 | | |
106 | | // Analyze the given select instruction, returning true if it cannot be |
107 | | // understood. It is assumed that MI->isSelect() is true. |
108 | | // |
109 | | // When successful, return the controlling condition and the operands that |
110 | | // determine the true and false result values. |
111 | | // |
112 | | // Result = SELECT Cond, TrueOp, FalseOp |
113 | | // |
114 | | // Lanai can optimize certain select instructions, for example by predicating |
115 | | // the instruction defining one of the operands and sets Optimizable to true. |
116 | | bool analyzeSelect(const MachineInstr &MI, |
117 | | SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, |
118 | | unsigned &FalseOp, bool &Optimizable) const override; |
119 | | |
120 | | // Given a select instruction that was understood by analyzeSelect and |
121 | | // returned Optimizable = true, attempt to optimize MI by merging it with one |
122 | | // of its operands. Returns NULL on failure. |
123 | | // |
124 | | // When successful, returns the new select instruction. The client is |
125 | | // responsible for deleting MI. |
126 | | // |
127 | | // If both sides of the select can be optimized, the TrueOp is modifed. |
128 | | // PreferFalse is not used. |
129 | | MachineInstr *optimizeSelect(MachineInstr &MI, |
130 | | SmallPtrSetImpl<MachineInstr *> &SeenMIs, |
131 | | bool PreferFalse) const override; |
132 | | |
133 | | bool reverseBranchCondition( |
134 | | SmallVectorImpl<MachineOperand> &Condition) const override; |
135 | | |
136 | | unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, |
137 | | MachineBasicBlock *FalseBlock, |
138 | | ArrayRef<MachineOperand> Condition, |
139 | | const DebugLoc &DL, |
140 | | int *BytesAdded = nullptr) const override; |
141 | | }; |
142 | | |
143 | 56 | static inline bool isSPLSOpcode(unsigned Opcode) { |
144 | 56 | switch (Opcode) { |
145 | 0 | case Lanai::LDBs_RI: |
146 | 0 | case Lanai::LDBz_RI: |
147 | 0 | case Lanai::LDHs_RI: |
148 | 0 | case Lanai::LDHz_RI: |
149 | 0 | case Lanai::STB_RI: |
150 | 0 | case Lanai::STH_RI: |
151 | 0 | return true; |
152 | 56 | default: |
153 | 56 | return false; |
154 | 56 | } |
155 | 56 | } Unexecuted instantiation: LanaiAsmPrinter.cpp:llvm::isSPLSOpcode(unsigned int) Unexecuted instantiation: LanaiDelaySlotFiller.cpp:llvm::isSPLSOpcode(unsigned int) Unexecuted instantiation: LanaiFrameLowering.cpp:llvm::isSPLSOpcode(unsigned int) Unexecuted instantiation: LanaiInstrInfo.cpp:llvm::isSPLSOpcode(unsigned int) Unexecuted instantiation: LanaiISelDAGToDAG.cpp:llvm::isSPLSOpcode(unsigned int) Unexecuted instantiation: LanaiISelLowering.cpp:llvm::isSPLSOpcode(unsigned int) Unexecuted instantiation: LanaiMemAluCombiner.cpp:llvm::isSPLSOpcode(unsigned int) LanaiRegisterInfo.cpp:llvm::isSPLSOpcode(unsigned int) Line | Count | Source | 143 | 56 | static inline bool isSPLSOpcode(unsigned Opcode) { | 144 | 56 | switch (Opcode) { | 145 | 0 | case Lanai::LDBs_RI: | 146 | 0 | case Lanai::LDBz_RI: | 147 | 0 | case Lanai::LDHs_RI: | 148 | 0 | case Lanai::LDHz_RI: | 149 | 0 | case Lanai::STB_RI: | 150 | 0 | case Lanai::STH_RI: | 151 | 0 | return true; | 152 | 56 | default: | 153 | 56 | return false; | 154 | 56 | } | 155 | 56 | } |
Unexecuted instantiation: LanaiSelectionDAGInfo.cpp:llvm::isSPLSOpcode(unsigned int) Unexecuted instantiation: LanaiSubtarget.cpp:llvm::isSPLSOpcode(unsigned int) Unexecuted instantiation: LanaiTargetMachine.cpp:llvm::isSPLSOpcode(unsigned int) Unexecuted instantiation: LanaiTargetObjectFile.cpp:llvm::isSPLSOpcode(unsigned int) |
156 | | |
157 | 0 | static inline bool isRMOpcode(unsigned Opcode) { |
158 | 0 | switch (Opcode) { |
159 | 0 | case Lanai::LDW_RI: |
160 | 0 | case Lanai::SW_RI: |
161 | 0 | return true; |
162 | 0 | default: |
163 | 0 | return false; |
164 | 0 | } |
165 | 0 | } Unexecuted instantiation: LanaiTargetObjectFile.cpp:llvm::isRMOpcode(unsigned int) Unexecuted instantiation: LanaiAsmPrinter.cpp:llvm::isRMOpcode(unsigned int) Unexecuted instantiation: LanaiTargetMachine.cpp:llvm::isRMOpcode(unsigned int) Unexecuted instantiation: LanaiSubtarget.cpp:llvm::isRMOpcode(unsigned int) Unexecuted instantiation: LanaiSelectionDAGInfo.cpp:llvm::isRMOpcode(unsigned int) Unexecuted instantiation: LanaiMemAluCombiner.cpp:llvm::isRMOpcode(unsigned int) Unexecuted instantiation: LanaiISelLowering.cpp:llvm::isRMOpcode(unsigned int) Unexecuted instantiation: LanaiISelDAGToDAG.cpp:llvm::isRMOpcode(unsigned int) Unexecuted instantiation: LanaiInstrInfo.cpp:llvm::isRMOpcode(unsigned int) Unexecuted instantiation: LanaiFrameLowering.cpp:llvm::isRMOpcode(unsigned int) Unexecuted instantiation: LanaiDelaySlotFiller.cpp:llvm::isRMOpcode(unsigned int) |
166 | | |
167 | 0 | static inline bool isRRMOpcode(unsigned Opcode) { |
168 | 0 | switch (Opcode) { |
169 | 0 | case Lanai::LDBs_RR: |
170 | 0 | case Lanai::LDBz_RR: |
171 | 0 | case Lanai::LDHs_RR: |
172 | 0 | case Lanai::LDHz_RR: |
173 | 0 | case Lanai::LDWz_RR: |
174 | 0 | case Lanai::LDW_RR: |
175 | 0 | case Lanai::STB_RR: |
176 | 0 | case Lanai::STH_RR: |
177 | 0 | case Lanai::SW_RR: |
178 | 0 | return true; |
179 | 0 | default: |
180 | 0 | return false; |
181 | 0 | } |
182 | 0 | } Unexecuted instantiation: LanaiTargetObjectFile.cpp:llvm::isRRMOpcode(unsigned int) Unexecuted instantiation: LanaiDelaySlotFiller.cpp:llvm::isRRMOpcode(unsigned int) Unexecuted instantiation: LanaiTargetMachine.cpp:llvm::isRRMOpcode(unsigned int) Unexecuted instantiation: LanaiSubtarget.cpp:llvm::isRRMOpcode(unsigned int) Unexecuted instantiation: LanaiSelectionDAGInfo.cpp:llvm::isRRMOpcode(unsigned int) Unexecuted instantiation: LanaiRegisterInfo.cpp:llvm::isRRMOpcode(unsigned int) Unexecuted instantiation: LanaiMemAluCombiner.cpp:llvm::isRRMOpcode(unsigned int) Unexecuted instantiation: LanaiAsmPrinter.cpp:llvm::isRRMOpcode(unsigned int) Unexecuted instantiation: LanaiISelDAGToDAG.cpp:llvm::isRRMOpcode(unsigned int) Unexecuted instantiation: LanaiInstrInfo.cpp:llvm::isRRMOpcode(unsigned int) Unexecuted instantiation: LanaiFrameLowering.cpp:llvm::isRRMOpcode(unsigned int) Unexecuted instantiation: LanaiISelLowering.cpp:llvm::isRRMOpcode(unsigned int) |
183 | | |
184 | | } // namespace llvm |
185 | | |
186 | | #endif // LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H |