/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
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1 | | //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This class prints an Mips MCInst to a .s file. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "MipsInstPrinter.h" |
15 | | #include "MCTargetDesc/MipsMCExpr.h" |
16 | | #include "MipsInstrInfo.h" |
17 | | #include "llvm/ADT/StringExtras.h" |
18 | | #include "llvm/MC/MCExpr.h" |
19 | | #include "llvm/MC/MCInst.h" |
20 | | #include "llvm/MC/MCInstrInfo.h" |
21 | | #include "llvm/MC/MCSymbol.h" |
22 | | #include "llvm/Support/ErrorHandling.h" |
23 | | #include "llvm/Support/raw_ostream.h" |
24 | | using namespace llvm; |
25 | | |
26 | | #define DEBUG_TYPE "asm-printer" |
27 | | |
28 | | #define PRINT_ALIAS_INSTR |
29 | | #include "MipsGenAsmWriter.inc" |
30 | | |
31 | | template<unsigned R> |
32 | 4.70k | static bool isReg(const MCInst &MI, unsigned OpNo) { |
33 | 4.70k | assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); |
34 | 4.70k | return MI.getOperand(OpNo).getReg() == R; |
35 | 4.70k | } MipsInstPrinter.cpp:bool isReg<21u>(llvm::MCInst const&, unsigned int) Line | Count | Source | 32 | 3.42k | static bool isReg(const MCInst &MI, unsigned OpNo) { | 33 | 3.42k | assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); | 34 | 3.42k | return MI.getOperand(OpNo).getReg() == R; | 35 | 3.42k | } |
MipsInstPrinter.cpp:bool isReg<355u>(llvm::MCInst const&, unsigned int) Line | Count | Source | 32 | 71 | static bool isReg(const MCInst &MI, unsigned OpNo) { | 33 | 71 | assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); | 34 | 71 | return MI.getOperand(OpNo).getReg() == R; | 35 | 71 | } |
MipsInstPrinter.cpp:bool isReg<179u>(llvm::MCInst const&, unsigned int) Line | Count | Source | 32 | 90 | static bool isReg(const MCInst &MI, unsigned OpNo) { | 33 | 90 | assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); | 34 | 90 | return MI.getOperand(OpNo).getReg() == R; | 35 | 90 | } |
MipsInstPrinter.cpp:bool isReg<19u>(llvm::MCInst const&, unsigned int) Line | Count | Source | 32 | 1.08k | static bool isReg(const MCInst &MI, unsigned OpNo) { | 33 | 1.08k | assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); | 34 | 1.08k | return MI.getOperand(OpNo).getReg() == R; | 35 | 1.08k | } |
MipsInstPrinter.cpp:bool isReg<301u>(llvm::MCInst const&, unsigned int) Line | Count | Source | 32 | 37 | static bool isReg(const MCInst &MI, unsigned OpNo) { | 33 | 37 | assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); | 34 | 37 | return MI.getOperand(OpNo).getReg() == R; | 35 | 37 | } |
|
36 | | |
37 | 451 | const char* Mips::MipsFCCToString(Mips::CondCode CC) { |
38 | 451 | switch (CC) { |
39 | 0 | case FCOND_F: |
40 | 0 | case FCOND_T: return "f"; |
41 | 35 | case FCOND_UN: |
42 | 35 | case FCOND_OR: return "un"; |
43 | 78 | case FCOND_OEQ: |
44 | 78 | case FCOND_UNE: return "eq"; |
45 | 54 | case FCOND_UEQ: |
46 | 54 | case FCOND_ONE: return "ueq"; |
47 | 86 | case FCOND_OLT: |
48 | 86 | case FCOND_UGE: return "olt"; |
49 | 48 | case FCOND_ULT: |
50 | 48 | case FCOND_OGE: return "ult"; |
51 | 68 | case FCOND_OLE: |
52 | 68 | case FCOND_UGT: return "ole"; |
53 | 82 | case FCOND_ULE: |
54 | 82 | case FCOND_OGT: return "ule"; |
55 | 0 | case FCOND_SF: |
56 | 0 | case FCOND_ST: return "sf"; |
57 | 0 | case FCOND_NGLE: |
58 | 0 | case FCOND_GLE: return "ngle"; |
59 | 0 | case FCOND_SEQ: |
60 | 0 | case FCOND_SNE: return "seq"; |
61 | 0 | case FCOND_NGL: |
62 | 0 | case FCOND_GL: return "ngl"; |
63 | 0 | case FCOND_LT: |
64 | 0 | case FCOND_NLT: return "lt"; |
65 | 0 | case FCOND_NGE: |
66 | 0 | case FCOND_GE: return "nge"; |
67 | 0 | case FCOND_LE: |
68 | 0 | case FCOND_NLE: return "le"; |
69 | 0 | case FCOND_NGT: |
70 | 0 | case FCOND_GT: return "ngt"; |
71 | 0 | } |
72 | 0 | llvm_unreachable0 ("Impossible condition code!"); |
73 | 0 | } |
74 | | |
75 | 279k | void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { |
76 | 279k | OS << '$' << StringRef(getRegisterName(RegNo)).lower(); |
77 | 279k | } |
78 | | |
79 | | void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O, |
80 | 201k | StringRef Annot, const MCSubtargetInfo &STI) { |
81 | 201k | switch (MI->getOpcode()) { |
82 | 200k | default: |
83 | 200k | break; |
84 | 88 | case Mips::RDHWR: |
85 | 88 | case Mips::RDHWR64: |
86 | 88 | O << "\t.set\tpush\n"; |
87 | 88 | O << "\t.set\tmips32r2\n"; |
88 | 88 | break; |
89 | 174 | case Mips::Save16: |
90 | 174 | O << "\tsave\t"; |
91 | 174 | printSaveRestore(MI, O); |
92 | 174 | O << " # 16 bit inst\n"; |
93 | 174 | return; |
94 | 72 | case Mips::SaveX16: |
95 | 72 | O << "\tsave\t"; |
96 | 72 | printSaveRestore(MI, O); |
97 | 72 | O << "\n"; |
98 | 72 | return; |
99 | 179 | case Mips::Restore16: |
100 | 179 | O << "\trestore\t"; |
101 | 179 | printSaveRestore(MI, O); |
102 | 179 | O << " # 16 bit inst\n"; |
103 | 179 | return; |
104 | 72 | case Mips::RestoreX16: |
105 | 72 | O << "\trestore\t"; |
106 | 72 | printSaveRestore(MI, O); |
107 | 72 | O << "\n"; |
108 | 72 | return; |
109 | 200k | } |
110 | 200k | |
111 | 200k | // Try to print any aliases first. |
112 | 200k | if (200k !printAliasInstr(MI, O) && 200k !printAlias(*MI, O)139k ) |
113 | 137k | printInstruction(MI, O); |
114 | 200k | printAnnotation(O, Annot); |
115 | 200k | |
116 | 200k | switch (MI->getOpcode()) { |
117 | 200k | default: |
118 | 200k | break; |
119 | 88 | case Mips::RDHWR: |
120 | 88 | case Mips::RDHWR64: |
121 | 88 | O << "\n\t.set\tpop"; |
122 | 201k | } |
123 | 201k | } |
124 | | |
125 | | void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, |
126 | 352k | raw_ostream &O) { |
127 | 352k | const MCOperand &Op = MI->getOperand(OpNo); |
128 | 352k | if (Op.isReg()352k ) { |
129 | 277k | printRegName(O, Op.getReg()); |
130 | 277k | return; |
131 | 277k | } |
132 | 74.5k | |
133 | 74.5k | if (74.5k Op.isImm()74.5k ) { |
134 | 48.0k | O << formatImm(Op.getImm()); |
135 | 48.0k | return; |
136 | 48.0k | } |
137 | 26.4k | |
138 | 74.5k | assert(Op.isExpr() && "unknown operand kind in printOperand"); |
139 | 26.4k | Op.getExpr()->print(O, &MAI, true); |
140 | 26.4k | } |
141 | | |
142 | | template <unsigned Bits, unsigned Offset> |
143 | 25.5k | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { |
144 | 25.5k | const MCOperand &MO = MI->getOperand(opNum); |
145 | 25.5k | if (MO.isImm()25.5k ) { |
146 | 18.7k | uint64_t Imm = MO.getImm(); |
147 | 18.7k | Imm -= Offset; |
148 | 18.7k | Imm &= (1 << Bits) - 1; |
149 | 18.7k | Imm += Offset; |
150 | 18.7k | O << formatImm(Imm); |
151 | 18.7k | return; |
152 | 18.7k | } |
153 | 6.76k | |
154 | 6.76k | printOperand(MI, opNum, O); |
155 | 6.76k | } void llvm::MipsInstPrinter::printUImm<10u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 861 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 861 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 861 | if (MO.isImm()861 ) { | 146 | 861 | uint64_t Imm = MO.getImm(); | 147 | 861 | Imm -= Offset; | 148 | 861 | Imm &= (1 << Bits) - 1; | 149 | 861 | Imm += Offset; | 150 | 861 | O << formatImm(Imm); | 151 | 861 | return; | 152 | 861 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<4u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 406 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 406 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 406 | if (MO.isImm()406 ) { | 146 | 406 | uint64_t Imm = MO.getImm(); | 147 | 406 | Imm -= Offset; | 148 | 406 | Imm &= (1 << Bits) - 1; | 149 | 406 | Imm += Offset; | 150 | 406 | O << formatImm(Imm); | 151 | 406 | return; | 152 | 406 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<5u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 4.66k | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 4.66k | const MCOperand &MO = MI->getOperand(opNum); | 145 | 4.66k | if (MO.isImm()4.66k ) { | 146 | 4.66k | uint64_t Imm = MO.getImm(); | 147 | 4.66k | Imm -= Offset; | 148 | 4.66k | Imm &= (1 << Bits) - 1; | 149 | 4.66k | Imm += Offset; | 150 | 4.66k | O << formatImm(Imm); | 151 | 4.66k | return; | 152 | 4.66k | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<26u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 417 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 417 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 417 | if (MO.isImm()417 ) { | 146 | 0 | uint64_t Imm = MO.getImm(); | 147 | 0 | Imm -= Offset; | 148 | 0 | Imm &= (1 << Bits) - 1; | 149 | 0 | Imm += Offset; | 150 | 0 | O << formatImm(Imm); | 151 | 0 | return; | 152 | 0 | } | 153 | 417 | | 154 | 417 | printOperand(MI, opNum, O); | 155 | 417 | } |
void llvm::MipsInstPrinter::printUImm<20u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 53 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 53 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 53 | if (MO.isImm()53 ) { | 146 | 53 | uint64_t Imm = MO.getImm(); | 147 | 53 | Imm -= Offset; | 148 | 53 | Imm &= (1 << Bits) - 1; | 149 | 53 | Imm += Offset; | 150 | 53 | O << formatImm(Imm); | 151 | 53 | return; | 152 | 53 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<16u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 13.5k | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 13.5k | const MCOperand &MO = MI->getOperand(opNum); | 145 | 13.5k | if (MO.isImm()13.5k ) { | 146 | 7.17k | uint64_t Imm = MO.getImm(); | 147 | 7.17k | Imm -= Offset; | 148 | 7.17k | Imm &= (1 << Bits) - 1; | 149 | 7.17k | Imm += Offset; | 150 | 7.17k | O << formatImm(Imm); | 151 | 7.17k | return; | 152 | 7.17k | } | 153 | 6.34k | | 154 | 6.34k | printOperand(MI, opNum, O); | 155 | 6.34k | } |
void llvm::MipsInstPrinter::printUImm<1u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 361 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 361 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 361 | if (MO.isImm()361 ) { | 146 | 361 | uint64_t Imm = MO.getImm(); | 147 | 361 | Imm -= Offset; | 148 | 361 | Imm &= (1 << Bits) - 1; | 149 | 361 | Imm += Offset; | 150 | 361 | O << formatImm(Imm); | 151 | 361 | return; | 152 | 361 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<3u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 1.00k | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 1.00k | const MCOperand &MO = MI->getOperand(opNum); | 145 | 1.00k | if (MO.isImm()1.00k ) { | 146 | 1.00k | uint64_t Imm = MO.getImm(); | 147 | 1.00k | Imm -= Offset; | 148 | 1.00k | Imm &= (1 << Bits) - 1; | 149 | 1.00k | Imm += Offset; | 150 | 1.00k | O << formatImm(Imm); | 151 | 1.00k | return; | 152 | 1.00k | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<2u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 958 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 958 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 958 | if (MO.isImm()958 ) { | 146 | 958 | uint64_t Imm = MO.getImm(); | 147 | 958 | Imm -= Offset; | 148 | 958 | Imm &= (1 << Bits) - 1; | 149 | 958 | Imm += Offset; | 150 | 958 | O << formatImm(Imm); | 151 | 958 | return; | 152 | 958 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<0u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 52 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 52 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 52 | if (MO.isImm()52 ) { | 146 | 52 | uint64_t Imm = MO.getImm(); | 147 | 52 | Imm -= Offset; | 148 | 52 | Imm &= (1 << Bits) - 1; | 149 | 52 | Imm += Offset; | 150 | 52 | O << formatImm(Imm); | 151 | 52 | return; | 152 | 52 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<7u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 6 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 6 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 6 | if (MO.isImm()6 ) { | 146 | 6 | uint64_t Imm = MO.getImm(); | 147 | 6 | Imm -= Offset; | 148 | 6 | Imm &= (1 << Bits) - 1; | 149 | 6 | Imm += Offset; | 150 | 6 | O << formatImm(Imm); | 151 | 6 | return; | 152 | 6 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<8u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 223 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 223 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 223 | if (MO.isImm()223 ) { | 146 | 223 | uint64_t Imm = MO.getImm(); | 147 | 223 | Imm -= Offset; | 148 | 223 | Imm &= (1 << Bits) - 1; | 149 | 223 | Imm += Offset; | 150 | 223 | O << formatImm(Imm); | 151 | 223 | return; | 152 | 223 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<2u, 1u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 45 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 45 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 45 | if (MO.isImm()45 ) { | 146 | 45 | uint64_t Imm = MO.getImm(); | 147 | 45 | Imm -= Offset; | 148 | 45 | Imm &= (1 << Bits) - 1; | 149 | 45 | Imm += Offset; | 150 | 45 | O << formatImm(Imm); | 151 | 45 | return; | 152 | 45 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<6u, 0u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 2.78k | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 2.78k | const MCOperand &MO = MI->getOperand(opNum); | 145 | 2.78k | if (MO.isImm()2.78k ) { | 146 | 2.78k | uint64_t Imm = MO.getImm(); | 147 | 2.78k | Imm -= Offset; | 148 | 2.78k | Imm &= (1 << Bits) - 1; | 149 | 2.78k | Imm += Offset; | 150 | 2.78k | O << formatImm(Imm); | 151 | 2.78k | return; | 152 | 2.78k | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<5u, 32u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 41 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 41 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 41 | if (MO.isImm()41 ) { | 146 | 41 | uint64_t Imm = MO.getImm(); | 147 | 41 | Imm -= Offset; | 148 | 41 | Imm &= (1 << Bits) - 1; | 149 | 41 | Imm += Offset; | 150 | 41 | O << formatImm(Imm); | 151 | 41 | return; | 152 | 41 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<5u, 1u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 66 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 66 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 66 | if (MO.isImm()66 ) { | 146 | 66 | uint64_t Imm = MO.getImm(); | 147 | 66 | Imm -= Offset; | 148 | 66 | Imm &= (1 << Bits) - 1; | 149 | 66 | Imm += Offset; | 150 | 66 | O << formatImm(Imm); | 151 | 66 | return; | 152 | 66 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<6u, 1u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 57 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 57 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 57 | if (MO.isImm()57 ) { | 146 | 57 | uint64_t Imm = MO.getImm(); | 147 | 57 | Imm -= Offset; | 148 | 57 | Imm &= (1 << Bits) - 1; | 149 | 57 | Imm += Offset; | 150 | 57 | O << formatImm(Imm); | 151 | 57 | return; | 152 | 57 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<5u, 33u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 11 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 11 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 11 | if (MO.isImm()11 ) { | 146 | 11 | uint64_t Imm = MO.getImm(); | 147 | 11 | Imm -= Offset; | 148 | 11 | Imm &= (1 << Bits) - 1; | 149 | 11 | Imm += Offset; | 150 | 11 | O << formatImm(Imm); | 151 | 11 | return; | 152 | 11 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
void llvm::MipsInstPrinter::printUImm<6u, 2u>(llvm::MCInst const*, int, llvm::raw_ostream&) Line | Count | Source | 143 | 12 | void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { | 144 | 12 | const MCOperand &MO = MI->getOperand(opNum); | 145 | 12 | if (MO.isImm()12 ) { | 146 | 12 | uint64_t Imm = MO.getImm(); | 147 | 12 | Imm -= Offset; | 148 | 12 | Imm &= (1 << Bits) - 1; | 149 | 12 | Imm += Offset; | 150 | 12 | O << formatImm(Imm); | 151 | 12 | return; | 152 | 12 | } | 153 | 0 |
| 154 | 0 | printOperand(MI, opNum, O); | 155 | 0 | } |
|
156 | | |
157 | | void MipsInstPrinter:: |
158 | 42.4k | printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) { |
159 | 42.4k | // Load/Store memory operands -- imm($reg) |
160 | 42.4k | // If PIC target the target is loaded as the |
161 | 42.4k | // pattern lw $25,%call16($28) |
162 | 42.4k | |
163 | 42.4k | // opNum can be invalid if instruction had reglist as operand. |
164 | 42.4k | // MemOperand is always last operand of instruction (base + offset). |
165 | 42.4k | switch (MI->getOpcode()) { |
166 | 42.3k | default: |
167 | 42.3k | break; |
168 | 101 | case Mips::SWM32_MM: |
169 | 101 | case Mips::LWM32_MM: |
170 | 101 | case Mips::SWM16_MM: |
171 | 101 | case Mips::SWM16_MMR6: |
172 | 101 | case Mips::LWM16_MM: |
173 | 101 | case Mips::LWM16_MMR6: |
174 | 101 | opNum = MI->getNumOperands() - 2; |
175 | 101 | break; |
176 | 42.4k | } |
177 | 42.4k | |
178 | 42.4k | printOperand(MI, opNum+1, O); |
179 | 42.4k | O << "("; |
180 | 42.4k | printOperand(MI, opNum, O); |
181 | 42.4k | O << ")"; |
182 | 42.4k | } |
183 | | |
184 | | void MipsInstPrinter:: |
185 | 225 | printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) { |
186 | 225 | // when using stack locations for not load/store instructions |
187 | 225 | // print the same way as all normal 3 operand instructions. |
188 | 225 | printOperand(MI, opNum, O); |
189 | 225 | O << ", "; |
190 | 225 | printOperand(MI, opNum+1, O); |
191 | 225 | return; |
192 | 225 | } |
193 | | |
194 | | void MipsInstPrinter:: |
195 | 451 | printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { |
196 | 451 | const MCOperand& MO = MI->getOperand(opNum); |
197 | 451 | O << MipsFCCToString((Mips::CondCode)MO.getImm()); |
198 | 451 | } |
199 | | |
200 | | void MipsInstPrinter:: |
201 | 18 | printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O) { |
202 | 18 | printRegName(O, MI->getOperand(opNum).getReg()); |
203 | 18 | } |
204 | | |
205 | | void MipsInstPrinter:: |
206 | 0 | printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) { |
207 | 0 | llvm_unreachable("TODO"); |
208 | 0 | } |
209 | | |
210 | | bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI, |
211 | 2.41k | unsigned OpNo, raw_ostream &OS) { |
212 | 2.41k | OS << "\t" << Str << "\t"; |
213 | 2.41k | printOperand(&MI, OpNo, OS); |
214 | 2.41k | return true; |
215 | 2.41k | } |
216 | | |
217 | | bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI, |
218 | | unsigned OpNo0, unsigned OpNo1, |
219 | 1.03k | raw_ostream &OS) { |
220 | 1.03k | printAlias(Str, MI, OpNo0, OS); |
221 | 1.03k | OS << ", "; |
222 | 1.03k | printOperand(&MI, OpNo1, OS); |
223 | 1.03k | return true; |
224 | 1.03k | } |
225 | | |
226 | 139k | bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) { |
227 | 139k | switch (MI.getOpcode()) { |
228 | 619 | case Mips::BEQ: |
229 | 619 | case Mips::BEQ_MM: |
230 | 619 | // beq $zero, $zero, $L2 => b $L2 |
231 | 619 | // beq $r0, $zero, $L2 => beqz $r0, $L2 |
232 | 250 | return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && |
233 | 238 | printAlias("b", MI, 2, OS)) || |
234 | 381 | (isReg<Mips::ZERO>(MI, 1) && 381 printAlias("beqz", MI, 0, 2, OS)288 ); |
235 | 8 | case Mips::BEQ64: |
236 | 8 | // beq $r0, $zero, $L2 => beqz $r0, $L2 |
237 | 8 | return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); |
238 | 573 | case Mips::BNE: |
239 | 573 | case Mips::BNE_MM: |
240 | 573 | // bne $r0, $zero, $L2 => bnez $r0, $L2 |
241 | 428 | return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); |
242 | 3 | case Mips::BNE64: |
243 | 3 | // bne $r0, $zero, $L2 => bnez $r0, $L2 |
244 | 2 | return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); |
245 | 124 | case Mips::BGEZAL: |
246 | 124 | // bgezal $zero, $L1 => bal $L1 |
247 | 63 | return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS); |
248 | 45 | case Mips::BC1T: |
249 | 45 | // bc1t $fcc0, $L1 => bc1t $L1 |
250 | 0 | return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); |
251 | 45 | case Mips::BC1F: |
252 | 45 | // bc1f $fcc0, $L1 => bc1f $L1 |
253 | 0 | return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS); |
254 | 1.08k | case Mips::JALR: |
255 | 1.08k | // jalr $ra, $r1 => jalr $r1 |
256 | 1.05k | return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS); |
257 | 37 | case Mips::JALR64: |
258 | 37 | // jalr $ra, $r1 => jalr $r1 |
259 | 26 | return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS); |
260 | 585 | case Mips::NOR: |
261 | 585 | case Mips::NOR_MM: |
262 | 585 | case Mips::NOR_MMR6: |
263 | 585 | // nor $r0, $r1, $zero => not $r0, $r1 |
264 | 297 | return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS); |
265 | 60 | case Mips::NOR64: |
266 | 60 | // nor $r0, $r1, $zero => not $r0, $r1 |
267 | 0 | return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS); |
268 | 892 | case Mips::OR: |
269 | 892 | // or $r0, $r1, $zero => move $r0, $r1 |
270 | 8 | return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS); |
271 | 135k | default: return false; |
272 | 0 | } |
273 | 0 | } |
274 | | |
275 | 497 | void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) { |
276 | 2.02k | for (unsigned i = 0, e = MI->getNumOperands(); i != e2.02k ; ++i1.53k ) { |
277 | 1.53k | if (i != 01.53k ) O << ", "1.03k ; |
278 | 1.53k | if (MI->getOperand(i).isReg()) |
279 | 1.03k | printRegName(O, MI->getOperand(i).getReg()); |
280 | 1.53k | else |
281 | 497 | printUImm<16>(MI, i, O); |
282 | 1.53k | } |
283 | 497 | } |
284 | | |
285 | | void MipsInstPrinter:: |
286 | 110 | printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) { |
287 | 110 | // - 2 because register List is always first operand of instruction and it is |
288 | 110 | // always followed by memory operand (base + offset). |
289 | 527 | for (int i = opNum, e = MI->getNumOperands() - 2; i != e527 ; ++i417 ) { |
290 | 417 | if (i != opNum) |
291 | 307 | O << ", "; |
292 | 417 | printRegName(O, MI->getOperand(i).getReg()); |
293 | 417 | } |
294 | 110 | } |