Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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//===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// Subclass of MipsTargetLowering specialized for mips16.
11
//
12
//===----------------------------------------------------------------------===//
13
#include "Mips16ISelLowering.h"
14
#include "MCTargetDesc/MipsBaseInfo.h"
15
#include "Mips16HardFloatInfo.h"
16
#include "MipsMachineFunction.h"
17
#include "MipsRegisterInfo.h"
18
#include "MipsTargetMachine.h"
19
#include "llvm/CodeGen/MachineInstrBuilder.h"
20
#include "llvm/Support/CommandLine.h"
21
#include "llvm/Target/TargetInstrInfo.h"
22
23
using namespace llvm;
24
25
#define DEBUG_TYPE "mips-lower"
26
27
static cl::opt<bool> DontExpandCondPseudos16(
28
  "mips16-dont-expand-cond-pseudo",
29
  cl::init(false),
30
  cl::desc("Don't expand conditional move related "
31
           "pseudos for Mips 16"),
32
  cl::Hidden);
33
34
namespace {
35
struct Mips16Libcall {
36
  RTLIB::Libcall Libcall;
37
  const char *Name;
38
39
5.49k
  bool operator<(const Mips16Libcall &RHS) const {
40
5.49k
    return std::strcmp(Name, RHS.Name) < 0;
41
5.49k
  }
42
};
43
44
struct Mips16IntrinsicHelperType{
45
  const char* Name;
46
  const char* Helper;
47
48
948
  bool operator<(const Mips16IntrinsicHelperType &RHS) const {
49
948
    return std::strcmp(Name, RHS.Name) < 0;
50
948
  }
51
190
  bool operator==(const Mips16IntrinsicHelperType &RHS) const {
52
190
    return std::strcmp(Name, RHS.Name) == 0;
53
190
  }
54
};
55
}
56
57
// Libcalls for which no helper is generated. Sorted by name for binary search.
58
static const Mips16Libcall HardFloatLibCalls[] = {
59
  { RTLIB::ADD_F64, "__mips16_adddf3" },
60
  { RTLIB::ADD_F32, "__mips16_addsf3" },
61
  { RTLIB::DIV_F64, "__mips16_divdf3" },
62
  { RTLIB::DIV_F32, "__mips16_divsf3" },
63
  { RTLIB::OEQ_F64, "__mips16_eqdf2" },
64
  { RTLIB::OEQ_F32, "__mips16_eqsf2" },
65
  { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" },
66
  { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" },
67
  { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" },
68
  { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" },
69
  { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" },
70
  { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" },
71
  { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" },
72
  { RTLIB::OGE_F64, "__mips16_gedf2" },
73
  { RTLIB::OGE_F32, "__mips16_gesf2" },
74
  { RTLIB::OGT_F64, "__mips16_gtdf2" },
75
  { RTLIB::OGT_F32, "__mips16_gtsf2" },
76
  { RTLIB::OLE_F64, "__mips16_ledf2" },
77
  { RTLIB::OLE_F32, "__mips16_lesf2" },
78
  { RTLIB::OLT_F64, "__mips16_ltdf2" },
79
  { RTLIB::OLT_F32, "__mips16_ltsf2" },
80
  { RTLIB::MUL_F64, "__mips16_muldf3" },
81
  { RTLIB::MUL_F32, "__mips16_mulsf3" },
82
  { RTLIB::UNE_F64, "__mips16_nedf2" },
83
  { RTLIB::UNE_F32, "__mips16_nesf2" },
84
  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall.
85
  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall.
86
  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall.
87
  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall.
88
  { RTLIB::SUB_F64, "__mips16_subdf3" },
89
  { RTLIB::SUB_F32, "__mips16_subsf3" },
90
  { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" },
91
  { RTLIB::UO_F64, "__mips16_unorddf2" },
92
  { RTLIB::UO_F32, "__mips16_unordsf2" }
93
};
94
95
static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
96
  {"__fixunsdfsi", "__mips16_call_stub_2" },
97
  {"ceil",  "__mips16_call_stub_df_2"},
98
  {"ceilf", "__mips16_call_stub_sf_1"},
99
  {"copysign",  "__mips16_call_stub_df_10"},
100
  {"copysignf", "__mips16_call_stub_sf_5"},
101
  {"cos",  "__mips16_call_stub_df_2"},
102
  {"cosf", "__mips16_call_stub_sf_1"},
103
  {"exp2",  "__mips16_call_stub_df_2"},
104
  {"exp2f", "__mips16_call_stub_sf_1"},
105
  {"floor",  "__mips16_call_stub_df_2"},
106
  {"floorf", "__mips16_call_stub_sf_1"},
107
  {"log2",  "__mips16_call_stub_df_2"},
108
  {"log2f", "__mips16_call_stub_sf_1"},
109
  {"nearbyint",  "__mips16_call_stub_df_2"},
110
  {"nearbyintf", "__mips16_call_stub_sf_1"},
111
  {"rint",  "__mips16_call_stub_df_2"},
112
  {"rintf", "__mips16_call_stub_sf_1"},
113
  {"sin",  "__mips16_call_stub_df_2"},
114
  {"sinf", "__mips16_call_stub_sf_1"},
115
  {"sqrt",  "__mips16_call_stub_df_2"},
116
  {"sqrtf", "__mips16_call_stub_sf_1"},
117
  {"trunc",  "__mips16_call_stub_df_2"},
118
  {"truncf", "__mips16_call_stub_sf_1"},
119
};
120
121
Mips16TargetLowering::Mips16TargetLowering(const MipsTargetMachine &TM,
122
                                           const MipsSubtarget &STI)
123
2.37k
    : MipsTargetLowering(TM, STI) {
124
2.37k
125
2.37k
  // Set up the register classes
126
2.37k
  addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
127
2.37k
128
2.37k
  if (!Subtarget.useSoftFloat())
129
2.21k
    setMips16HardFloatLibCalls();
130
2.37k
131
2.37k
  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Expand);
132
2.37k
  setOperationAction(ISD::ATOMIC_CMP_SWAP,    MVT::i32,   Expand);
133
2.37k
  setOperationAction(ISD::ATOMIC_SWAP,        MVT::i32,   Expand);
134
2.37k
  setOperationAction(ISD::ATOMIC_LOAD_ADD,    MVT::i32,   Expand);
135
2.37k
  setOperationAction(ISD::ATOMIC_LOAD_SUB,    MVT::i32,   Expand);
136
2.37k
  setOperationAction(ISD::ATOMIC_LOAD_AND,    MVT::i32,   Expand);
137
2.37k
  setOperationAction(ISD::ATOMIC_LOAD_OR,     MVT::i32,   Expand);
138
2.37k
  setOperationAction(ISD::ATOMIC_LOAD_XOR,    MVT::i32,   Expand);
139
2.37k
  setOperationAction(ISD::ATOMIC_LOAD_NAND,   MVT::i32,   Expand);
140
2.37k
  setOperationAction(ISD::ATOMIC_LOAD_MIN,    MVT::i32,   Expand);
141
2.37k
  setOperationAction(ISD::ATOMIC_LOAD_MAX,    MVT::i32,   Expand);
142
2.37k
  setOperationAction(ISD::ATOMIC_LOAD_UMIN,   MVT::i32,   Expand);
143
2.37k
  setOperationAction(ISD::ATOMIC_LOAD_UMAX,   MVT::i32,   Expand);
144
2.37k
145
2.37k
  setOperationAction(ISD::ROTR, MVT::i32,  Expand);
146
2.37k
  setOperationAction(ISD::ROTR, MVT::i64,  Expand);
147
2.37k
  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
148
2.37k
  setOperationAction(ISD::BSWAP, MVT::i64, Expand);
149
2.37k
150
2.37k
  computeRegisterProperties(STI.getRegisterInfo());
151
2.37k
}
152
153
const MipsTargetLowering *
154
llvm::createMips16TargetLowering(const MipsTargetMachine &TM,
155
2.37k
                                 const MipsSubtarget &STI) {
156
2.37k
  return new Mips16TargetLowering(TM, STI);
157
2.37k
}
158
159
bool
160
Mips16TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
161
                                                     unsigned,
162
                                                     unsigned,
163
3
                                                     bool *Fast) const {
164
3
  return false;
165
3
}
166
167
MachineBasicBlock *
168
Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
169
182
                                                  MachineBasicBlock *BB) const {
170
182
  switch (MI.getOpcode()) {
171
0
  default:
172
0
    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
173
4
  case Mips::SelBeqZ:
174
4
    return emitSel16(Mips::BeqzRxImm16, MI, BB);
175
6
  case Mips::SelBneZ:
176
6
    return emitSel16(Mips::BnezRxImm16, MI, BB);
177
5
  case Mips::SelTBteqZCmpi:
178
5
    return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB);
179
0
  case Mips::SelTBteqZSlti:
180
0
    return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB);
181
0
  case Mips::SelTBteqZSltiu:
182
0
    return emitSeliT16(Mips::Bteqz16, Mips::SltiuRxImmX16, MI, BB);
183
5
  case Mips::SelTBtneZCmpi:
184
5
    return emitSeliT16(Mips::Btnez16, Mips::CmpiRxImmX16, MI, BB);
185
3
  case Mips::SelTBtneZSlti:
186
3
    return emitSeliT16(Mips::Btnez16, Mips::SltiRxImmX16, MI, BB);
187
0
  case Mips::SelTBtneZSltiu:
188
0
    return emitSeliT16(Mips::Btnez16, Mips::SltiuRxImmX16, MI, BB);
189
3
  case Mips::SelTBteqZCmp:
190
3
    return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
191
8
  case Mips::SelTBteqZSlt:
192
8
    return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
193
8
  case Mips::SelTBteqZSltu:
194
8
    return emitSelT16(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
195
3
  case Mips::SelTBtneZCmp:
196
3
    return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
197
6
  case Mips::SelTBtneZSlt:
198
6
    return emitSelT16(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
199
4
  case Mips::SelTBtneZSltu:
200
4
    return emitSelT16(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
201
5
  case Mips::BteqzT8CmpX16:
202
5
    return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
203
12
  case Mips::BteqzT8SltX16:
204
12
    return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
205
0
  case Mips::BteqzT8SltuX16:
206
0
    // TBD: figure out a way to get this or remove the instruction
207
0
    // altogether.
208
0
    return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
209
9
  case Mips::BtnezT8CmpX16:
210
9
    return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
211
13
  case Mips::BtnezT8SltX16:
212
13
    return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
213
0
  case Mips::BtnezT8SltuX16:
214
0
    // TBD: figure out a way to get this or remove the instruction
215
0
    // altogether.
216
0
    return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
217
5
  case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
218
5
    Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
219
0
  case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
220
0
    Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
221
0
  case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
222
0
    Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
223
6
  case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
224
6
    Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
225
7
  case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
226
7
    Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
227
0
  case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
228
0
    Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
229
0
    break;
230
11
  case Mips::SltCCRxRy16:
231
11
    return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
232
0
    break;
233
10
  case Mips::SltiCCRxImmX16:
234
10
    return emitFEXT_CCRXI16_ins
235
10
      (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
236
30
  case Mips::SltiuCCRxImmX16:
237
30
    return emitFEXT_CCRXI16_ins
238
30
      (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
239
19
  case Mips::SltuCCRxRy16:
240
19
    return emitFEXT_CCRX16_ins
241
19
      (Mips::SltuRxRy16, MI, BB);
242
0
  }
243
0
}
244
245
bool Mips16TargetLowering::isEligibleForTailCallOptimization(
246
    const CCState &CCInfo, unsigned NextStackOffset,
247
14
    const MipsFunctionInfo &FI) const {
248
14
  // No tail call optimization for mips16.
249
14
  return false;
250
14
}
251
252
2.21k
void Mips16TargetLowering::setMips16HardFloatLibCalls() {
253
77.3k
  for (unsigned I = 0; 
I != array_lengthof(HardFloatLibCalls)77.3k
;
++I75.1k
) {
254
75.1k
    assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
255
75.1k
           "Array not sorted!");
256
75.1k
    if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL)
257
66.3k
      setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name);
258
75.1k
  }
259
2.21k
260
2.21k
  setLibcallName(RTLIB::O_F64, "__mips16_unorddf2");
261
2.21k
  setLibcallName(RTLIB::O_F32, "__mips16_unordsf2");
262
2.21k
}
263
264
//
265
// The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
266
// cleaner way to do all of this but it will have to wait until the traditional
267
// gcc mechanism is completed.
268
//
269
// For Pic, in order for Mips16 code to call Mips32 code which according the abi
270
// have either arguments or returned values placed in floating point registers,
271
// we use a set of helper functions. (This includes functions which return type
272
//  complex which on Mips are returned in a pair of floating point registers).
273
//
274
// This is an encoding that we inherited from gcc.
275
// In Mips traditional O32, N32 ABI, floating point numbers are passed in
276
// floating point argument registers 1,2 only when the first and optionally
277
// the second arguments are float (sf) or double (df).
278
// For Mips16 we are only concerned with the situations where floating point
279
// arguments are being passed in floating point registers by the ABI, because
280
// Mips16 mode code cannot execute floating point instructions to load those
281
// values and hence helper functions are needed.
282
// The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
283
// the helper function suffixs for these are:
284
//                        0,  1,    5,        9,         2,   6,        10
285
// this suffix can then be calculated as follows:
286
// for a given argument Arg:
287
//     Arg1x, Arg2x = 1 :  Arg is sf
288
//                    2 :  Arg is df
289
//                    0:   Arg is neither sf or df
290
// So this stub is the string for number Arg1x + Arg2x*4.
291
// However not all numbers between 0 and 10 are possible, we check anyway and
292
// assert if the impossible exists.
293
//
294
295
unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
296
789
  (ArgListTy &Args) const {
297
789
  unsigned int resultNum = 0;
298
789
  if (
Args.size() >= 1789
) {
299
358
    Type *t = Args[0].Ty;
300
358
    if (
t->isFloatTy()358
) {
301
66
      resultNum = 1;
302
66
    }
303
292
    else 
if (292
t->isDoubleTy()292
) {
304
64
      resultNum = 2;
305
64
    }
306
358
  }
307
789
  if (
resultNum789
) {
308
130
    if (
Args.size() >=2130
) {
309
42
      Type *t = Args[1].Ty;
310
42
      if (
t->isFloatTy()42
) {
311
26
        resultNum += 4;
312
26
      }
313
16
      else 
if (16
t->isDoubleTy()16
) {
314
16
        resultNum += 8;
315
16
      }
316
42
    }
317
130
  }
318
789
  return resultNum;
319
789
}
320
321
//
322
// Prefixes are attached to stub numbers depending on the return type.
323
// return type: float  sf_
324
//              double df_
325
//              single complex sc_
326
//              double complext dc_
327
//              others  NO PREFIX
328
//
329
//
330
// The full name of a helper function is__mips16_call_stub +
331
//    return type dependent prefix + stub number
332
//
333
// FIXME: This is something that probably should be in a different source file
334
// and perhaps done differently but my main purpose is to not waste runtime
335
// on something that we can enumerate in the source. Another possibility is
336
// to have a python script to generate these mapping tables. This will do
337
// for now. There are a whole series of helper function mapping arrays, one
338
// for each return type class as outlined above. There there are 11 possible
339
// entries. Ones with 0 are ones which should never be selected.
340
//
341
// All the arrays are similar except for ones which return neither
342
// sf, df, sc, dc, in which we only care about ones which have sf or df as a
343
// first parameter.
344
//
345
#define P_ "__mips16_call_stub_"
346
#define MAX_STUB_NUMBER 10
347
#define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
348
#define T P "0" , T1
349
#define P P_
350
static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
351
  {nullptr, T1 };
352
#undef P
353
#define P P_ "sf_"
354
static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
355
  { T };
356
#undef P
357
#define P P_ "df_"
358
static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
359
  { T };
360
#undef P
361
#define P P_ "sc_"
362
static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
363
  { T };
364
#undef P
365
#define P P_ "dc_"
366
static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
367
  { T };
368
#undef P
369
#undef P_
370
371
372
const char* Mips16TargetLowering::
373
  getMips16HelperFunction
374
789
    (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
375
789
  const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
376
#ifndef NDEBUG
377
  const unsigned int maxStubNum = 10;
378
  assert(stubNum <= maxStubNum);
379
  const bool validStubNum[maxStubNum+1] =
380
    {true, true, true, false, false, true, true, false, false, true, true};
381
  assert(validStubNum[stubNum]);
382
#endif
383
  const char *result;
384
789
  if (
RetTy->isFloatTy()789
) {
385
38
    result = sfMips16Helper[stubNum];
386
38
  }
387
751
  else 
if (751
RetTy ->isDoubleTy()751
) {
388
27
    result = dfMips16Helper[stubNum];
389
27
  }
390
724
  else 
if (724
RetTy->isStructTy()724
) {
391
30
    // check if it's complex
392
30
    if (
RetTy->getNumContainedTypes() == 230
) {
393
30
      if ((RetTy->getContainedType(0)->isFloatTy()) &&
394
30
          
(RetTy->getContainedType(1)->isFloatTy())15
) {
395
15
        result = scMips16Helper[stubNum];
396
15
      }
397
15
      else 
if (15
(RetTy->getContainedType(0)->isDoubleTy()) &&
398
15
               
(RetTy->getContainedType(1)->isDoubleTy())15
) {
399
15
        result = dcMips16Helper[stubNum];
400
15
      }
401
0
      else {
402
0
        llvm_unreachable("Uncovered condition");
403
15
      }
404
30
    }
405
0
    else {
406
0
      llvm_unreachable("Uncovered condition");
407
0
    }
408
724
  }
409
694
  else {
410
694
    if (
stubNum == 0694
) {
411
636
      needHelper = false;
412
636
      return "";
413
636
    }
414
58
    result = vMips16Helper[stubNum];
415
58
  }
416
153
  needHelper = true;
417
153
  return result;
418
789
}
419
420
void Mips16TargetLowering::
421
getOpndList(SmallVectorImpl<SDValue> &Ops,
422
            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
423
            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
424
            bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
425
999
            SDValue Chain) const {
426
999
  SelectionDAG &DAG = CLI.DAG;
427
999
  MachineFunction &MF = DAG.getMachineFunction();
428
999
  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
429
999
  const char* Mips16HelperFunction = nullptr;
430
999
  bool NeedMips16Helper = false;
431
999
432
999
  if (
Subtarget.inMips16HardFloat()999
) {
433
997
    //
434
997
    // currently we don't have symbols tagged with the mips16 or mips32
435
997
    // qualifier so we will assume that we don't know what kind it is.
436
997
    // and generate the helper
437
997
    //
438
997
    bool LookupHelper = true;
439
997
    if (ExternalSymbolSDNode *
S997
= dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
440
344
      Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() };
441
344
442
344
      if (std::binary_search(std::begin(HardFloatLibCalls),
443
344
                             std::end(HardFloatLibCalls), Find))
444
154
        LookupHelper = false;
445
190
      else {
446
190
        const char *Symbol = S->getSymbol();
447
190
        Mips16IntrinsicHelperType IntrinsicFind = { Symbol, "" };
448
190
        const Mips16HardFloatInfo::FuncSignature *Signature =
449
190
            Mips16HardFloatInfo::findFuncSignature(Symbol);
450
190
        if (
!IsPICCall && 190
(Signature && 164
(FuncInfo->StubsNeeded.find(Symbol) ==
451
190
                                         FuncInfo->StubsNeeded.end()))) {
452
100
          FuncInfo->StubsNeeded[Symbol] = Signature;
453
100
          //
454
100
          // S2 is normally saved if the stub is for a function which
455
100
          // returns a float or double value and is not otherwise. This is
456
100
          // because more work is required after the function the stub
457
100
          // is calling completes, and so the stub cannot directly return
458
100
          // and the stub has no stack space to store the return address so
459
100
          // S2 is used for that purpose.
460
100
          // In order to take advantage of not saving S2, we need to also
461
100
          // optimize the call in the stub and this requires some further
462
100
          // functionality in MipsAsmPrinter which we don't have yet.
463
100
          // So for now we always save S2. The optimization will be done
464
100
          // in a follow-on patch.
465
100
          //
466
100
          if (
1 || 100
(Signature->RetSig != Mips16HardFloatInfo::NoFPRet)0
)
467
100
            FuncInfo->setSaveS2();
468
100
        }
469
190
        // one more look at list of intrinsics
470
190
        const Mips16IntrinsicHelperType *Helper =
471
190
            std::lower_bound(std::begin(Mips16IntrinsicHelper),
472
190
                             std::end(Mips16IntrinsicHelper), IntrinsicFind);
473
190
        if (Helper != std::end(Mips16IntrinsicHelper) &&
474
190
            
*Helper == IntrinsicFind190
) {
475
24
          Mips16HelperFunction = Helper->Helper;
476
24
          NeedMips16Helper = true;
477
24
          LookupHelper = false;
478
24
        }
479
190
480
190
      }
481
997
    } else 
if (GlobalAddressSDNode *653
G653
=
482
649
                   dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
483
649
      Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL,
484
649
                             G->getGlobal()->getName().data() };
485
649
486
649
      if (std::binary_search(std::begin(HardFloatLibCalls),
487
649
                             std::end(HardFloatLibCalls), Find))
488
30
        LookupHelper = false;
489
653
    }
490
997
    if (LookupHelper)
491
789
      Mips16HelperFunction =
492
789
        getMips16HelperFunction(CLI.RetTy, CLI.getArgs(), NeedMips16Helper);
493
997
  }
494
999
495
999
  SDValue JumpTarget = Callee;
496
999
497
999
  // T9 should contain the address of the callee function if
498
999
  // -relocation-model=pic or it is an indirect call.
499
999
  if (
IsPICCall || 999
!GlobalOrExternal406
) {
500
593
    unsigned V0Reg = Mips::V0;
501
593
    if (
NeedMips16Helper593
) {
502
91
      RegsToPass.push_front(std::make_pair(V0Reg, Callee));
503
91
      JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction,
504
91
                                         getPointerTy(DAG.getDataLayout()));
505
91
      ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(JumpTarget);
506
91
      JumpTarget = getAddrGlobal(S, CLI.DL, JumpTarget.getValueType(), DAG,
507
91
                                 MipsII::MO_GOT, Chain,
508
91
                                 FuncInfo->callPtrInfo(S->getSymbol()));
509
91
    } else
510
502
      RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
511
593
  }
512
999
513
999
  Ops.push_back(JumpTarget);
514
999
515
999
  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
516
999
                                  InternalLinkage, IsCallReloc, CLI, Callee,
517
999
                                  Chain);
518
999
}
519
520
MachineBasicBlock *
521
Mips16TargetLowering::emitSel16(unsigned Opc, MachineInstr &MI,
522
10
                                MachineBasicBlock *BB) const {
523
10
  if (DontExpandCondPseudos16)
524
0
    return BB;
525
10
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
526
10
  DebugLoc DL = MI.getDebugLoc();
527
10
  // To "insert" a SELECT_CC instruction, we actually have to insert the
528
10
  // diamond control-flow pattern.  The incoming instruction knows the
529
10
  // destination vreg to set, the condition code register to branch on, the
530
10
  // true/false values to select between, and a branch opcode to use.
531
10
  const BasicBlock *LLVM_BB = BB->getBasicBlock();
532
10
  MachineFunction::iterator It = ++BB->getIterator();
533
10
534
10
  //  thisMBB:
535
10
  //  ...
536
10
  //   TrueVal = ...
537
10
  //   setcc r1, r2, r3
538
10
  //   bNE   r1, r0, copy1MBB
539
10
  //   fallthrough --> copy0MBB
540
10
  MachineBasicBlock *thisMBB  = BB;
541
10
  MachineFunction *F = BB->getParent();
542
10
  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
543
10
  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
544
10
  F->insert(It, copy0MBB);
545
10
  F->insert(It, sinkMBB);
546
10
547
10
  // Transfer the remainder of BB and its successor edges to sinkMBB.
548
10
  sinkMBB->splice(sinkMBB->begin(), BB,
549
10
                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
550
10
  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
551
10
552
10
  // Next, add the true and fallthrough blocks as its successors.
553
10
  BB->addSuccessor(copy0MBB);
554
10
  BB->addSuccessor(sinkMBB);
555
10
556
10
  BuildMI(BB, DL, TII->get(Opc))
557
10
      .addReg(MI.getOperand(3).getReg())
558
10
      .addMBB(sinkMBB);
559
10
560
10
  //  copy0MBB:
561
10
  //   %FalseValue = ...
562
10
  //   # fallthrough to sinkMBB
563
10
  BB = copy0MBB;
564
10
565
10
  // Update machine-CFG edges
566
10
  BB->addSuccessor(sinkMBB);
567
10
568
10
  //  sinkMBB:
569
10
  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
570
10
  //  ...
571
10
  BB = sinkMBB;
572
10
573
10
  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
574
10
      .addReg(MI.getOperand(1).getReg())
575
10
      .addMBB(thisMBB)
576
10
      .addReg(MI.getOperand(2).getReg())
577
10
      .addMBB(copy0MBB);
578
10
579
10
  MI.eraseFromParent(); // The pseudo instruction is gone now.
580
10
  return BB;
581
10
}
582
583
MachineBasicBlock *
584
Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI,
585
32
                                 MachineBasicBlock *BB) const {
586
32
  if (DontExpandCondPseudos16)
587
0
    return BB;
588
32
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
589
32
  DebugLoc DL = MI.getDebugLoc();
590
32
  // To "insert" a SELECT_CC instruction, we actually have to insert the
591
32
  // diamond control-flow pattern.  The incoming instruction knows the
592
32
  // destination vreg to set, the condition code register to branch on, the
593
32
  // true/false values to select between, and a branch opcode to use.
594
32
  const BasicBlock *LLVM_BB = BB->getBasicBlock();
595
32
  MachineFunction::iterator It = ++BB->getIterator();
596
32
597
32
  //  thisMBB:
598
32
  //  ...
599
32
  //   TrueVal = ...
600
32
  //   setcc r1, r2, r3
601
32
  //   bNE   r1, r0, copy1MBB
602
32
  //   fallthrough --> copy0MBB
603
32
  MachineBasicBlock *thisMBB  = BB;
604
32
  MachineFunction *F = BB->getParent();
605
32
  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
606
32
  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
607
32
  F->insert(It, copy0MBB);
608
32
  F->insert(It, sinkMBB);
609
32
610
32
  // Transfer the remainder of BB and its successor edges to sinkMBB.
611
32
  sinkMBB->splice(sinkMBB->begin(), BB,
612
32
                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
613
32
  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
614
32
615
32
  // Next, add the true and fallthrough blocks as its successors.
616
32
  BB->addSuccessor(copy0MBB);
617
32
  BB->addSuccessor(sinkMBB);
618
32
619
32
  BuildMI(BB, DL, TII->get(Opc2))
620
32
      .addReg(MI.getOperand(3).getReg())
621
32
      .addReg(MI.getOperand(4).getReg());
622
32
  BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
623
32
624
32
  //  copy0MBB:
625
32
  //   %FalseValue = ...
626
32
  //   # fallthrough to sinkMBB
627
32
  BB = copy0MBB;
628
32
629
32
  // Update machine-CFG edges
630
32
  BB->addSuccessor(sinkMBB);
631
32
632
32
  //  sinkMBB:
633
32
  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
634
32
  //  ...
635
32
  BB = sinkMBB;
636
32
637
32
  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
638
32
      .addReg(MI.getOperand(1).getReg())
639
32
      .addMBB(thisMBB)
640
32
      .addReg(MI.getOperand(2).getReg())
641
32
      .addMBB(copy0MBB);
642
32
643
32
  MI.eraseFromParent(); // The pseudo instruction is gone now.
644
32
  return BB;
645
32
646
32
}
647
648
MachineBasicBlock *
649
Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2,
650
                                  MachineInstr &MI,
651
13
                                  MachineBasicBlock *BB) const {
652
13
  if (DontExpandCondPseudos16)
653
0
    return BB;
654
13
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
655
13
  DebugLoc DL = MI.getDebugLoc();
656
13
  // To "insert" a SELECT_CC instruction, we actually have to insert the
657
13
  // diamond control-flow pattern.  The incoming instruction knows the
658
13
  // destination vreg to set, the condition code register to branch on, the
659
13
  // true/false values to select between, and a branch opcode to use.
660
13
  const BasicBlock *LLVM_BB = BB->getBasicBlock();
661
13
  MachineFunction::iterator It = ++BB->getIterator();
662
13
663
13
  //  thisMBB:
664
13
  //  ...
665
13
  //   TrueVal = ...
666
13
  //   setcc r1, r2, r3
667
13
  //   bNE   r1, r0, copy1MBB
668
13
  //   fallthrough --> copy0MBB
669
13
  MachineBasicBlock *thisMBB  = BB;
670
13
  MachineFunction *F = BB->getParent();
671
13
  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
672
13
  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
673
13
  F->insert(It, copy0MBB);
674
13
  F->insert(It, sinkMBB);
675
13
676
13
  // Transfer the remainder of BB and its successor edges to sinkMBB.
677
13
  sinkMBB->splice(sinkMBB->begin(), BB,
678
13
                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
679
13
  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
680
13
681
13
  // Next, add the true and fallthrough blocks as its successors.
682
13
  BB->addSuccessor(copy0MBB);
683
13
  BB->addSuccessor(sinkMBB);
684
13
685
13
  BuildMI(BB, DL, TII->get(Opc2))
686
13
      .addReg(MI.getOperand(3).getReg())
687
13
      .addImm(MI.getOperand(4).getImm());
688
13
  BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
689
13
690
13
  //  copy0MBB:
691
13
  //   %FalseValue = ...
692
13
  //   # fallthrough to sinkMBB
693
13
  BB = copy0MBB;
694
13
695
13
  // Update machine-CFG edges
696
13
  BB->addSuccessor(sinkMBB);
697
13
698
13
  //  sinkMBB:
699
13
  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
700
13
  //  ...
701
13
  BB = sinkMBB;
702
13
703
13
  BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
704
13
      .addReg(MI.getOperand(1).getReg())
705
13
      .addMBB(thisMBB)
706
13
      .addReg(MI.getOperand(2).getReg())
707
13
      .addMBB(copy0MBB);
708
13
709
13
  MI.eraseFromParent(); // The pseudo instruction is gone now.
710
13
  return BB;
711
13
712
13
}
713
714
MachineBasicBlock *
715
Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
716
                                          MachineInstr &MI,
717
39
                                          MachineBasicBlock *BB) const {
718
39
  if (DontExpandCondPseudos16)
719
0
    return BB;
720
39
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
721
39
  unsigned regX = MI.getOperand(0).getReg();
722
39
  unsigned regY = MI.getOperand(1).getReg();
723
39
  MachineBasicBlock *target = MI.getOperand(2).getMBB();
724
39
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc))
725
39
      .addReg(regX)
726
39
      .addReg(regY);
727
39
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
728
39
  MI.eraseFromParent(); // The pseudo instruction is gone now.
729
39
  return BB;
730
39
}
731
732
MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
733
    unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned,
734
18
    MachineInstr &MI, MachineBasicBlock *BB) const {
735
18
  if (DontExpandCondPseudos16)
736
0
    return BB;
737
18
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
738
18
  unsigned regX = MI.getOperand(0).getReg();
739
18
  int64_t imm = MI.getOperand(1).getImm();
740
18
  MachineBasicBlock *target = MI.getOperand(2).getMBB();
741
18
  unsigned CmpOpc;
742
18
  if (isUInt<8>(imm))
743
12
    CmpOpc = CmpiOpc;
744
6
  else 
if (6
(!ImmSigned && 6
isUInt<16>(imm)4
) ||
745
2
           
(ImmSigned && 2
isInt<16>(imm)2
))
746
6
    CmpOpc = CmpiXOpc;
747
6
  else
748
0
    llvm_unreachable("immediate field not usable");
749
18
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
750
18
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
751
18
  MI.eraseFromParent(); // The pseudo instruction is gone now.
752
18
  return BB;
753
18
}
754
755
static unsigned Mips16WhichOp8uOr16simm
756
40
  (unsigned shortOp, unsigned longOp, int64_t Imm) {
757
40
  if (isUInt<8>(Imm))
758
39
    return shortOp;
759
1
  else 
if (1
isInt<16>(Imm)1
)
760
1
    return longOp;
761
1
  else
762
1
    llvm_unreachable("immediate field not usable");
763
40
}
764
765
MachineBasicBlock *
766
Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI,
767
30
                                          MachineBasicBlock *BB) const {
768
30
  if (DontExpandCondPseudos16)
769
0
    return BB;
770
30
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
771
30
  unsigned CC = MI.getOperand(0).getReg();
772
30
  unsigned regX = MI.getOperand(1).getReg();
773
30
  unsigned regY = MI.getOperand(2).getReg();
774
30
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc))
775
30
      .addReg(regX)
776
30
      .addReg(regY);
777
30
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
778
30
      .addReg(Mips::T8);
779
30
  MI.eraseFromParent(); // The pseudo instruction is gone now.
780
30
  return BB;
781
30
}
782
783
MachineBasicBlock *
784
Mips16TargetLowering::emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc,
785
                                           MachineInstr &MI,
786
40
                                           MachineBasicBlock *BB) const {
787
40
  if (DontExpandCondPseudos16)
788
0
    return BB;
789
40
  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
790
40
  unsigned CC = MI.getOperand(0).getReg();
791
40
  unsigned regX = MI.getOperand(1).getReg();
792
40
  int64_t Imm = MI.getOperand(2).getImm();
793
40
  unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
794
40
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)).addReg(regX).addImm(Imm);
795
40
  BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
796
40
      .addReg(Mips::T8);
797
40
  MI.eraseFromParent(); // The pseudo instruction is gone now.
798
40
  return BB;
799
40
800
40
}