Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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//===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that NVPTX uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
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#define LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
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#include "NVPTX.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace NVPTXISD {
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enum NodeType : unsigned {
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  // Start the numbering from where ISD NodeType finishes.
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  FIRST_NUMBER = ISD::BUILTIN_OP_END,
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  Wrapper,
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  CALL,
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  RET_FLAG,
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  LOAD_PARAM,
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  DeclareParam,
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  DeclareScalarParam,
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  DeclareRetParam,
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  DeclareRet,
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  DeclareScalarRet,
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  PrintCall,
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  PrintConvergentCall,
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  PrintCallUni,
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  PrintConvergentCallUni,
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  CallArgBegin,
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  CallArg,
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  LastCallArg,
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  CallArgEnd,
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  CallVoid,
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  CallVal,
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  CallSymbol,
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  Prototype,
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  MoveParam,
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  PseudoUseParam,
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  RETURN,
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  CallSeqBegin,
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  CallSeqEnd,
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  CallPrototype,
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  FUN_SHFL_CLAMP,
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  FUN_SHFR_CLAMP,
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  MUL_WIDE_SIGNED,
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  MUL_WIDE_UNSIGNED,
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  IMAD,
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  SETP_F16X2,
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  Dummy,
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  LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
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  LoadV4,
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  LDGV2, // LDG.v2
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  LDGV4, // LDG.v4
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  LDUV2, // LDU.v2
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  LDUV4, // LDU.v4
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  StoreV2,
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  StoreV4,
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  LoadParam,
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  LoadParamV2,
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  LoadParamV4,
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  StoreParam,
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  StoreParamV2,
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  StoreParamV4,
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  StoreParamS32, // to sext and store a <32bit value, not used currently
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  StoreParamU32, // to zext and store a <32bit value, not used currently
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  StoreRetval,
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  StoreRetvalV2,
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  StoreRetvalV4,
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  // Texture intrinsics
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  Tex1DFloatS32,
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  Tex1DFloatFloat,
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  Tex1DFloatFloatLevel,
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  Tex1DFloatFloatGrad,
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  Tex1DS32S32,
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  Tex1DS32Float,
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  Tex1DS32FloatLevel,
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  Tex1DS32FloatGrad,
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  Tex1DU32S32,
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  Tex1DU32Float,
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  Tex1DU32FloatLevel,
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  Tex1DU32FloatGrad,
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  Tex1DArrayFloatS32,
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  Tex1DArrayFloatFloat,
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  Tex1DArrayFloatFloatLevel,
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  Tex1DArrayFloatFloatGrad,
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  Tex1DArrayS32S32,
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  Tex1DArrayS32Float,
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  Tex1DArrayS32FloatLevel,
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  Tex1DArrayS32FloatGrad,
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  Tex1DArrayU32S32,
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  Tex1DArrayU32Float,
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  Tex1DArrayU32FloatLevel,
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  Tex1DArrayU32FloatGrad,
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  Tex2DFloatS32,
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  Tex2DFloatFloat,
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  Tex2DFloatFloatLevel,
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  Tex2DFloatFloatGrad,
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  Tex2DS32S32,
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  Tex2DS32Float,
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  Tex2DS32FloatLevel,
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  Tex2DS32FloatGrad,
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  Tex2DU32S32,
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  Tex2DU32Float,
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  Tex2DU32FloatLevel,
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  Tex2DU32FloatGrad,
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  Tex2DArrayFloatS32,
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  Tex2DArrayFloatFloat,
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  Tex2DArrayFloatFloatLevel,
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  Tex2DArrayFloatFloatGrad,
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  Tex2DArrayS32S32,
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  Tex2DArrayS32Float,
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  Tex2DArrayS32FloatLevel,
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  Tex2DArrayS32FloatGrad,
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  Tex2DArrayU32S32,
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  Tex2DArrayU32Float,
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  Tex2DArrayU32FloatLevel,
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  Tex2DArrayU32FloatGrad,
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  Tex3DFloatS32,
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  Tex3DFloatFloat,
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  Tex3DFloatFloatLevel,
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  Tex3DFloatFloatGrad,
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  Tex3DS32S32,
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  Tex3DS32Float,
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  Tex3DS32FloatLevel,
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  Tex3DS32FloatGrad,
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  Tex3DU32S32,
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  Tex3DU32Float,
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  Tex3DU32FloatLevel,
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  Tex3DU32FloatGrad,
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  TexCubeFloatFloat,
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  TexCubeFloatFloatLevel,
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  TexCubeS32Float,
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  TexCubeS32FloatLevel,
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  TexCubeU32Float,
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  TexCubeU32FloatLevel,
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  TexCubeArrayFloatFloat,
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  TexCubeArrayFloatFloatLevel,
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  TexCubeArrayS32Float,
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  TexCubeArrayS32FloatLevel,
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  TexCubeArrayU32Float,
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  TexCubeArrayU32FloatLevel,
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  Tld4R2DFloatFloat,
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  Tld4G2DFloatFloat,
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  Tld4B2DFloatFloat,
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  Tld4A2DFloatFloat,
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  Tld4R2DS64Float,
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  Tld4G2DS64Float,
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  Tld4B2DS64Float,
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  Tld4A2DS64Float,
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  Tld4R2DU64Float,
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  Tld4G2DU64Float,
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  Tld4B2DU64Float,
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  Tld4A2DU64Float,
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  TexUnified1DFloatS32,
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  TexUnified1DFloatFloat,
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  TexUnified1DFloatFloatLevel,
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  TexUnified1DFloatFloatGrad,
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  TexUnified1DS32S32,
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  TexUnified1DS32Float,
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  TexUnified1DS32FloatLevel,
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  TexUnified1DS32FloatGrad,
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  TexUnified1DU32S32,
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  TexUnified1DU32Float,
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  TexUnified1DU32FloatLevel,
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  TexUnified1DU32FloatGrad,
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  TexUnified1DArrayFloatS32,
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  TexUnified1DArrayFloatFloat,
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  TexUnified1DArrayFloatFloatLevel,
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  TexUnified1DArrayFloatFloatGrad,
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  TexUnified1DArrayS32S32,
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  TexUnified1DArrayS32Float,
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  TexUnified1DArrayS32FloatLevel,
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  TexUnified1DArrayS32FloatGrad,
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  TexUnified1DArrayU32S32,
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  TexUnified1DArrayU32Float,
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  TexUnified1DArrayU32FloatLevel,
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  TexUnified1DArrayU32FloatGrad,
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  TexUnified2DFloatS32,
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  TexUnified2DFloatFloat,
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  TexUnified2DFloatFloatLevel,
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  TexUnified2DFloatFloatGrad,
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  TexUnified2DS32S32,
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  TexUnified2DS32Float,
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  TexUnified2DS32FloatLevel,
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  TexUnified2DS32FloatGrad,
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  TexUnified2DU32S32,
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  TexUnified2DU32Float,
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  TexUnified2DU32FloatLevel,
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  TexUnified2DU32FloatGrad,
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  TexUnified2DArrayFloatS32,
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  TexUnified2DArrayFloatFloat,
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  TexUnified2DArrayFloatFloatLevel,
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  TexUnified2DArrayFloatFloatGrad,
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  TexUnified2DArrayS32S32,
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  TexUnified2DArrayS32Float,
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  TexUnified2DArrayS32FloatLevel,
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  TexUnified2DArrayS32FloatGrad,
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  TexUnified2DArrayU32S32,
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  TexUnified2DArrayU32Float,
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  TexUnified2DArrayU32FloatLevel,
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  TexUnified2DArrayU32FloatGrad,
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  TexUnified3DFloatS32,
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  TexUnified3DFloatFloat,
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  TexUnified3DFloatFloatLevel,
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  TexUnified3DFloatFloatGrad,
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  TexUnified3DS32S32,
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  TexUnified3DS32Float,
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  TexUnified3DS32FloatLevel,
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  TexUnified3DS32FloatGrad,
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  TexUnified3DU32S32,
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  TexUnified3DU32Float,
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  TexUnified3DU32FloatLevel,
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  TexUnified3DU32FloatGrad,
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  TexUnifiedCubeFloatFloat,
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  TexUnifiedCubeFloatFloatLevel,
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  TexUnifiedCubeS32Float,
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  TexUnifiedCubeS32FloatLevel,
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  TexUnifiedCubeU32Float,
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  TexUnifiedCubeU32FloatLevel,
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  TexUnifiedCubeArrayFloatFloat,
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  TexUnifiedCubeArrayFloatFloatLevel,
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  TexUnifiedCubeArrayS32Float,
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  TexUnifiedCubeArrayS32FloatLevel,
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  TexUnifiedCubeArrayU32Float,
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  TexUnifiedCubeArrayU32FloatLevel,
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  Tld4UnifiedR2DFloatFloat,
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  Tld4UnifiedG2DFloatFloat,
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  Tld4UnifiedB2DFloatFloat,
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  Tld4UnifiedA2DFloatFloat,
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  Tld4UnifiedR2DS64Float,
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  Tld4UnifiedG2DS64Float,
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  Tld4UnifiedB2DS64Float,
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  Tld4UnifiedA2DS64Float,
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  Tld4UnifiedR2DU64Float,
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  Tld4UnifiedG2DU64Float,
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  Tld4UnifiedB2DU64Float,
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  Tld4UnifiedA2DU64Float,
251
252
  // Surface intrinsics
253
  Suld1DI8Clamp,
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  Suld1DI16Clamp,
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  Suld1DI32Clamp,
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  Suld1DI64Clamp,
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  Suld1DV2I8Clamp,
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  Suld1DV2I16Clamp,
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  Suld1DV2I32Clamp,
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  Suld1DV2I64Clamp,
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  Suld1DV4I8Clamp,
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  Suld1DV4I16Clamp,
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  Suld1DV4I32Clamp,
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265
  Suld1DArrayI8Clamp,
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  Suld1DArrayI16Clamp,
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  Suld1DArrayI32Clamp,
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  Suld1DArrayI64Clamp,
269
  Suld1DArrayV2I8Clamp,
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  Suld1DArrayV2I16Clamp,
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  Suld1DArrayV2I32Clamp,
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  Suld1DArrayV2I64Clamp,
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  Suld1DArrayV4I8Clamp,
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  Suld1DArrayV4I16Clamp,
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  Suld1DArrayV4I32Clamp,
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  Suld2DI8Clamp,
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  Suld2DI16Clamp,
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  Suld2DI32Clamp,
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  Suld2DI64Clamp,
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  Suld2DV2I8Clamp,
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  Suld2DV2I16Clamp,
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  Suld2DV2I32Clamp,
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  Suld2DV2I64Clamp,
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  Suld2DV4I8Clamp,
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  Suld2DV4I16Clamp,
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  Suld2DV4I32Clamp,
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  Suld2DArrayI8Clamp,
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  Suld2DArrayI16Clamp,
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  Suld2DArrayI32Clamp,
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  Suld2DArrayI64Clamp,
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  Suld2DArrayV2I8Clamp,
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  Suld2DArrayV2I16Clamp,
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  Suld2DArrayV2I32Clamp,
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  Suld2DArrayV2I64Clamp,
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  Suld2DArrayV4I8Clamp,
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  Suld2DArrayV4I16Clamp,
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  Suld2DArrayV4I32Clamp,
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  Suld3DI8Clamp,
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  Suld3DI16Clamp,
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  Suld3DI32Clamp,
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  Suld3DI64Clamp,
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  Suld3DV2I8Clamp,
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  Suld3DV2I16Clamp,
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  Suld3DV2I32Clamp,
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  Suld3DV2I64Clamp,
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  Suld3DV4I8Clamp,
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  Suld3DV4I16Clamp,
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  Suld3DV4I32Clamp,
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313
  Suld1DI8Trap,
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  Suld1DI16Trap,
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  Suld1DI32Trap,
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  Suld1DI64Trap,
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  Suld1DV2I8Trap,
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  Suld1DV2I16Trap,
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  Suld1DV2I32Trap,
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  Suld1DV2I64Trap,
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  Suld1DV4I8Trap,
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  Suld1DV4I16Trap,
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  Suld1DV4I32Trap,
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325
  Suld1DArrayI8Trap,
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  Suld1DArrayI16Trap,
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  Suld1DArrayI32Trap,
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  Suld1DArrayI64Trap,
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  Suld1DArrayV2I8Trap,
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  Suld1DArrayV2I16Trap,
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  Suld1DArrayV2I32Trap,
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  Suld1DArrayV2I64Trap,
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  Suld1DArrayV4I8Trap,
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  Suld1DArrayV4I16Trap,
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  Suld1DArrayV4I32Trap,
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337
  Suld2DI8Trap,
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  Suld2DI16Trap,
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  Suld2DI32Trap,
340
  Suld2DI64Trap,
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  Suld2DV2I8Trap,
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  Suld2DV2I16Trap,
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  Suld2DV2I32Trap,
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  Suld2DV2I64Trap,
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  Suld2DV4I8Trap,
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  Suld2DV4I16Trap,
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  Suld2DV4I32Trap,
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349
  Suld2DArrayI8Trap,
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  Suld2DArrayI16Trap,
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  Suld2DArrayI32Trap,
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  Suld2DArrayI64Trap,
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  Suld2DArrayV2I8Trap,
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  Suld2DArrayV2I16Trap,
355
  Suld2DArrayV2I32Trap,
356
  Suld2DArrayV2I64Trap,
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  Suld2DArrayV4I8Trap,
358
  Suld2DArrayV4I16Trap,
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  Suld2DArrayV4I32Trap,
360
361
  Suld3DI8Trap,
362
  Suld3DI16Trap,
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  Suld3DI32Trap,
364
  Suld3DI64Trap,
365
  Suld3DV2I8Trap,
366
  Suld3DV2I16Trap,
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  Suld3DV2I32Trap,
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  Suld3DV2I64Trap,
369
  Suld3DV4I8Trap,
370
  Suld3DV4I16Trap,
371
  Suld3DV4I32Trap,
372
373
  Suld1DI8Zero,
374
  Suld1DI16Zero,
375
  Suld1DI32Zero,
376
  Suld1DI64Zero,
377
  Suld1DV2I8Zero,
378
  Suld1DV2I16Zero,
379
  Suld1DV2I32Zero,
380
  Suld1DV2I64Zero,
381
  Suld1DV4I8Zero,
382
  Suld1DV4I16Zero,
383
  Suld1DV4I32Zero,
384
385
  Suld1DArrayI8Zero,
386
  Suld1DArrayI16Zero,
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  Suld1DArrayI32Zero,
388
  Suld1DArrayI64Zero,
389
  Suld1DArrayV2I8Zero,
390
  Suld1DArrayV2I16Zero,
391
  Suld1DArrayV2I32Zero,
392
  Suld1DArrayV2I64Zero,
393
  Suld1DArrayV4I8Zero,
394
  Suld1DArrayV4I16Zero,
395
  Suld1DArrayV4I32Zero,
396
397
  Suld2DI8Zero,
398
  Suld2DI16Zero,
399
  Suld2DI32Zero,
400
  Suld2DI64Zero,
401
  Suld2DV2I8Zero,
402
  Suld2DV2I16Zero,
403
  Suld2DV2I32Zero,
404
  Suld2DV2I64Zero,
405
  Suld2DV4I8Zero,
406
  Suld2DV4I16Zero,
407
  Suld2DV4I32Zero,
408
409
  Suld2DArrayI8Zero,
410
  Suld2DArrayI16Zero,
411
  Suld2DArrayI32Zero,
412
  Suld2DArrayI64Zero,
413
  Suld2DArrayV2I8Zero,
414
  Suld2DArrayV2I16Zero,
415
  Suld2DArrayV2I32Zero,
416
  Suld2DArrayV2I64Zero,
417
  Suld2DArrayV4I8Zero,
418
  Suld2DArrayV4I16Zero,
419
  Suld2DArrayV4I32Zero,
420
421
  Suld3DI8Zero,
422
  Suld3DI16Zero,
423
  Suld3DI32Zero,
424
  Suld3DI64Zero,
425
  Suld3DV2I8Zero,
426
  Suld3DV2I16Zero,
427
  Suld3DV2I32Zero,
428
  Suld3DV2I64Zero,
429
  Suld3DV4I8Zero,
430
  Suld3DV4I16Zero,
431
  Suld3DV4I32Zero
432
};
433
}
434
435
class NVPTXSubtarget;
436
437
//===--------------------------------------------------------------------===//
438
// TargetLowering Implementation
439
//===--------------------------------------------------------------------===//
440
class NVPTXTargetLowering : public TargetLowering {
441
public:
442
  explicit NVPTXTargetLowering(const NVPTXTargetMachine &TM,
443
                               const NVPTXSubtarget &STI);
444
  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
445
446
  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
447
448
  const char *getTargetNodeName(unsigned Opcode) const override;
449
450
  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
451
                          unsigned Intrinsic) const override;
452
453
  /// isLegalAddressingMode - Return true if the addressing mode represented
454
  /// by AM is legal for this target, for a load/store of the specified type
455
  /// Used to guide target specific optimizations, like loop strength
456
  /// reduction (LoopStrengthReduce.cpp) and memory optimization for
457
  /// address mode (CodeGenPrepare.cpp)
458
  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
459
                             unsigned AS,
460
                             Instruction *I = nullptr) const override;
461
462
98
  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override {
463
98
    // Truncating 64-bit to 32-bit is free in SASS.
464
98
    if (
!SrcTy->isIntegerTy() || 98
!DstTy->isIntegerTy()98
)
465
0
      return false;
466
98
    return SrcTy->getPrimitiveSizeInBits() == 64 &&
467
51
           DstTy->getPrimitiveSizeInBits() == 32;
468
98
  }
469
470
  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
471
620
                         EVT VT) const override {
472
620
    if (VT.isVector())
473
0
      return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
474
620
    return MVT::i1;
475
620
  }
476
477
  ConstraintType getConstraintType(StringRef Constraint) const override;
478
  std::pair<unsigned, const TargetRegisterClass *>
479
  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
480
                               StringRef Constraint, MVT VT) const override;
481
482
  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
483
                               bool isVarArg,
484
                               const SmallVectorImpl<ISD::InputArg> &Ins,
485
                               const SDLoc &dl, SelectionDAG &DAG,
486
                               SmallVectorImpl<SDValue> &InVals) const override;
487
488
  SDValue LowerCall(CallLoweringInfo &CLI,
489
                    SmallVectorImpl<SDValue> &InVals) const override;
490
491
  std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &,
492
                           const SmallVectorImpl<ISD::OutputArg> &,
493
                           unsigned retAlignment,
494
                           ImmutableCallSite CS) const;
495
496
  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
497
                      const SmallVectorImpl<ISD::OutputArg> &Outs,
498
                      const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
499
                      SelectionDAG &DAG) const override;
500
501
  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
502
                                    std::vector<SDValue> &Ops,
503
                                    SelectionDAG &DAG) const override;
504
505
  const NVPTXTargetMachine *nvTM;
506
507
  // PTX always uses 32-bit shift amounts
508
632
  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
509
632
    return MVT::i32;
510
632
  }
511
512
  TargetLoweringBase::LegalizeTypeAction
513
  getPreferredVectorAction(EVT VT) const override;
514
515
  // Get the degree of precision we want from 32-bit floating point division
516
  // operations.
517
  //
518
  //  0 - Use ptx div.approx
519
  //  1 - Use ptx.div.full (approximate, but less so than div.approx)
520
  //  2 - Use IEEE-compliant div instructions, if available.
521
  int getDivF32Level() const;
522
523
  // Get whether we should use a precise or approximate 32-bit floating point
524
  // sqrt instruction.
525
  bool usePrecSqrtF32() const;
526
527
  // Get whether we should use instructions that flush floating-point denormals
528
  // to sign-preserving zero.
529
  bool useF32FTZ(const MachineFunction &MF) const;
530
531
  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
532
                          int &ExtraSteps, bool &UseOneConst,
533
                          bool Reciprocal) const override;
534
535
16
  unsigned combineRepeatedFPDivisors() const override { return 2; }
536
537
  bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;
538
  bool allowUnsafeFPMath(MachineFunction &MF) const;
539
540
450
  bool isFMAFasterThanFMulAndFAdd(EVT) const override { return true; }
541
542
73
  bool enableAggressiveFMAFusion(EVT VT) const override { return true; }
543
544
  // The default is to transform llvm.ctlz(x, false) (where false indicates that
545
  // x == 0 is not undefined behavior) into a branch that checks whether x is 0
546
  // and avoids calling ctlz in that case.  We have a dedicated ctlz
547
  // instruction, so we say that ctlz is cheap to speculate.
548
7
  bool isCheapToSpeculateCtlz() const override { return true; }
549
550
private:
551
  const NVPTXSubtarget &STI; // cache the subtarget here
552
  SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
553
554
  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
555
  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
556
  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
559
  SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
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  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
562
  SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
563
  SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
564
565
  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
566
  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
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568
  SDValue LowerSelect(SDValue Op, SelectionDAG &DAG) const;
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  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
571
                          SelectionDAG &DAG) const override;
572
  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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  unsigned getArgumentAlignment(SDValue Callee, ImmutableCallSite CS, Type *Ty,
575
                                unsigned Idx, const DataLayout &DL) const;
576
};
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} // namespace llvm
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#endif