/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
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1 | | //===--------------- PPCVSXFMAMutate.cpp - VSX FMA Mutation ---------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This pass mutates the form of VSX FMA instructions to avoid unnecessary |
11 | | // copies. |
12 | | // |
13 | | //===----------------------------------------------------------------------===// |
14 | | |
15 | | #include "MCTargetDesc/PPCPredicates.h" |
16 | | #include "PPC.h" |
17 | | #include "PPCInstrBuilder.h" |
18 | | #include "PPCInstrInfo.h" |
19 | | #include "PPCMachineFunctionInfo.h" |
20 | | #include "PPCTargetMachine.h" |
21 | | #include "llvm/ADT/STLExtras.h" |
22 | | #include "llvm/ADT/Statistic.h" |
23 | | #include "llvm/CodeGen/LiveIntervalAnalysis.h" |
24 | | #include "llvm/CodeGen/MachineDominators.h" |
25 | | #include "llvm/CodeGen/MachineFrameInfo.h" |
26 | | #include "llvm/CodeGen/MachineFunctionPass.h" |
27 | | #include "llvm/CodeGen/MachineInstrBuilder.h" |
28 | | #include "llvm/CodeGen/MachineMemOperand.h" |
29 | | #include "llvm/CodeGen/MachineRegisterInfo.h" |
30 | | #include "llvm/CodeGen/PseudoSourceValue.h" |
31 | | #include "llvm/CodeGen/ScheduleDAG.h" |
32 | | #include "llvm/CodeGen/SlotIndexes.h" |
33 | | #include "llvm/MC/MCAsmInfo.h" |
34 | | #include "llvm/Support/CommandLine.h" |
35 | | #include "llvm/Support/Debug.h" |
36 | | #include "llvm/Support/ErrorHandling.h" |
37 | | #include "llvm/Support/TargetRegistry.h" |
38 | | #include "llvm/Support/raw_ostream.h" |
39 | | |
40 | | using namespace llvm; |
41 | | |
42 | | // Temporarily disable FMA mutation by default, since it doesn't handle |
43 | | // cross-basic-block intervals well. |
44 | | // See: http://lists.llvm.org/pipermail/llvm-dev/2016-February/095669.html |
45 | | // http://reviews.llvm.org/D17087 |
46 | | static cl::opt<bool> DisableVSXFMAMutate( |
47 | | "disable-ppc-vsx-fma-mutation", |
48 | | cl::desc("Disable VSX FMA instruction mutation"), cl::init(true), |
49 | | cl::Hidden); |
50 | | |
51 | | #define DEBUG_TYPE "ppc-vsx-fma-mutate" |
52 | | |
53 | | namespace llvm { namespace PPC { |
54 | | int getAltVSXFMAOpcode(uint16_t Opcode); |
55 | | } } |
56 | | |
57 | | namespace { |
58 | | // PPCVSXFMAMutate pass - For copies between VSX registers and non-VSX registers |
59 | | // (Altivec and scalar floating-point registers), we need to transform the |
60 | | // copies into subregister copies with other restrictions. |
61 | | struct PPCVSXFMAMutate : public MachineFunctionPass { |
62 | | static char ID; |
63 | 1.22k | PPCVSXFMAMutate() : MachineFunctionPass(ID) { |
64 | 1.22k | initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry()); |
65 | 1.22k | } |
66 | | |
67 | | LiveIntervals *LIS; |
68 | | const PPCInstrInfo *TII; |
69 | | |
70 | | protected: |
71 | 84 | bool processBlock(MachineBasicBlock &MBB) { |
72 | 84 | bool Changed = false; |
73 | 84 | |
74 | 84 | MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); |
75 | 84 | const TargetRegisterInfo *TRI = &TII->getRegisterInfo(); |
76 | 84 | for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end(); |
77 | 778 | I != IE778 ; ++I694 ) { |
78 | 694 | MachineInstr &MI = *I; |
79 | 694 | |
80 | 694 | // The default (A-type) VSX FMA form kills the addend (it is taken from |
81 | 694 | // the target register, which is then updated to reflect the result of |
82 | 694 | // the FMA). If the instruction, however, kills one of the registers |
83 | 694 | // used for the product, then we can use the M-form instruction (which |
84 | 694 | // will take that value from the to-be-defined register). |
85 | 694 | |
86 | 694 | int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode()); |
87 | 694 | if (AltOpc == -1) |
88 | 588 | continue; |
89 | 106 | |
90 | 106 | // This pass is run after register coalescing, and so we're looking for |
91 | 106 | // a situation like this: |
92 | 106 | // ... |
93 | 106 | // %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9 |
94 | 106 | // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16, |
95 | 106 | // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16 |
96 | 106 | // ... |
97 | 106 | // %vreg9<def,tied1> = XSMADDADP %vreg9<tied0>, %vreg17, %vreg19, |
98 | 106 | // %RM<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19 |
99 | 106 | // ... |
100 | 106 | // Where we can eliminate the copy by changing from the A-type to the |
101 | 106 | // M-type instruction. Specifically, for this example, this means: |
102 | 106 | // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16, |
103 | 106 | // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16 |
104 | 106 | // is replaced by: |
105 | 106 | // %vreg16<def,tied1> = XSMADDMDP %vreg16<tied0>, %vreg18, %vreg9, |
106 | 106 | // %RM<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9 |
107 | 106 | // and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9 |
108 | 106 | |
109 | 106 | SlotIndex FMAIdx = LIS->getInstructionIndex(MI); |
110 | 106 | |
111 | 106 | VNInfo *AddendValNo = |
112 | 106 | LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn(); |
113 | 106 | |
114 | 106 | // This can be null if the register is undef. |
115 | 106 | if (!AddendValNo) |
116 | 0 | continue; |
117 | 106 | |
118 | 106 | MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def); |
119 | 106 | |
120 | 106 | // The addend and this instruction must be in the same block. |
121 | 106 | |
122 | 106 | if (!AddendMI || 106 AddendMI->getParent() != MI.getParent()106 ) |
123 | 0 | continue; |
124 | 106 | |
125 | 106 | // The addend must be a full copy within the same register class. |
126 | 106 | |
127 | 106 | if (106 !AddendMI->isFullCopy()106 ) |
128 | 25 | continue; |
129 | 81 | |
130 | 81 | unsigned AddendSrcReg = AddendMI->getOperand(1).getReg(); |
131 | 81 | if (TargetRegisterInfo::isVirtualRegister(AddendSrcReg)81 ) { |
132 | 6 | if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != |
133 | 6 | MRI.getRegClass(AddendSrcReg)) |
134 | 0 | continue; |
135 | 75 | } else { |
136 | 75 | // If AddendSrcReg is a physical register, make sure the destination |
137 | 75 | // register class contains it. |
138 | 75 | if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) |
139 | 75 | ->contains(AddendSrcReg)) |
140 | 0 | continue; |
141 | 81 | } |
142 | 81 | |
143 | 81 | // In theory, there could be other uses of the addend copy before this |
144 | 81 | // fma. We could deal with this, but that would require additional |
145 | 81 | // logic below and I suspect it will not occur in any relevant |
146 | 81 | // situations. Additionally, check whether the copy source is killed |
147 | 81 | // prior to the fma. In order to replace the addend here with the |
148 | 81 | // source of the copy, it must still be live here. We can't use |
149 | 81 | // interval testing for a physical register, so as long as we're |
150 | 81 | // walking the MIs we may as well test liveness here. |
151 | 81 | // |
152 | 81 | // FIXME: There is a case that occurs in practice, like this: |
153 | 81 | // %vreg9<def> = COPY %F1; VSSRC:%vreg9 |
154 | 81 | // ... |
155 | 81 | // %vreg6<def> = COPY %vreg9; VSSRC:%vreg6,%vreg9 |
156 | 81 | // %vreg7<def> = COPY %vreg9; VSSRC:%vreg7,%vreg9 |
157 | 81 | // %vreg9<def,tied1> = XSMADDASP %vreg9<tied0>, %vreg1, %vreg4; VSSRC: |
158 | 81 | // %vreg6<def,tied1> = XSMADDASP %vreg6<tied0>, %vreg1, %vreg2; VSSRC: |
159 | 81 | // %vreg7<def,tied1> = XSMADDASP %vreg7<tied0>, %vreg1, %vreg3; VSSRC: |
160 | 81 | // which prevents an otherwise-profitable transformation. |
161 | 81 | bool OtherUsers = false, KillsAddendSrc = false; |
162 | 81 | for (auto J = std::prev(I), JE = MachineBasicBlock::iterator(AddendMI); |
163 | 257 | J != JE257 ; --J176 ) { |
164 | 184 | if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())184 ) { |
165 | 4 | OtherUsers = true; |
166 | 4 | break; |
167 | 4 | } |
168 | 180 | if (180 J->modifiesRegister(AddendSrcReg, TRI) || |
169 | 180 | J->killsRegister(AddendSrcReg, TRI)176 ) { |
170 | 4 | KillsAddendSrc = true; |
171 | 4 | break; |
172 | 4 | } |
173 | 184 | } |
174 | 81 | |
175 | 81 | if (OtherUsers || 81 KillsAddendSrc77 ) |
176 | 8 | continue; |
177 | 73 | |
178 | 73 | |
179 | 73 | // The transformation doesn't work well with things like: |
180 | 73 | // %vreg5 = A-form-op %vreg5, %vreg11, %vreg5; |
181 | 73 | // unless vreg11 is also a kill, so skip when it is not, |
182 | 73 | // and check operand 3 to see it is also a kill to handle the case: |
183 | 73 | // %vreg5 = A-form-op %vreg5, %vreg5, %vreg11; |
184 | 73 | // where vreg5 and vreg11 are both kills. This case would be skipped |
185 | 73 | // otherwise. |
186 | 73 | unsigned OldFMAReg = MI.getOperand(0).getReg(); |
187 | 73 | |
188 | 73 | // Find one of the product operands that is killed by this instruction. |
189 | 73 | unsigned KilledProdOp = 0, OtherProdOp = 0; |
190 | 73 | unsigned Reg2 = MI.getOperand(2).getReg(); |
191 | 73 | unsigned Reg3 = MI.getOperand(3).getReg(); |
192 | 73 | if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() |
193 | 73 | && Reg2 != OldFMAReg64 ) { |
194 | 64 | KilledProdOp = 2; |
195 | 64 | OtherProdOp = 3; |
196 | 73 | } else if (9 LIS->getInterval(Reg3).Query(FMAIdx).isKill() |
197 | 9 | && Reg3 != OldFMAReg2 ) { |
198 | 1 | KilledProdOp = 3; |
199 | 1 | OtherProdOp = 2; |
200 | 1 | } |
201 | 73 | |
202 | 73 | // If there are no usable killed product operands, then this |
203 | 73 | // transformation is likely not profitable. |
204 | 73 | if (!KilledProdOp) |
205 | 8 | continue; |
206 | 65 | |
207 | 65 | // If the addend copy is used only by this MI, then the addend source |
208 | 65 | // register is likely not live here. This could be fixed (based on the |
209 | 65 | // legality checks above, the live range for the addend source register |
210 | 65 | // could be extended), but it seems likely that such a trivial copy can |
211 | 65 | // be coalesced away later, and thus is not worth the effort. |
212 | 65 | if (65 TargetRegisterInfo::isVirtualRegister(AddendSrcReg) && |
213 | 1 | !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx)) |
214 | 0 | continue; |
215 | 65 | |
216 | 65 | // Transform: (O2 * O3) + O1 -> (O2 * O1) + O3. |
217 | 65 | |
218 | 65 | unsigned KilledProdReg = MI.getOperand(KilledProdOp).getReg(); |
219 | 65 | unsigned OtherProdReg = MI.getOperand(OtherProdOp).getReg(); |
220 | 65 | |
221 | 65 | unsigned AddSubReg = AddendMI->getOperand(1).getSubReg(); |
222 | 65 | unsigned KilledProdSubReg = MI.getOperand(KilledProdOp).getSubReg(); |
223 | 65 | unsigned OtherProdSubReg = MI.getOperand(OtherProdOp).getSubReg(); |
224 | 65 | |
225 | 65 | bool AddRegKill = AddendMI->getOperand(1).isKill(); |
226 | 65 | bool KilledProdRegKill = MI.getOperand(KilledProdOp).isKill(); |
227 | 65 | bool OtherProdRegKill = MI.getOperand(OtherProdOp).isKill(); |
228 | 65 | |
229 | 65 | bool AddRegUndef = AddendMI->getOperand(1).isUndef(); |
230 | 65 | bool KilledProdRegUndef = MI.getOperand(KilledProdOp).isUndef(); |
231 | 65 | bool OtherProdRegUndef = MI.getOperand(OtherProdOp).isUndef(); |
232 | 65 | |
233 | 65 | // If there isn't a class that fits, we can't perform the transform. |
234 | 65 | // This is needed for correctness with a mixture of VSX and Altivec |
235 | 65 | // instructions to make sure that a low VSX register is not assigned to |
236 | 65 | // the Altivec instruction. |
237 | 65 | if (!MRI.constrainRegClass(KilledProdReg, |
238 | 65 | MRI.getRegClass(OldFMAReg))) |
239 | 0 | continue; |
240 | 65 | |
241 | 65 | assert(OldFMAReg == AddendMI->getOperand(0).getReg() && |
242 | 65 | "Addend copy not tied to old FMA output!"); |
243 | 65 | |
244 | 65 | DEBUG(dbgs() << "VSX FMA Mutation:\n " << MI); |
245 | 65 | |
246 | 65 | MI.getOperand(0).setReg(KilledProdReg); |
247 | 65 | MI.getOperand(1).setReg(KilledProdReg); |
248 | 65 | MI.getOperand(3).setReg(AddendSrcReg); |
249 | 65 | |
250 | 65 | MI.getOperand(0).setSubReg(KilledProdSubReg); |
251 | 65 | MI.getOperand(1).setSubReg(KilledProdSubReg); |
252 | 65 | MI.getOperand(3).setSubReg(AddSubReg); |
253 | 65 | |
254 | 65 | MI.getOperand(1).setIsKill(KilledProdRegKill); |
255 | 65 | MI.getOperand(3).setIsKill(AddRegKill); |
256 | 65 | |
257 | 65 | MI.getOperand(1).setIsUndef(KilledProdRegUndef); |
258 | 65 | MI.getOperand(3).setIsUndef(AddRegUndef); |
259 | 65 | |
260 | 65 | MI.setDesc(TII->get(AltOpc)); |
261 | 65 | |
262 | 65 | // If the addend is also a multiplicand, replace it with the addend |
263 | 65 | // source in both places. |
264 | 65 | if (OtherProdReg == AddendMI->getOperand(0).getReg()65 ) { |
265 | 0 | MI.getOperand(2).setReg(AddendSrcReg); |
266 | 0 | MI.getOperand(2).setSubReg(AddSubReg); |
267 | 0 | MI.getOperand(2).setIsKill(AddRegKill); |
268 | 0 | MI.getOperand(2).setIsUndef(AddRegUndef); |
269 | 65 | } else { |
270 | 65 | MI.getOperand(2).setReg(OtherProdReg); |
271 | 65 | MI.getOperand(2).setSubReg(OtherProdSubReg); |
272 | 65 | MI.getOperand(2).setIsKill(OtherProdRegKill); |
273 | 65 | MI.getOperand(2).setIsUndef(OtherProdRegUndef); |
274 | 65 | } |
275 | 65 | |
276 | 65 | DEBUG(dbgs() << " -> " << MI); |
277 | 65 | |
278 | 65 | // The killed product operand was killed here, so we can reuse it now |
279 | 65 | // for the result of the fma. |
280 | 65 | |
281 | 65 | LiveInterval &FMAInt = LIS->getInterval(OldFMAReg); |
282 | 65 | VNInfo *FMAValNo = FMAInt.getVNInfoAt(FMAIdx.getRegSlot()); |
283 | 65 | for (auto UI = MRI.reg_nodbg_begin(OldFMAReg), UE = MRI.reg_nodbg_end(); |
284 | 235 | UI != UE235 ;) { |
285 | 170 | MachineOperand &UseMO = *UI; |
286 | 170 | MachineInstr *UseMI = UseMO.getParent(); |
287 | 170 | ++UI; |
288 | 170 | |
289 | 170 | // Don't replace the result register of the copy we're about to erase. |
290 | 170 | if (UseMI == AddendMI) |
291 | 65 | continue; |
292 | 105 | |
293 | 105 | UseMO.substVirtReg(KilledProdReg, KilledProdSubReg, *TRI); |
294 | 105 | } |
295 | 65 | |
296 | 65 | // Extend the live intervals of the killed product operand to hold the |
297 | 65 | // fma result. |
298 | 65 | |
299 | 65 | LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg); |
300 | 65 | for (LiveInterval::iterator AI = FMAInt.begin(), AE = FMAInt.end(); |
301 | 215 | AI != AE215 ; ++AI150 ) { |
302 | 150 | // Don't add the segment that corresponds to the original copy. |
303 | 150 | if (AI->valno == AddendValNo) |
304 | 65 | continue; |
305 | 85 | |
306 | 85 | VNInfo *NewFMAValNo = |
307 | 85 | NewFMAInt.getNextValue(AI->start, |
308 | 85 | LIS->getVNInfoAllocator()); |
309 | 85 | |
310 | 85 | NewFMAInt.addSegment(LiveInterval::Segment(AI->start, AI->end, |
311 | 85 | NewFMAValNo)); |
312 | 85 | } |
313 | 65 | DEBUG(dbgs() << " extended: " << NewFMAInt << '\n'); |
314 | 65 | |
315 | 65 | // Extend the live interval of the addend source (it might end at the |
316 | 65 | // copy to be removed, or somewhere in between there and here). This |
317 | 65 | // is necessary only if it is a physical register. |
318 | 65 | if (!TargetRegisterInfo::isVirtualRegister(AddendSrcReg)) |
319 | 128 | for (MCRegUnitIterator Units(AddendSrcReg, TRI); 64 Units.isValid()128 ; |
320 | 64 | ++Units64 ) { |
321 | 64 | unsigned Unit = *Units; |
322 | 64 | |
323 | 64 | LiveRange &AddendSrcRange = LIS->getRegUnit(Unit); |
324 | 64 | AddendSrcRange.extendInBlock(LIS->getMBBStartIdx(&MBB), |
325 | 64 | FMAIdx.getRegSlot()); |
326 | 64 | DEBUG(dbgs() << " extended: " << AddendSrcRange << '\n'); |
327 | 64 | } |
328 | 65 | |
329 | 65 | FMAInt.removeValNo(FMAValNo); |
330 | 65 | DEBUG(dbgs() << " trimmed: " << FMAInt << '\n'); |
331 | 65 | |
332 | 65 | // Remove the (now unused) copy. |
333 | 65 | |
334 | 65 | DEBUG(dbgs() << " removing: " << *AddendMI << '\n'); |
335 | 694 | LIS->RemoveMachineInstrFromMaps(*AddendMI); |
336 | 694 | AddendMI->eraseFromParent(); |
337 | 694 | |
338 | 694 | Changed = true; |
339 | 694 | } |
340 | 84 | |
341 | 84 | return Changed; |
342 | 84 | } |
343 | | |
344 | | public: |
345 | 6.86k | bool runOnMachineFunction(MachineFunction &MF) override { |
346 | 6.86k | if (skipFunction(*MF.getFunction())) |
347 | 1 | return false; |
348 | 6.85k | |
349 | 6.85k | // If we don't have VSX then go ahead and return without doing |
350 | 6.85k | // anything. |
351 | 6.85k | const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>(); |
352 | 6.85k | if (!STI.hasVSX()) |
353 | 2.19k | return false; |
354 | 4.66k | |
355 | 4.66k | LIS = &getAnalysis<LiveIntervals>(); |
356 | 4.66k | |
357 | 4.66k | TII = STI.getInstrInfo(); |
358 | 4.66k | |
359 | 4.66k | bool Changed = false; |
360 | 4.66k | |
361 | 4.66k | if (DisableVSXFMAMutate) |
362 | 4.58k | return Changed; |
363 | 82 | |
364 | 166 | for (MachineFunction::iterator I = MF.begin(); 82 I != MF.end()166 ;) { |
365 | 84 | MachineBasicBlock &B = *I++; |
366 | 84 | if (processBlock(B)) |
367 | 65 | Changed = true; |
368 | 84 | } |
369 | 6.86k | |
370 | 6.86k | return Changed; |
371 | 6.86k | } |
372 | | |
373 | 1.22k | void getAnalysisUsage(AnalysisUsage &AU) const override { |
374 | 1.22k | AU.addRequired<LiveIntervals>(); |
375 | 1.22k | AU.addPreserved<LiveIntervals>(); |
376 | 1.22k | AU.addRequired<SlotIndexes>(); |
377 | 1.22k | AU.addPreserved<SlotIndexes>(); |
378 | 1.22k | AU.addRequired<MachineDominatorTree>(); |
379 | 1.22k | AU.addPreserved<MachineDominatorTree>(); |
380 | 1.22k | MachineFunctionPass::getAnalysisUsage(AU); |
381 | 1.22k | } |
382 | | }; |
383 | | } |
384 | | |
385 | 1.23k | INITIALIZE_PASS_BEGIN1.23k (PPCVSXFMAMutate, DEBUG_TYPE,
|
386 | 1.23k | "PowerPC VSX FMA Mutation", false, false) |
387 | 1.23k | INITIALIZE_PASS_DEPENDENCY(LiveIntervals) |
388 | 1.23k | INITIALIZE_PASS_DEPENDENCY(SlotIndexes) |
389 | 1.23k | INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) |
390 | 1.23k | INITIALIZE_PASS_END(PPCVSXFMAMutate, DEBUG_TYPE, |
391 | | "PowerPC VSX FMA Mutation", false, false) |
392 | | |
393 | | char &llvm::PPCVSXFMAMutateID = PPCVSXFMAMutate::ID; |
394 | | |
395 | | char PPCVSXFMAMutate::ID = 0; |
396 | 0 | FunctionPass *llvm::createPPCVSXFMAMutatePass() { |
397 | 0 | return new PPCVSXFMAMutate(); |
398 | 0 | } |