/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
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1 | | //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | /// |
10 | | /// This file provides RISCV-specific target descriptions. |
11 | | /// |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "RISCVMCTargetDesc.h" |
15 | | #include "RISCVMCAsmInfo.h" |
16 | | #include "llvm/ADT/STLExtras.h" |
17 | | #include "llvm/MC/MCAsmInfo.h" |
18 | | #include "llvm/MC/MCInstrInfo.h" |
19 | | #include "llvm/MC/MCRegisterInfo.h" |
20 | | #include "llvm/MC/MCStreamer.h" |
21 | | #include "llvm/MC/MCSubtargetInfo.h" |
22 | | #include "llvm/Support/ErrorHandling.h" |
23 | | #include "llvm/Support/TargetRegistry.h" |
24 | | |
25 | | #define GET_INSTRINFO_MC_DESC |
26 | | #include "RISCVGenInstrInfo.inc" |
27 | | |
28 | | #define GET_REGINFO_MC_DESC |
29 | | #include "RISCVGenRegisterInfo.inc" |
30 | | |
31 | | using namespace llvm; |
32 | | |
33 | 0 | static MCInstrInfo *createRISCVMCInstrInfo() { |
34 | 0 | MCInstrInfo *X = new MCInstrInfo(); |
35 | 0 | InitRISCVMCInstrInfo(X); |
36 | 0 | return X; |
37 | 0 | } |
38 | | |
39 | 0 | static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) { |
40 | 0 | MCRegisterInfo *X = new MCRegisterInfo(); |
41 | 0 | InitRISCVMCRegisterInfo(X, RISCV::X1_32); |
42 | 0 | return X; |
43 | 0 | } |
44 | | |
45 | | static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, |
46 | 0 | const Triple &TT) { |
47 | 0 | return new RISCVMCAsmInfo(TT); |
48 | 0 | } |
49 | | |
50 | 68.9k | extern "C" void LLVMInitializeRISCVTargetMC() { |
51 | 137k | for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) { |
52 | 137k | TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo); |
53 | 137k | TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo); |
54 | 137k | TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo); |
55 | 137k | TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend); |
56 | 137k | TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter); |
57 | 137k | } |
58 | 68.9k | } |