Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Sparc/SparcInstrInfo.h
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//===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Sparc implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
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#define LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
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#include "SparcRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "SparcGenInstrInfo.inc"
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namespace llvm {
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class SparcSubtarget;
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/// SPII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace SPII {
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  enum {
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    Pseudo = (1<<0),
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    Load = (1<<1),
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    Store = (1<<2),
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    DelaySlot = (1<<3)
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  };
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}
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class SparcInstrInfo : public SparcGenInstrInfo {
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  const SparcRegisterInfo RI;
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  const SparcSubtarget& Subtarget;
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  virtual void anchor();
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public:
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  explicit SparcInstrInfo(SparcSubtarget &ST);
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  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
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  /// such, whenever a client has an instance of instruction info, it should
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  /// always be able to get register info as well (through this method).
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  ///
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  const SparcRegisterInfo &getRegisterInfo() const { return RI; }
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  /// isLoadFromStackSlot - If the specified machine instruction is a direct
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  /// load from a stack slot, return the virtual or physical register number of
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  /// the destination along with the FrameIndex of the loaded stack slot.  If
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  /// not, return 0.  This predicate must return 0 if the instruction has
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  /// any side effects other than loading from the stack slot.
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  unsigned isLoadFromStackSlot(const MachineInstr &MI,
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                               int &FrameIndex) const override;
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  /// isStoreToStackSlot - If the specified machine instruction is a direct
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  /// store to a stack slot, return the virtual or physical register number of
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  /// the source reg along with the FrameIndex of the loaded stack slot.  If
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  /// not, return 0.  This predicate must return 0 if the instruction has
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  /// any side effects other than storing to the stack slot.
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  unsigned isStoreToStackSlot(const MachineInstr &MI,
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                              int &FrameIndex) const override;
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  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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                     MachineBasicBlock *&FBB,
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                     SmallVectorImpl<MachineOperand> &Cond,
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                     bool AllowModify = false) const override;
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  unsigned removeBranch(MachineBasicBlock &MBB,
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                        int *BytesRemoved = nullptr) const override;
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  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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                        MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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                        const DebugLoc &DL,
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                        int *BytesAdded = nullptr) const override;
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  bool
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  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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                   const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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                   bool KillSrc) const override;
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  void storeRegToStackSlot(MachineBasicBlock &MBB,
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                           MachineBasicBlock::iterator MBBI,
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                           unsigned SrcReg, bool isKill, int FrameIndex,
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                           const TargetRegisterClass *RC,
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                           const TargetRegisterInfo *TRI) const override;
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  void loadRegFromStackSlot(MachineBasicBlock &MBB,
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                            MachineBasicBlock::iterator MBBI,
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                            unsigned DestReg, int FrameIndex,
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                            const TargetRegisterClass *RC,
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                            const TargetRegisterInfo *TRI) const override;
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  unsigned getGlobalBaseReg(MachineFunction *MF) const;
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  // Lower pseudo instructions after register allocation.
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  bool expandPostRAPseudo(MachineInstr &MI) const override;
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};
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}
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#endif