Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/X86/X86RegisterBankInfo.cpp
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//===- X86RegisterBankInfo.cpp -----------------------------------*- C++ -*-==//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the RegisterBankInfo class for X86.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "X86RegisterBankInfo.h"
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#include "X86InstrInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_TARGET_REGBANK_IMPL
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#include "X86GenRegisterBank.inc"
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using namespace llvm;
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// This file will be TableGen'ed at some point.
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#define GET_TARGET_REGBANK_INFO_IMPL
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#include "X86GenRegisterBankInfo.def"
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X86RegisterBankInfo::X86RegisterBankInfo(const TargetRegisterInfo &TRI)
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    : X86GenRegisterBankInfo() {
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  // validate RegBank initialization.
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  const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID);
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  (void)RBGPR;
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  assert(&X86::GPRRegBank == &RBGPR && "Incorrect RegBanks inizalization.");
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  // The GPR register bank is fully defined by all the registers in
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  // GR64 + its subclasses.
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  assert(RBGPR.covers(*TRI.getRegClass(X86::GR64RegClassID)) &&
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         "Subclass not added?");
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  assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
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}
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const RegisterBank &X86RegisterBankInfo::getRegBankFromRegClass(
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    const TargetRegisterClass &RC) const {
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  if (X86::GR8RegClass.hasSubClassEq(&RC) ||
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      X86::GR16RegClass.hasSubClassEq(&RC) ||
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      X86::GR32RegClass.hasSubClassEq(&RC) ||
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      X86::GR64RegClass.hasSubClassEq(&RC))
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    return getRegBank(X86::GPRRegBankID);
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if (2.96k
X86::FR32XRegClass.hasSubClassEq(&RC) ||
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      X86::FR64XRegClass.hasSubClassEq(&RC) ||
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      X86::VR128XRegClass.hasSubClassEq(&RC) ||
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      X86::VR256XRegClass.hasSubClassEq(&RC) ||
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      X86::VR512RegClass.hasSubClassEq(&RC))
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    return getRegBank(X86::VECRRegBankID);
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0
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0
  
llvm_unreachable0
("Unsupported register kind yet.");
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0
}
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X86GenRegisterBankInfo::PartialMappingIdx
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X86GenRegisterBankInfo::getPartialMappingIdx(const LLT &Ty, bool isFP) {
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  if (
(Ty.isScalar() && 1.98k
!isFP1.05k
) ||
Ty.isPointer()1.02k
) {
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    switch (Ty.getSizeInBits()) {
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    case 1:
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    case 8:
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      return PMI_GPR8;
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    case 16:
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      return PMI_GPR16;
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    case 32:
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      return PMI_GPR32;
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    case 64:
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      return PMI_GPR64;
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0
      break;
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    default:
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      llvm_unreachable("Unsupported register size.");
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    }
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  } else 
if (389
Ty.isScalar()389
) {
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    switch (Ty.getSizeInBits()) {
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    case 32:
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      return PMI_FP32;
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    case 64:
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      return PMI_FP64;
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    default:
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      llvm_unreachable("Unsupported register size.");
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    }
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  } else {
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    switch (Ty.getSizeInBits()) {
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    case 128:
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      return PMI_VEC128;
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    case 256:
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      return PMI_VEC256;
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    case 512:
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      return PMI_VEC512;
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    default:
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      llvm_unreachable("Unsupported register size.");
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    }
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  }
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  return PMI_None;
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}
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void X86RegisterBankInfo::getInstrPartialMappingIdxs(
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    const MachineInstr &MI, const MachineRegisterInfo &MRI, const bool isFP,
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    SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx) {
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  unsigned NumOperands = MI.getNumOperands();
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  for (unsigned Idx = 0; 
Idx < NumOperands3.03k
;
++Idx2.07k
) {
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    auto &MO = MI.getOperand(Idx);
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    if (!MO.isReg())
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      OpRegBankIdx[Idx] = PMI_None;
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    else
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      OpRegBankIdx[Idx] = getPartialMappingIdx(MRI.getType(MO.getReg()), isFP);
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  }
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}
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bool X86RegisterBankInfo::getInstrValueMapping(
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    const MachineInstr &MI,
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    const SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx,
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    SmallVectorImpl<const ValueMapping *> &OpdsMapping) {
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  unsigned NumOperands = MI.getNumOperands();
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  for (unsigned Idx = 0; 
Idx < NumOperands3.03k
;
++Idx2.07k
) {
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    if (!MI.getOperand(Idx).isReg())
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      continue;
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    auto Mapping = getValueMapping(OpRegBankIdx[Idx], 1);
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    if (!Mapping->isValid())
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      return false;
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    OpdsMapping[Idx] = Mapping;
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  }
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  return true;
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}
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const RegisterBankInfo::InstructionMapping &
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X86RegisterBankInfo::getSameOperandsMapping(const MachineInstr &MI,
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                                            bool isFP) const {
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  const MachineFunction &MF = *MI.getParent()->getParent();
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  const MachineRegisterInfo &MRI = MF.getRegInfo();
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  unsigned NumOperands = MI.getNumOperands();
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  LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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  if (
NumOperands != 3 || 192
(Ty != MRI.getType(MI.getOperand(1).getReg()))192
||
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      (Ty != MRI.getType(MI.getOperand(2).getReg())))
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    llvm_unreachable("Unsupported operand mapping yet.");
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  auto Mapping = getValueMapping(getPartialMappingIdx(Ty, isFP), 3);
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  return getInstructionMapping(DefaultMappingID, 1, Mapping, NumOperands);
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}
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const RegisterBankInfo::InstructionMapping &
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X86RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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  const MachineFunction &MF = *MI.getParent()->getParent();
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  const MachineRegisterInfo &MRI = MF.getRegInfo();
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  auto Opc = MI.getOpcode();
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  // Try the default logic for non-generic instructions that are either copies
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  // or already have some operands assigned to banks.
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  if (
!isPreISelGenericOpcode(Opc) || 2.18k
Opc == TargetOpcode::G_PHI1.06k
) {
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    const InstructionMapping &Mapping = getInstrMappingImpl(MI);
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    if (Mapping.isValid())
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      return Mapping;
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  }
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  switch (Opc) {
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  case TargetOpcode::G_ADD:
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  case TargetOpcode::G_SUB:
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    return getSameOperandsMapping(MI, false);
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    break;
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  case TargetOpcode::G_FADD:
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  case TargetOpcode::G_FSUB:
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  case TargetOpcode::G_FMUL:
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  case TargetOpcode::G_FDIV:
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    return getSameOperandsMapping(MI, true);
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    break;
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  default:
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    break;
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  }
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  unsigned NumOperands = MI.getNumOperands();
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  SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
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  switch (Opc) {
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  case TargetOpcode::G_FPEXT:
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  case TargetOpcode::G_FCONSTANT:
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    // Instruction having only floating-point operands (all scalars in VECRReg)
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    getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx);
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    break;
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  default:
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    // Track the bank of each register, use NotFP mapping (all scalars in GPRs)
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    getInstrPartialMappingIdxs(MI, MRI, /* isFP */ false, OpRegBankIdx);
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    break;
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  }
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  // Finally construct the computed mapping.
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  SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
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  if (!getInstrValueMapping(MI, OpRegBankIdx, OpdsMapping))
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    return getInvalidInstructionMapping();
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  return getInstructionMapping(DefaultMappingID, /* Cost */ 1,
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                               getOperandsMapping(OpdsMapping), NumOperands);
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}
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void X86RegisterBankInfo::applyMappingImpl(
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    const OperandsMapper &OpdMapper) const {
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  return applyDefaultMapping(OpdMapper);
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}
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RegisterBankInfo::InstructionMappings
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X86RegisterBankInfo::getInstrAlternativeMappings(const MachineInstr &MI) const {
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  const MachineFunction &MF = *MI.getParent()->getParent();
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  const TargetSubtargetInfo &STI = MF.getSubtarget();
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  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
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  const MachineRegisterInfo &MRI = MF.getRegInfo();
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  switch (MI.getOpcode()) {
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  case TargetOpcode::G_LOAD:
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  case TargetOpcode::G_STORE:
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  case TargetOpcode::G_IMPLICIT_DEF: {
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    // we going to try to map 32/64 bit to PMI_FP32/PMI_FP64
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    unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
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    if (
Size != 32 && 74
Size != 6444
)
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      break;
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    unsigned NumOperands = MI.getNumOperands();
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    // Track the bank of each register, use FP mapping (all scalars in VEC)
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    SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
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    getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx);
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    // Finally construct the computed mapping.
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    SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
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    if (!getInstrValueMapping(MI, OpRegBankIdx, OpdsMapping))
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      break;
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    const RegisterBankInfo::InstructionMapping &Mapping = getInstructionMapping(
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        /*ID*/ 1, /*Cost*/ 1, getOperandsMapping(OpdsMapping), NumOperands);
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    InstructionMappings AltMappings;
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    AltMappings.push_back(&Mapping);
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    return AltMappings;
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  }
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  default:
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    break;
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  }
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  return RegisterBankInfo::getInstrAlternativeMappings(MI);
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}