Coverage Report

Created: 2017-09-19 22:28

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/tools/lld/ELF/Arch/AArch64.cpp
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//===- AArch64.cpp --------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#include "Error.h"
11
#include "Symbols.h"
12
#include "SyntheticSections.h"
13
#include "Target.h"
14
#include "Thunks.h"
15
#include "llvm/Object/ELF.h"
16
#include "llvm/Support/Endian.h"
17
18
using namespace llvm;
19
using namespace llvm::support::endian;
20
using namespace llvm::ELF;
21
using namespace lld;
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using namespace lld::elf;
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24
// Page(Expr) is the page address of the expression Expr, defined
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// as (Expr & ~0xFFF). (This applies even if the machine page size
26
// supported by the platform has a different value.)
27
88
uint64_t elf::getAArch64Page(uint64_t Expr) {
28
88
  return Expr & ~static_cast<uint64_t>(0xFFF);
29
88
}
30
31
namespace {
32
class AArch64 final : public TargetInfo {
33
public:
34
  AArch64();
35
  RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, const InputFile &File,
36
                     const uint8_t *Loc) const override;
37
  bool isPicRel(uint32_t Type) const override;
38
  void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
39
  void writePltHeader(uint8_t *Buf) const override;
40
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
41
                int32_t Index, unsigned RelOff) const override;
42
  bool usesOnlyLowPageBits(uint32_t Type) const override;
43
  void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
44
  RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
45
                          RelExpr Expr) const override;
46
  void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
47
  void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
48
  void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
49
};
50
} // namespace
51
52
72
AArch64::AArch64() {
53
72
  CopyRel = R_AARCH64_COPY;
54
72
  RelativeRel = R_AARCH64_RELATIVE;
55
72
  IRelativeRel = R_AARCH64_IRELATIVE;
56
72
  GotRel = R_AARCH64_GLOB_DAT;
57
72
  PltRel = R_AARCH64_JUMP_SLOT;
58
72
  TlsDescRel = R_AARCH64_TLSDESC;
59
72
  TlsGotRel = R_AARCH64_TLS_TPREL64;
60
72
  GotEntrySize = 8;
61
72
  GotPltEntrySize = 8;
62
72
  PltEntrySize = 16;
63
72
  PltHeaderSize = 32;
64
72
  DefaultMaxPageSize = 65536;
65
72
66
72
  // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant
67
72
  // 1 of the tls structures and the tcb size is 16.
68
72
  TcbSize = 16;
69
72
}
70
71
RelExpr AArch64::getRelExpr(uint32_t Type, const SymbolBody &S,
72
178
                            const InputFile &File, const uint8_t *Loc) const {
73
178
  switch (Type) {
74
52
  default:
75
52
    return R_ABS;
76
6
  case R_AARCH64_TLSDESC_ADR_PAGE21:
77
6
    return R_TLSDESC_PAGE;
78
12
  case R_AARCH64_TLSDESC_LD64_LO12:
79
12
  case R_AARCH64_TLSDESC_ADD_LO12:
80
12
    return R_TLSDESC;
81
6
  case R_AARCH64_TLSDESC_CALL:
82
6
    return R_TLSDESC_CALL;
83
4
  case R_AARCH64_TLSLE_ADD_TPREL_HI12:
84
4
  case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
85
4
    return R_TLS;
86
42
  case R_AARCH64_CALL26:
87
42
  case R_AARCH64_CONDBR19:
88
42
  case R_AARCH64_JUMP26:
89
42
  case R_AARCH64_TSTBR14:
90
42
    return R_PLT_PC;
91
27
  case R_AARCH64_PREL16:
92
27
  case R_AARCH64_PREL32:
93
27
  case R_AARCH64_PREL64:
94
27
  case R_AARCH64_ADR_PREL_LO21:
95
27
    return R_PC;
96
7
  case R_AARCH64_ADR_PREL_PG_HI21:
97
7
    return R_PAGE_PC;
98
10
  case R_AARCH64_LD64_GOT_LO12_NC:
99
10
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
100
10
    return R_GOT;
101
11
  case R_AARCH64_ADR_GOT_PAGE:
102
11
  case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
103
11
    return R_GOT_PAGE_PC;
104
1
  case R_AARCH64_NONE:
105
1
    return R_NONE;
106
0
  }
107
0
}
108
109
RelExpr AArch64::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
110
8
                                 RelExpr Expr) const {
111
8
  if (
Expr == R_RELAX_TLS_GD_TO_IE8
) {
112
4
    if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
113
1
      return R_RELAX_TLS_GD_TO_IE_PAGE_PC;
114
3
    return R_RELAX_TLS_GD_TO_IE_ABS;
115
3
  }
116
4
  return Expr;
117
4
}
118
119
42
bool AArch64::usesOnlyLowPageBits(uint32_t Type) const {
120
42
  switch (Type) {
121
1
  default:
122
1
    return false;
123
41
  case R_AARCH64_ADD_ABS_LO12_NC:
124
41
  case R_AARCH64_LD64_GOT_LO12_NC:
125
41
  case R_AARCH64_LDST128_ABS_LO12_NC:
126
41
  case R_AARCH64_LDST16_ABS_LO12_NC:
127
41
  case R_AARCH64_LDST32_ABS_LO12_NC:
128
41
  case R_AARCH64_LDST64_ABS_LO12_NC:
129
41
  case R_AARCH64_LDST8_ABS_LO12_NC:
130
41
  case R_AARCH64_TLSDESC_ADD_LO12:
131
41
  case R_AARCH64_TLSDESC_LD64_LO12:
132
41
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
133
41
    return true;
134
0
  }
135
0
}
136
137
5
bool AArch64::isPicRel(uint32_t Type) const {
138
5
  return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64;
139
5
}
140
141
20
void AArch64::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
142
20
  write64le(Buf, InX::Plt->getVA());
143
20
}
144
145
6
void AArch64::writePltHeader(uint8_t *Buf) const {
146
6
  const uint8_t PltData[] = {
147
6
      0xf0, 0x7b, 0xbf, 0xa9, // stp    x16, x30, [sp,#-16]!
148
6
      0x10, 0x00, 0x00, 0x90, // adrp   x16, Page(&(.plt.got[2]))
149
6
      0x11, 0x02, 0x40, 0xf9, // ldr    x17, [x16, Offset(&(.plt.got[2]))]
150
6
      0x10, 0x02, 0x00, 0x91, // add    x16, x16, Offset(&(.plt.got[2]))
151
6
      0x20, 0x02, 0x1f, 0xd6, // br     x17
152
6
      0x1f, 0x20, 0x03, 0xd5, // nop
153
6
      0x1f, 0x20, 0x03, 0xd5, // nop
154
6
      0x1f, 0x20, 0x03, 0xd5  // nop
155
6
  };
156
6
  memcpy(Buf, PltData, sizeof(PltData));
157
6
158
6
  uint64_t Got = InX::GotPlt->getVA();
159
6
  uint64_t Plt = InX::Plt->getVA();
160
6
  relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
161
6
              getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
162
6
  relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
163
6
  relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16);
164
6
}
165
166
void AArch64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
167
                       uint64_t PltEntryAddr, int32_t Index,
168
20
                       unsigned RelOff) const {
169
20
  const uint8_t Inst[] = {
170
20
      0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n]))
171
20
      0x11, 0x02, 0x40, 0xf9, // ldr  x17, [x16, Offset(&(.plt.got[n]))]
172
20
      0x10, 0x02, 0x00, 0x91, // add  x16, x16, Offset(&(.plt.got[n]))
173
20
      0x20, 0x02, 0x1f, 0xd6  // br   x17
174
20
  };
175
20
  memcpy(Buf, Inst, sizeof(Inst));
176
20
177
20
  relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21,
178
20
              getAArch64Page(GotPltEntryAddr) - getAArch64Page(PltEntryAddr));
179
20
  relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotPltEntryAddr);
180
20
  relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotPltEntryAddr);
181
20
}
182
183
48
static void write32AArch64Addr(uint8_t *L, uint64_t Imm) {
184
48
  uint32_t ImmLo = (Imm & 0x3) << 29;
185
48
  uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
186
48
  uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
187
48
  write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
188
48
}
189
190
// Return the bits [Start, End] from Val shifted Start bits.
191
// For instance, getBits(0xF0, 4, 8) returns 0xF.
192
47
static uint64_t getBits(uint64_t Val, int Start, int End) {
193
47
  uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
194
47
  return (Val >> Start) & Mask;
195
47
}
196
197
143
static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
198
199
// Update the immediate field in a AARCH64 ldr, str, and add instruction.
200
85
static void or32AArch64Imm(uint8_t *L, uint64_t Imm) {
201
85
  or32le(L, (Imm & 0xFFF) << 10);
202
85
}
203
204
227
void AArch64::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
205
227
  switch (Type) {
206
13
  case R_AARCH64_ABS16:
207
13
  case R_AARCH64_PREL16:
208
13
    checkIntUInt<16>(Loc, Val, Type);
209
13
    write16le(Loc, Val);
210
13
    break;
211
16
  case R_AARCH64_ABS32:
212
16
  case R_AARCH64_PREL32:
213
16
    checkIntUInt<32>(Loc, Val, Type);
214
16
    write32le(Loc, Val);
215
16
    break;
216
5
  case R_AARCH64_ABS64:
217
5
  case R_AARCH64_GLOB_DAT:
218
5
  case R_AARCH64_PREL64:
219
5
    write64le(Loc, Val);
220
5
    break;
221
30
  case R_AARCH64_ADD_ABS_LO12_NC:
222
30
    or32AArch64Imm(Loc, Val);
223
30
    break;
224
44
  case R_AARCH64_ADR_GOT_PAGE:
225
44
  case R_AARCH64_ADR_PREL_PG_HI21:
226
44
  case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
227
44
  case R_AARCH64_TLSDESC_ADR_PAGE21:
228
44
    checkInt<33>(Loc, Val, Type);
229
44
    write32AArch64Addr(Loc, Val >> 12);
230
44
    break;
231
4
  case R_AARCH64_ADR_PREL_LO21:
232
4
    checkInt<21>(Loc, Val, Type);
233
4
    write32AArch64Addr(Loc, Val);
234
4
    break;
235
12
  case R_AARCH64_JUMP26:
236
12
    // Normally we would just write the bits of the immediate field, however
237
12
    // when patching instructions for the cpu errata fix -fix-cortex-a53-843419
238
12
    // we want to replace a non-branch instruction with a branch immediate
239
12
    // instruction. By writing all the bits of the instruction including the
240
12
    // opcode and the immediate (0 001 | 01 imm26) we can do this
241
12
    // transformation by placing a R_AARCH64_JUMP26 relocation at the offset of
242
12
    // the instruction we want to patch.
243
12
    write32le(Loc, 0x14000000);
244
12
    LLVM_FALLTHROUGH;
245
25
  case R_AARCH64_CALL26:
246
25
    checkInt<28>(Loc, Val, Type);
247
25
    or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
248
25
    break;
249
9
  case R_AARCH64_CONDBR19:
250
9
    checkInt<21>(Loc, Val, Type);
251
9
    or32le(Loc, (Val & 0x1FFFFC) << 3);
252
9
    break;
253
12
  case R_AARCH64_LD64_GOT_LO12_NC:
254
12
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
255
12
  case R_AARCH64_TLSDESC_LD64_LO12:
256
12
    checkAlignment<8>(Loc, Val, Type);
257
12
    or32le(Loc, (Val & 0xFF8) << 7);
258
12
    break;
259
3
  case R_AARCH64_LDST8_ABS_LO12_NC:
260
3
    or32AArch64Imm(Loc, getBits(Val, 0, 11));
261
3
    break;
262
6
  case R_AARCH64_LDST16_ABS_LO12_NC:
263
6
    checkAlignment<2>(Loc, Val, Type);
264
6
    or32AArch64Imm(Loc, getBits(Val, 1, 11));
265
6
    break;
266
4
  case R_AARCH64_LDST32_ABS_LO12_NC:
267
4
    checkAlignment<4>(Loc, Val, Type);
268
4
    or32AArch64Imm(Loc, getBits(Val, 2, 11));
269
4
    break;
270
30
  case R_AARCH64_LDST64_ABS_LO12_NC:
271
30
    checkAlignment<8>(Loc, Val, Type);
272
30
    or32AArch64Imm(Loc, getBits(Val, 3, 11));
273
30
    break;
274
4
  case R_AARCH64_LDST128_ABS_LO12_NC:
275
4
    checkAlignment<16>(Loc, Val, Type);
276
4
    or32AArch64Imm(Loc, getBits(Val, 4, 11));
277
4
    break;
278
1
  case R_AARCH64_MOVW_UABS_G0_NC:
279
1
    or32le(Loc, (Val & 0xFFFF) << 5);
280
1
    break;
281
1
  case R_AARCH64_MOVW_UABS_G1_NC:
282
1
    or32le(Loc, (Val & 0xFFFF0000) >> 11);
283
1
    break;
284
1
  case R_AARCH64_MOVW_UABS_G2_NC:
285
1
    or32le(Loc, (Val & 0xFFFF00000000) >> 27);
286
1
    break;
287
2
  case R_AARCH64_MOVW_UABS_G3:
288
2
    or32le(Loc, (Val & 0xFFFF000000000000) >> 43);
289
2
    break;
290
8
  case R_AARCH64_TSTBR14:
291
8
    checkInt<16>(Loc, Val, Type);
292
8
    or32le(Loc, (Val & 0xFFFC) << 3);
293
8
    break;
294
2
  case R_AARCH64_TLSLE_ADD_TPREL_HI12:
295
2
    checkInt<24>(Loc, Val, Type);
296
2
    or32AArch64Imm(Loc, Val >> 12);
297
2
    break;
298
6
  case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
299
6
  case R_AARCH64_TLSDESC_ADD_LO12:
300
6
    or32AArch64Imm(Loc, Val);
301
6
    break;
302
0
  default:
303
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
304
227
  }
305
227
}
306
307
4
void AArch64::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
308
4
  // TLSDESC Global-Dynamic relocation are in the form:
309
4
  //   adrp    x0, :tlsdesc:v             [R_AARCH64_TLSDESC_ADR_PAGE21]
310
4
  //   ldr     x1, [x0, #:tlsdesc_lo12:v  [R_AARCH64_TLSDESC_LD64_LO12]
311
4
  //   add     x0, x0, :tlsdesc_los:v     [R_AARCH64_TLSDESC_ADD_LO12]
312
4
  //   .tlsdesccall                       [R_AARCH64_TLSDESC_CALL]
313
4
  //   blr     x1
314
4
  // And it can optimized to:
315
4
  //   movz    x0, #0x0, lsl #16
316
4
  //   movk    x0, #0x10
317
4
  //   nop
318
4
  //   nop
319
4
  checkUInt<32>(Loc, Val, Type);
320
4
321
4
  switch (Type) {
322
2
  case R_AARCH64_TLSDESC_ADD_LO12:
323
2
  case R_AARCH64_TLSDESC_CALL:
324
2
    write32le(Loc, 0xd503201f); // nop
325
2
    return;
326
1
  case R_AARCH64_TLSDESC_ADR_PAGE21:
327
1
    write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
328
1
    return;
329
1
  case R_AARCH64_TLSDESC_LD64_LO12:
330
1
    write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk
331
1
    return;
332
0
  default:
333
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
334
0
  }
335
0
}
336
337
4
void AArch64::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
338
4
  // TLSDESC Global-Dynamic relocation are in the form:
339
4
  //   adrp    x0, :tlsdesc:v             [R_AARCH64_TLSDESC_ADR_PAGE21]
340
4
  //   ldr     x1, [x0, #:tlsdesc_lo12:v  [R_AARCH64_TLSDESC_LD64_LO12]
341
4
  //   add     x0, x0, :tlsdesc_los:v     [R_AARCH64_TLSDESC_ADD_LO12]
342
4
  //   .tlsdesccall                       [R_AARCH64_TLSDESC_CALL]
343
4
  //   blr     x1
344
4
  // And it can optimized to:
345
4
  //   adrp    x0, :gottprel:v
346
4
  //   ldr     x0, [x0, :gottprel_lo12:v]
347
4
  //   nop
348
4
  //   nop
349
4
350
4
  switch (Type) {
351
2
  case R_AARCH64_TLSDESC_ADD_LO12:
352
2
  case R_AARCH64_TLSDESC_CALL:
353
2
    write32le(Loc, 0xd503201f); // nop
354
2
    break;
355
1
  case R_AARCH64_TLSDESC_ADR_PAGE21:
356
1
    write32le(Loc, 0x90000000); // adrp
357
1
    relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val);
358
1
    break;
359
1
  case R_AARCH64_TLSDESC_LD64_LO12:
360
1
    write32le(Loc, 0xf9400000); // ldr
361
1
    relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val);
362
1
    break;
363
0
  default:
364
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
365
4
  }
366
4
}
367
368
7
void AArch64::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
369
7
  checkUInt<32>(Loc, Val, Type);
370
7
371
7
  if (
Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE217
) {
372
4
    // Generate MOVZ.
373
4
    uint32_t RegNo = read32le(Loc) & 0x1f;
374
4
    write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
375
4
    return;
376
4
  }
377
3
  
if (3
Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC3
) {
378
3
    // Generate MOVK.
379
3
    uint32_t RegNo = read32le(Loc) & 0x1f;
380
3
    write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
381
3
    return;
382
3
  }
383
0
  
llvm_unreachable0
("invalid relocation for TLS IE to LE relaxation");
384
0
}
385
386
72
TargetInfo *elf::getAArch64TargetInfo() {
387
72
  static AArch64 Target;
388
72
  return &Target;
389
72
}