Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/tools/lld/ELF/Arch/AArch64.cpp
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//===- AArch64.cpp --------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#include "Error.h"
11
#include "Symbols.h"
12
#include "SyntheticSections.h"
13
#include "Target.h"
14
#include "Thunks.h"
15
#include "llvm/Object/ELF.h"
16
#include "llvm/Support/Endian.h"
17
18
using namespace llvm;
19
using namespace llvm::support::endian;
20
using namespace llvm::ELF;
21
using namespace lld;
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using namespace lld::elf;
23
24
// Page(Expr) is the page address of the expression Expr, defined
25
// as (Expr & ~0xFFF). (This applies even if the machine page size
26
// supported by the platform has a different value.)
27
86
uint64_t elf::getAArch64Page(uint64_t Expr) {
28
86
  return Expr & ~static_cast<uint64_t>(0xFFF);
29
86
}
30
31
namespace {
32
class AArch64 final : public TargetInfo {
33
public:
34
  AArch64();
35
  RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, const InputFile &File,
36
                     const uint8_t *Loc) const override;
37
  bool isPicRel(uint32_t Type) const override;
38
  void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
39
  void writePltHeader(uint8_t *Buf) const override;
40
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
41
                int32_t Index, unsigned RelOff) const override;
42
  bool usesOnlyLowPageBits(uint32_t Type) const override;
43
  void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
44
  RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
45
                          RelExpr Expr) const override;
46
  void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
47
  void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
48
  void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
49
};
50
} // namespace
51
52
75
AArch64::AArch64() {
53
75
  CopyRel = R_AARCH64_COPY;
54
75
  RelativeRel = R_AARCH64_RELATIVE;
55
75
  IRelativeRel = R_AARCH64_IRELATIVE;
56
75
  GotRel = R_AARCH64_GLOB_DAT;
57
75
  PltRel = R_AARCH64_JUMP_SLOT;
58
75
  TlsDescRel = R_AARCH64_TLSDESC;
59
75
  TlsGotRel = R_AARCH64_TLS_TPREL64;
60
75
  GotEntrySize = 8;
61
75
  GotPltEntrySize = 8;
62
75
  PltEntrySize = 16;
63
75
  PltHeaderSize = 32;
64
75
  DefaultMaxPageSize = 65536;
65
75
66
75
  // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant
67
75
  // 1 of the tls structures and the tcb size is 16.
68
75
  TcbSize = 16;
69
75
}
70
71
RelExpr AArch64::getRelExpr(uint32_t Type, const SymbolBody &S,
72
182
                            const InputFile &File, const uint8_t *Loc) const {
73
182
  switch (Type) {
74
52
  default:
75
52
    return R_ABS;
76
6
  case R_AARCH64_TLSDESC_ADR_PAGE21:
77
6
    return R_TLSDESC_PAGE;
78
12
  case R_AARCH64_TLSDESC_LD64_LO12:
79
12
  case R_AARCH64_TLSDESC_ADD_LO12:
80
12
    return R_TLSDESC;
81
6
  case R_AARCH64_TLSDESC_CALL:
82
6
    return R_TLSDESC_CALL;
83
4
  case R_AARCH64_TLSLE_ADD_TPREL_HI12:
84
4
  case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
85
4
    return R_TLS;
86
42
  case R_AARCH64_CALL26:
87
42
  case R_AARCH64_CONDBR19:
88
42
  case R_AARCH64_JUMP26:
89
42
  case R_AARCH64_TSTBR14:
90
42
    return R_PLT_PC;
91
31
  case R_AARCH64_PREL16:
92
31
  case R_AARCH64_PREL32:
93
31
  case R_AARCH64_PREL64:
94
31
  case R_AARCH64_ADR_PREL_LO21:
95
31
  case R_AARCH64_LD_PREL_LO19:
96
31
    return R_PC;
97
7
  case R_AARCH64_ADR_PREL_PG_HI21:
98
7
    return R_PAGE_PC;
99
10
  case R_AARCH64_LD64_GOT_LO12_NC:
100
10
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
101
10
    return R_GOT;
102
11
  case R_AARCH64_ADR_GOT_PAGE:
103
11
  case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
104
11
    return R_GOT_PAGE_PC;
105
1
  case R_AARCH64_NONE:
106
1
    return R_NONE;
107
0
  }
108
0
}
109
110
RelExpr AArch64::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
111
8
                                 RelExpr Expr) const {
112
8
  if (
Expr == R_RELAX_TLS_GD_TO_IE8
) {
113
4
    if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
114
1
      return R_RELAX_TLS_GD_TO_IE_PAGE_PC;
115
3
    return R_RELAX_TLS_GD_TO_IE_ABS;
116
3
  }
117
4
  return Expr;
118
4
}
119
120
42
bool AArch64::usesOnlyLowPageBits(uint32_t Type) const {
121
42
  switch (Type) {
122
1
  default:
123
1
    return false;
124
41
  case R_AARCH64_ADD_ABS_LO12_NC:
125
41
  case R_AARCH64_LD64_GOT_LO12_NC:
126
41
  case R_AARCH64_LDST128_ABS_LO12_NC:
127
41
  case R_AARCH64_LDST16_ABS_LO12_NC:
128
41
  case R_AARCH64_LDST32_ABS_LO12_NC:
129
41
  case R_AARCH64_LDST64_ABS_LO12_NC:
130
41
  case R_AARCH64_LDST8_ABS_LO12_NC:
131
41
  case R_AARCH64_TLSDESC_ADD_LO12:
132
41
  case R_AARCH64_TLSDESC_LD64_LO12:
133
41
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
134
41
    return true;
135
0
  }
136
0
}
137
138
5
bool AArch64::isPicRel(uint32_t Type) const {
139
5
  return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64;
140
5
}
141
142
20
void AArch64::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
143
20
  write64le(Buf, InX::Plt->getVA());
144
20
}
145
146
6
void AArch64::writePltHeader(uint8_t *Buf) const {
147
6
  const uint8_t PltData[] = {
148
6
      0xf0, 0x7b, 0xbf, 0xa9, // stp    x16, x30, [sp,#-16]!
149
6
      0x10, 0x00, 0x00, 0x90, // adrp   x16, Page(&(.plt.got[2]))
150
6
      0x11, 0x02, 0x40, 0xf9, // ldr    x17, [x16, Offset(&(.plt.got[2]))]
151
6
      0x10, 0x02, 0x00, 0x91, // add    x16, x16, Offset(&(.plt.got[2]))
152
6
      0x20, 0x02, 0x1f, 0xd6, // br     x17
153
6
      0x1f, 0x20, 0x03, 0xd5, // nop
154
6
      0x1f, 0x20, 0x03, 0xd5, // nop
155
6
      0x1f, 0x20, 0x03, 0xd5  // nop
156
6
  };
157
6
  memcpy(Buf, PltData, sizeof(PltData));
158
6
159
6
  uint64_t Got = InX::GotPlt->getVA();
160
6
  uint64_t Plt = InX::Plt->getVA();
161
6
  relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
162
6
              getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
163
6
  relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
164
6
  relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16);
165
6
}
166
167
void AArch64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
168
                       uint64_t PltEntryAddr, int32_t Index,
169
19
                       unsigned RelOff) const {
170
19
  const uint8_t Inst[] = {
171
19
      0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n]))
172
19
      0x11, 0x02, 0x40, 0xf9, // ldr  x17, [x16, Offset(&(.plt.got[n]))]
173
19
      0x10, 0x02, 0x00, 0x91, // add  x16, x16, Offset(&(.plt.got[n]))
174
19
      0x20, 0x02, 0x1f, 0xd6  // br   x17
175
19
  };
176
19
  memcpy(Buf, Inst, sizeof(Inst));
177
19
178
19
  relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21,
179
19
              getAArch64Page(GotPltEntryAddr) - getAArch64Page(PltEntryAddr));
180
19
  relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotPltEntryAddr);
181
19
  relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotPltEntryAddr);
182
19
}
183
184
48
static void write32AArch64Addr(uint8_t *L, uint64_t Imm) {
185
48
  uint32_t ImmLo = (Imm & 0x3) << 29;
186
48
  uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
187
48
  uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
188
48
  write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
189
48
}
190
191
// Return the bits [Start, End] from Val shifted Start bits.
192
// For instance, getBits(0xF0, 4, 8) returns 0xF.
193
47
static uint64_t getBits(uint64_t Val, int Start, int End) {
194
47
  uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
195
47
  return (Val >> Start) & Mask;
196
47
}
197
198
148
static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
199
200
// Update the immediate field in a AARCH64 ldr, str, and add instruction.
201
85
static void or32AArch64Imm(uint8_t *L, uint64_t Imm) {
202
85
  or32le(L, (Imm & 0xFFF) << 10);
203
85
}
204
205
229
void AArch64::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
206
229
  switch (Type) {
207
13
  case R_AARCH64_ABS16:
208
13
  case R_AARCH64_PREL16:
209
13
    checkIntUInt<16>(Loc, Val, Type);
210
13
    write16le(Loc, Val);
211
13
    break;
212
16
  case R_AARCH64_ABS32:
213
16
  case R_AARCH64_PREL32:
214
16
    checkIntUInt<32>(Loc, Val, Type);
215
16
    write32le(Loc, Val);
216
16
    break;
217
5
  case R_AARCH64_ABS64:
218
5
  case R_AARCH64_GLOB_DAT:
219
5
  case R_AARCH64_PREL64:
220
5
    write64le(Loc, Val);
221
5
    break;
222
31
  case R_AARCH64_ADD_ABS_LO12_NC:
223
31
    or32AArch64Imm(Loc, Val);
224
31
    break;
225
44
  case R_AARCH64_ADR_GOT_PAGE:
226
44
  case R_AARCH64_ADR_PREL_PG_HI21:
227
44
  case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
228
44
  case R_AARCH64_TLSDESC_ADR_PAGE21:
229
44
    checkInt<33>(Loc, Val, Type);
230
44
    write32AArch64Addr(Loc, Val >> 12);
231
44
    break;
232
4
  case R_AARCH64_ADR_PREL_LO21:
233
4
    checkInt<21>(Loc, Val, Type);
234
4
    write32AArch64Addr(Loc, Val);
235
4
    break;
236
12
  case R_AARCH64_JUMP26:
237
12
    // Normally we would just write the bits of the immediate field, however
238
12
    // when patching instructions for the cpu errata fix -fix-cortex-a53-843419
239
12
    // we want to replace a non-branch instruction with a branch immediate
240
12
    // instruction. By writing all the bits of the instruction including the
241
12
    // opcode and the immediate (0 001 | 01 imm26) we can do this
242
12
    // transformation by placing a R_AARCH64_JUMP26 relocation at the offset of
243
12
    // the instruction we want to patch.
244
12
    write32le(Loc, 0x14000000);
245
12
    LLVM_FALLTHROUGH;
246
25
  case R_AARCH64_CALL26:
247
25
    checkInt<28>(Loc, Val, Type);
248
25
    or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
249
25
    break;
250
13
  case R_AARCH64_CONDBR19:
251
13
  case R_AARCH64_LD_PREL_LO19:
252
13
    checkAlignment<4>(Loc, Val, Type);
253
13
    checkInt<21>(Loc, Val, Type);
254
13
    or32le(Loc, (Val & 0x1FFFFC) << 3);
255
13
    break;
256
12
  case R_AARCH64_LD64_GOT_LO12_NC:
257
12
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
258
12
  case R_AARCH64_TLSDESC_LD64_LO12:
259
12
    checkAlignment<8>(Loc, Val, Type);
260
12
    or32le(Loc, (Val & 0xFF8) << 7);
261
12
    break;
262
3
  case R_AARCH64_LDST8_ABS_LO12_NC:
263
3
    or32AArch64Imm(Loc, getBits(Val, 0, 11));
264
3
    break;
265
6
  case R_AARCH64_LDST16_ABS_LO12_NC:
266
6
    checkAlignment<2>(Loc, Val, Type);
267
6
    or32AArch64Imm(Loc, getBits(Val, 1, 11));
268
6
    break;
269
4
  case R_AARCH64_LDST32_ABS_LO12_NC:
270
4
    checkAlignment<4>(Loc, Val, Type);
271
4
    or32AArch64Imm(Loc, getBits(Val, 2, 11));
272
4
    break;
273
30
  case R_AARCH64_LDST64_ABS_LO12_NC:
274
30
    checkAlignment<8>(Loc, Val, Type);
275
30
    or32AArch64Imm(Loc, getBits(Val, 3, 11));
276
30
    break;
277
4
  case R_AARCH64_LDST128_ABS_LO12_NC:
278
4
    checkAlignment<16>(Loc, Val, Type);
279
4
    or32AArch64Imm(Loc, getBits(Val, 4, 11));
280
4
    break;
281
1
  case R_AARCH64_MOVW_UABS_G0_NC:
282
1
    or32le(Loc, (Val & 0xFFFF) << 5);
283
1
    break;
284
1
  case R_AARCH64_MOVW_UABS_G1_NC:
285
1
    or32le(Loc, (Val & 0xFFFF0000) >> 11);
286
1
    break;
287
1
  case R_AARCH64_MOVW_UABS_G2_NC:
288
1
    or32le(Loc, (Val & 0xFFFF00000000) >> 27);
289
1
    break;
290
2
  case R_AARCH64_MOVW_UABS_G3:
291
2
    or32le(Loc, (Val & 0xFFFF000000000000) >> 43);
292
2
    break;
293
8
  case R_AARCH64_TSTBR14:
294
8
    checkInt<16>(Loc, Val, Type);
295
8
    or32le(Loc, (Val & 0xFFFC) << 3);
296
8
    break;
297
2
  case R_AARCH64_TLSLE_ADD_TPREL_HI12:
298
2
    checkInt<24>(Loc, Val, Type);
299
2
    or32AArch64Imm(Loc, Val >> 12);
300
2
    break;
301
6
  case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
302
6
  case R_AARCH64_TLSDESC_ADD_LO12:
303
6
    or32AArch64Imm(Loc, Val);
304
6
    break;
305
0
  default:
306
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
307
229
  }
308
229
}
309
310
4
void AArch64::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
311
4
  // TLSDESC Global-Dynamic relocation are in the form:
312
4
  //   adrp    x0, :tlsdesc:v             [R_AARCH64_TLSDESC_ADR_PAGE21]
313
4
  //   ldr     x1, [x0, #:tlsdesc_lo12:v  [R_AARCH64_TLSDESC_LD64_LO12]
314
4
  //   add     x0, x0, :tlsdesc_los:v     [R_AARCH64_TLSDESC_ADD_LO12]
315
4
  //   .tlsdesccall                       [R_AARCH64_TLSDESC_CALL]
316
4
  //   blr     x1
317
4
  // And it can optimized to:
318
4
  //   movz    x0, #0x0, lsl #16
319
4
  //   movk    x0, #0x10
320
4
  //   nop
321
4
  //   nop
322
4
  checkUInt<32>(Loc, Val, Type);
323
4
324
4
  switch (Type) {
325
2
  case R_AARCH64_TLSDESC_ADD_LO12:
326
2
  case R_AARCH64_TLSDESC_CALL:
327
2
    write32le(Loc, 0xd503201f); // nop
328
2
    return;
329
1
  case R_AARCH64_TLSDESC_ADR_PAGE21:
330
1
    write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
331
1
    return;
332
1
  case R_AARCH64_TLSDESC_LD64_LO12:
333
1
    write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk
334
1
    return;
335
0
  default:
336
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
337
0
  }
338
0
}
339
340
4
void AArch64::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
341
4
  // TLSDESC Global-Dynamic relocation are in the form:
342
4
  //   adrp    x0, :tlsdesc:v             [R_AARCH64_TLSDESC_ADR_PAGE21]
343
4
  //   ldr     x1, [x0, #:tlsdesc_lo12:v  [R_AARCH64_TLSDESC_LD64_LO12]
344
4
  //   add     x0, x0, :tlsdesc_los:v     [R_AARCH64_TLSDESC_ADD_LO12]
345
4
  //   .tlsdesccall                       [R_AARCH64_TLSDESC_CALL]
346
4
  //   blr     x1
347
4
  // And it can optimized to:
348
4
  //   adrp    x0, :gottprel:v
349
4
  //   ldr     x0, [x0, :gottprel_lo12:v]
350
4
  //   nop
351
4
  //   nop
352
4
353
4
  switch (Type) {
354
2
  case R_AARCH64_TLSDESC_ADD_LO12:
355
2
  case R_AARCH64_TLSDESC_CALL:
356
2
    write32le(Loc, 0xd503201f); // nop
357
2
    break;
358
1
  case R_AARCH64_TLSDESC_ADR_PAGE21:
359
1
    write32le(Loc, 0x90000000); // adrp
360
1
    relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val);
361
1
    break;
362
1
  case R_AARCH64_TLSDESC_LD64_LO12:
363
1
    write32le(Loc, 0xf9400000); // ldr
364
1
    relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val);
365
1
    break;
366
0
  default:
367
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
368
4
  }
369
4
}
370
371
7
void AArch64::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
372
7
  checkUInt<32>(Loc, Val, Type);
373
7
374
7
  if (
Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE217
) {
375
4
    // Generate MOVZ.
376
4
    uint32_t RegNo = read32le(Loc) & 0x1f;
377
4
    write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
378
4
    return;
379
4
  }
380
3
  
if (3
Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC3
) {
381
3
    // Generate MOVK.
382
3
    uint32_t RegNo = read32le(Loc) & 0x1f;
383
3
    write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
384
3
    return;
385
3
  }
386
0
  
llvm_unreachable0
("invalid relocation for TLS IE to LE relaxation");
387
0
}
388
389
75
TargetInfo *elf::getAArch64TargetInfo() {
390
75
  static AArch64 Target;
391
75
  return &Target;
392
75
}