Coverage Report

Created: 2017-09-19 22:28

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/tools/lld/ELF/Arch/Mips.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- MIPS.cpp -----------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#include "Error.h"
11
#include "InputFiles.h"
12
#include "OutputSections.h"
13
#include "Symbols.h"
14
#include "SyntheticSections.h"
15
#include "Target.h"
16
#include "Thunks.h"
17
#include "llvm/Object/ELF.h"
18
#include "llvm/Support/Endian.h"
19
20
using namespace llvm;
21
using namespace llvm::object;
22
using namespace llvm::support::endian;
23
using namespace llvm::ELF;
24
using namespace lld;
25
using namespace lld::elf;
26
27
namespace {
28
template <class ELFT> class MIPS final : public TargetInfo {
29
public:
30
  MIPS();
31
  RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, const InputFile &File,
32
                     const uint8_t *Loc) const override;
33
  int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
34
  bool isPicRel(uint32_t Type) const override;
35
  uint32_t getDynRel(uint32_t Type) const override;
36
  void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
37
  void writePltHeader(uint8_t *Buf) const override;
38
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
39
                int32_t Index, unsigned RelOff) const override;
40
  bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File,
41
                  const SymbolBody &S) const override;
42
  void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
43
  bool usesOnlyLowPageBits(uint32_t Type) const override;
44
};
45
} // namespace
46
47
138
template <class ELFT> MIPS<ELFT>::MIPS() {
48
138
  GotPltHeaderEntriesNum = 2;
49
138
  DefaultMaxPageSize = 65536;
50
138
  GotEntrySize = sizeof(typename ELFT::uint);
51
138
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
138
  PltEntrySize = 16;
53
138
  PltHeaderSize = 32;
54
138
  CopyRel = R_MIPS_COPY;
55
138
  PltRel = R_MIPS_JUMP_SLOT;
56
138
  NeedsThunks = true;
57
138
  TrapInstr = 0xefefefef;
58
138
59
138
  if (
ELFT::Is64Bits138
) {
60
30
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
61
30
    TlsGotRel = R_MIPS_TLS_TPREL64;
62
30
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
63
30
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
64
138
  } else {
65
108
    RelativeRel = R_MIPS_REL32;
66
108
    TlsGotRel = R_MIPS_TLS_TPREL32;
67
108
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
68
108
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
69
108
  }
70
138
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::MIPS()
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Source
47
28
template <class ELFT> MIPS<ELFT>::MIPS() {
48
28
  GotPltHeaderEntriesNum = 2;
49
28
  DefaultMaxPageSize = 65536;
50
28
  GotEntrySize = sizeof(typename ELFT::uint);
51
28
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
28
  PltEntrySize = 16;
53
28
  PltHeaderSize = 32;
54
28
  CopyRel = R_MIPS_COPY;
55
28
  PltRel = R_MIPS_JUMP_SLOT;
56
28
  NeedsThunks = true;
57
28
  TrapInstr = 0xefefefef;
58
28
59
28
  if (
ELFT::Is64Bits28
) {
60
28
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
61
28
    TlsGotRel = R_MIPS_TLS_TPREL64;
62
28
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
63
28
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
64
28
  } else {
65
0
    RelativeRel = R_MIPS_REL32;
66
0
    TlsGotRel = R_MIPS_TLS_TPREL32;
67
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
68
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
69
0
  }
70
28
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::MIPS()
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Source
47
94
template <class ELFT> MIPS<ELFT>::MIPS() {
48
94
  GotPltHeaderEntriesNum = 2;
49
94
  DefaultMaxPageSize = 65536;
50
94
  GotEntrySize = sizeof(typename ELFT::uint);
51
94
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
94
  PltEntrySize = 16;
53
94
  PltHeaderSize = 32;
54
94
  CopyRel = R_MIPS_COPY;
55
94
  PltRel = R_MIPS_JUMP_SLOT;
56
94
  NeedsThunks = true;
57
94
  TrapInstr = 0xefefefef;
58
94
59
94
  if (
ELFT::Is64Bits94
) {
60
0
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
61
0
    TlsGotRel = R_MIPS_TLS_TPREL64;
62
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
63
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
64
94
  } else {
65
94
    RelativeRel = R_MIPS_REL32;
66
94
    TlsGotRel = R_MIPS_TLS_TPREL32;
67
94
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
68
94
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
69
94
  }
70
94
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::MIPS()
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Count
Source
47
2
template <class ELFT> MIPS<ELFT>::MIPS() {
48
2
  GotPltHeaderEntriesNum = 2;
49
2
  DefaultMaxPageSize = 65536;
50
2
  GotEntrySize = sizeof(typename ELFT::uint);
51
2
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
2
  PltEntrySize = 16;
53
2
  PltHeaderSize = 32;
54
2
  CopyRel = R_MIPS_COPY;
55
2
  PltRel = R_MIPS_JUMP_SLOT;
56
2
  NeedsThunks = true;
57
2
  TrapInstr = 0xefefefef;
58
2
59
2
  if (
ELFT::Is64Bits2
) {
60
2
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
61
2
    TlsGotRel = R_MIPS_TLS_TPREL64;
62
2
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
63
2
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
64
2
  } else {
65
0
    RelativeRel = R_MIPS_REL32;
66
0
    TlsGotRel = R_MIPS_TLS_TPREL32;
67
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
68
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
69
0
  }
70
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::MIPS()
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Count
Source
47
14
template <class ELFT> MIPS<ELFT>::MIPS() {
48
14
  GotPltHeaderEntriesNum = 2;
49
14
  DefaultMaxPageSize = 65536;
50
14
  GotEntrySize = sizeof(typename ELFT::uint);
51
14
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
14
  PltEntrySize = 16;
53
14
  PltHeaderSize = 32;
54
14
  CopyRel = R_MIPS_COPY;
55
14
  PltRel = R_MIPS_JUMP_SLOT;
56
14
  NeedsThunks = true;
57
14
  TrapInstr = 0xefefefef;
58
14
59
14
  if (
ELFT::Is64Bits14
) {
60
0
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
61
0
    TlsGotRel = R_MIPS_TLS_TPREL64;
62
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
63
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
64
14
  } else {
65
14
    RelativeRel = R_MIPS_REL32;
66
14
    TlsGotRel = R_MIPS_TLS_TPREL32;
67
14
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
68
14
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
69
14
  }
70
14
}
71
72
template <class ELFT>
73
RelExpr MIPS<ELFT>::getRelExpr(uint32_t Type, const SymbolBody &S,
74
                               const InputFile &File,
75
291
                               const uint8_t *Loc) const {
76
291
  // See comment in the calculateMipsRelChain.
77
291
  if (
ELFT::Is64Bits || 291
Config->MipsN32Abi240
)
78
54
    Type &= 0xff;
79
291
  switch (Type) {
80
35
  default:
81
35
    return R_ABS;
82
1
  case R_MIPS_JALR:
83
1
  case R_MICROMIPS_JALR:
84
1
    return R_HINT;
85
18
  case R_MIPS_GPREL16:
86
18
  case R_MIPS_GPREL32:
87
18
  case R_MICROMIPS_GPREL16:
88
18
  case R_MICROMIPS_GPREL7_S2:
89
18
    return R_MIPS_GOTREL;
90
48
  case R_MIPS_26:
91
48
    return R_PLT;
92
4
  case R_MICROMIPS_26_S1:
93
4
    return R_PLT;
94
0
  case R_MICROMIPS_PC26_S1:
95
0
    return R_PLT_PC;
96
62
  case R_MIPS_HI16:
97
62
  case R_MIPS_LO16:
98
62
  case R_MICROMIPS_HI16:
99
62
  case R_MICROMIPS_LO16:
100
62
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
101
62
    // offset between start of function and 'gp' value which by default
102
62
    // equal to the start of .got section. In that case we consider these
103
62
    // relocations as relative.
104
62
    if (&S == ElfSym::MipsGpDisp)
105
18
      return R_MIPS_GOT_GP_PC;
106
44
    
if (44
&S == ElfSym::MipsLocalGp44
)
107
2
      return R_MIPS_GOT_GP;
108
42
    
LLVM_FALLTHROUGH42
;
109
45
  case R_MIPS_GOT_OFST:
110
45
  case R_MICROMIPS_GOT_OFST:
111
45
    return R_ABS;
112
15
  case R_MIPS_PC32:
113
15
  case R_MIPS_PC16:
114
15
  case R_MIPS_PC19_S2:
115
15
  case R_MIPS_PC21_S2:
116
15
  case R_MIPS_PC26_S2:
117
15
  case R_MIPS_PCHI16:
118
15
  case R_MIPS_PCLO16:
119
15
  case R_MICROMIPS_PC7_S1:
120
15
  case R_MICROMIPS_PC10_S1:
121
15
  case R_MICROMIPS_PC16_S1:
122
15
  case R_MICROMIPS_PC18_S3:
123
15
  case R_MICROMIPS_PC19_S2:
124
15
  case R_MICROMIPS_PC23_S2:
125
15
  case R_MICROMIPS_PC21_S1:
126
15
    return R_PC;
127
38
  case R_MIPS_GOT16:
128
38
  case R_MICROMIPS_GOT16:
129
38
    if (S.isLocal())
130
13
      return R_MIPS_GOT_LOCAL_PAGE;
131
25
    
LLVM_FALLTHROUGH25
;
132
57
  case R_MIPS_CALL16:
133
57
  case R_MIPS_GOT_DISP:
134
57
  case R_MIPS_TLS_GOTTPREL:
135
57
  case R_MICROMIPS_CALL16:
136
57
  case R_MICROMIPS_GOT_DISP:
137
57
  case R_MICROMIPS_TLS_GOTTPREL:
138
57
    return R_MIPS_GOT_OFF;
139
16
  case R_MIPS_CALL_HI16:
140
16
  case R_MIPS_CALL_LO16:
141
16
  case R_MIPS_GOT_HI16:
142
16
  case R_MIPS_GOT_LO16:
143
16
  case R_MICROMIPS_CALL_HI16:
144
16
  case R_MICROMIPS_CALL_LO16:
145
16
  case R_MICROMIPS_GOT_HI16:
146
16
  case R_MICROMIPS_GOT_LO16:
147
16
    return R_MIPS_GOT_OFF32;
148
5
  case R_MIPS_GOT_PAGE:
149
5
  case R_MICROMIPS_GOT_PAGE:
150
5
    return R_MIPS_GOT_LOCAL_PAGE;
151
9
  case R_MIPS_TLS_GD:
152
9
  case R_MICROMIPS_TLS_GD:
153
9
    return R_MIPS_TLSGD;
154
5
  case R_MIPS_TLS_LDM:
155
5
  case R_MICROMIPS_TLS_LDM:
156
5
    return R_MIPS_TLSLD;
157
0
  }
158
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getRelExpr(unsigned int, lld::elf::SymbolBody const&, lld::elf::InputFile const&, unsigned char const*) const
Line
Count
Source
75
51
                               const uint8_t *Loc) const {
76
51
  // See comment in the calculateMipsRelChain.
77
51
  if (
ELFT::Is64Bits || 51
Config->MipsN32Abi0
)
78
51
    Type &= 0xff;
79
51
  switch (Type) {
80
12
  default:
81
12
    return R_ABS;
82
0
  case R_MIPS_JALR:
83
0
  case R_MICROMIPS_JALR:
84
0
    return R_HINT;
85
10
  case R_MIPS_GPREL16:
86
10
  case R_MIPS_GPREL32:
87
10
  case R_MICROMIPS_GPREL16:
88
10
  case R_MICROMIPS_GPREL7_S2:
89
10
    return R_MIPS_GOTREL;
90
0
  case R_MIPS_26:
91
0
    return R_PLT;
92
0
  case R_MICROMIPS_26_S1:
93
0
    return R_PLT;
94
0
  case R_MICROMIPS_PC26_S1:
95
0
    return R_PLT_PC;
96
0
  case R_MIPS_HI16:
97
0
  case R_MIPS_LO16:
98
0
  case R_MICROMIPS_HI16:
99
0
  case R_MICROMIPS_LO16:
100
0
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
101
0
    // offset between start of function and 'gp' value which by default
102
0
    // equal to the start of .got section. In that case we consider these
103
0
    // relocations as relative.
104
0
    if (&S == ElfSym::MipsGpDisp)
105
0
      return R_MIPS_GOT_GP_PC;
106
0
    
if (0
&S == ElfSym::MipsLocalGp0
)
107
0
      return R_MIPS_GOT_GP;
108
0
    
LLVM_FALLTHROUGH0
;
109
3
  case R_MIPS_GOT_OFST:
110
3
  case R_MICROMIPS_GOT_OFST:
111
3
    return R_ABS;
112
1
  case R_MIPS_PC32:
113
1
  case R_MIPS_PC16:
114
1
  case R_MIPS_PC19_S2:
115
1
  case R_MIPS_PC21_S2:
116
1
  case R_MIPS_PC26_S2:
117
1
  case R_MIPS_PCHI16:
118
1
  case R_MIPS_PCLO16:
119
1
  case R_MICROMIPS_PC7_S1:
120
1
  case R_MICROMIPS_PC10_S1:
121
1
  case R_MICROMIPS_PC16_S1:
122
1
  case R_MICROMIPS_PC18_S3:
123
1
  case R_MICROMIPS_PC19_S2:
124
1
  case R_MICROMIPS_PC23_S2:
125
1
  case R_MICROMIPS_PC21_S1:
126
1
    return R_PC;
127
0
  case R_MIPS_GOT16:
128
0
  case R_MICROMIPS_GOT16:
129
0
    if (S.isLocal())
130
0
      return R_MIPS_GOT_LOCAL_PAGE;
131
0
    
LLVM_FALLTHROUGH0
;
132
14
  case R_MIPS_CALL16:
133
14
  case R_MIPS_GOT_DISP:
134
14
  case R_MIPS_TLS_GOTTPREL:
135
14
  case R_MICROMIPS_CALL16:
136
14
  case R_MICROMIPS_GOT_DISP:
137
14
  case R_MICROMIPS_TLS_GOTTPREL:
138
14
    return R_MIPS_GOT_OFF;
139
0
  case R_MIPS_CALL_HI16:
140
0
  case R_MIPS_CALL_LO16:
141
0
  case R_MIPS_GOT_HI16:
142
0
  case R_MIPS_GOT_LO16:
143
0
  case R_MICROMIPS_CALL_HI16:
144
0
  case R_MICROMIPS_CALL_LO16:
145
0
  case R_MICROMIPS_GOT_HI16:
146
0
  case R_MICROMIPS_GOT_LO16:
147
0
    return R_MIPS_GOT_OFF32;
148
5
  case R_MIPS_GOT_PAGE:
149
5
  case R_MICROMIPS_GOT_PAGE:
150
5
    return R_MIPS_GOT_LOCAL_PAGE;
151
4
  case R_MIPS_TLS_GD:
152
4
  case R_MICROMIPS_TLS_GD:
153
4
    return R_MIPS_TLSGD;
154
2
  case R_MIPS_TLS_LDM:
155
2
  case R_MICROMIPS_TLS_LDM:
156
2
    return R_MIPS_TLSLD;
157
0
  }
158
0
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getRelExpr(unsigned int, lld::elf::SymbolBody const&, lld::elf::InputFile const&, unsigned char const*) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getRelExpr(unsigned int, lld::elf::SymbolBody const&, lld::elf::InputFile const&, unsigned char const*) const
Line
Count
Source
75
224
                               const uint8_t *Loc) const {
76
224
  // See comment in the calculateMipsRelChain.
77
224
  if (
ELFT::Is64Bits || 224
Config->MipsN32Abi224
)
78
3
    Type &= 0xff;
79
224
  switch (Type) {
80
21
  default:
81
21
    return R_ABS;
82
0
  case R_MIPS_JALR:
83
0
  case R_MICROMIPS_JALR:
84
0
    return R_HINT;
85
8
  case R_MIPS_GPREL16:
86
8
  case R_MIPS_GPREL32:
87
8
  case R_MICROMIPS_GPREL16:
88
8
  case R_MICROMIPS_GPREL7_S2:
89
8
    return R_MIPS_GOTREL;
90
48
  case R_MIPS_26:
91
48
    return R_PLT;
92
2
  case R_MICROMIPS_26_S1:
93
2
    return R_PLT;
94
0
  case R_MICROMIPS_PC26_S1:
95
0
    return R_PLT_PC;
96
60
  case R_MIPS_HI16:
97
60
  case R_MIPS_LO16:
98
60
  case R_MICROMIPS_HI16:
99
60
  case R_MICROMIPS_LO16:
100
60
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
101
60
    // offset between start of function and 'gp' value which by default
102
60
    // equal to the start of .got section. In that case we consider these
103
60
    // relocations as relative.
104
60
    if (&S == ElfSym::MipsGpDisp)
105
16
      return R_MIPS_GOT_GP_PC;
106
44
    
if (44
&S == ElfSym::MipsLocalGp44
)
107
2
      return R_MIPS_GOT_GP;
108
42
    
LLVM_FALLTHROUGH42
;
109
42
  case R_MIPS_GOT_OFST:
110
42
  case R_MICROMIPS_GOT_OFST:
111
42
    return R_ABS;
112
11
  case R_MIPS_PC32:
113
11
  case R_MIPS_PC16:
114
11
  case R_MIPS_PC19_S2:
115
11
  case R_MIPS_PC21_S2:
116
11
  case R_MIPS_PC26_S2:
117
11
  case R_MIPS_PCHI16:
118
11
  case R_MIPS_PCLO16:
119
11
  case R_MICROMIPS_PC7_S1:
120
11
  case R_MICROMIPS_PC10_S1:
121
11
  case R_MICROMIPS_PC16_S1:
122
11
  case R_MICROMIPS_PC18_S3:
123
11
  case R_MICROMIPS_PC19_S2:
124
11
  case R_MICROMIPS_PC23_S2:
125
11
  case R_MICROMIPS_PC21_S1:
126
11
    return R_PC;
127
33
  case R_MIPS_GOT16:
128
33
  case R_MICROMIPS_GOT16:
129
33
    if (S.isLocal())
130
13
      return R_MIPS_GOT_LOCAL_PAGE;
131
20
    
LLVM_FALLTHROUGH20
;
132
37
  case R_MIPS_CALL16:
133
37
  case R_MIPS_GOT_DISP:
134
37
  case R_MIPS_TLS_GOTTPREL:
135
37
  case R_MICROMIPS_CALL16:
136
37
  case R_MICROMIPS_GOT_DISP:
137
37
  case R_MICROMIPS_TLS_GOTTPREL:
138
37
    return R_MIPS_GOT_OFF;
139
16
  case R_MIPS_CALL_HI16:
140
16
  case R_MIPS_CALL_LO16:
141
16
  case R_MIPS_GOT_HI16:
142
16
  case R_MIPS_GOT_LO16:
143
16
  case R_MICROMIPS_CALL_HI16:
144
16
  case R_MICROMIPS_CALL_LO16:
145
16
  case R_MICROMIPS_GOT_HI16:
146
16
  case R_MICROMIPS_GOT_LO16:
147
16
    return R_MIPS_GOT_OFF32;
148
0
  case R_MIPS_GOT_PAGE:
149
0
  case R_MICROMIPS_GOT_PAGE:
150
0
    return R_MIPS_GOT_LOCAL_PAGE;
151
5
  case R_MIPS_TLS_GD:
152
5
  case R_MICROMIPS_TLS_GD:
153
5
    return R_MIPS_TLSGD;
154
3
  case R_MIPS_TLS_LDM:
155
3
  case R_MICROMIPS_TLS_LDM:
156
3
    return R_MIPS_TLSLD;
157
0
  }
158
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getRelExpr(unsigned int, lld::elf::SymbolBody const&, lld::elf::InputFile const&, unsigned char const*) const
Line
Count
Source
75
16
                               const uint8_t *Loc) const {
76
16
  // See comment in the calculateMipsRelChain.
77
16
  if (
ELFT::Is64Bits || 16
Config->MipsN32Abi16
)
78
0
    Type &= 0xff;
79
16
  switch (Type) {
80
2
  default:
81
2
    return R_ABS;
82
1
  case R_MIPS_JALR:
83
1
  case R_MICROMIPS_JALR:
84
1
    return R_HINT;
85
0
  case R_MIPS_GPREL16:
86
0
  case R_MIPS_GPREL32:
87
0
  case R_MICROMIPS_GPREL16:
88
0
  case R_MICROMIPS_GPREL7_S2:
89
0
    return R_MIPS_GOTREL;
90
0
  case R_MIPS_26:
91
0
    return R_PLT;
92
2
  case R_MICROMIPS_26_S1:
93
2
    return R_PLT;
94
0
  case R_MICROMIPS_PC26_S1:
95
0
    return R_PLT_PC;
96
2
  case R_MIPS_HI16:
97
2
  case R_MIPS_LO16:
98
2
  case R_MICROMIPS_HI16:
99
2
  case R_MICROMIPS_LO16:
100
2
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
101
2
    // offset between start of function and 'gp' value which by default
102
2
    // equal to the start of .got section. In that case we consider these
103
2
    // relocations as relative.
104
2
    if (&S == ElfSym::MipsGpDisp)
105
2
      return R_MIPS_GOT_GP_PC;
106
0
    
if (0
&S == ElfSym::MipsLocalGp0
)
107
0
      return R_MIPS_GOT_GP;
108
0
    
LLVM_FALLTHROUGH0
;
109
0
  case R_MIPS_GOT_OFST:
110
0
  case R_MICROMIPS_GOT_OFST:
111
0
    return R_ABS;
112
3
  case R_MIPS_PC32:
113
3
  case R_MIPS_PC16:
114
3
  case R_MIPS_PC19_S2:
115
3
  case R_MIPS_PC21_S2:
116
3
  case R_MIPS_PC26_S2:
117
3
  case R_MIPS_PCHI16:
118
3
  case R_MIPS_PCLO16:
119
3
  case R_MICROMIPS_PC7_S1:
120
3
  case R_MICROMIPS_PC10_S1:
121
3
  case R_MICROMIPS_PC16_S1:
122
3
  case R_MICROMIPS_PC18_S3:
123
3
  case R_MICROMIPS_PC19_S2:
124
3
  case R_MICROMIPS_PC23_S2:
125
3
  case R_MICROMIPS_PC21_S1:
126
3
    return R_PC;
127
5
  case R_MIPS_GOT16:
128
5
  case R_MICROMIPS_GOT16:
129
5
    if (S.isLocal())
130
0
      return R_MIPS_GOT_LOCAL_PAGE;
131
5
    
LLVM_FALLTHROUGH5
;
132
6
  case R_MIPS_CALL16:
133
6
  case R_MIPS_GOT_DISP:
134
6
  case R_MIPS_TLS_GOTTPREL:
135
6
  case R_MICROMIPS_CALL16:
136
6
  case R_MICROMIPS_GOT_DISP:
137
6
  case R_MICROMIPS_TLS_GOTTPREL:
138
6
    return R_MIPS_GOT_OFF;
139
0
  case R_MIPS_CALL_HI16:
140
0
  case R_MIPS_CALL_LO16:
141
0
  case R_MIPS_GOT_HI16:
142
0
  case R_MIPS_GOT_LO16:
143
0
  case R_MICROMIPS_CALL_HI16:
144
0
  case R_MICROMIPS_CALL_LO16:
145
0
  case R_MICROMIPS_GOT_HI16:
146
0
  case R_MICROMIPS_GOT_LO16:
147
0
    return R_MIPS_GOT_OFF32;
148
0
  case R_MIPS_GOT_PAGE:
149
0
  case R_MICROMIPS_GOT_PAGE:
150
0
    return R_MIPS_GOT_LOCAL_PAGE;
151
0
  case R_MIPS_TLS_GD:
152
0
  case R_MICROMIPS_TLS_GD:
153
0
    return R_MIPS_TLSGD;
154
0
  case R_MIPS_TLS_LDM:
155
0
  case R_MICROMIPS_TLS_LDM:
156
0
    return R_MIPS_TLSLD;
157
0
  }
158
0
}
159
160
3
template <class ELFT> bool MIPS<ELFT>::isPicRel(uint32_t Type) const {
161
1
  return Type == R_MIPS_32 || Type == R_MIPS_64;
162
3
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::isPicRel(unsigned int) const
Line
Count
Source
160
1
template <class ELFT> bool MIPS<ELFT>::isPicRel(uint32_t Type) const {
161
1
  return Type == R_MIPS_32 || Type == R_MIPS_64;
162
1
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::isPicRel(unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::isPicRel(unsigned int) const
Line
Count
Source
160
1
template <class ELFT> bool MIPS<ELFT>::isPicRel(uint32_t Type) const {
161
0
  return Type == R_MIPS_32 || Type == R_MIPS_64;
162
1
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::isPicRel(unsigned int) const
Line
Count
Source
160
1
template <class ELFT> bool MIPS<ELFT>::isPicRel(uint32_t Type) const {
161
0
  return Type == R_MIPS_32 || Type == R_MIPS_64;
162
1
}
163
164
3
template <class ELFT> uint32_t MIPS<ELFT>::getDynRel(uint32_t Type) const {
165
3
  return RelativeRel;
166
3
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getDynRel(unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getDynRel(unsigned int) const
Line
Count
Source
164
1
template <class ELFT> uint32_t MIPS<ELFT>::getDynRel(uint32_t Type) const {
165
1
  return RelativeRel;
166
1
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getDynRel(unsigned int) const
Line
Count
Source
164
1
template <class ELFT> uint32_t MIPS<ELFT>::getDynRel(uint32_t Type) const {
165
1
  return RelativeRel;
166
1
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getDynRel(unsigned int) const
Line
Count
Source
164
1
template <class ELFT> uint32_t MIPS<ELFT>::getDynRel(uint32_t Type) const {
165
1
  return RelativeRel;
166
1
}
167
168
template <class ELFT>
169
10
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
170
10
  write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA());
171
10
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writeGotPlt(unsigned char*, lld::elf::SymbolBody const&) const
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writeGotPlt(unsigned char*, lld::elf::SymbolBody const&) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writeGotPlt(unsigned char*, lld::elf::SymbolBody const&) const
Line
Count
Source
169
8
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
170
8
  write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA());
171
8
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writeGotPlt(unsigned char*, lld::elf::SymbolBody const&) const
Line
Count
Source
169
2
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
170
2
  write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA());
171
2
}
172
173
17
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
174
17
  // The major opcode of a microMIPS instruction needs to appear
175
17
  // in the first 16-bit word (lowest address) for efficient hardware
176
17
  // decode so that it knows if the instruction is 16-bit or 32-bit
177
17
  // as early as possible. To do so, little-endian binaries keep 16-bit
178
17
  // words in a big-endian order. That is why we have to swap these
179
17
  // words to get a correct value.
180
17
  uint32_t V = read32<E>(Loc);
181
17
  if (E == support::little)
182
7
    return (V << 16) | (V >> 16);
183
10
  return V;
184
10
}
Mips.cpp:unsigned int readShuffle<(llvm::support::endianness)0>(unsigned char const*)
Line
Count
Source
173
10
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
174
10
  // The major opcode of a microMIPS instruction needs to appear
175
10
  // in the first 16-bit word (lowest address) for efficient hardware
176
10
  // decode so that it knows if the instruction is 16-bit or 32-bit
177
10
  // as early as possible. To do so, little-endian binaries keep 16-bit
178
10
  // words in a big-endian order. That is why we have to swap these
179
10
  // words to get a correct value.
180
10
  uint32_t V = read32<E>(Loc);
181
10
  if (E == support::little)
182
0
    return (V << 16) | (V >> 16);
183
10
  return V;
184
10
}
Mips.cpp:unsigned int readShuffle<(llvm::support::endianness)1>(unsigned char const*)
Line
Count
Source
173
7
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
174
7
  // The major opcode of a microMIPS instruction needs to appear
175
7
  // in the first 16-bit word (lowest address) for efficient hardware
176
7
  // decode so that it knows if the instruction is 16-bit or 32-bit
177
7
  // as early as possible. To do so, little-endian binaries keep 16-bit
178
7
  // words in a big-endian order. That is why we have to swap these
179
7
  // words to get a correct value.
180
7
  uint32_t V = read32<E>(Loc);
181
7
  if (E == support::little)
182
7
    return (V << 16) | (V >> 16);
183
0
  return V;
184
0
}
185
186
template <endianness E>
187
static void writeRelocation(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
188
353
                            uint8_t Shift) {
189
353
  uint32_t Instr = read32<E>(Loc);
190
353
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
191
353
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
192
353
  write32<E>(Loc, Data);
193
353
}
Mips.cpp:void writeRelocation<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
188
15
                            uint8_t Shift) {
189
15
  uint32_t Instr = read32<E>(Loc);
190
15
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
191
15
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
192
15
  write32<E>(Loc, Data);
193
15
}
Mips.cpp:void writeRelocation<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
188
338
                            uint8_t Shift) {
189
338
  uint32_t Instr = read32<E>(Loc);
190
338
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
191
338
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
192
338
  write32<E>(Loc, Data);
193
338
}
194
195
template <endianness E>
196
static void writeMicroRelocation32(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
197
28
                                   uint8_t Shift) {
198
28
  // See comments in readShuffle for purpose of this code.
199
28
  uint16_t *Words = (uint16_t *)Loc;
200
28
  if (E == support::little)
201
11
    std::swap(Words[0], Words[1]);
202
28
203
28
  writeRelocation<E>(Loc, V, BitsSize, Shift);
204
28
205
28
  if (E == support::little)
206
11
    std::swap(Words[0], Words[1]);
207
28
}
Mips.cpp:void writeMicroRelocation32<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
197
17
                                   uint8_t Shift) {
198
17
  // See comments in readShuffle for purpose of this code.
199
17
  uint16_t *Words = (uint16_t *)Loc;
200
17
  if (E == support::little)
201
0
    std::swap(Words[0], Words[1]);
202
17
203
17
  writeRelocation<E>(Loc, V, BitsSize, Shift);
204
17
205
17
  if (E == support::little)
206
0
    std::swap(Words[0], Words[1]);
207
17
}
Mips.cpp:void writeMicroRelocation32<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
197
11
                                   uint8_t Shift) {
198
11
  // See comments in readShuffle for purpose of this code.
199
11
  uint16_t *Words = (uint16_t *)Loc;
200
11
  if (E == support::little)
201
11
    std::swap(Words[0], Words[1]);
202
11
203
11
  writeRelocation<E>(Loc, V, BitsSize, Shift);
204
11
205
11
  if (E == support::little)
206
11
    std::swap(Words[0], Words[1]);
207
11
}
208
209
template <endianness E>
210
static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
211
4
                                   uint8_t Shift) {
212
4
  uint16_t Instr = read16<E>(Loc);
213
4
  uint16_t Mask = 0xffff >> (16 - BitsSize);
214
4
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
215
4
  write16<E>(Loc, Data);
216
4
}
Mips.cpp:void writeMicroRelocation16<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
211
2
                                   uint8_t Shift) {
212
2
  uint16_t Instr = read16<E>(Loc);
213
2
  uint16_t Mask = 0xffff >> (16 - BitsSize);
214
2
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
215
2
  write16<E>(Loc, Data);
216
2
}
Mips.cpp:void writeMicroRelocation16<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
211
2
                                   uint8_t Shift) {
212
2
  uint16_t Instr = read16<E>(Loc);
213
2
  uint16_t Mask = 0xffff >> (16 - BitsSize);
214
2
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
215
2
  write16<E>(Loc, Data);
216
2
}
217
218
18
template <class ELFT> static bool isMicroMips() {
219
18
  // FIXME (simon): This code does not support the case when both
220
18
  // microMIPS and MIPS object files are linked together.
221
18
  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
222
18
  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH_ASE;
223
18
  return Arch == EF_MIPS_MICROMIPS;
224
18
}
Unexecuted instantiation: Mips.cpp:bool isMicroMips<llvm::object::ELFType<(llvm::support::endianness)1, true> >()
Unexecuted instantiation: Mips.cpp:bool isMicroMips<llvm::object::ELFType<(llvm::support::endianness)0, true> >()
Mips.cpp:bool isMicroMips<llvm::object::ELFType<(llvm::support::endianness)1, false> >()
Line
Count
Source
218
4
template <class ELFT> static bool isMicroMips() {
219
4
  // FIXME (simon): This code does not support the case when both
220
4
  // microMIPS and MIPS object files are linked together.
221
4
  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
222
4
  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH_ASE;
223
4
  return Arch == EF_MIPS_MICROMIPS;
224
4
}
Mips.cpp:bool isMicroMips<llvm::object::ELFType<(llvm::support::endianness)0, false> >()
Line
Count
Source
218
14
template <class ELFT> static bool isMicroMips() {
219
14
  // FIXME (simon): This code does not support the case when both
220
14
  // microMIPS and MIPS object files are linked together.
221
14
  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
222
14
  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH_ASE;
223
14
  return Arch == EF_MIPS_MICROMIPS;
224
14
}
225
226
18
template <class ELFT> static bool isMipsR6() {
227
18
  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
228
18
  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH;
229
11
  return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6;
230
18
}
Mips.cpp:bool isMipsR6<llvm::object::ELFType<(llvm::support::endianness)1, false> >()
Line
Count
Source
226
6
template <class ELFT> static bool isMipsR6() {
227
6
  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
228
6
  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH;
229
3
  return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6;
230
6
}
Mips.cpp:bool isMipsR6<llvm::object::ELFType<(llvm::support::endianness)0, false> >()
Line
Count
Source
226
12
template <class ELFT> static bool isMipsR6() {
227
12
  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
228
12
  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH;
229
8
  return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6;
230
12
}
Unexecuted instantiation: Mips.cpp:bool isMipsR6<llvm::object::ELFType<(llvm::support::endianness)1, true> >()
Unexecuted instantiation: Mips.cpp:bool isMipsR6<llvm::object::ELFType<(llvm::support::endianness)0, true> >()
231
232
8
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
233
8
  const endianness E = ELFT::TargetEndianness;
234
8
  if (
isMicroMips<ELFT>()8
) {
235
4
    uint64_t GotPlt = In<ELFT>::GotPlt->getVA();
236
4
    uint64_t Plt = In<ELFT>::Plt->getVA();
237
4
    // Overwrite trap instructions written by Writer::writeTrapInstr.
238
4
    memset(Buf, 0, PltHeaderSize);
239
4
240
4
    write16<E>(Buf, isMipsR6<ELFT>() ? 
0x78602
:
0x79802
);
241
4
                                    // addiupc v1, (GOTPLT) - .
242
4
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
243
4
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
244
4
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
245
4
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
246
4
    write16<E>(Buf + 14, 0xfffe);
247
4
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
248
4
    if (
isMipsR6<ELFT>()4
) {
249
2
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
250
2
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
251
2
      write16<E>(Buf + 22, 0x0c00); // nop
252
2
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
253
4
    } else {
254
2
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
255
2
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
256
2
      write16<E>(Buf + 22, 0x0c00); // nop
257
2
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
258
2
    }
259
4
    return;
260
4
  }
261
4
262
4
  
if (4
Config->MipsN32Abi4
) {
263
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
264
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
265
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
266
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
267
4
  } else {
268
4
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
269
4
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
270
4
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
271
4
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
272
4
  }
273
8
274
8
  write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
275
8
  write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
276
8
  write32<E>(Buf + 24, 0x0320f809); // jalr  $25
277
8
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
278
8
279
8
  uint64_t GotPlt = InX::GotPlt->getVA();
280
8
  writeRelocation<E>(Buf, GotPlt + 0x8000, 16, 16);
281
8
  writeRelocation<E>(Buf + 4, GotPlt, 16, 0);
282
8
  writeRelocation<E>(Buf + 8, GotPlt, 16, 0);
283
8
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writePltHeader(unsigned char*) const
Line
Count
Source
232
2
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
233
2
  const endianness E = ELFT::TargetEndianness;
234
2
  if (
isMicroMips<ELFT>()2
) {
235
2
    uint64_t GotPlt = In<ELFT>::GotPlt->getVA();
236
2
    uint64_t Plt = In<ELFT>::Plt->getVA();
237
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
238
2
    memset(Buf, 0, PltHeaderSize);
239
2
240
2
    write16<E>(Buf, isMipsR6<ELFT>() ? 
0x78601
:
0x79801
);
241
2
                                    // addiupc v1, (GOTPLT) - .
242
2
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
243
2
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
244
2
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
245
2
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
246
2
    write16<E>(Buf + 14, 0xfffe);
247
2
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
248
2
    if (
isMipsR6<ELFT>()2
) {
249
1
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
250
1
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
251
1
      write16<E>(Buf + 22, 0x0c00); // nop
252
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
253
2
    } else {
254
1
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
255
1
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
256
1
      write16<E>(Buf + 22, 0x0c00); // nop
257
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
258
1
    }
259
2
    return;
260
2
  }
261
0
262
0
  
if (0
Config->MipsN32Abi0
) {
263
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
264
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
265
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
266
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
267
0
  } else {
268
0
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
269
0
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
270
0
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
271
0
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
272
0
  }
273
2
274
2
  write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
275
2
  write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
276
2
  write32<E>(Buf + 24, 0x0320f809); // jalr  $25
277
2
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
278
2
279
2
  uint64_t GotPlt = InX::GotPlt->getVA();
280
2
  writeRelocation<E>(Buf, GotPlt + 0x8000, 16, 16);
281
2
  writeRelocation<E>(Buf + 4, GotPlt, 16, 0);
282
2
  writeRelocation<E>(Buf + 8, GotPlt, 16, 0);
283
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writePltHeader(unsigned char*) const
Line
Count
Source
232
6
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
233
6
  const endianness E = ELFT::TargetEndianness;
234
6
  if (
isMicroMips<ELFT>()6
) {
235
2
    uint64_t GotPlt = In<ELFT>::GotPlt->getVA();
236
2
    uint64_t Plt = In<ELFT>::Plt->getVA();
237
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
238
2
    memset(Buf, 0, PltHeaderSize);
239
2
240
2
    write16<E>(Buf, isMipsR6<ELFT>() ? 
0x78601
:
0x79801
);
241
2
                                    // addiupc v1, (GOTPLT) - .
242
2
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
243
2
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
244
2
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
245
2
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
246
2
    write16<E>(Buf + 14, 0xfffe);
247
2
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
248
2
    if (
isMipsR6<ELFT>()2
) {
249
1
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
250
1
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
251
1
      write16<E>(Buf + 22, 0x0c00); // nop
252
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
253
2
    } else {
254
1
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
255
1
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
256
1
      write16<E>(Buf + 22, 0x0c00); // nop
257
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
258
1
    }
259
2
    return;
260
2
  }
261
4
262
4
  
if (4
Config->MipsN32Abi4
) {
263
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
264
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
265
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
266
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
267
4
  } else {
268
4
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
269
4
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
270
4
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
271
4
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
272
4
  }
273
6
274
6
  write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
275
6
  write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
276
6
  write32<E>(Buf + 24, 0x0320f809); // jalr  $25
277
6
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
278
6
279
6
  uint64_t GotPlt = InX::GotPlt->getVA();
280
6
  writeRelocation<E>(Buf, GotPlt + 0x8000, 16, 16);
281
6
  writeRelocation<E>(Buf + 4, GotPlt, 16, 0);
282
6
  writeRelocation<E>(Buf + 8, GotPlt, 16, 0);
283
6
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writePltHeader(unsigned char*) const
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writePltHeader(unsigned char*) const
284
285
template <class ELFT>
286
void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
287
                          uint64_t PltEntryAddr, int32_t Index,
288
10
                          unsigned RelOff) const {
289
10
  const endianness E = ELFT::TargetEndianness;
290
10
  if (
isMicroMips<ELFT>()10
) {
291
4
    // Overwrite trap instructions written by Writer::writeTrapInstr.
292
4
    memset(Buf, 0, PltEntrySize);
293
4
294
4
    if (
isMipsR6<ELFT>()4
) {
295
2
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
296
2
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
297
2
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
298
2
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
299
2
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
300
4
    } else {
301
2
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
302
2
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
303
2
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
304
2
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
305
2
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
306
2
    }
307
4
    return;
308
4
  }
309
6
310
6
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
311
6
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
312
6
                                   // jr    $25
313
6
  write32<E>(Buf + 8, isMipsR6<ELFT>() ? 
0x032000091
:
0x032000085
);
314
10
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
315
10
  writeRelocation<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
316
10
  writeRelocation<E>(Buf + 4, GotPltEntryAddr, 16, 0);
317
10
  writeRelocation<E>(Buf + 12, GotPltEntryAddr, 16, 0);
318
10
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
288
8
                          unsigned RelOff) const {
289
8
  const endianness E = ELFT::TargetEndianness;
290
8
  if (
isMicroMips<ELFT>()8
) {
291
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
292
2
    memset(Buf, 0, PltEntrySize);
293
2
294
2
    if (
isMipsR6<ELFT>()2
) {
295
1
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
296
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
297
1
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
298
1
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
299
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
300
2
    } else {
301
1
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
302
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
303
1
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
304
1
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
305
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
306
1
    }
307
2
    return;
308
2
  }
309
6
310
6
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
311
6
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
312
6
                                   // jr    $25
313
6
  write32<E>(Buf + 8, isMipsR6<ELFT>() ? 
0x032000091
:
0x032000085
);
314
8
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
315
8
  writeRelocation<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
316
8
  writeRelocation<E>(Buf + 4, GotPltEntryAddr, 16, 0);
317
8
  writeRelocation<E>(Buf + 12, GotPltEntryAddr, 16, 0);
318
8
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
288
2
                          unsigned RelOff) const {
289
2
  const endianness E = ELFT::TargetEndianness;
290
2
  if (
isMicroMips<ELFT>()2
) {
291
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
292
2
    memset(Buf, 0, PltEntrySize);
293
2
294
2
    if (
isMipsR6<ELFT>()2
) {
295
1
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
296
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
297
1
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
298
1
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
299
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
300
2
    } else {
301
1
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
302
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
303
1
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
304
1
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
305
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
306
1
    }
307
2
    return;
308
2
  }
309
0
310
0
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
311
0
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
312
0
                                   // jr    $25
313
0
  write32<E>(Buf + 8, isMipsR6<ELFT>() ? 
0x032000090
:
0x032000080
);
314
2
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
315
2
  writeRelocation<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
316
2
  writeRelocation<E>(Buf + 4, GotPltEntryAddr, 16, 0);
317
2
  writeRelocation<E>(Buf + 12, GotPltEntryAddr, 16, 0);
318
2
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
319
320
template <class ELFT>
321
bool MIPS<ELFT>::needsThunk(RelExpr Expr, uint32_t Type, const InputFile *File,
322
266
                            const SymbolBody &S) const {
323
266
  // Any MIPS PIC code function is invoked with its address in register $t9.
324
266
  // So if we have a branch instruction from non-PIC code to the PIC one
325
266
  // we cannot make the jump directly and need to create a small stubs
326
266
  // to save the target function address.
327
266
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
328
266
  if (
Type != R_MIPS_26 && 266
Type != R_MICROMIPS_26_S1211
&&
329
207
      Type != R_MICROMIPS_PC26_S1)
330
207
    return false;
331
59
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
332
59
  if (!F)
333
0
    return false;
334
59
  // If current file has PIC code, LA25 stub is not required.
335
59
  
if (59
F->getObj().getHeader()->e_flags & EF_MIPS_PIC59
)
336
0
    return false;
337
59
  auto *D = dyn_cast<DefinedRegular>(&S);
338
59
  // LA25 is required if target file has PIC code
339
59
  // or target symbol is a PIC symbol.
340
52
  return D && D->isMipsPIC<ELFT>();
341
266
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, lld::elf::SymbolBody const&) const
Line
Count
Source
322
42
                            const SymbolBody &S) const {
323
42
  // Any MIPS PIC code function is invoked with its address in register $t9.
324
42
  // So if we have a branch instruction from non-PIC code to the PIC one
325
42
  // we cannot make the jump directly and need to create a small stubs
326
42
  // to save the target function address.
327
42
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
328
42
  if (
Type != R_MIPS_26 && 42
Type != R_MICROMIPS_26_S142
&&
329
42
      Type != R_MICROMIPS_PC26_S1)
330
42
    return false;
331
0
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
332
0
  if (!F)
333
0
    return false;
334
0
  // If current file has PIC code, LA25 stub is not required.
335
0
  
if (0
F->getObj().getHeader()->e_flags & EF_MIPS_PIC0
)
336
0
    return false;
337
0
  auto *D = dyn_cast<DefinedRegular>(&S);
338
0
  // LA25 is required if target file has PIC code
339
0
  // or target symbol is a PIC symbol.
340
0
  return D && D->isMipsPIC<ELFT>();
341
42
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, lld::elf::SymbolBody const&) const
Line
Count
Source
322
13
                            const SymbolBody &S) const {
323
13
  // Any MIPS PIC code function is invoked with its address in register $t9.
324
13
  // So if we have a branch instruction from non-PIC code to the PIC one
325
13
  // we cannot make the jump directly and need to create a small stubs
326
13
  // to save the target function address.
327
13
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
328
13
  if (
Type != R_MIPS_26 && 13
Type != R_MICROMIPS_26_S113
&&
329
11
      Type != R_MICROMIPS_PC26_S1)
330
11
    return false;
331
2
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
332
2
  if (!F)
333
0
    return false;
334
2
  // If current file has PIC code, LA25 stub is not required.
335
2
  
if (2
F->getObj().getHeader()->e_flags & EF_MIPS_PIC2
)
336
0
    return false;
337
2
  auto *D = dyn_cast<DefinedRegular>(&S);
338
2
  // LA25 is required if target file has PIC code
339
2
  // or target symbol is a PIC symbol.
340
0
  return D && D->isMipsPIC<ELFT>();
341
13
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, lld::elf::SymbolBody const&) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, lld::elf::SymbolBody const&) const
Line
Count
Source
322
211
                            const SymbolBody &S) const {
323
211
  // Any MIPS PIC code function is invoked with its address in register $t9.
324
211
  // So if we have a branch instruction from non-PIC code to the PIC one
325
211
  // we cannot make the jump directly and need to create a small stubs
326
211
  // to save the target function address.
327
211
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
328
211
  if (
Type != R_MIPS_26 && 211
Type != R_MICROMIPS_26_S1156
&&
329
154
      Type != R_MICROMIPS_PC26_S1)
330
154
    return false;
331
57
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
332
57
  if (!F)
333
0
    return false;
334
57
  // If current file has PIC code, LA25 stub is not required.
335
57
  
if (57
F->getObj().getHeader()->e_flags & EF_MIPS_PIC57
)
336
0
    return false;
337
57
  auto *D = dyn_cast<DefinedRegular>(&S);
338
57
  // LA25 is required if target file has PIC code
339
57
  // or target symbol is a PIC symbol.
340
52
  return D && D->isMipsPIC<ELFT>();
341
211
}
342
343
template <class ELFT>
344
280
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const {
345
280
  const endianness E = ELFT::TargetEndianness;
346
280
  switch (Type) {
347
42
  default:
348
42
    return 0;
349
23
  case R_MIPS_32:
350
23
  case R_MIPS_GPREL32:
351
23
  case R_MIPS_TLS_DTPREL32:
352
23
  case R_MIPS_TLS_TPREL32:
353
23
    return SignExtend64<32>(read32<E>(Buf));
354
48
  case R_MIPS_26:
355
48
    // FIXME (simon): If the relocation target symbol is not a PLT entry
356
48
    // we should use another expression for calculation:
357
48
    // ((A << 2) | (P & 0xf0000000)) >> 2
358
48
    return SignExtend64<28>(read32<E>(Buf) << 2);
359
60
  case R_MIPS_GOT16:
360
60
  case R_MIPS_HI16:
361
60
  case R_MIPS_PCHI16:
362
60
    return SignExtend64<16>(read32<E>(Buf)) << 16;
363
80
  case R_MIPS_GPREL16:
364
80
  case R_MIPS_LO16:
365
80
  case R_MIPS_PCLO16:
366
80
  case R_MIPS_TLS_DTPREL_HI16:
367
80
  case R_MIPS_TLS_DTPREL_LO16:
368
80
  case R_MIPS_TLS_TPREL_HI16:
369
80
  case R_MIPS_TLS_TPREL_LO16:
370
80
    return SignExtend64<16>(read32<E>(Buf));
371
5
  case R_MICROMIPS_GOT16:
372
5
  case R_MICROMIPS_HI16:
373
5
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
374
6
  case R_MICROMIPS_GPREL16:
375
6
  case R_MICROMIPS_LO16:
376
6
  case R_MICROMIPS_TLS_DTPREL_HI16:
377
6
  case R_MICROMIPS_TLS_DTPREL_LO16:
378
6
  case R_MICROMIPS_TLS_TPREL_HI16:
379
6
  case R_MICROMIPS_TLS_TPREL_LO16:
380
6
    return SignExtend64<16>(readShuffle<E>(Buf));
381
0
  case R_MICROMIPS_GPREL7_S2:
382
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
383
2
  case R_MIPS_PC16:
384
2
    return SignExtend64<18>(read32<E>(Buf) << 2);
385
1
  case R_MIPS_PC19_S2:
386
1
    return SignExtend64<21>(read32<E>(Buf) << 2);
387
1
  case R_MIPS_PC21_S2:
388
1
    return SignExtend64<23>(read32<E>(Buf) << 2);
389
1
  case R_MIPS_PC26_S2:
390
1
    return SignExtend64<28>(read32<E>(Buf) << 2);
391
1
  case R_MIPS_PC32:
392
1
    return SignExtend64<32>(read32<E>(Buf));
393
4
  case R_MICROMIPS_26_S1:
394
4
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
395
2
  case R_MICROMIPS_PC7_S1:
396
2
    return SignExtend64<8>(read16<E>(Buf) << 1);
397
2
  case R_MICROMIPS_PC10_S1:
398
2
    return SignExtend64<11>(read16<E>(Buf) << 1);
399
2
  case R_MICROMIPS_PC16_S1:
400
2
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
401
0
  case R_MICROMIPS_PC18_S3:
402
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
403
0
  case R_MICROMIPS_PC19_S2:
404
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
405
0
  case R_MICROMIPS_PC21_S1:
406
0
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
407
0
  case R_MICROMIPS_PC23_S2:
408
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
409
0
  case R_MICROMIPS_PC26_S1:
410
0
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
411
0
  }
412
0
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getImplicitAddend(unsigned char const*, unsigned int) const
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getImplicitAddend(unsigned char const*, unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getImplicitAddend(unsigned char const*, unsigned int) const
Line
Count
Source
344
264
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const {
345
264
  const endianness E = ELFT::TargetEndianness;
346
264
  switch (Type) {
347
41
  default:
348
41
    return 0;
349
21
  case R_MIPS_32:
350
21
  case R_MIPS_GPREL32:
351
21
  case R_MIPS_TLS_DTPREL32:
352
21
  case R_MIPS_TLS_TPREL32:
353
21
    return SignExtend64<32>(read32<E>(Buf));
354
48
  case R_MIPS_26:
355
48
    // FIXME (simon): If the relocation target symbol is not a PLT entry
356
48
    // we should use another expression for calculation:
357
48
    // ((A << 2) | (P & 0xf0000000)) >> 2
358
48
    return SignExtend64<28>(read32<E>(Buf) << 2);
359
56
  case R_MIPS_GOT16:
360
56
  case R_MIPS_HI16:
361
56
  case R_MIPS_PCHI16:
362
56
    return SignExtend64<16>(read32<E>(Buf)) << 16;
363
80
  case R_MIPS_GPREL16:
364
80
  case R_MIPS_LO16:
365
80
  case R_MIPS_PCLO16:
366
80
  case R_MIPS_TLS_DTPREL_HI16:
367
80
  case R_MIPS_TLS_DTPREL_LO16:
368
80
  case R_MIPS_TLS_TPREL_HI16:
369
80
  case R_MIPS_TLS_TPREL_LO16:
370
80
    return SignExtend64<16>(read32<E>(Buf));
371
3
  case R_MICROMIPS_GOT16:
372
3
  case R_MICROMIPS_HI16:
373
3
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
374
4
  case R_MICROMIPS_GPREL16:
375
4
  case R_MICROMIPS_LO16:
376
4
  case R_MICROMIPS_TLS_DTPREL_HI16:
377
4
  case R_MICROMIPS_TLS_DTPREL_LO16:
378
4
  case R_MICROMIPS_TLS_TPREL_HI16:
379
4
  case R_MICROMIPS_TLS_TPREL_LO16:
380
4
    return SignExtend64<16>(readShuffle<E>(Buf));
381
0
  case R_MICROMIPS_GPREL7_S2:
382
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
383
2
  case R_MIPS_PC16:
384
2
    return SignExtend64<18>(read32<E>(Buf) << 2);
385
1
  case R_MIPS_PC19_S2:
386
1
    return SignExtend64<21>(read32<E>(Buf) << 2);
387
1
  case R_MIPS_PC21_S2:
388
1
    return SignExtend64<23>(read32<E>(Buf) << 2);
389
1
  case R_MIPS_PC26_S2:
390
1
    return SignExtend64<28>(read32<E>(Buf) << 2);
391
1
  case R_MIPS_PC32:
392
1
    return SignExtend64<32>(read32<E>(Buf));
393
2
  case R_MICROMIPS_26_S1:
394
2
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
395
1
  case R_MICROMIPS_PC7_S1:
396
1
    return SignExtend64<8>(read16<E>(Buf) << 1);
397
1
  case R_MICROMIPS_PC10_S1:
398
1
    return SignExtend64<11>(read16<E>(Buf) << 1);
399
1
  case R_MICROMIPS_PC16_S1:
400
1
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
401
0
  case R_MICROMIPS_PC18_S3:
402
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
403
0
  case R_MICROMIPS_PC19_S2:
404
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
405
0
  case R_MICROMIPS_PC21_S1:
406
0
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
407
0
  case R_MICROMIPS_PC23_S2:
408
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
409
0
  case R_MICROMIPS_PC26_S1:
410
0
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
411
0
  }
412
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getImplicitAddend(unsigned char const*, unsigned int) const
Line
Count
Source
344
16
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const {
345
16
  const endianness E = ELFT::TargetEndianness;
346
16
  switch (Type) {
347
1
  default:
348
1
    return 0;
349
2
  case R_MIPS_32:
350
2
  case R_MIPS_GPREL32:
351
2
  case R_MIPS_TLS_DTPREL32:
352
2
  case R_MIPS_TLS_TPREL32:
353
2
    return SignExtend64<32>(read32<E>(Buf));
354
0
  case R_MIPS_26:
355
0
    // FIXME (simon): If the relocation target symbol is not a PLT entry
356
0
    // we should use another expression for calculation:
357
0
    // ((A << 2) | (P & 0xf0000000)) >> 2
358
0
    return SignExtend64<28>(read32<E>(Buf) << 2);
359
4
  case R_MIPS_GOT16:
360
4
  case R_MIPS_HI16:
361
4
  case R_MIPS_PCHI16:
362
4
    return SignExtend64<16>(read32<E>(Buf)) << 16;
363
0
  case R_MIPS_GPREL16:
364
0
  case R_MIPS_LO16:
365
0
  case R_MIPS_PCLO16:
366
0
  case R_MIPS_TLS_DTPREL_HI16:
367
0
  case R_MIPS_TLS_DTPREL_LO16:
368
0
  case R_MIPS_TLS_TPREL_HI16:
369
0
  case R_MIPS_TLS_TPREL_LO16:
370
0
    return SignExtend64<16>(read32<E>(Buf));
371
2
  case R_MICROMIPS_GOT16:
372
2
  case R_MICROMIPS_HI16:
373
2
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
374
2
  case R_MICROMIPS_GPREL16:
375
2
  case R_MICROMIPS_LO16:
376
2
  case R_MICROMIPS_TLS_DTPREL_HI16:
377
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
378
2
  case R_MICROMIPS_TLS_TPREL_HI16:
379
2
  case R_MICROMIPS_TLS_TPREL_LO16:
380
2
    return SignExtend64<16>(readShuffle<E>(Buf));
381
0
  case R_MICROMIPS_GPREL7_S2:
382
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
383
0
  case R_MIPS_PC16:
384
0
    return SignExtend64<18>(read32<E>(Buf) << 2);
385
0
  case R_MIPS_PC19_S2:
386
0
    return SignExtend64<21>(read32<E>(Buf) << 2);
387
0
  case R_MIPS_PC21_S2:
388
0
    return SignExtend64<23>(read32<E>(Buf) << 2);
389
0
  case R_MIPS_PC26_S2:
390
0
    return SignExtend64<28>(read32<E>(Buf) << 2);
391
0
  case R_MIPS_PC32:
392
0
    return SignExtend64<32>(read32<E>(Buf));
393
2
  case R_MICROMIPS_26_S1:
394
2
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
395
1
  case R_MICROMIPS_PC7_S1:
396
1
    return SignExtend64<8>(read16<E>(Buf) << 1);
397
1
  case R_MICROMIPS_PC10_S1:
398
1
    return SignExtend64<11>(read16<E>(Buf) << 1);
399
1
  case R_MICROMIPS_PC16_S1:
400
1
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
401
0
  case R_MICROMIPS_PC18_S3:
402
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
403
0
  case R_MICROMIPS_PC19_S2:
404
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
405
0
  case R_MICROMIPS_PC21_S1:
406
0
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
407
0
  case R_MICROMIPS_PC23_S2:
408
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
409
0
  case R_MICROMIPS_PC26_S1:
410
0
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
411
0
  }
412
0
}
413
414
static std::pair<uint32_t, uint64_t>
415
50
calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) {
416
50
  // MIPS N64 ABI packs multiple relocations into the single relocation
417
50
  // record. In general, all up to three relocations can have arbitrary
418
50
  // types. In fact, Clang and GCC uses only a few combinations. For now,
419
50
  // we support two of them. That is allow to pass at least all LLVM
420
50
  // test suite cases.
421
50
  // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
422
50
  // <any relocation> / R_MIPS_64 / R_MIPS_NONE
423
50
  // The first relocation is a 'real' relocation which is calculated
424
50
  // using the corresponding symbol's value. The second and the third
425
50
  // relocations used to modify result of the first one: extend it to
426
50
  // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
427
50
  // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
428
50
  uint32_t Type2 = (Type >> 8) & 0xff;
429
50
  uint32_t Type3 = (Type >> 16) & 0xff;
430
50
  if (
Type2 == R_MIPS_NONE && 50
Type3 == R_MIPS_NONE38
)
431
38
    return std::make_pair(Type, Val);
432
12
  
if (12
Type2 == R_MIPS_64 && 12
Type3 == R_MIPS_NONE1
)
433
1
    return std::make_pair(Type2, Val);
434
11
  
if (11
Type2 == R_MIPS_SUB && 11
(Type3 == R_MIPS_HI16 || 11
Type3 == R_MIPS_LO164
))
435
11
    return std::make_pair(Type3, -Val);
436
0
  
if (0
Type2 == R_MICROMIPS_SUB &&
437
0
      
(Type3 == R_MICROMIPS_HI16 || 0
Type3 == R_MICROMIPS_LO160
))
438
0
    return std::make_pair(Type3, -Val);
439
0
  error(getErrorLocation(Loc) + "unsupported relocations combination " +
440
0
        Twine(Type));
441
0
  return std::make_pair(Type & 0xff, Val);
442
0
}
443
444
template <class ELFT>
445
354
void MIPS<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
446
354
  const endianness E = ELFT::TargetEndianness;
447
354
  // Thread pointer and DRP offsets from the start of TLS data area.
448
354
  // https://www.linux-mips.org/wiki/NPTL
449
354
  if (
Type == R_MIPS_TLS_DTPREL_HI16 || 354
Type == R_MIPS_TLS_DTPREL_LO16352
||
450
354
      
Type == R_MIPS_TLS_DTPREL32350
||
Type == R_MIPS_TLS_DTPREL64349
||
451
348
      Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
452
348
      Type == R_MICROMIPS_TLS_DTPREL_LO16)
453
6
    Val -= 0x8000;
454
348
  else 
if (348
Type == R_MIPS_TLS_TPREL_HI16 || 348
Type == R_MIPS_TLS_TPREL_LO16344
||
455
348
           
Type == R_MIPS_TLS_TPREL32343
||
Type == R_MIPS_TLS_TPREL64343
||
456
341
           Type == R_MICROMIPS_TLS_TPREL_HI16 ||
457
341
           Type == R_MICROMIPS_TLS_TPREL_LO16)
458
6
    Val -= 0x7000;
459
354
  if (
ELFT::Is64Bits || 354
Config->MipsN32Abi306
)
460
50
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
461
354
  switch (Type) {
462
24
  case R_MIPS_32:
463
24
  case R_MIPS_GPREL32:
464
24
  case R_MIPS_TLS_DTPREL32:
465
24
  case R_MIPS_TLS_TPREL32:
466
24
    write32<E>(Loc, Val);
467
24
    break;
468
3
  case R_MIPS_64:
469
3
  case R_MIPS_TLS_DTPREL64:
470
3
  case R_MIPS_TLS_TPREL64:
471
3
    write64<E>(Loc, Val);
472
3
    break;
473
48
  case R_MIPS_26:
474
48
    writeRelocation<E>(Loc, Val, 26, 2);
475
48
    break;
476
37
  case R_MIPS_GOT16:
477
37
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
478
37
    // is updated addend (not a GOT index). In that case write high 16 bits
479
37
    // to store a correct addend value.
480
37
    if (
Config->Relocatable37
) {
481
2
      writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
482
37
    } else {
483
35
      checkInt<16>(Loc, Val, Type);
484
35
      writeRelocation<E>(Loc, Val, 16, 0);
485
35
    }
486
37
    break;
487
3
  case R_MICROMIPS_GOT16:
488
3
    if (
Config->Relocatable3
) {
489
0
      writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
490
3
    } else {
491
3
      checkInt<16>(Loc, Val, Type);
492
3
      writeMicroRelocation32<E>(Loc, Val, 16, 0);
493
3
    }
494
3
    break;
495
26
  case R_MIPS_GOT_DISP:
496
26
  case R_MIPS_GOT_PAGE:
497
26
  case R_MIPS_GPREL16:
498
26
  case R_MIPS_TLS_GD:
499
26
  case R_MIPS_TLS_LDM:
500
26
    checkInt<16>(Loc, Val, Type);
501
26
    LLVM_FALLTHROUGH;
502
130
  case R_MIPS_CALL16:
503
130
  case R_MIPS_CALL_LO16:
504
130
  case R_MIPS_GOT_LO16:
505
130
  case R_MIPS_GOT_OFST:
506
130
  case R_MIPS_LO16:
507
130
  case R_MIPS_PCLO16:
508
130
  case R_MIPS_TLS_DTPREL_LO16:
509
130
  case R_MIPS_TLS_GOTTPREL:
510
130
  case R_MIPS_TLS_TPREL_LO16:
511
130
    writeRelocation<E>(Loc, Val, 16, 0);
512
130
    break;
513
1
  case R_MICROMIPS_GOT_DISP:
514
1
  case R_MICROMIPS_GOT_PAGE:
515
1
  case R_MICROMIPS_GPREL16:
516
1
  case R_MICROMIPS_TLS_GD:
517
1
  case R_MICROMIPS_TLS_LDM:
518
1
    checkInt<16>(Loc, Val, Type);
519
1
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
520
1
    break;
521
8
  case R_MICROMIPS_CALL16:
522
8
  case R_MICROMIPS_CALL_LO16:
523
8
  case R_MICROMIPS_GOT_OFST:
524
8
  case R_MICROMIPS_LO16:
525
8
  case R_MICROMIPS_TLS_DTPREL_LO16:
526
8
  case R_MICROMIPS_TLS_GOTTPREL:
527
8
  case R_MICROMIPS_TLS_TPREL_LO16:
528
8
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
529
8
    break;
530
0
  case R_MICROMIPS_GPREL7_S2:
531
0
    checkInt<7>(Loc, Val, Type);
532
0
    writeMicroRelocation32<E>(Loc, Val, 7, 2);
533
0
    break;
534
70
  case R_MIPS_CALL_HI16:
535
70
  case R_MIPS_GOT_HI16:
536
70
  case R_MIPS_HI16:
537
70
  case R_MIPS_PCHI16:
538
70
  case R_MIPS_TLS_DTPREL_HI16:
539
70
  case R_MIPS_TLS_TPREL_HI16:
540
70
    writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
541
70
    break;
542
2
  case R_MICROMIPS_CALL_HI16:
543
2
  case R_MICROMIPS_GOT_HI16:
544
2
  case R_MICROMIPS_HI16:
545
2
  case R_MICROMIPS_TLS_DTPREL_HI16:
546
2
  case R_MICROMIPS_TLS_TPREL_HI16:
547
2
    writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
548
2
    break;
549
2
  case R_MIPS_HIGHER:
550
2
    writeRelocation<E>(Loc, Val + 0x80008000, 16, 32);
551
2
    break;
552
2
  case R_MIPS_HIGHEST:
553
2
    writeRelocation<E>(Loc, Val + 0x800080008000, 16, 48);
554
2
    break;
555
0
  case R_MICROMIPS_HIGHER:
556
0
    writeMicroRelocation32<E>(Loc, Val + 0x80008000, 16, 32);
557
0
    break;
558
0
  case R_MICROMIPS_HIGHEST:
559
0
    writeMicroRelocation32<E>(Loc, Val + 0x800080008000, 16, 48);
560
0
    break;
561
0
  case R_MIPS_JALR:
562
0
  case R_MICROMIPS_JALR:
563
0
    // Ignore this optimization relocation for now
564
0
    break;
565
2
  case R_MIPS_PC16:
566
2
    checkAlignment<4>(Loc, Val, Type);
567
2
    checkInt<18>(Loc, Val, Type);
568
2
    writeRelocation<E>(Loc, Val, 16, 2);
569
2
    break;
570
1
  case R_MIPS_PC19_S2:
571
1
    checkAlignment<4>(Loc, Val, Type);
572
1
    checkInt<21>(Loc, Val, Type);
573
1
    writeRelocation<E>(Loc, Val, 19, 2);
574
1
    break;
575
1
  case R_MIPS_PC21_S2:
576
1
    checkAlignment<4>(Loc, Val, Type);
577
1
    checkInt<23>(Loc, Val, Type);
578
1
    writeRelocation<E>(Loc, Val, 21, 2);
579
1
    break;
580
1
  case R_MIPS_PC26_S2:
581
1
    checkAlignment<4>(Loc, Val, Type);
582
1
    checkInt<28>(Loc, Val, Type);
583
1
    writeRelocation<E>(Loc, Val, 26, 2);
584
1
    break;
585
2
  case R_MIPS_PC32:
586
2
    writeRelocation<E>(Loc, Val, 32, 0);
587
2
    break;
588
4
  case R_MICROMIPS_26_S1:
589
4
  case R_MICROMIPS_PC26_S1:
590
4
    checkInt<27>(Loc, Val, Type);
591
4
    writeMicroRelocation32<E>(Loc, Val, 26, 1);
592
4
    break;
593
2
  case R_MICROMIPS_PC7_S1:
594
2
    checkInt<8>(Loc, Val, Type);
595
2
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
596
2
    break;
597
2
  case R_MICROMIPS_PC10_S1:
598
2
    checkInt<11>(Loc, Val, Type);
599
2
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
600
2
    break;
601
2
  case R_MICROMIPS_PC16_S1:
602
2
    checkInt<17>(Loc, Val, Type);
603
2
    writeMicroRelocation32<E>(Loc, Val, 16, 1);
604
2
    break;
605
0
  case R_MICROMIPS_PC18_S3:
606
0
    checkInt<21>(Loc, Val, Type);
607
0
    writeMicroRelocation32<E>(Loc, Val, 18, 3);
608
0
    break;
609
4
  case R_MICROMIPS_PC19_S2:
610
4
    checkInt<21>(Loc, Val, Type);
611
4
    writeMicroRelocation32<E>(Loc, Val, 19, 2);
612
4
    break;
613
0
  case R_MICROMIPS_PC21_S1:
614
0
    checkInt<22>(Loc, Val, Type);
615
0
    writeMicroRelocation32<E>(Loc, Val, 21, 1);
616
0
    break;
617
4
  case R_MICROMIPS_PC23_S2:
618
4
    checkInt<25>(Loc, Val, Type);
619
4
    writeMicroRelocation32<E>(Loc, Val, 23, 2);
620
4
    break;
621
0
  default:
622
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
623
354
  }
624
354
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
445
18
void MIPS<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
446
18
  const endianness E = ELFT::TargetEndianness;
447
18
  // Thread pointer and DRP offsets from the start of TLS data area.
448
18
  // https://www.linux-mips.org/wiki/NPTL
449
18
  if (
Type == R_MIPS_TLS_DTPREL_HI16 || 18
Type == R_MIPS_TLS_DTPREL_LO1618
||
450
18
      
Type == R_MIPS_TLS_DTPREL3218
||
Type == R_MIPS_TLS_DTPREL6418
||
451
18
      Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
452
18
      Type == R_MICROMIPS_TLS_DTPREL_LO16)
453
0
    Val -= 0x8000;
454
18
  else 
if (18
Type == R_MIPS_TLS_TPREL_HI16 || 18
Type == R_MIPS_TLS_TPREL_LO1618
||
455
18
           
Type == R_MIPS_TLS_TPREL3218
||
Type == R_MIPS_TLS_TPREL6418
||
456
18
           Type == R_MICROMIPS_TLS_TPREL_HI16 ||
457
18
           Type == R_MICROMIPS_TLS_TPREL_LO16)
458
0
    Val -= 0x7000;
459
18
  if (
ELFT::Is64Bits || 18
Config->MipsN32Abi18
)
460
0
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
461
18
  switch (Type) {
462
1
  case R_MIPS_32:
463
1
  case R_MIPS_GPREL32:
464
1
  case R_MIPS_TLS_DTPREL32:
465
1
  case R_MIPS_TLS_TPREL32:
466
1
    write32<E>(Loc, Val);
467
1
    break;
468
0
  case R_MIPS_64:
469
0
  case R_MIPS_TLS_DTPREL64:
470
0
  case R_MIPS_TLS_TPREL64:
471
0
    write64<E>(Loc, Val);
472
0
    break;
473
0
  case R_MIPS_26:
474
0
    writeRelocation<E>(Loc, Val, 26, 2);
475
0
    break;
476
4
  case R_MIPS_GOT16:
477
4
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
478
4
    // is updated addend (not a GOT index). In that case write high 16 bits
479
4
    // to store a correct addend value.
480
4
    if (
Config->Relocatable4
) {
481
0
      writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
482
4
    } else {
483
4
      checkInt<16>(Loc, Val, Type);
484
4
      writeRelocation<E>(Loc, Val, 16, 0);
485
4
    }
486
4
    break;
487
1
  case R_MICROMIPS_GOT16:
488
1
    if (
Config->Relocatable1
) {
489
0
      writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
490
1
    } else {
491
1
      checkInt<16>(Loc, Val, Type);
492
1
      writeMicroRelocation32<E>(Loc, Val, 16, 0);
493
1
    }
494
1
    break;
495
0
  case R_MIPS_GOT_DISP:
496
0
  case R_MIPS_GOT_PAGE:
497
0
  case R_MIPS_GPREL16:
498
0
  case R_MIPS_TLS_GD:
499
0
  case R_MIPS_TLS_LDM:
500
0
    checkInt<16>(Loc, Val, Type);
501
0
    LLVM_FALLTHROUGH;
502
0
  case R_MIPS_CALL16:
503
0
  case R_MIPS_CALL_LO16:
504
0
  case R_MIPS_GOT_LO16:
505
0
  case R_MIPS_GOT_OFST:
506
0
  case R_MIPS_LO16:
507
0
  case R_MIPS_PCLO16:
508
0
  case R_MIPS_TLS_DTPREL_LO16:
509
0
  case R_MIPS_TLS_GOTTPREL:
510
0
  case R_MIPS_TLS_TPREL_LO16:
511
0
    writeRelocation<E>(Loc, Val, 16, 0);
512
0
    break;
513
0
  case R_MICROMIPS_GOT_DISP:
514
0
  case R_MICROMIPS_GOT_PAGE:
515
0
  case R_MICROMIPS_GPREL16:
516
0
  case R_MICROMIPS_TLS_GD:
517
0
  case R_MICROMIPS_TLS_LDM:
518
0
    checkInt<16>(Loc, Val, Type);
519
0
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
520
0
    break;
521
2
  case R_MICROMIPS_CALL16:
522
2
  case R_MICROMIPS_CALL_LO16:
523
2
  case R_MICROMIPS_GOT_OFST:
524
2
  case R_MICROMIPS_LO16:
525
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
526
2
  case R_MICROMIPS_TLS_GOTTPREL:
527
2
  case R_MICROMIPS_TLS_TPREL_LO16:
528
2
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
529
2
    break;
530
0
  case R_MICROMIPS_GPREL7_S2:
531
0
    checkInt<7>(Loc, Val, Type);
532
0
    writeMicroRelocation32<E>(Loc, Val, 7, 2);
533
0
    break;
534
0
  case R_MIPS_CALL_HI16:
535
0
  case R_MIPS_GOT_HI16:
536
0
  case R_MIPS_HI16:
537
0
  case R_MIPS_PCHI16:
538
0
  case R_MIPS_TLS_DTPREL_HI16:
539
0
  case R_MIPS_TLS_TPREL_HI16:
540
0
    writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
541
0
    break;
542
1
  case R_MICROMIPS_CALL_HI16:
543
1
  case R_MICROMIPS_GOT_HI16:
544
1
  case R_MICROMIPS_HI16:
545
1
  case R_MICROMIPS_TLS_DTPREL_HI16:
546
1
  case R_MICROMIPS_TLS_TPREL_HI16:
547
1
    writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
548
1
    break;
549
0
  case R_MIPS_HIGHER:
550
0
    writeRelocation<E>(Loc, Val + 0x80008000, 16, 32);
551
0
    break;
552
0
  case R_MIPS_HIGHEST:
553
0
    writeRelocation<E>(Loc, Val + 0x800080008000, 16, 48);
554
0
    break;
555
0
  case R_MICROMIPS_HIGHER:
556
0
    writeMicroRelocation32<E>(Loc, Val + 0x80008000, 16, 32);
557
0
    break;
558
0
  case R_MICROMIPS_HIGHEST:
559
0
    writeMicroRelocation32<E>(Loc, Val + 0x800080008000, 16, 48);
560
0
    break;
561
0
  case R_MIPS_JALR:
562
0
  case R_MICROMIPS_JALR:
563
0
    // Ignore this optimization relocation for now
564
0
    break;
565
0
  case R_MIPS_PC16:
566
0
    checkAlignment<4>(Loc, Val, Type);
567
0
    checkInt<18>(Loc, Val, Type);
568
0
    writeRelocation<E>(Loc, Val, 16, 2);
569
0
    break;
570
0
  case R_MIPS_PC19_S2:
571
0
    checkAlignment<4>(Loc, Val, Type);
572
0
    checkInt<21>(Loc, Val, Type);
573
0
    writeRelocation<E>(Loc, Val, 19, 2);
574
0
    break;
575
0
  case R_MIPS_PC21_S2:
576
0
    checkAlignment<4>(Loc, Val, Type);
577
0
    checkInt<23>(Loc, Val, Type);
578
0
    writeRelocation<E>(Loc, Val, 21, 2);
579
0
    break;
580
0
  case R_MIPS_PC26_S2:
581
0
    checkAlignment<4>(Loc, Val, Type);
582
0
    checkInt<28>(Loc, Val, Type);
583
0
    writeRelocation<E>(Loc, Val, 26, 2);
584
0
    break;
585
0
  case R_MIPS_PC32:
586
0
    writeRelocation<E>(Loc, Val, 32, 0);
587
0
    break;
588
2
  case R_MICROMIPS_26_S1:
589
2
  case R_MICROMIPS_PC26_S1:
590
2
    checkInt<27>(Loc, Val, Type);
591
2
    writeMicroRelocation32<E>(Loc, Val, 26, 1);
592
2
    break;
593
1
  case R_MICROMIPS_PC7_S1:
594
1
    checkInt<8>(Loc, Val, Type);
595
1
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
596
1
    break;
597
1
  case R_MICROMIPS_PC10_S1:
598
1
    checkInt<11>(Loc, Val, Type);
599
1
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
600
1
    break;
601
1
  case R_MICROMIPS_PC16_S1:
602
1
    checkInt<17>(Loc, Val, Type);
603
1
    writeMicroRelocation32<E>(Loc, Val, 16, 1);
604
1
    break;
605
0
  case R_MICROMIPS_PC18_S3:
606
0
    checkInt<21>(Loc, Val, Type);
607
0
    writeMicroRelocation32<E>(Loc, Val, 18, 3);
608
0
    break;
609
2
  case R_MICROMIPS_PC19_S2:
610
2
    checkInt<21>(Loc, Val, Type);
611
2
    writeMicroRelocation32<E>(Loc, Val, 19, 2);
612
2
    break;
613
0
  case R_MICROMIPS_PC21_S1:
614
0
    checkInt<22>(Loc, Val, Type);
615
0
    writeMicroRelocation32<E>(Loc, Val, 21, 1);
616
0
    break;
617
2
  case R_MICROMIPS_PC23_S2:
618
2
    checkInt<25>(Loc, Val, Type);
619
2
    writeMicroRelocation32<E>(Loc, Val, 23, 2);
620
2
    break;
621
0
  default:
622
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
623
18
  }
624
18
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
445
289
void MIPS<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
446
289
  const endianness E = ELFT::TargetEndianness;
447
289
  // Thread pointer and DRP offsets from the start of TLS data area.
448
289
  // https://www.linux-mips.org/wiki/NPTL
449
289
  if (
Type == R_MIPS_TLS_DTPREL_HI16 || 289
Type == R_MIPS_TLS_DTPREL_LO16287
||
450
289
      
Type == R_MIPS_TLS_DTPREL32285
||
Type == R_MIPS_TLS_DTPREL64284
||
451
284
      Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
452
284
      Type == R_MICROMIPS_TLS_DTPREL_LO16)
453
5
    Val -= 0x8000;
454
284
  else 
if (284
Type == R_MIPS_TLS_TPREL_HI16 || 284
Type == R_MIPS_TLS_TPREL_LO16280
||
455
284
           
Type == R_MIPS_TLS_TPREL32279
||
Type == R_MIPS_TLS_TPREL64279
||
456
278
           Type == R_MICROMIPS_TLS_TPREL_HI16 ||
457
278
           Type == R_MICROMIPS_TLS_TPREL_LO16)
458
5
    Val -= 0x7000;
459
289
  if (
ELFT::Is64Bits || 289
Config->MipsN32Abi288
)
460
3
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
461
289
  switch (Type) {
462
21
  case R_MIPS_32:
463
21
  case R_MIPS_GPREL32:
464
21
  case R_MIPS_TLS_DTPREL32:
465
21
  case R_MIPS_TLS_TPREL32:
466
21
    write32<E>(Loc, Val);
467
21
    break;
468
0
  case R_MIPS_64:
469
0
  case R_MIPS_TLS_DTPREL64:
470
0
  case R_MIPS_TLS_TPREL64:
471
0
    write64<E>(Loc, Val);
472
0
    break;
473
48
  case R_MIPS_26:
474
48
    writeRelocation<E>(Loc, Val, 26, 2);
475
48
    break;
476
33
  case R_MIPS_GOT16:
477
33
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
478
33
    // is updated addend (not a GOT index). In that case write high 16 bits
479
33
    // to store a correct addend value.
480
33
    if (
Config->Relocatable33
) {
481
2
      writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
482
33
    } else {
483
31
      checkInt<16>(Loc, Val, Type);
484
31
      writeRelocation<E>(Loc, Val, 16, 0);
485
31
    }
486
33
    break;
487
2
  case R_MICROMIPS_GOT16:
488
2
    if (
Config->Relocatable2
) {
489
0
      writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
490
2
    } else {
491
2
      checkInt<16>(Loc, Val, Type);
492
2
      writeMicroRelocation32<E>(Loc, Val, 16, 0);
493
2
    }
494
2
    break;
495
8
  case R_MIPS_GOT_DISP:
496
8
  case R_MIPS_GOT_PAGE:
497
8
  case R_MIPS_GPREL16:
498
8
  case R_MIPS_TLS_GD:
499
8
  case R_MIPS_TLS_LDM:
500
8
    checkInt<16>(Loc, Val, Type);
501
8
    LLVM_FALLTHROUGH;
502
102
  case R_MIPS_CALL16:
503
102
  case R_MIPS_CALL_LO16:
504
102
  case R_MIPS_GOT_LO16:
505
102
  case R_MIPS_GOT_OFST:
506
102
  case R_MIPS_LO16:
507
102
  case R_MIPS_PCLO16:
508
102
  case R_MIPS_TLS_DTPREL_LO16:
509
102
  case R_MIPS_TLS_GOTTPREL:
510
102
  case R_MIPS_TLS_TPREL_LO16:
511
102
    writeRelocation<E>(Loc, Val, 16, 0);
512
102
    break;
513
0
  case R_MICROMIPS_GOT_DISP:
514
0
  case R_MICROMIPS_GOT_PAGE:
515
0
  case R_MICROMIPS_GPREL16:
516
0
  case R_MICROMIPS_TLS_GD:
517
0
  case R_MICROMIPS_TLS_LDM:
518
0
    checkInt<16>(Loc, Val, Type);
519
0
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
520
0
    break;
521
4
  case R_MICROMIPS_CALL16:
522
4
  case R_MICROMIPS_CALL_LO16:
523
4
  case R_MICROMIPS_GOT_OFST:
524
4
  case R_MICROMIPS_LO16:
525
4
  case R_MICROMIPS_TLS_DTPREL_LO16:
526
4
  case R_MICROMIPS_TLS_GOTTPREL:
527
4
  case R_MICROMIPS_TLS_TPREL_LO16:
528
4
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
529
4
    break;
530
0
  case R_MICROMIPS_GPREL7_S2:
531
0
    checkInt<7>(Loc, Val, Type);
532
0
    writeMicroRelocation32<E>(Loc, Val, 7, 2);
533
0
    break;
534
64
  case R_MIPS_CALL_HI16:
535
64
  case R_MIPS_GOT_HI16:
536
64
  case R_MIPS_HI16:
537
64
  case R_MIPS_PCHI16:
538
64
  case R_MIPS_TLS_DTPREL_HI16:
539
64
  case R_MIPS_TLS_TPREL_HI16:
540
64
    writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
541
64
    break;
542
1
  case R_MICROMIPS_CALL_HI16:
543
1
  case R_MICROMIPS_GOT_HI16:
544
1
  case R_MICROMIPS_HI16:
545
1
  case R_MICROMIPS_TLS_DTPREL_HI16:
546
1
  case R_MICROMIPS_TLS_TPREL_HI16:
547
1
    writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
548
1
    break;
549
0
  case R_MIPS_HIGHER:
550
0
    writeRelocation<E>(Loc, Val + 0x80008000, 16, 32);
551
0
    break;
552
0
  case R_MIPS_HIGHEST:
553
0
    writeRelocation<E>(Loc, Val + 0x800080008000, 16, 48);
554
0
    break;
555
0
  case R_MICROMIPS_HIGHER:
556
0
    writeMicroRelocation32<E>(Loc, Val + 0x80008000, 16, 32);
557
0
    break;
558
0
  case R_MICROMIPS_HIGHEST:
559
0
    writeMicroRelocation32<E>(Loc, Val + 0x800080008000, 16, 48);
560
0
    break;
561
0
  case R_MIPS_JALR:
562
0
  case R_MICROMIPS_JALR:
563
0
    // Ignore this optimization relocation for now
564
0
    break;
565
2
  case R_MIPS_PC16:
566
2
    checkAlignment<4>(Loc, Val, Type);
567
2
    checkInt<18>(Loc, Val, Type);
568
2
    writeRelocation<E>(Loc, Val, 16, 2);
569
2
    break;
570
1
  case R_MIPS_PC19_S2:
571
1
    checkAlignment<4>(Loc, Val, Type);
572
1
    checkInt<21>(Loc, Val, Type);
573
1
    writeRelocation<E>(Loc, Val, 19, 2);
574
1
    break;
575
1
  case R_MIPS_PC21_S2:
576
1
    checkAlignment<4>(Loc, Val, Type);
577
1
    checkInt<23>(Loc, Val, Type);
578
1
    writeRelocation<E>(Loc, Val, 21, 2);
579
1
    break;
580
1
  case R_MIPS_PC26_S2:
581
1
    checkAlignment<4>(Loc, Val, Type);
582
1
    checkInt<28>(Loc, Val, Type);
583
1
    writeRelocation<E>(Loc, Val, 26, 2);
584
1
    break;
585
1
  case R_MIPS_PC32:
586
1
    writeRelocation<E>(Loc, Val, 32, 0);
587
1
    break;
588
2
  case R_MICROMIPS_26_S1:
589
2
  case R_MICROMIPS_PC26_S1:
590
2
    checkInt<27>(Loc, Val, Type);
591
2
    writeMicroRelocation32<E>(Loc, Val, 26, 1);
592
2
    break;
593
1
  case R_MICROMIPS_PC7_S1:
594
1
    checkInt<8>(Loc, Val, Type);
595
1
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
596
1
    break;
597
1
  case R_MICROMIPS_PC10_S1:
598
1
    checkInt<11>(Loc, Val, Type);
599
1
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
600
1
    break;
601
1
  case R_MICROMIPS_PC16_S1:
602
1
    checkInt<17>(Loc, Val, Type);
603
1
    writeMicroRelocation32<E>(Loc, Val, 16, 1);
604
1
    break;
605
0
  case R_MICROMIPS_PC18_S3:
606
0
    checkInt<21>(Loc, Val, Type);
607
0
    writeMicroRelocation32<E>(Loc, Val, 18, 3);
608
0
    break;
609
2
  case R_MICROMIPS_PC19_S2:
610
2
    checkInt<21>(Loc, Val, Type);
611
2
    writeMicroRelocation32<E>(Loc, Val, 19, 2);
612
2
    break;
613
0
  case R_MICROMIPS_PC21_S1:
614
0
    checkInt<22>(Loc, Val, Type);
615
0
    writeMicroRelocation32<E>(Loc, Val, 21, 1);
616
0
    break;
617
2
  case R_MICROMIPS_PC23_S2:
618
2
    checkInt<25>(Loc, Val, Type);
619
2
    writeMicroRelocation32<E>(Loc, Val, 23, 2);
620
2
    break;
621
0
  default:
622
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
623
289
  }
624
289
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
445
47
void MIPS<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
446
47
  const endianness E = ELFT::TargetEndianness;
447
47
  // Thread pointer and DRP offsets from the start of TLS data area.
448
47
  // https://www.linux-mips.org/wiki/NPTL
449
47
  if (
Type == R_MIPS_TLS_DTPREL_HI16 || 47
Type == R_MIPS_TLS_DTPREL_LO1647
||
450
47
      
Type == R_MIPS_TLS_DTPREL3247
||
Type == R_MIPS_TLS_DTPREL6447
||
451
46
      Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
452
46
      Type == R_MICROMIPS_TLS_DTPREL_LO16)
453
1
    Val -= 0x8000;
454
46
  else 
if (46
Type == R_MIPS_TLS_TPREL_HI16 || 46
Type == R_MIPS_TLS_TPREL_LO1646
||
455
46
           
Type == R_MIPS_TLS_TPREL3246
||
Type == R_MIPS_TLS_TPREL6446
||
456
45
           Type == R_MICROMIPS_TLS_TPREL_HI16 ||
457
45
           Type == R_MICROMIPS_TLS_TPREL_LO16)
458
1
    Val -= 0x7000;
459
47
  if (
ELFT::Is64Bits || 47
Config->MipsN32Abi0
)
460
47
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
461
47
  switch (Type) {
462
2
  case R_MIPS_32:
463
2
  case R_MIPS_GPREL32:
464
2
  case R_MIPS_TLS_DTPREL32:
465
2
  case R_MIPS_TLS_TPREL32:
466
2
    write32<E>(Loc, Val);
467
2
    break;
468
3
  case R_MIPS_64:
469
3
  case R_MIPS_TLS_DTPREL64:
470
3
  case R_MIPS_TLS_TPREL64:
471
3
    write64<E>(Loc, Val);
472
3
    break;
473
0
  case R_MIPS_26:
474
0
    writeRelocation<E>(Loc, Val, 26, 2);
475
0
    break;
476
0
  case R_MIPS_GOT16:
477
0
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
478
0
    // is updated addend (not a GOT index). In that case write high 16 bits
479
0
    // to store a correct addend value.
480
0
    if (
Config->Relocatable0
) {
481
0
      writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
482
0
    } else {
483
0
      checkInt<16>(Loc, Val, Type);
484
0
      writeRelocation<E>(Loc, Val, 16, 0);
485
0
    }
486
0
    break;
487
0
  case R_MICROMIPS_GOT16:
488
0
    if (
Config->Relocatable0
) {
489
0
      writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
490
0
    } else {
491
0
      checkInt<16>(Loc, Val, Type);
492
0
      writeMicroRelocation32<E>(Loc, Val, 16, 0);
493
0
    }
494
0
    break;
495
18
  case R_MIPS_GOT_DISP:
496
18
  case R_MIPS_GOT_PAGE:
497
18
  case R_MIPS_GPREL16:
498
18
  case R_MIPS_TLS_GD:
499
18
  case R_MIPS_TLS_LDM:
500
18
    checkInt<16>(Loc, Val, Type);
501
18
    LLVM_FALLTHROUGH;
502
28
  case R_MIPS_CALL16:
503
28
  case R_MIPS_CALL_LO16:
504
28
  case R_MIPS_GOT_LO16:
505
28
  case R_MIPS_GOT_OFST:
506
28
  case R_MIPS_LO16:
507
28
  case R_MIPS_PCLO16:
508
28
  case R_MIPS_TLS_DTPREL_LO16:
509
28
  case R_MIPS_TLS_GOTTPREL:
510
28
  case R_MIPS_TLS_TPREL_LO16:
511
28
    writeRelocation<E>(Loc, Val, 16, 0);
512
28
    break;
513
1
  case R_MICROMIPS_GOT_DISP:
514
1
  case R_MICROMIPS_GOT_PAGE:
515
1
  case R_MICROMIPS_GPREL16:
516
1
  case R_MICROMIPS_TLS_GD:
517
1
  case R_MICROMIPS_TLS_LDM:
518
1
    checkInt<16>(Loc, Val, Type);
519
1
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
520
1
    break;
521
2
  case R_MICROMIPS_CALL16:
522
2
  case R_MICROMIPS_CALL_LO16:
523
2
  case R_MICROMIPS_GOT_OFST:
524
2
  case R_MICROMIPS_LO16:
525
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
526
2
  case R_MICROMIPS_TLS_GOTTPREL:
527
2
  case R_MICROMIPS_TLS_TPREL_LO16:
528
2
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
529
2
    break;
530
0
  case R_MICROMIPS_GPREL7_S2:
531
0
    checkInt<7>(Loc, Val, Type);
532
0
    writeMicroRelocation32<E>(Loc, Val, 7, 2);
533
0
    break;
534
6
  case R_MIPS_CALL_HI16:
535
6
  case R_MIPS_GOT_HI16:
536
6
  case R_MIPS_HI16:
537
6
  case R_MIPS_PCHI16:
538
6
  case R_MIPS_TLS_DTPREL_HI16:
539
6
  case R_MIPS_TLS_TPREL_HI16:
540
6
    writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
541
6
    break;
542
0
  case R_MICROMIPS_CALL_HI16:
543
0
  case R_MICROMIPS_GOT_HI16:
544
0
  case R_MICROMIPS_HI16:
545
0
  case R_MICROMIPS_TLS_DTPREL_HI16:
546
0
  case R_MICROMIPS_TLS_TPREL_HI16:
547
0
    writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
548
0
    break;
549
2
  case R_MIPS_HIGHER:
550
2
    writeRelocation<E>(Loc, Val + 0x80008000, 16, 32);
551
2
    break;
552
2
  case R_MIPS_HIGHEST:
553
2
    writeRelocation<E>(Loc, Val + 0x800080008000, 16, 48);
554
2
    break;
555
0
  case R_MICROMIPS_HIGHER:
556
0
    writeMicroRelocation32<E>(Loc, Val + 0x80008000, 16, 32);
557
0
    break;
558
0
  case R_MICROMIPS_HIGHEST:
559
0
    writeMicroRelocation32<E>(Loc, Val + 0x800080008000, 16, 48);
560
0
    break;
561
0
  case R_MIPS_JALR:
562
0
  case R_MICROMIPS_JALR:
563
0
    // Ignore this optimization relocation for now
564
0
    break;
565
0
  case R_MIPS_PC16:
566
0
    checkAlignment<4>(Loc, Val, Type);
567
0
    checkInt<18>(Loc, Val, Type);
568
0
    writeRelocation<E>(Loc, Val, 16, 2);
569
0
    break;
570
0
  case R_MIPS_PC19_S2:
571
0
    checkAlignment<4>(Loc, Val, Type);
572
0
    checkInt<21>(Loc, Val, Type);
573
0
    writeRelocation<E>(Loc, Val, 19, 2);
574
0
    break;
575
0
  case R_MIPS_PC21_S2:
576
0
    checkAlignment<4>(Loc, Val, Type);
577
0
    checkInt<23>(Loc, Val, Type);
578
0
    writeRelocation<E>(Loc, Val, 21, 2);
579
0
    break;
580
0
  case R_MIPS_PC26_S2:
581
0
    checkAlignment<4>(Loc, Val, Type);
582
0
    checkInt<28>(Loc, Val, Type);
583
0
    writeRelocation<E>(Loc, Val, 26, 2);
584
0
    break;
585
1
  case R_MIPS_PC32:
586
1
    writeRelocation<E>(Loc, Val, 32, 0);
587
1
    break;
588
0
  case R_MICROMIPS_26_S1:
589
0
  case R_MICROMIPS_PC26_S1:
590
0
    checkInt<27>(Loc, Val, Type);
591
0
    writeMicroRelocation32<E>(Loc, Val, 26, 1);
592
0
    break;
593
0
  case R_MICROMIPS_PC7_S1:
594
0
    checkInt<8>(Loc, Val, Type);
595
0
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
596
0
    break;
597
0
  case R_MICROMIPS_PC10_S1:
598
0
    checkInt<11>(Loc, Val, Type);
599
0
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
600
0
    break;
601
0
  case R_MICROMIPS_PC16_S1:
602
0
    checkInt<17>(Loc, Val, Type);
603
0
    writeMicroRelocation32<E>(Loc, Val, 16, 1);
604
0
    break;
605
0
  case R_MICROMIPS_PC18_S3:
606
0
    checkInt<21>(Loc, Val, Type);
607
0
    writeMicroRelocation32<E>(Loc, Val, 18, 3);
608
0
    break;
609
0
  case R_MICROMIPS_PC19_S2:
610
0
    checkInt<21>(Loc, Val, Type);
611
0
    writeMicroRelocation32<E>(Loc, Val, 19, 2);
612
0
    break;
613
0
  case R_MICROMIPS_PC21_S1:
614
0
    checkInt<22>(Loc, Val, Type);
615
0
    writeMicroRelocation32<E>(Loc, Val, 21, 1);
616
0
    break;
617
0
  case R_MICROMIPS_PC23_S2:
618
0
    checkInt<25>(Loc, Val, Type);
619
0
    writeMicroRelocation32<E>(Loc, Val, 23, 2);
620
0
    break;
621
0
  default:
622
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
623
47
  }
624
47
}
625
626
template <class ELFT>
627
48
bool MIPS<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
628
24
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
629
48
         
Type == R_MICROMIPS_LO1622
||
Type == R_MICROMIPS_GOT_OFST22
;
630
48
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
627
5
bool MIPS<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
628
5
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
629
5
         
Type == R_MICROMIPS_LO163
||
Type == R_MICROMIPS_GOT_OFST3
;
630
5
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::usesOnlyLowPageBits(unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
627
38
bool MIPS<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
628
14
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
629
38
         
Type == R_MICROMIPS_LO1614
||
Type == R_MICROMIPS_GOT_OFST14
;
630
38
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
627
5
bool MIPS<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
628
5
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
629
5
         
Type == R_MICROMIPS_LO165
||
Type == R_MICROMIPS_GOT_OFST5
;
630
5
}
631
632
138
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
633
138
  static MIPS<ELFT> Target;
634
138
  return &Target;
635
138
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)0, true> >()
Line
Count
Source
632
28
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
633
28
  static MIPS<ELFT> Target;
634
28
  return &Target;
635
28
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)1, true> >()
Line
Count
Source
632
2
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
633
2
  static MIPS<ELFT> Target;
634
2
  return &Target;
635
2
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)1, false> >()
Line
Count
Source
632
14
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
633
14
  static MIPS<ELFT> Target;
634
14
  return &Target;
635
14
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)0, false> >()
Line
Count
Source
632
94
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
633
94
  static MIPS<ELFT> Target;
634
94
  return &Target;
635
94
}
636
637
template TargetInfo *elf::getMipsTargetInfo<ELF32LE>();
638
template TargetInfo *elf::getMipsTargetInfo<ELF32BE>();
639
template TargetInfo *elf::getMipsTargetInfo<ELF64LE>();
640
template TargetInfo *elf::getMipsTargetInfo<ELF64BE>();