Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/tools/lld/ELF/Arch/Mips.cpp
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Source (jump to first uncovered line)
1
//===- MIPS.cpp -----------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#include "Error.h"
11
#include "InputFiles.h"
12
#include "OutputSections.h"
13
#include "Symbols.h"
14
#include "SyntheticSections.h"
15
#include "Target.h"
16
#include "Thunks.h"
17
#include "llvm/Object/ELF.h"
18
#include "llvm/Support/Endian.h"
19
20
using namespace llvm;
21
using namespace llvm::object;
22
using namespace llvm::support::endian;
23
using namespace llvm::ELF;
24
using namespace lld;
25
using namespace lld::elf;
26
27
namespace {
28
template <class ELFT> class MIPS final : public TargetInfo {
29
public:
30
  MIPS();
31
  RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, const InputFile &File,
32
                     const uint8_t *Loc) const override;
33
  int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
34
  bool isPicRel(uint32_t Type) const override;
35
  uint32_t getDynRel(uint32_t Type) const override;
36
  void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
37
  void writePltHeader(uint8_t *Buf) const override;
38
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
39
                int32_t Index, unsigned RelOff) const override;
40
  bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File,
41
                  const SymbolBody &S) const override;
42
  void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
43
  bool usesOnlyLowPageBits(uint32_t Type) const override;
44
};
45
} // namespace
46
47
139
template <class ELFT> MIPS<ELFT>::MIPS() {
48
139
  GotPltHeaderEntriesNum = 2;
49
139
  DefaultMaxPageSize = 65536;
50
139
  GotEntrySize = sizeof(typename ELFT::uint);
51
139
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
139
  PltEntrySize = 16;
53
139
  PltHeaderSize = 32;
54
139
  CopyRel = R_MIPS_COPY;
55
139
  PltRel = R_MIPS_JUMP_SLOT;
56
139
  NeedsThunks = true;
57
139
  TrapInstr = 0xefefefef;
58
139
59
139
  if (
ELFT::Is64Bits139
) {
60
30
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
61
30
    TlsGotRel = R_MIPS_TLS_TPREL64;
62
30
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
63
30
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
64
139
  } else {
65
109
    RelativeRel = R_MIPS_REL32;
66
109
    TlsGotRel = R_MIPS_TLS_TPREL32;
67
109
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
68
109
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
69
109
  }
70
139
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::MIPS()
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Source
47
14
template <class ELFT> MIPS<ELFT>::MIPS() {
48
14
  GotPltHeaderEntriesNum = 2;
49
14
  DefaultMaxPageSize = 65536;
50
14
  GotEntrySize = sizeof(typename ELFT::uint);
51
14
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
14
  PltEntrySize = 16;
53
14
  PltHeaderSize = 32;
54
14
  CopyRel = R_MIPS_COPY;
55
14
  PltRel = R_MIPS_JUMP_SLOT;
56
14
  NeedsThunks = true;
57
14
  TrapInstr = 0xefefefef;
58
14
59
14
  if (
ELFT::Is64Bits14
) {
60
0
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
61
0
    TlsGotRel = R_MIPS_TLS_TPREL64;
62
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
63
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
64
14
  } else {
65
14
    RelativeRel = R_MIPS_REL32;
66
14
    TlsGotRel = R_MIPS_TLS_TPREL32;
67
14
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
68
14
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
69
14
  }
70
14
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::MIPS()
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Source
47
28
template <class ELFT> MIPS<ELFT>::MIPS() {
48
28
  GotPltHeaderEntriesNum = 2;
49
28
  DefaultMaxPageSize = 65536;
50
28
  GotEntrySize = sizeof(typename ELFT::uint);
51
28
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
28
  PltEntrySize = 16;
53
28
  PltHeaderSize = 32;
54
28
  CopyRel = R_MIPS_COPY;
55
28
  PltRel = R_MIPS_JUMP_SLOT;
56
28
  NeedsThunks = true;
57
28
  TrapInstr = 0xefefefef;
58
28
59
28
  if (
ELFT::Is64Bits28
) {
60
28
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
61
28
    TlsGotRel = R_MIPS_TLS_TPREL64;
62
28
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
63
28
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
64
28
  } else {
65
0
    RelativeRel = R_MIPS_REL32;
66
0
    TlsGotRel = R_MIPS_TLS_TPREL32;
67
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
68
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
69
0
  }
70
28
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::MIPS()
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Count
Source
47
2
template <class ELFT> MIPS<ELFT>::MIPS() {
48
2
  GotPltHeaderEntriesNum = 2;
49
2
  DefaultMaxPageSize = 65536;
50
2
  GotEntrySize = sizeof(typename ELFT::uint);
51
2
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
2
  PltEntrySize = 16;
53
2
  PltHeaderSize = 32;
54
2
  CopyRel = R_MIPS_COPY;
55
2
  PltRel = R_MIPS_JUMP_SLOT;
56
2
  NeedsThunks = true;
57
2
  TrapInstr = 0xefefefef;
58
2
59
2
  if (
ELFT::Is64Bits2
) {
60
2
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
61
2
    TlsGotRel = R_MIPS_TLS_TPREL64;
62
2
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
63
2
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
64
2
  } else {
65
0
    RelativeRel = R_MIPS_REL32;
66
0
    TlsGotRel = R_MIPS_TLS_TPREL32;
67
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
68
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
69
0
  }
70
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::MIPS()
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Source
47
95
template <class ELFT> MIPS<ELFT>::MIPS() {
48
95
  GotPltHeaderEntriesNum = 2;
49
95
  DefaultMaxPageSize = 65536;
50
95
  GotEntrySize = sizeof(typename ELFT::uint);
51
95
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
95
  PltEntrySize = 16;
53
95
  PltHeaderSize = 32;
54
95
  CopyRel = R_MIPS_COPY;
55
95
  PltRel = R_MIPS_JUMP_SLOT;
56
95
  NeedsThunks = true;
57
95
  TrapInstr = 0xefefefef;
58
95
59
95
  if (
ELFT::Is64Bits95
) {
60
0
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
61
0
    TlsGotRel = R_MIPS_TLS_TPREL64;
62
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
63
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
64
95
  } else {
65
95
    RelativeRel = R_MIPS_REL32;
66
95
    TlsGotRel = R_MIPS_TLS_TPREL32;
67
95
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
68
95
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
69
95
  }
70
95
}
71
72
template <class ELFT>
73
RelExpr MIPS<ELFT>::getRelExpr(uint32_t Type, const SymbolBody &S,
74
                               const InputFile &File,
75
294
                               const uint8_t *Loc) const {
76
294
  // See comment in the calculateMipsRelChain.
77
294
  if (
ELFT::Is64Bits || 294
Config->MipsN32Abi243
)
78
54
    Type &= 0xff;
79
294
  switch (Type) {
80
1
  case R_MIPS_JALR:
81
1
  case R_MICROMIPS_JALR:
82
1
    return R_HINT;
83
19
  case R_MIPS_GPREL16:
84
19
  case R_MIPS_GPREL32:
85
19
  case R_MICROMIPS_GPREL16:
86
19
  case R_MICROMIPS_GPREL7_S2:
87
19
    return R_MIPS_GOTREL;
88
52
  case R_MIPS_26:
89
52
  case R_MICROMIPS_26_S1:
90
52
    return R_PLT;
91
0
  case R_MICROMIPS_PC26_S1:
92
0
    return R_PLT_PC;
93
68
  case R_MIPS_HI16:
94
68
  case R_MIPS_LO16:
95
68
  case R_MIPS_HIGHER:
96
68
  case R_MIPS_HIGHEST:
97
68
  case R_MICROMIPS_HI16:
98
68
  case R_MICROMIPS_LO16:
99
68
  case R_MICROMIPS_HIGHER:
100
68
  case R_MICROMIPS_HIGHEST:
101
68
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
102
68
    // offset between start of function and 'gp' value which by default
103
68
    // equal to the start of .got section. In that case we consider these
104
68
    // relocations as relative.
105
68
    if (&S == ElfSym::MipsGpDisp)
106
20
      return R_MIPS_GOT_GP_PC;
107
48
    
if (48
&S == ElfSym::MipsLocalGp48
)
108
2
      return R_MIPS_GOT_GP;
109
46
    
LLVM_FALLTHROUGH46
;
110
79
  case R_MIPS_32:
111
79
  case R_MIPS_64:
112
79
  case R_MIPS_GOT_OFST:
113
79
  case R_MIPS_SUB:
114
79
  case R_MIPS_TLS_DTPREL_HI16:
115
79
  case R_MIPS_TLS_DTPREL_LO16:
116
79
  case R_MIPS_TLS_DTPREL32:
117
79
  case R_MIPS_TLS_DTPREL64:
118
79
  case R_MIPS_TLS_TPREL_HI16:
119
79
  case R_MIPS_TLS_TPREL_LO16:
120
79
  case R_MIPS_TLS_TPREL32:
121
79
  case R_MIPS_TLS_TPREL64:
122
79
  case R_MICROMIPS_GOT_OFST:
123
79
  case R_MICROMIPS_SUB:
124
79
  case R_MICROMIPS_TLS_DTPREL_HI16:
125
79
  case R_MICROMIPS_TLS_DTPREL_LO16:
126
79
  case R_MICROMIPS_TLS_TPREL_HI16:
127
79
  case R_MICROMIPS_TLS_TPREL_LO16:
128
79
    return R_ABS;
129
15
  case R_MIPS_PC32:
130
15
  case R_MIPS_PC16:
131
15
  case R_MIPS_PC19_S2:
132
15
  case R_MIPS_PC21_S2:
133
15
  case R_MIPS_PC26_S2:
134
15
  case R_MIPS_PCHI16:
135
15
  case R_MIPS_PCLO16:
136
15
  case R_MICROMIPS_PC7_S1:
137
15
  case R_MICROMIPS_PC10_S1:
138
15
  case R_MICROMIPS_PC16_S1:
139
15
  case R_MICROMIPS_PC18_S3:
140
15
  case R_MICROMIPS_PC19_S2:
141
15
  case R_MICROMIPS_PC23_S2:
142
15
  case R_MICROMIPS_PC21_S1:
143
15
    return R_PC;
144
38
  case R_MIPS_GOT16:
145
38
  case R_MICROMIPS_GOT16:
146
38
    if (S.isLocal())
147
13
      return R_MIPS_GOT_LOCAL_PAGE;
148
25
    
LLVM_FALLTHROUGH25
;
149
58
  case R_MIPS_CALL16:
150
58
  case R_MIPS_GOT_DISP:
151
58
  case R_MIPS_TLS_GOTTPREL:
152
58
  case R_MICROMIPS_CALL16:
153
58
  case R_MICROMIPS_GOT_DISP:
154
58
  case R_MICROMIPS_TLS_GOTTPREL:
155
58
    return R_MIPS_GOT_OFF;
156
16
  case R_MIPS_CALL_HI16:
157
16
  case R_MIPS_CALL_LO16:
158
16
  case R_MIPS_GOT_HI16:
159
16
  case R_MIPS_GOT_LO16:
160
16
  case R_MICROMIPS_CALL_HI16:
161
16
  case R_MICROMIPS_CALL_LO16:
162
16
  case R_MICROMIPS_GOT_HI16:
163
16
  case R_MICROMIPS_GOT_LO16:
164
16
    return R_MIPS_GOT_OFF32;
165
5
  case R_MIPS_GOT_PAGE:
166
5
  case R_MICROMIPS_GOT_PAGE:
167
5
    return R_MIPS_GOT_LOCAL_PAGE;
168
9
  case R_MIPS_TLS_GD:
169
9
  case R_MICROMIPS_TLS_GD:
170
9
    return R_MIPS_TLSGD;
171
5
  case R_MIPS_TLS_LDM:
172
5
  case R_MICROMIPS_TLS_LDM:
173
5
    return R_MIPS_TLSLD;
174
0
  case R_MIPS_NONE:
175
0
    return R_NONE;
176
0
  default:
177
0
    error("do not know how to handle relocation '" + toString(Type) + "' (" +
178
0
          Twine(Type) + ")");
179
0
    return R_HINT;
180
0
  }
181
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getRelExpr(unsigned int, lld::elf::SymbolBody const&, lld::elf::InputFile const&, unsigned char const*) const
Line
Count
Source
75
16
                               const uint8_t *Loc) const {
76
16
  // See comment in the calculateMipsRelChain.
77
16
  if (
ELFT::Is64Bits || 16
Config->MipsN32Abi16
)
78
0
    Type &= 0xff;
79
16
  switch (Type) {
80
1
  case R_MIPS_JALR:
81
1
  case R_MICROMIPS_JALR:
82
1
    return R_HINT;
83
0
  case R_MIPS_GPREL16:
84
0
  case R_MIPS_GPREL32:
85
0
  case R_MICROMIPS_GPREL16:
86
0
  case R_MICROMIPS_GPREL7_S2:
87
0
    return R_MIPS_GOTREL;
88
2
  case R_MIPS_26:
89
2
  case R_MICROMIPS_26_S1:
90
2
    return R_PLT;
91
0
  case R_MICROMIPS_PC26_S1:
92
0
    return R_PLT_PC;
93
2
  case R_MIPS_HI16:
94
2
  case R_MIPS_LO16:
95
2
  case R_MIPS_HIGHER:
96
2
  case R_MIPS_HIGHEST:
97
2
  case R_MICROMIPS_HI16:
98
2
  case R_MICROMIPS_LO16:
99
2
  case R_MICROMIPS_HIGHER:
100
2
  case R_MICROMIPS_HIGHEST:
101
2
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
102
2
    // offset between start of function and 'gp' value which by default
103
2
    // equal to the start of .got section. In that case we consider these
104
2
    // relocations as relative.
105
2
    if (&S == ElfSym::MipsGpDisp)
106
2
      return R_MIPS_GOT_GP_PC;
107
0
    
if (0
&S == ElfSym::MipsLocalGp0
)
108
0
      return R_MIPS_GOT_GP;
109
0
    
LLVM_FALLTHROUGH0
;
110
2
  case R_MIPS_32:
111
2
  case R_MIPS_64:
112
2
  case R_MIPS_GOT_OFST:
113
2
  case R_MIPS_SUB:
114
2
  case R_MIPS_TLS_DTPREL_HI16:
115
2
  case R_MIPS_TLS_DTPREL_LO16:
116
2
  case R_MIPS_TLS_DTPREL32:
117
2
  case R_MIPS_TLS_DTPREL64:
118
2
  case R_MIPS_TLS_TPREL_HI16:
119
2
  case R_MIPS_TLS_TPREL_LO16:
120
2
  case R_MIPS_TLS_TPREL32:
121
2
  case R_MIPS_TLS_TPREL64:
122
2
  case R_MICROMIPS_GOT_OFST:
123
2
  case R_MICROMIPS_SUB:
124
2
  case R_MICROMIPS_TLS_DTPREL_HI16:
125
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
126
2
  case R_MICROMIPS_TLS_TPREL_HI16:
127
2
  case R_MICROMIPS_TLS_TPREL_LO16:
128
2
    return R_ABS;
129
3
  case R_MIPS_PC32:
130
3
  case R_MIPS_PC16:
131
3
  case R_MIPS_PC19_S2:
132
3
  case R_MIPS_PC21_S2:
133
3
  case R_MIPS_PC26_S2:
134
3
  case R_MIPS_PCHI16:
135
3
  case R_MIPS_PCLO16:
136
3
  case R_MICROMIPS_PC7_S1:
137
3
  case R_MICROMIPS_PC10_S1:
138
3
  case R_MICROMIPS_PC16_S1:
139
3
  case R_MICROMIPS_PC18_S3:
140
3
  case R_MICROMIPS_PC19_S2:
141
3
  case R_MICROMIPS_PC23_S2:
142
3
  case R_MICROMIPS_PC21_S1:
143
3
    return R_PC;
144
5
  case R_MIPS_GOT16:
145
5
  case R_MICROMIPS_GOT16:
146
5
    if (S.isLocal())
147
0
      return R_MIPS_GOT_LOCAL_PAGE;
148
5
    
LLVM_FALLTHROUGH5
;
149
6
  case R_MIPS_CALL16:
150
6
  case R_MIPS_GOT_DISP:
151
6
  case R_MIPS_TLS_GOTTPREL:
152
6
  case R_MICROMIPS_CALL16:
153
6
  case R_MICROMIPS_GOT_DISP:
154
6
  case R_MICROMIPS_TLS_GOTTPREL:
155
6
    return R_MIPS_GOT_OFF;
156
0
  case R_MIPS_CALL_HI16:
157
0
  case R_MIPS_CALL_LO16:
158
0
  case R_MIPS_GOT_HI16:
159
0
  case R_MIPS_GOT_LO16:
160
0
  case R_MICROMIPS_CALL_HI16:
161
0
  case R_MICROMIPS_CALL_LO16:
162
0
  case R_MICROMIPS_GOT_HI16:
163
0
  case R_MICROMIPS_GOT_LO16:
164
0
    return R_MIPS_GOT_OFF32;
165
0
  case R_MIPS_GOT_PAGE:
166
0
  case R_MICROMIPS_GOT_PAGE:
167
0
    return R_MIPS_GOT_LOCAL_PAGE;
168
0
  case R_MIPS_TLS_GD:
169
0
  case R_MICROMIPS_TLS_GD:
170
0
    return R_MIPS_TLSGD;
171
0
  case R_MIPS_TLS_LDM:
172
0
  case R_MICROMIPS_TLS_LDM:
173
0
    return R_MIPS_TLSLD;
174
0
  case R_MIPS_NONE:
175
0
    return R_NONE;
176
0
  default:
177
0
    error("do not know how to handle relocation '" + toString(Type) + "' (" +
178
0
          Twine(Type) + ")");
179
0
    return R_HINT;
180
0
  }
181
0
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getRelExpr(unsigned int, lld::elf::SymbolBody const&, lld::elf::InputFile const&, unsigned char const*) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getRelExpr(unsigned int, lld::elf::SymbolBody const&, lld::elf::InputFile const&, unsigned char const*) const
Line
Count
Source
75
51
                               const uint8_t *Loc) const {
76
51
  // See comment in the calculateMipsRelChain.
77
51
  if (
ELFT::Is64Bits || 51
Config->MipsN32Abi0
)
78
51
    Type &= 0xff;
79
51
  switch (Type) {
80
0
  case R_MIPS_JALR:
81
0
  case R_MICROMIPS_JALR:
82
0
    return R_HINT;
83
10
  case R_MIPS_GPREL16:
84
10
  case R_MIPS_GPREL32:
85
10
  case R_MICROMIPS_GPREL16:
86
10
  case R_MICROMIPS_GPREL7_S2:
87
10
    return R_MIPS_GOTREL;
88
0
  case R_MIPS_26:
89
0
  case R_MICROMIPS_26_S1:
90
0
    return R_PLT;
91
0
  case R_MICROMIPS_PC26_S1:
92
0
    return R_PLT_PC;
93
4
  case R_MIPS_HI16:
94
4
  case R_MIPS_LO16:
95
4
  case R_MIPS_HIGHER:
96
4
  case R_MIPS_HIGHEST:
97
4
  case R_MICROMIPS_HI16:
98
4
  case R_MICROMIPS_LO16:
99
4
  case R_MICROMIPS_HIGHER:
100
4
  case R_MICROMIPS_HIGHEST:
101
4
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
102
4
    // offset between start of function and 'gp' value which by default
103
4
    // equal to the start of .got section. In that case we consider these
104
4
    // relocations as relative.
105
4
    if (&S == ElfSym::MipsGpDisp)
106
0
      return R_MIPS_GOT_GP_PC;
107
4
    
if (4
&S == ElfSym::MipsLocalGp4
)
108
0
      return R_MIPS_GOT_GP;
109
4
    
LLVM_FALLTHROUGH4
;
110
15
  case R_MIPS_32:
111
15
  case R_MIPS_64:
112
15
  case R_MIPS_GOT_OFST:
113
15
  case R_MIPS_SUB:
114
15
  case R_MIPS_TLS_DTPREL_HI16:
115
15
  case R_MIPS_TLS_DTPREL_LO16:
116
15
  case R_MIPS_TLS_DTPREL32:
117
15
  case R_MIPS_TLS_DTPREL64:
118
15
  case R_MIPS_TLS_TPREL_HI16:
119
15
  case R_MIPS_TLS_TPREL_LO16:
120
15
  case R_MIPS_TLS_TPREL32:
121
15
  case R_MIPS_TLS_TPREL64:
122
15
  case R_MICROMIPS_GOT_OFST:
123
15
  case R_MICROMIPS_SUB:
124
15
  case R_MICROMIPS_TLS_DTPREL_HI16:
125
15
  case R_MICROMIPS_TLS_DTPREL_LO16:
126
15
  case R_MICROMIPS_TLS_TPREL_HI16:
127
15
  case R_MICROMIPS_TLS_TPREL_LO16:
128
15
    return R_ABS;
129
1
  case R_MIPS_PC32:
130
1
  case R_MIPS_PC16:
131
1
  case R_MIPS_PC19_S2:
132
1
  case R_MIPS_PC21_S2:
133
1
  case R_MIPS_PC26_S2:
134
1
  case R_MIPS_PCHI16:
135
1
  case R_MIPS_PCLO16:
136
1
  case R_MICROMIPS_PC7_S1:
137
1
  case R_MICROMIPS_PC10_S1:
138
1
  case R_MICROMIPS_PC16_S1:
139
1
  case R_MICROMIPS_PC18_S3:
140
1
  case R_MICROMIPS_PC19_S2:
141
1
  case R_MICROMIPS_PC23_S2:
142
1
  case R_MICROMIPS_PC21_S1:
143
1
    return R_PC;
144
0
  case R_MIPS_GOT16:
145
0
  case R_MICROMIPS_GOT16:
146
0
    if (S.isLocal())
147
0
      return R_MIPS_GOT_LOCAL_PAGE;
148
0
    
LLVM_FALLTHROUGH0
;
149
14
  case R_MIPS_CALL16:
150
14
  case R_MIPS_GOT_DISP:
151
14
  case R_MIPS_TLS_GOTTPREL:
152
14
  case R_MICROMIPS_CALL16:
153
14
  case R_MICROMIPS_GOT_DISP:
154
14
  case R_MICROMIPS_TLS_GOTTPREL:
155
14
    return R_MIPS_GOT_OFF;
156
0
  case R_MIPS_CALL_HI16:
157
0
  case R_MIPS_CALL_LO16:
158
0
  case R_MIPS_GOT_HI16:
159
0
  case R_MIPS_GOT_LO16:
160
0
  case R_MICROMIPS_CALL_HI16:
161
0
  case R_MICROMIPS_CALL_LO16:
162
0
  case R_MICROMIPS_GOT_HI16:
163
0
  case R_MICROMIPS_GOT_LO16:
164
0
    return R_MIPS_GOT_OFF32;
165
5
  case R_MIPS_GOT_PAGE:
166
5
  case R_MICROMIPS_GOT_PAGE:
167
5
    return R_MIPS_GOT_LOCAL_PAGE;
168
4
  case R_MIPS_TLS_GD:
169
4
  case R_MICROMIPS_TLS_GD:
170
4
    return R_MIPS_TLSGD;
171
2
  case R_MIPS_TLS_LDM:
172
2
  case R_MICROMIPS_TLS_LDM:
173
2
    return R_MIPS_TLSLD;
174
0
  case R_MIPS_NONE:
175
0
    return R_NONE;
176
0
  default:
177
0
    error("do not know how to handle relocation '" + toString(Type) + "' (" +
178
0
          Twine(Type) + ")");
179
0
    return R_HINT;
180
0
  }
181
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getRelExpr(unsigned int, lld::elf::SymbolBody const&, lld::elf::InputFile const&, unsigned char const*) const
Line
Count
Source
75
227
                               const uint8_t *Loc) const {
76
227
  // See comment in the calculateMipsRelChain.
77
227
  if (
ELFT::Is64Bits || 227
Config->MipsN32Abi227
)
78
3
    Type &= 0xff;
79
227
  switch (Type) {
80
0
  case R_MIPS_JALR:
81
0
  case R_MICROMIPS_JALR:
82
0
    return R_HINT;
83
9
  case R_MIPS_GPREL16:
84
9
  case R_MIPS_GPREL32:
85
9
  case R_MICROMIPS_GPREL16:
86
9
  case R_MICROMIPS_GPREL7_S2:
87
9
    return R_MIPS_GOTREL;
88
50
  case R_MIPS_26:
89
50
  case R_MICROMIPS_26_S1:
90
50
    return R_PLT;
91
0
  case R_MICROMIPS_PC26_S1:
92
0
    return R_PLT_PC;
93
62
  case R_MIPS_HI16:
94
62
  case R_MIPS_LO16:
95
62
  case R_MIPS_HIGHER:
96
62
  case R_MIPS_HIGHEST:
97
62
  case R_MICROMIPS_HI16:
98
62
  case R_MICROMIPS_LO16:
99
62
  case R_MICROMIPS_HIGHER:
100
62
  case R_MICROMIPS_HIGHEST:
101
62
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
102
62
    // offset between start of function and 'gp' value which by default
103
62
    // equal to the start of .got section. In that case we consider these
104
62
    // relocations as relative.
105
62
    if (&S == ElfSym::MipsGpDisp)
106
18
      return R_MIPS_GOT_GP_PC;
107
44
    
if (44
&S == ElfSym::MipsLocalGp44
)
108
2
      return R_MIPS_GOT_GP;
109
42
    
LLVM_FALLTHROUGH42
;
110
62
  case R_MIPS_32:
111
62
  case R_MIPS_64:
112
62
  case R_MIPS_GOT_OFST:
113
62
  case R_MIPS_SUB:
114
62
  case R_MIPS_TLS_DTPREL_HI16:
115
62
  case R_MIPS_TLS_DTPREL_LO16:
116
62
  case R_MIPS_TLS_DTPREL32:
117
62
  case R_MIPS_TLS_DTPREL64:
118
62
  case R_MIPS_TLS_TPREL_HI16:
119
62
  case R_MIPS_TLS_TPREL_LO16:
120
62
  case R_MIPS_TLS_TPREL32:
121
62
  case R_MIPS_TLS_TPREL64:
122
62
  case R_MICROMIPS_GOT_OFST:
123
62
  case R_MICROMIPS_SUB:
124
62
  case R_MICROMIPS_TLS_DTPREL_HI16:
125
62
  case R_MICROMIPS_TLS_DTPREL_LO16:
126
62
  case R_MICROMIPS_TLS_TPREL_HI16:
127
62
  case R_MICROMIPS_TLS_TPREL_LO16:
128
62
    return R_ABS;
129
11
  case R_MIPS_PC32:
130
11
  case R_MIPS_PC16:
131
11
  case R_MIPS_PC19_S2:
132
11
  case R_MIPS_PC21_S2:
133
11
  case R_MIPS_PC26_S2:
134
11
  case R_MIPS_PCHI16:
135
11
  case R_MIPS_PCLO16:
136
11
  case R_MICROMIPS_PC7_S1:
137
11
  case R_MICROMIPS_PC10_S1:
138
11
  case R_MICROMIPS_PC16_S1:
139
11
  case R_MICROMIPS_PC18_S3:
140
11
  case R_MICROMIPS_PC19_S2:
141
11
  case R_MICROMIPS_PC23_S2:
142
11
  case R_MICROMIPS_PC21_S1:
143
11
    return R_PC;
144
33
  case R_MIPS_GOT16:
145
33
  case R_MICROMIPS_GOT16:
146
33
    if (S.isLocal())
147
13
      return R_MIPS_GOT_LOCAL_PAGE;
148
20
    
LLVM_FALLTHROUGH20
;
149
38
  case R_MIPS_CALL16:
150
38
  case R_MIPS_GOT_DISP:
151
38
  case R_MIPS_TLS_GOTTPREL:
152
38
  case R_MICROMIPS_CALL16:
153
38
  case R_MICROMIPS_GOT_DISP:
154
38
  case R_MICROMIPS_TLS_GOTTPREL:
155
38
    return R_MIPS_GOT_OFF;
156
16
  case R_MIPS_CALL_HI16:
157
16
  case R_MIPS_CALL_LO16:
158
16
  case R_MIPS_GOT_HI16:
159
16
  case R_MIPS_GOT_LO16:
160
16
  case R_MICROMIPS_CALL_HI16:
161
16
  case R_MICROMIPS_CALL_LO16:
162
16
  case R_MICROMIPS_GOT_HI16:
163
16
  case R_MICROMIPS_GOT_LO16:
164
16
    return R_MIPS_GOT_OFF32;
165
0
  case R_MIPS_GOT_PAGE:
166
0
  case R_MICROMIPS_GOT_PAGE:
167
0
    return R_MIPS_GOT_LOCAL_PAGE;
168
5
  case R_MIPS_TLS_GD:
169
5
  case R_MICROMIPS_TLS_GD:
170
5
    return R_MIPS_TLSGD;
171
3
  case R_MIPS_TLS_LDM:
172
3
  case R_MICROMIPS_TLS_LDM:
173
3
    return R_MIPS_TLSLD;
174
0
  case R_MIPS_NONE:
175
0
    return R_NONE;
176
0
  default:
177
0
    error("do not know how to handle relocation '" + toString(Type) + "' (" +
178
0
          Twine(Type) + ")");
179
0
    return R_HINT;
180
0
  }
181
0
}
182
183
3
template <class ELFT> bool MIPS<ELFT>::isPicRel(uint32_t Type) const {
184
1
  return Type == R_MIPS_32 || Type == R_MIPS_64;
185
3
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::isPicRel(unsigned int) const
Line
Count
Source
183
1
template <class ELFT> bool MIPS<ELFT>::isPicRel(uint32_t Type) const {
184
0
  return Type == R_MIPS_32 || Type == R_MIPS_64;
185
1
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::isPicRel(unsigned int) const
Line
Count
Source
183
1
template <class ELFT> bool MIPS<ELFT>::isPicRel(uint32_t Type) const {
184
0
  return Type == R_MIPS_32 || Type == R_MIPS_64;
185
1
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::isPicRel(unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::isPicRel(unsigned int) const
Line
Count
Source
183
1
template <class ELFT> bool MIPS<ELFT>::isPicRel(uint32_t Type) const {
184
1
  return Type == R_MIPS_32 || Type == R_MIPS_64;
185
1
}
186
187
3
template <class ELFT> uint32_t MIPS<ELFT>::getDynRel(uint32_t Type) const {
188
3
  return RelativeRel;
189
3
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getDynRel(unsigned int) const
Line
Count
Source
187
1
template <class ELFT> uint32_t MIPS<ELFT>::getDynRel(uint32_t Type) const {
188
1
  return RelativeRel;
189
1
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getDynRel(unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getDynRel(unsigned int) const
Line
Count
Source
187
1
template <class ELFT> uint32_t MIPS<ELFT>::getDynRel(uint32_t Type) const {
188
1
  return RelativeRel;
189
1
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getDynRel(unsigned int) const
Line
Count
Source
187
1
template <class ELFT> uint32_t MIPS<ELFT>::getDynRel(uint32_t Type) const {
188
1
  return RelativeRel;
189
1
}
190
191
template <class ELFT>
192
10
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
193
10
  write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA());
194
10
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writeGotPlt(unsigned char*, lld::elf::SymbolBody const&) const
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writeGotPlt(unsigned char*, lld::elf::SymbolBody const&) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writeGotPlt(unsigned char*, lld::elf::SymbolBody const&) const
Line
Count
Source
192
2
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
193
2
  write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA());
194
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writeGotPlt(unsigned char*, lld::elf::SymbolBody const&) const
Line
Count
Source
192
8
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
193
8
  write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA());
194
8
}
195
196
17
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
197
17
  // The major opcode of a microMIPS instruction needs to appear
198
17
  // in the first 16-bit word (lowest address) for efficient hardware
199
17
  // decode so that it knows if the instruction is 16-bit or 32-bit
200
17
  // as early as possible. To do so, little-endian binaries keep 16-bit
201
17
  // words in a big-endian order. That is why we have to swap these
202
17
  // words to get a correct value.
203
17
  uint32_t V = read32<E>(Loc);
204
17
  if (E == support::little)
205
7
    return (V << 16) | (V >> 16);
206
10
  return V;
207
10
}
Mips.cpp:unsigned int readShuffle<(llvm::support::endianness)1>(unsigned char const*)
Line
Count
Source
196
7
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
197
7
  // The major opcode of a microMIPS instruction needs to appear
198
7
  // in the first 16-bit word (lowest address) for efficient hardware
199
7
  // decode so that it knows if the instruction is 16-bit or 32-bit
200
7
  // as early as possible. To do so, little-endian binaries keep 16-bit
201
7
  // words in a big-endian order. That is why we have to swap these
202
7
  // words to get a correct value.
203
7
  uint32_t V = read32<E>(Loc);
204
7
  if (E == support::little)
205
7
    return (V << 16) | (V >> 16);
206
0
  return V;
207
0
}
Mips.cpp:unsigned int readShuffle<(llvm::support::endianness)0>(unsigned char const*)
Line
Count
Source
196
10
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
197
10
  // The major opcode of a microMIPS instruction needs to appear
198
10
  // in the first 16-bit word (lowest address) for efficient hardware
199
10
  // decode so that it knows if the instruction is 16-bit or 32-bit
200
10
  // as early as possible. To do so, little-endian binaries keep 16-bit
201
10
  // words in a big-endian order. That is why we have to swap these
202
10
  // words to get a correct value.
203
10
  uint32_t V = read32<E>(Loc);
204
10
  if (E == support::little)
205
0
    return (V << 16) | (V >> 16);
206
10
  return V;
207
10
}
208
209
template <endianness E>
210
static void writeRelocation(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
211
355
                            uint8_t Shift) {
212
355
  uint32_t Instr = read32<E>(Loc);
213
355
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
214
355
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
215
355
  write32<E>(Loc, Data);
216
355
}
Mips.cpp:void writeRelocation<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
211
15
                            uint8_t Shift) {
212
15
  uint32_t Instr = read32<E>(Loc);
213
15
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
214
15
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
215
15
  write32<E>(Loc, Data);
216
15
}
Mips.cpp:void writeRelocation<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
211
340
                            uint8_t Shift) {
212
340
  uint32_t Instr = read32<E>(Loc);
213
340
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
214
340
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
215
340
  write32<E>(Loc, Data);
216
340
}
217
218
template <endianness E>
219
static void writeMicroRelocation32(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
220
28
                                   uint8_t Shift) {
221
28
  // See comments in readShuffle for purpose of this code.
222
28
  uint16_t *Words = (uint16_t *)Loc;
223
28
  if (E == support::little)
224
11
    std::swap(Words[0], Words[1]);
225
28
226
28
  writeRelocation<E>(Loc, V, BitsSize, Shift);
227
28
228
28
  if (E == support::little)
229
11
    std::swap(Words[0], Words[1]);
230
28
}
Mips.cpp:void writeMicroRelocation32<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
220
17
                                   uint8_t Shift) {
221
17
  // See comments in readShuffle for purpose of this code.
222
17
  uint16_t *Words = (uint16_t *)Loc;
223
17
  if (E == support::little)
224
0
    std::swap(Words[0], Words[1]);
225
17
226
17
  writeRelocation<E>(Loc, V, BitsSize, Shift);
227
17
228
17
  if (E == support::little)
229
0
    std::swap(Words[0], Words[1]);
230
17
}
Mips.cpp:void writeMicroRelocation32<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
220
11
                                   uint8_t Shift) {
221
11
  // See comments in readShuffle for purpose of this code.
222
11
  uint16_t *Words = (uint16_t *)Loc;
223
11
  if (E == support::little)
224
11
    std::swap(Words[0], Words[1]);
225
11
226
11
  writeRelocation<E>(Loc, V, BitsSize, Shift);
227
11
228
11
  if (E == support::little)
229
11
    std::swap(Words[0], Words[1]);
230
11
}
231
232
template <endianness E>
233
static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
234
4
                                   uint8_t Shift) {
235
4
  uint16_t Instr = read16<E>(Loc);
236
4
  uint16_t Mask = 0xffff >> (16 - BitsSize);
237
4
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
238
4
  write16<E>(Loc, Data);
239
4
}
Mips.cpp:void writeMicroRelocation16<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
234
2
                                   uint8_t Shift) {
235
2
  uint16_t Instr = read16<E>(Loc);
236
2
  uint16_t Mask = 0xffff >> (16 - BitsSize);
237
2
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
238
2
  write16<E>(Loc, Data);
239
2
}
Mips.cpp:void writeMicroRelocation16<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
234
2
                                   uint8_t Shift) {
235
2
  uint16_t Instr = read16<E>(Loc);
236
2
  uint16_t Mask = 0xffff >> (16 - BitsSize);
237
2
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
238
2
  write16<E>(Loc, Data);
239
2
}
240
241
18
template <class ELFT> static bool isMicroMips() {
242
18
  // FIXME (simon): This code does not support the case when both
243
18
  // microMIPS and MIPS object files are linked together.
244
18
  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
245
18
  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH_ASE;
246
18
  return Arch == EF_MIPS_MICROMIPS;
247
18
}
Unexecuted instantiation: Mips.cpp:bool isMicroMips<llvm::object::ELFType<(llvm::support::endianness)1, true> >()
Unexecuted instantiation: Mips.cpp:bool isMicroMips<llvm::object::ELFType<(llvm::support::endianness)0, true> >()
Mips.cpp:bool isMicroMips<llvm::object::ELFType<(llvm::support::endianness)1, false> >()
Line
Count
Source
241
4
template <class ELFT> static bool isMicroMips() {
242
4
  // FIXME (simon): This code does not support the case when both
243
4
  // microMIPS and MIPS object files are linked together.
244
4
  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
245
4
  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH_ASE;
246
4
  return Arch == EF_MIPS_MICROMIPS;
247
4
}
Mips.cpp:bool isMicroMips<llvm::object::ELFType<(llvm::support::endianness)0, false> >()
Line
Count
Source
241
14
template <class ELFT> static bool isMicroMips() {
242
14
  // FIXME (simon): This code does not support the case when both
243
14
  // microMIPS and MIPS object files are linked together.
244
14
  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
245
14
  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH_ASE;
246
14
  return Arch == EF_MIPS_MICROMIPS;
247
14
}
248
249
18
template <class ELFT> static bool isMipsR6() {
250
18
  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
251
18
  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH;
252
11
  return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6;
253
18
}
Mips.cpp:bool isMipsR6<llvm::object::ELFType<(llvm::support::endianness)1, false> >()
Line
Count
Source
249
6
template <class ELFT> static bool isMipsR6() {
250
6
  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
251
6
  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH;
252
3
  return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6;
253
6
}
Unexecuted instantiation: Mips.cpp:bool isMipsR6<llvm::object::ELFType<(llvm::support::endianness)1, true> >()
Mips.cpp:bool isMipsR6<llvm::object::ELFType<(llvm::support::endianness)0, false> >()
Line
Count
Source
249
12
template <class ELFT> static bool isMipsR6() {
250
12
  const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
251
12
  uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH;
252
8
  return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6;
253
12
}
Unexecuted instantiation: Mips.cpp:bool isMipsR6<llvm::object::ELFType<(llvm::support::endianness)0, true> >()
254
255
8
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
256
8
  const endianness E = ELFT::TargetEndianness;
257
8
  if (
isMicroMips<ELFT>()8
) {
258
4
    uint64_t GotPlt = In<ELFT>::GotPlt->getVA();
259
4
    uint64_t Plt = In<ELFT>::Plt->getVA();
260
4
    // Overwrite trap instructions written by Writer::writeTrapInstr.
261
4
    memset(Buf, 0, PltHeaderSize);
262
4
263
4
    write16<E>(Buf, isMipsR6<ELFT>() ? 
0x78602
:
0x79802
);
264
4
                                    // addiupc v1, (GOTPLT) - .
265
4
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
266
4
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
267
4
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
268
4
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
269
4
    write16<E>(Buf + 14, 0xfffe);
270
4
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
271
4
    if (
isMipsR6<ELFT>()4
) {
272
2
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
273
2
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
274
2
      write16<E>(Buf + 22, 0x0c00); // nop
275
2
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
276
4
    } else {
277
2
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
278
2
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
279
2
      write16<E>(Buf + 22, 0x0c00); // nop
280
2
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
281
2
    }
282
4
    return;
283
4
  }
284
4
285
4
  
if (4
Config->MipsN32Abi4
) {
286
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
287
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
288
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
289
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
290
4
  } else {
291
4
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
292
4
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
293
4
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
294
4
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
295
4
  }
296
8
297
8
  write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
298
8
  write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
299
8
  write32<E>(Buf + 24, 0x0320f809); // jalr  $25
300
8
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
301
8
302
8
  uint64_t GotPlt = InX::GotPlt->getVA();
303
8
  writeRelocation<E>(Buf, GotPlt + 0x8000, 16, 16);
304
8
  writeRelocation<E>(Buf + 4, GotPlt, 16, 0);
305
8
  writeRelocation<E>(Buf + 8, GotPlt, 16, 0);
306
8
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writePltHeader(unsigned char*) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writePltHeader(unsigned char*) const
Line
Count
Source
255
6
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
256
6
  const endianness E = ELFT::TargetEndianness;
257
6
  if (
isMicroMips<ELFT>()6
) {
258
2
    uint64_t GotPlt = In<ELFT>::GotPlt->getVA();
259
2
    uint64_t Plt = In<ELFT>::Plt->getVA();
260
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
261
2
    memset(Buf, 0, PltHeaderSize);
262
2
263
2
    write16<E>(Buf, isMipsR6<ELFT>() ? 
0x78601
:
0x79801
);
264
2
                                    // addiupc v1, (GOTPLT) - .
265
2
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
266
2
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
267
2
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
268
2
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
269
2
    write16<E>(Buf + 14, 0xfffe);
270
2
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
271
2
    if (
isMipsR6<ELFT>()2
) {
272
1
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
273
1
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
274
1
      write16<E>(Buf + 22, 0x0c00); // nop
275
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
276
2
    } else {
277
1
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
278
1
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
279
1
      write16<E>(Buf + 22, 0x0c00); // nop
280
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
281
1
    }
282
2
    return;
283
2
  }
284
4
285
4
  
if (4
Config->MipsN32Abi4
) {
286
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
287
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
288
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
289
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
290
4
  } else {
291
4
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
292
4
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
293
4
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
294
4
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
295
4
  }
296
6
297
6
  write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
298
6
  write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
299
6
  write32<E>(Buf + 24, 0x0320f809); // jalr  $25
300
6
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
301
6
302
6
  uint64_t GotPlt = InX::GotPlt->getVA();
303
6
  writeRelocation<E>(Buf, GotPlt + 0x8000, 16, 16);
304
6
  writeRelocation<E>(Buf + 4, GotPlt, 16, 0);
305
6
  writeRelocation<E>(Buf + 8, GotPlt, 16, 0);
306
6
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writePltHeader(unsigned char*) const
Line
Count
Source
255
2
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
256
2
  const endianness E = ELFT::TargetEndianness;
257
2
  if (
isMicroMips<ELFT>()2
) {
258
2
    uint64_t GotPlt = In<ELFT>::GotPlt->getVA();
259
2
    uint64_t Plt = In<ELFT>::Plt->getVA();
260
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
261
2
    memset(Buf, 0, PltHeaderSize);
262
2
263
2
    write16<E>(Buf, isMipsR6<ELFT>() ? 
0x78601
:
0x79801
);
264
2
                                    // addiupc v1, (GOTPLT) - .
265
2
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
266
2
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
267
2
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
268
2
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
269
2
    write16<E>(Buf + 14, 0xfffe);
270
2
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
271
2
    if (
isMipsR6<ELFT>()2
) {
272
1
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
273
1
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
274
1
      write16<E>(Buf + 22, 0x0c00); // nop
275
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
276
2
    } else {
277
1
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
278
1
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
279
1
      write16<E>(Buf + 22, 0x0c00); // nop
280
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
281
1
    }
282
2
    return;
283
2
  }
284
0
285
0
  
if (0
Config->MipsN32Abi0
) {
286
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
287
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
288
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
289
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
290
0
  } else {
291
0
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
292
0
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
293
0
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
294
0
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
295
0
  }
296
2
297
2
  write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
298
2
  write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
299
2
  write32<E>(Buf + 24, 0x0320f809); // jalr  $25
300
2
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
301
2
302
2
  uint64_t GotPlt = InX::GotPlt->getVA();
303
2
  writeRelocation<E>(Buf, GotPlt + 0x8000, 16, 16);
304
2
  writeRelocation<E>(Buf + 4, GotPlt, 16, 0);
305
2
  writeRelocation<E>(Buf + 8, GotPlt, 16, 0);
306
2
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writePltHeader(unsigned char*) const
307
308
template <class ELFT>
309
void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
310
                          uint64_t PltEntryAddr, int32_t Index,
311
10
                          unsigned RelOff) const {
312
10
  const endianness E = ELFT::TargetEndianness;
313
10
  if (
isMicroMips<ELFT>()10
) {
314
4
    // Overwrite trap instructions written by Writer::writeTrapInstr.
315
4
    memset(Buf, 0, PltEntrySize);
316
4
317
4
    if (
isMipsR6<ELFT>()4
) {
318
2
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
319
2
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
320
2
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
321
2
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
322
2
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
323
4
    } else {
324
2
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
325
2
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
326
2
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
327
2
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
328
2
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
329
2
    }
330
4
    return;
331
4
  }
332
6
333
6
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
334
6
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
335
6
                                   // jr    $25
336
6
  write32<E>(Buf + 8, isMipsR6<ELFT>() ? 
0x032000091
:
0x032000085
);
337
10
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
338
10
  writeRelocation<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
339
10
  writeRelocation<E>(Buf + 4, GotPltEntryAddr, 16, 0);
340
10
  writeRelocation<E>(Buf + 12, GotPltEntryAddr, 16, 0);
341
10
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
311
8
                          unsigned RelOff) const {
312
8
  const endianness E = ELFT::TargetEndianness;
313
8
  if (
isMicroMips<ELFT>()8
) {
314
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
315
2
    memset(Buf, 0, PltEntrySize);
316
2
317
2
    if (
isMipsR6<ELFT>()2
) {
318
1
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
319
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
320
1
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
321
1
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
322
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
323
2
    } else {
324
1
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
325
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
326
1
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
327
1
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
328
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
329
1
    }
330
2
    return;
331
2
  }
332
6
333
6
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
334
6
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
335
6
                                   // jr    $25
336
6
  write32<E>(Buf + 8, isMipsR6<ELFT>() ? 
0x032000091
:
0x032000085
);
337
8
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
338
8
  writeRelocation<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
339
8
  writeRelocation<E>(Buf + 4, GotPltEntryAddr, 16, 0);
340
8
  writeRelocation<E>(Buf + 12, GotPltEntryAddr, 16, 0);
341
8
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
311
2
                          unsigned RelOff) const {
312
2
  const endianness E = ELFT::TargetEndianness;
313
2
  if (
isMicroMips<ELFT>()2
) {
314
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
315
2
    memset(Buf, 0, PltEntrySize);
316
2
317
2
    if (
isMipsR6<ELFT>()2
) {
318
1
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
319
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
320
1
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
321
1
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
322
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
323
2
    } else {
324
1
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
325
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
326
1
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
327
1
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
328
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
329
1
    }
330
2
    return;
331
2
  }
332
0
333
0
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
334
0
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
335
0
                                   // jr    $25
336
0
  write32<E>(Buf + 8, isMipsR6<ELFT>() ? 
0x032000090
:
0x032000080
);
337
2
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
338
2
  writeRelocation<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
339
2
  writeRelocation<E>(Buf + 4, GotPltEntryAddr, 16, 0);
340
2
  writeRelocation<E>(Buf + 12, GotPltEntryAddr, 16, 0);
341
2
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
342
343
template <class ELFT>
344
bool MIPS<ELFT>::needsThunk(RelExpr Expr, uint32_t Type, const InputFile *File,
345
269
                            const SymbolBody &S) const {
346
269
  // Any MIPS PIC code function is invoked with its address in register $t9.
347
269
  // So if we have a branch instruction from non-PIC code to the PIC one
348
269
  // we cannot make the jump directly and need to create a small stubs
349
269
  // to save the target function address.
350
269
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
351
269
  if (
Type != R_MIPS_26 && 269
Type != R_MICROMIPS_26_S1214
&&
352
210
      Type != R_MICROMIPS_PC26_S1)
353
210
    return false;
354
59
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
355
59
  if (!F)
356
0
    return false;
357
59
  // If current file has PIC code, LA25 stub is not required.
358
59
  
if (59
F->getObj().getHeader()->e_flags & EF_MIPS_PIC59
)
359
0
    return false;
360
59
  auto *D = dyn_cast<DefinedRegular>(&S);
361
59
  // LA25 is required if target file has PIC code
362
59
  // or target symbol is a PIC symbol.
363
52
  return D && D->isMipsPIC<ELFT>();
364
269
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, lld::elf::SymbolBody const&) const
Line
Count
Source
345
214
                            const SymbolBody &S) const {
346
214
  // Any MIPS PIC code function is invoked with its address in register $t9.
347
214
  // So if we have a branch instruction from non-PIC code to the PIC one
348
214
  // we cannot make the jump directly and need to create a small stubs
349
214
  // to save the target function address.
350
214
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
351
214
  if (
Type != R_MIPS_26 && 214
Type != R_MICROMIPS_26_S1159
&&
352
157
      Type != R_MICROMIPS_PC26_S1)
353
157
    return false;
354
57
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
355
57
  if (!F)
356
0
    return false;
357
57
  // If current file has PIC code, LA25 stub is not required.
358
57
  
if (57
F->getObj().getHeader()->e_flags & EF_MIPS_PIC57
)
359
0
    return false;
360
57
  auto *D = dyn_cast<DefinedRegular>(&S);
361
57
  // LA25 is required if target file has PIC code
362
57
  // or target symbol is a PIC symbol.
363
52
  return D && D->isMipsPIC<ELFT>();
364
214
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, lld::elf::SymbolBody const&) const
Line
Count
Source
345
13
                            const SymbolBody &S) const {
346
13
  // Any MIPS PIC code function is invoked with its address in register $t9.
347
13
  // So if we have a branch instruction from non-PIC code to the PIC one
348
13
  // we cannot make the jump directly and need to create a small stubs
349
13
  // to save the target function address.
350
13
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
351
13
  if (
Type != R_MIPS_26 && 13
Type != R_MICROMIPS_26_S113
&&
352
11
      Type != R_MICROMIPS_PC26_S1)
353
11
    return false;
354
2
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
355
2
  if (!F)
356
0
    return false;
357
2
  // If current file has PIC code, LA25 stub is not required.
358
2
  
if (2
F->getObj().getHeader()->e_flags & EF_MIPS_PIC2
)
359
0
    return false;
360
2
  auto *D = dyn_cast<DefinedRegular>(&S);
361
2
  // LA25 is required if target file has PIC code
362
2
  // or target symbol is a PIC symbol.
363
0
  return D && D->isMipsPIC<ELFT>();
364
13
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, lld::elf::SymbolBody const&) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, lld::elf::SymbolBody const&) const
Line
Count
Source
345
42
                            const SymbolBody &S) const {
346
42
  // Any MIPS PIC code function is invoked with its address in register $t9.
347
42
  // So if we have a branch instruction from non-PIC code to the PIC one
348
42
  // we cannot make the jump directly and need to create a small stubs
349
42
  // to save the target function address.
350
42
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
351
42
  if (
Type != R_MIPS_26 && 42
Type != R_MICROMIPS_26_S142
&&
352
42
      Type != R_MICROMIPS_PC26_S1)
353
42
    return false;
354
0
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
355
0
  if (!F)
356
0
    return false;
357
0
  // If current file has PIC code, LA25 stub is not required.
358
0
  
if (0
F->getObj().getHeader()->e_flags & EF_MIPS_PIC0
)
359
0
    return false;
360
0
  auto *D = dyn_cast<DefinedRegular>(&S);
361
0
  // LA25 is required if target file has PIC code
362
0
  // or target symbol is a PIC symbol.
363
0
  return D && D->isMipsPIC<ELFT>();
364
42
}
365
366
template <class ELFT>
367
285
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const {
368
285
  const endianness E = ELFT::TargetEndianness;
369
285
  switch (Type) {
370
43
  default:
371
43
    return 0;
372
24
  case R_MIPS_32:
373
24
  case R_MIPS_GPREL32:
374
24
  case R_MIPS_TLS_DTPREL32:
375
24
  case R_MIPS_TLS_TPREL32:
376
24
    return SignExtend64<32>(read32<E>(Buf));
377
48
  case R_MIPS_26:
378
48
    // FIXME (simon): If the relocation target symbol is not a PLT entry
379
48
    // we should use another expression for calculation:
380
48
    // ((A << 2) | (P & 0xf0000000)) >> 2
381
48
    return SignExtend64<28>(read32<E>(Buf) << 2);
382
61
  case R_MIPS_GOT16:
383
61
  case R_MIPS_HI16:
384
61
  case R_MIPS_PCHI16:
385
61
    return SignExtend64<16>(read32<E>(Buf)) << 16;
386
82
  case R_MIPS_GPREL16:
387
82
  case R_MIPS_LO16:
388
82
  case R_MIPS_PCLO16:
389
82
  case R_MIPS_TLS_DTPREL_HI16:
390
82
  case R_MIPS_TLS_DTPREL_LO16:
391
82
  case R_MIPS_TLS_TPREL_HI16:
392
82
  case R_MIPS_TLS_TPREL_LO16:
393
82
    return SignExtend64<16>(read32<E>(Buf));
394
5
  case R_MICROMIPS_GOT16:
395
5
  case R_MICROMIPS_HI16:
396
5
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
397
6
  case R_MICROMIPS_GPREL16:
398
6
  case R_MICROMIPS_LO16:
399
6
  case R_MICROMIPS_TLS_DTPREL_HI16:
400
6
  case R_MICROMIPS_TLS_DTPREL_LO16:
401
6
  case R_MICROMIPS_TLS_TPREL_HI16:
402
6
  case R_MICROMIPS_TLS_TPREL_LO16:
403
6
    return SignExtend64<16>(readShuffle<E>(Buf));
404
0
  case R_MICROMIPS_GPREL7_S2:
405
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
406
2
  case R_MIPS_PC16:
407
2
    return SignExtend64<18>(read32<E>(Buf) << 2);
408
1
  case R_MIPS_PC19_S2:
409
1
    return SignExtend64<21>(read32<E>(Buf) << 2);
410
1
  case R_MIPS_PC21_S2:
411
1
    return SignExtend64<23>(read32<E>(Buf) << 2);
412
1
  case R_MIPS_PC26_S2:
413
1
    return SignExtend64<28>(read32<E>(Buf) << 2);
414
1
  case R_MIPS_PC32:
415
1
    return SignExtend64<32>(read32<E>(Buf));
416
4
  case R_MICROMIPS_26_S1:
417
4
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
418
2
  case R_MICROMIPS_PC7_S1:
419
2
    return SignExtend64<8>(read16<E>(Buf) << 1);
420
2
  case R_MICROMIPS_PC10_S1:
421
2
    return SignExtend64<11>(read16<E>(Buf) << 1);
422
2
  case R_MICROMIPS_PC16_S1:
423
2
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
424
0
  case R_MICROMIPS_PC18_S3:
425
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
426
0
  case R_MICROMIPS_PC19_S2:
427
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
428
0
  case R_MICROMIPS_PC21_S1:
429
0
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
430
0
  case R_MICROMIPS_PC23_S2:
431
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
432
0
  case R_MICROMIPS_PC26_S1:
433
0
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
434
0
  }
435
0
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getImplicitAddend(unsigned char const*, unsigned int) const
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getImplicitAddend(unsigned char const*, unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getImplicitAddend(unsigned char const*, unsigned int) const
Line
Count
Source
367
16
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const {
368
16
  const endianness E = ELFT::TargetEndianness;
369
16
  switch (Type) {
370
1
  default:
371
1
    return 0;
372
2
  case R_MIPS_32:
373
2
  case R_MIPS_GPREL32:
374
2
  case R_MIPS_TLS_DTPREL32:
375
2
  case R_MIPS_TLS_TPREL32:
376
2
    return SignExtend64<32>(read32<E>(Buf));
377
0
  case R_MIPS_26:
378
0
    // FIXME (simon): If the relocation target symbol is not a PLT entry
379
0
    // we should use another expression for calculation:
380
0
    // ((A << 2) | (P & 0xf0000000)) >> 2
381
0
    return SignExtend64<28>(read32<E>(Buf) << 2);
382
4
  case R_MIPS_GOT16:
383
4
  case R_MIPS_HI16:
384
4
  case R_MIPS_PCHI16:
385
4
    return SignExtend64<16>(read32<E>(Buf)) << 16;
386
0
  case R_MIPS_GPREL16:
387
0
  case R_MIPS_LO16:
388
0
  case R_MIPS_PCLO16:
389
0
  case R_MIPS_TLS_DTPREL_HI16:
390
0
  case R_MIPS_TLS_DTPREL_LO16:
391
0
  case R_MIPS_TLS_TPREL_HI16:
392
0
  case R_MIPS_TLS_TPREL_LO16:
393
0
    return SignExtend64<16>(read32<E>(Buf));
394
2
  case R_MICROMIPS_GOT16:
395
2
  case R_MICROMIPS_HI16:
396
2
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
397
2
  case R_MICROMIPS_GPREL16:
398
2
  case R_MICROMIPS_LO16:
399
2
  case R_MICROMIPS_TLS_DTPREL_HI16:
400
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
401
2
  case R_MICROMIPS_TLS_TPREL_HI16:
402
2
  case R_MICROMIPS_TLS_TPREL_LO16:
403
2
    return SignExtend64<16>(readShuffle<E>(Buf));
404
0
  case R_MICROMIPS_GPREL7_S2:
405
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
406
0
  case R_MIPS_PC16:
407
0
    return SignExtend64<18>(read32<E>(Buf) << 2);
408
0
  case R_MIPS_PC19_S2:
409
0
    return SignExtend64<21>(read32<E>(Buf) << 2);
410
0
  case R_MIPS_PC21_S2:
411
0
    return SignExtend64<23>(read32<E>(Buf) << 2);
412
0
  case R_MIPS_PC26_S2:
413
0
    return SignExtend64<28>(read32<E>(Buf) << 2);
414
0
  case R_MIPS_PC32:
415
0
    return SignExtend64<32>(read32<E>(Buf));
416
2
  case R_MICROMIPS_26_S1:
417
2
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
418
1
  case R_MICROMIPS_PC7_S1:
419
1
    return SignExtend64<8>(read16<E>(Buf) << 1);
420
1
  case R_MICROMIPS_PC10_S1:
421
1
    return SignExtend64<11>(read16<E>(Buf) << 1);
422
1
  case R_MICROMIPS_PC16_S1:
423
1
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
424
0
  case R_MICROMIPS_PC18_S3:
425
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
426
0
  case R_MICROMIPS_PC19_S2:
427
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
428
0
  case R_MICROMIPS_PC21_S1:
429
0
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
430
0
  case R_MICROMIPS_PC23_S2:
431
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
432
0
  case R_MICROMIPS_PC26_S1:
433
0
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
434
0
  }
435
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getImplicitAddend(unsigned char const*, unsigned int) const
Line
Count
Source
367
269
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const {
368
269
  const endianness E = ELFT::TargetEndianness;
369
269
  switch (Type) {
370
42
  default:
371
42
    return 0;
372
22
  case R_MIPS_32:
373
22
  case R_MIPS_GPREL32:
374
22
  case R_MIPS_TLS_DTPREL32:
375
22
  case R_MIPS_TLS_TPREL32:
376
22
    return SignExtend64<32>(read32<E>(Buf));
377
48
  case R_MIPS_26:
378
48
    // FIXME (simon): If the relocation target symbol is not a PLT entry
379
48
    // we should use another expression for calculation:
380
48
    // ((A << 2) | (P & 0xf0000000)) >> 2
381
48
    return SignExtend64<28>(read32<E>(Buf) << 2);
382
57
  case R_MIPS_GOT16:
383
57
  case R_MIPS_HI16:
384
57
  case R_MIPS_PCHI16:
385
57
    return SignExtend64<16>(read32<E>(Buf)) << 16;
386
82
  case R_MIPS_GPREL16:
387
82
  case R_MIPS_LO16:
388
82
  case R_MIPS_PCLO16:
389
82
  case R_MIPS_TLS_DTPREL_HI16:
390
82
  case R_MIPS_TLS_DTPREL_LO16:
391
82
  case R_MIPS_TLS_TPREL_HI16:
392
82
  case R_MIPS_TLS_TPREL_LO16:
393
82
    return SignExtend64<16>(read32<E>(Buf));
394
3
  case R_MICROMIPS_GOT16:
395
3
  case R_MICROMIPS_HI16:
396
3
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
397
4
  case R_MICROMIPS_GPREL16:
398
4
  case R_MICROMIPS_LO16:
399
4
  case R_MICROMIPS_TLS_DTPREL_HI16:
400
4
  case R_MICROMIPS_TLS_DTPREL_LO16:
401
4
  case R_MICROMIPS_TLS_TPREL_HI16:
402
4
  case R_MICROMIPS_TLS_TPREL_LO16:
403
4
    return SignExtend64<16>(readShuffle<E>(Buf));
404
0
  case R_MICROMIPS_GPREL7_S2:
405
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
406
2
  case R_MIPS_PC16:
407
2
    return SignExtend64<18>(read32<E>(Buf) << 2);
408
1
  case R_MIPS_PC19_S2:
409
1
    return SignExtend64<21>(read32<E>(Buf) << 2);
410
1
  case R_MIPS_PC21_S2:
411
1
    return SignExtend64<23>(read32<E>(Buf) << 2);
412
1
  case R_MIPS_PC26_S2:
413
1
    return SignExtend64<28>(read32<E>(Buf) << 2);
414
1
  case R_MIPS_PC32:
415
1
    return SignExtend64<32>(read32<E>(Buf));
416
2
  case R_MICROMIPS_26_S1:
417
2
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
418
1
  case R_MICROMIPS_PC7_S1:
419
1
    return SignExtend64<8>(read16<E>(Buf) << 1);
420
1
  case R_MICROMIPS_PC10_S1:
421
1
    return SignExtend64<11>(read16<E>(Buf) << 1);
422
1
  case R_MICROMIPS_PC16_S1:
423
1
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
424
0
  case R_MICROMIPS_PC18_S3:
425
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
426
0
  case R_MICROMIPS_PC19_S2:
427
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
428
0
  case R_MICROMIPS_PC21_S1:
429
0
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
430
0
  case R_MICROMIPS_PC23_S2:
431
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
432
0
  case R_MICROMIPS_PC26_S1:
433
0
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
434
0
  }
435
0
}
436
437
static std::pair<uint32_t, uint64_t>
438
50
calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) {
439
50
  // MIPS N64 ABI packs multiple relocations into the single relocation
440
50
  // record. In general, all up to three relocations can have arbitrary
441
50
  // types. In fact, Clang and GCC uses only a few combinations. For now,
442
50
  // we support two of them. That is allow to pass at least all LLVM
443
50
  // test suite cases.
444
50
  // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
445
50
  // <any relocation> / R_MIPS_64 / R_MIPS_NONE
446
50
  // The first relocation is a 'real' relocation which is calculated
447
50
  // using the corresponding symbol's value. The second and the third
448
50
  // relocations used to modify result of the first one: extend it to
449
50
  // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
450
50
  // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
451
50
  uint32_t Type2 = (Type >> 8) & 0xff;
452
50
  uint32_t Type3 = (Type >> 16) & 0xff;
453
50
  if (
Type2 == R_MIPS_NONE && 50
Type3 == R_MIPS_NONE38
)
454
38
    return std::make_pair(Type, Val);
455
12
  
if (12
Type2 == R_MIPS_64 && 12
Type3 == R_MIPS_NONE1
)
456
1
    return std::make_pair(Type2, Val);
457
11
  
if (11
Type2 == R_MIPS_SUB && 11
(Type3 == R_MIPS_HI16 || 11
Type3 == R_MIPS_LO164
))
458
11
    return std::make_pair(Type3, -Val);
459
0
  
if (0
Type2 == R_MICROMIPS_SUB &&
460
0
      
(Type3 == R_MICROMIPS_HI16 || 0
Type3 == R_MICROMIPS_LO160
))
461
0
    return std::make_pair(Type3, -Val);
462
0
  error(getErrorLocation(Loc) + "unsupported relocations combination " +
463
0
        Twine(Type));
464
0
  return std::make_pair(Type & 0xff, Val);
465
0
}
466
467
template <class ELFT>
468
358
void MIPS<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
469
358
  const endianness E = ELFT::TargetEndianness;
470
358
  // Thread pointer and DRP offsets from the start of TLS data area.
471
358
  // https://www.linux-mips.org/wiki/NPTL
472
358
  if (
Type == R_MIPS_TLS_DTPREL_HI16 || 358
Type == R_MIPS_TLS_DTPREL_LO16356
||
473
358
      
Type == R_MIPS_TLS_DTPREL32354
||
Type == R_MIPS_TLS_DTPREL64353
||
474
353
      Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
475
353
      Type == R_MICROMIPS_TLS_DTPREL_LO16)
476
6
    Val -= 0x8000;
477
352
  else 
if (352
Type == R_MIPS_TLS_TPREL_HI16 || 352
Type == R_MIPS_TLS_TPREL_LO16350
||
478
352
           
Type == R_MIPS_TLS_TPREL32349
||
Type == R_MIPS_TLS_TPREL64348
||
479
346
           Type == R_MICROMIPS_TLS_TPREL_HI16 ||
480
347
           Type == R_MICROMIPS_TLS_TPREL_LO16)
481
6
    Val -= 0x7000;
482
358
  if (
ELFT::Is64Bits || 358
Config->MipsN32Abi311
)
483
50
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
484
358
  switch (Type) {
485
24
  case R_MIPS_32:
486
24
  case R_MIPS_GPREL32:
487
24
  case R_MIPS_TLS_DTPREL32:
488
24
  case R_MIPS_TLS_TPREL32:
489
24
    write32<E>(Loc, Val);
490
24
    break;
491
3
  case R_MIPS_64:
492
3
  case R_MIPS_TLS_DTPREL64:
493
3
  case R_MIPS_TLS_TPREL64:
494
3
    write64<E>(Loc, Val);
495
3
    break;
496
48
  case R_MIPS_26:
497
48
    writeRelocation<E>(Loc, Val, 26, 2);
498
48
    break;
499
36
  case R_MIPS_GOT16:
500
36
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
501
36
    // is updated addend (not a GOT index). In that case write high 16 bits
502
36
    // to store a correct addend value.
503
36
    if (
Config->Relocatable36
) {
504
1
      writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
505
36
    } else {
506
35
      checkInt<16>(Loc, Val, Type);
507
35
      writeRelocation<E>(Loc, Val, 16, 0);
508
35
    }
509
36
    break;
510
3
  case R_MICROMIPS_GOT16:
511
3
    if (
Config->Relocatable3
) {
512
0
      writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
513
3
    } else {
514
3
      checkInt<16>(Loc, Val, Type);
515
3
      writeMicroRelocation32<E>(Loc, Val, 16, 0);
516
3
    }
517
3
    break;
518
26
  case R_MIPS_GOT_DISP:
519
26
  case R_MIPS_GOT_PAGE:
520
26
  case R_MIPS_GPREL16:
521
26
  case R_MIPS_TLS_GD:
522
26
  case R_MIPS_TLS_LDM:
523
26
    checkInt<16>(Loc, Val, Type);
524
26
    LLVM_FALLTHROUGH;
525
132
  case R_MIPS_CALL16:
526
132
  case R_MIPS_CALL_LO16:
527
132
  case R_MIPS_GOT_LO16:
528
132
  case R_MIPS_GOT_OFST:
529
132
  case R_MIPS_LO16:
530
132
  case R_MIPS_PCLO16:
531
132
  case R_MIPS_TLS_DTPREL_LO16:
532
132
  case R_MIPS_TLS_GOTTPREL:
533
132
  case R_MIPS_TLS_TPREL_LO16:
534
132
    writeRelocation<E>(Loc, Val, 16, 0);
535
132
    break;
536
1
  case R_MICROMIPS_GOT_DISP:
537
1
  case R_MICROMIPS_GOT_PAGE:
538
1
  case R_MICROMIPS_GPREL16:
539
1
  case R_MICROMIPS_TLS_GD:
540
1
  case R_MICROMIPS_TLS_LDM:
541
1
    checkInt<16>(Loc, Val, Type);
542
1
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
543
1
    break;
544
8
  case R_MICROMIPS_CALL16:
545
8
  case R_MICROMIPS_CALL_LO16:
546
8
  case R_MICROMIPS_GOT_OFST:
547
8
  case R_MICROMIPS_LO16:
548
8
  case R_MICROMIPS_TLS_DTPREL_LO16:
549
8
  case R_MICROMIPS_TLS_GOTTPREL:
550
8
  case R_MICROMIPS_TLS_TPREL_LO16:
551
8
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
552
8
    break;
553
0
  case R_MICROMIPS_GPREL7_S2:
554
0
    checkInt<7>(Loc, Val, Type);
555
0
    writeMicroRelocation32<E>(Loc, Val, 7, 2);
556
0
    break;
557
70
  case R_MIPS_CALL_HI16:
558
70
  case R_MIPS_GOT_HI16:
559
70
  case R_MIPS_HI16:
560
70
  case R_MIPS_PCHI16:
561
70
  case R_MIPS_TLS_DTPREL_HI16:
562
70
  case R_MIPS_TLS_TPREL_HI16:
563
70
    writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
564
70
    break;
565
2
  case R_MICROMIPS_CALL_HI16:
566
2
  case R_MICROMIPS_GOT_HI16:
567
2
  case R_MICROMIPS_HI16:
568
2
  case R_MICROMIPS_TLS_DTPREL_HI16:
569
2
  case R_MICROMIPS_TLS_TPREL_HI16:
570
2
    writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
571
2
    break;
572
2
  case R_MIPS_HIGHER:
573
2
    writeRelocation<E>(Loc, Val + 0x80008000, 16, 32);
574
2
    break;
575
2
  case R_MIPS_HIGHEST:
576
2
    writeRelocation<E>(Loc, Val + 0x800080008000, 16, 48);
577
2
    break;
578
0
  case R_MICROMIPS_HIGHER:
579
0
    writeMicroRelocation32<E>(Loc, Val + 0x80008000, 16, 32);
580
0
    break;
581
0
  case R_MICROMIPS_HIGHEST:
582
0
    writeMicroRelocation32<E>(Loc, Val + 0x800080008000, 16, 48);
583
0
    break;
584
0
  case R_MIPS_JALR:
585
0
  case R_MICROMIPS_JALR:
586
0
    // Ignore this optimization relocation for now
587
0
    break;
588
2
  case R_MIPS_PC16:
589
2
    checkAlignment<4>(Loc, Val, Type);
590
2
    checkInt<18>(Loc, Val, Type);
591
2
    writeRelocation<E>(Loc, Val, 16, 2);
592
2
    break;
593
1
  case R_MIPS_PC19_S2:
594
1
    checkAlignment<4>(Loc, Val, Type);
595
1
    checkInt<21>(Loc, Val, Type);
596
1
    writeRelocation<E>(Loc, Val, 19, 2);
597
1
    break;
598
1
  case R_MIPS_PC21_S2:
599
1
    checkAlignment<4>(Loc, Val, Type);
600
1
    checkInt<23>(Loc, Val, Type);
601
1
    writeRelocation<E>(Loc, Val, 21, 2);
602
1
    break;
603
1
  case R_MIPS_PC26_S2:
604
1
    checkAlignment<4>(Loc, Val, Type);
605
1
    checkInt<28>(Loc, Val, Type);
606
1
    writeRelocation<E>(Loc, Val, 26, 2);
607
1
    break;
608
2
  case R_MIPS_PC32:
609
2
    writeRelocation<E>(Loc, Val, 32, 0);
610
2
    break;
611
4
  case R_MICROMIPS_26_S1:
612
4
  case R_MICROMIPS_PC26_S1:
613
4
    checkInt<27>(Loc, Val, Type);
614
4
    writeMicroRelocation32<E>(Loc, Val, 26, 1);
615
4
    break;
616
2
  case R_MICROMIPS_PC7_S1:
617
2
    checkInt<8>(Loc, Val, Type);
618
2
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
619
2
    break;
620
2
  case R_MICROMIPS_PC10_S1:
621
2
    checkInt<11>(Loc, Val, Type);
622
2
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
623
2
    break;
624
2
  case R_MICROMIPS_PC16_S1:
625
2
    checkInt<17>(Loc, Val, Type);
626
2
    writeMicroRelocation32<E>(Loc, Val, 16, 1);
627
2
    break;
628
0
  case R_MICROMIPS_PC18_S3:
629
0
    checkInt<21>(Loc, Val, Type);
630
0
    writeMicroRelocation32<E>(Loc, Val, 18, 3);
631
0
    break;
632
4
  case R_MICROMIPS_PC19_S2:
633
4
    checkInt<21>(Loc, Val, Type);
634
4
    writeMicroRelocation32<E>(Loc, Val, 19, 2);
635
4
    break;
636
0
  case R_MICROMIPS_PC21_S1:
637
0
    checkInt<22>(Loc, Val, Type);
638
0
    writeMicroRelocation32<E>(Loc, Val, 21, 1);
639
0
    break;
640
4
  case R_MICROMIPS_PC23_S2:
641
4
    checkInt<25>(Loc, Val, Type);
642
4
    writeMicroRelocation32<E>(Loc, Val, 23, 2);
643
4
    break;
644
0
  default:
645
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
646
358
  }
647
358
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
468
293
void MIPS<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
469
293
  const endianness E = ELFT::TargetEndianness;
470
293
  // Thread pointer and DRP offsets from the start of TLS data area.
471
293
  // https://www.linux-mips.org/wiki/NPTL
472
293
  if (
Type == R_MIPS_TLS_DTPREL_HI16 || 293
Type == R_MIPS_TLS_DTPREL_LO16291
||
473
293
      
Type == R_MIPS_TLS_DTPREL32289
||
Type == R_MIPS_TLS_DTPREL64288
||
474
289
      Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
475
289
      Type == R_MICROMIPS_TLS_DTPREL_LO16)
476
5
    Val -= 0x8000;
477
288
  else 
if (288
Type == R_MIPS_TLS_TPREL_HI16 || 288
Type == R_MIPS_TLS_TPREL_LO16286
||
478
288
           
Type == R_MIPS_TLS_TPREL32285
||
Type == R_MIPS_TLS_TPREL64284
||
479
283
           Type == R_MICROMIPS_TLS_TPREL_HI16 ||
480
284
           Type == R_MICROMIPS_TLS_TPREL_LO16)
481
5
    Val -= 0x7000;
482
293
  if (
ELFT::Is64Bits || 293
Config->MipsN32Abi293
)
483
3
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
484
293
  switch (Type) {
485
21
  case R_MIPS_32:
486
21
  case R_MIPS_GPREL32:
487
21
  case R_MIPS_TLS_DTPREL32:
488
21
  case R_MIPS_TLS_TPREL32:
489
21
    write32<E>(Loc, Val);
490
21
    break;
491
0
  case R_MIPS_64:
492
0
  case R_MIPS_TLS_DTPREL64:
493
0
  case R_MIPS_TLS_TPREL64:
494
0
    write64<E>(Loc, Val);
495
0
    break;
496
48
  case R_MIPS_26:
497
48
    writeRelocation<E>(Loc, Val, 26, 2);
498
48
    break;
499
32
  case R_MIPS_GOT16:
500
32
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
501
32
    // is updated addend (not a GOT index). In that case write high 16 bits
502
32
    // to store a correct addend value.
503
32
    if (
Config->Relocatable32
) {
504
1
      writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
505
32
    } else {
506
31
      checkInt<16>(Loc, Val, Type);
507
31
      writeRelocation<E>(Loc, Val, 16, 0);
508
31
    }
509
32
    break;
510
2
  case R_MICROMIPS_GOT16:
511
2
    if (
Config->Relocatable2
) {
512
0
      writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
513
2
    } else {
514
2
      checkInt<16>(Loc, Val, Type);
515
2
      writeMicroRelocation32<E>(Loc, Val, 16, 0);
516
2
    }
517
2
    break;
518
8
  case R_MIPS_GOT_DISP:
519
8
  case R_MIPS_GOT_PAGE:
520
8
  case R_MIPS_GPREL16:
521
8
  case R_MIPS_TLS_GD:
522
8
  case R_MIPS_TLS_LDM:
523
8
    checkInt<16>(Loc, Val, Type);
524
8
    LLVM_FALLTHROUGH;
525
104
  case R_MIPS_CALL16:
526
104
  case R_MIPS_CALL_LO16:
527
104
  case R_MIPS_GOT_LO16:
528
104
  case R_MIPS_GOT_OFST:
529
104
  case R_MIPS_LO16:
530
104
  case R_MIPS_PCLO16:
531
104
  case R_MIPS_TLS_DTPREL_LO16:
532
104
  case R_MIPS_TLS_GOTTPREL:
533
104
  case R_MIPS_TLS_TPREL_LO16:
534
104
    writeRelocation<E>(Loc, Val, 16, 0);
535
104
    break;
536
0
  case R_MICROMIPS_GOT_DISP:
537
0
  case R_MICROMIPS_GOT_PAGE:
538
0
  case R_MICROMIPS_GPREL16:
539
0
  case R_MICROMIPS_TLS_GD:
540
0
  case R_MICROMIPS_TLS_LDM:
541
0
    checkInt<16>(Loc, Val, Type);
542
0
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
543
0
    break;
544
4
  case R_MICROMIPS_CALL16:
545
4
  case R_MICROMIPS_CALL_LO16:
546
4
  case R_MICROMIPS_GOT_OFST:
547
4
  case R_MICROMIPS_LO16:
548
4
  case R_MICROMIPS_TLS_DTPREL_LO16:
549
4
  case R_MICROMIPS_TLS_GOTTPREL:
550
4
  case R_MICROMIPS_TLS_TPREL_LO16:
551
4
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
552
4
    break;
553
0
  case R_MICROMIPS_GPREL7_S2:
554
0
    checkInt<7>(Loc, Val, Type);
555
0
    writeMicroRelocation32<E>(Loc, Val, 7, 2);
556
0
    break;
557
64
  case R_MIPS_CALL_HI16:
558
64
  case R_MIPS_GOT_HI16:
559
64
  case R_MIPS_HI16:
560
64
  case R_MIPS_PCHI16:
561
64
  case R_MIPS_TLS_DTPREL_HI16:
562
64
  case R_MIPS_TLS_TPREL_HI16:
563
64
    writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
564
64
    break;
565
1
  case R_MICROMIPS_CALL_HI16:
566
1
  case R_MICROMIPS_GOT_HI16:
567
1
  case R_MICROMIPS_HI16:
568
1
  case R_MICROMIPS_TLS_DTPREL_HI16:
569
1
  case R_MICROMIPS_TLS_TPREL_HI16:
570
1
    writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
571
1
    break;
572
0
  case R_MIPS_HIGHER:
573
0
    writeRelocation<E>(Loc, Val + 0x80008000, 16, 32);
574
0
    break;
575
0
  case R_MIPS_HIGHEST:
576
0
    writeRelocation<E>(Loc, Val + 0x800080008000, 16, 48);
577
0
    break;
578
0
  case R_MICROMIPS_HIGHER:
579
0
    writeMicroRelocation32<E>(Loc, Val + 0x80008000, 16, 32);
580
0
    break;
581
0
  case R_MICROMIPS_HIGHEST:
582
0
    writeMicroRelocation32<E>(Loc, Val + 0x800080008000, 16, 48);
583
0
    break;
584
0
  case R_MIPS_JALR:
585
0
  case R_MICROMIPS_JALR:
586
0
    // Ignore this optimization relocation for now
587
0
    break;
588
2
  case R_MIPS_PC16:
589
2
    checkAlignment<4>(Loc, Val, Type);
590
2
    checkInt<18>(Loc, Val, Type);
591
2
    writeRelocation<E>(Loc, Val, 16, 2);
592
2
    break;
593
1
  case R_MIPS_PC19_S2:
594
1
    checkAlignment<4>(Loc, Val, Type);
595
1
    checkInt<21>(Loc, Val, Type);
596
1
    writeRelocation<E>(Loc, Val, 19, 2);
597
1
    break;
598
1
  case R_MIPS_PC21_S2:
599
1
    checkAlignment<4>(Loc, Val, Type);
600
1
    checkInt<23>(Loc, Val, Type);
601
1
    writeRelocation<E>(Loc, Val, 21, 2);
602
1
    break;
603
1
  case R_MIPS_PC26_S2:
604
1
    checkAlignment<4>(Loc, Val, Type);
605
1
    checkInt<28>(Loc, Val, Type);
606
1
    writeRelocation<E>(Loc, Val, 26, 2);
607
1
    break;
608
1
  case R_MIPS_PC32:
609
1
    writeRelocation<E>(Loc, Val, 32, 0);
610
1
    break;
611
2
  case R_MICROMIPS_26_S1:
612
2
  case R_MICROMIPS_PC26_S1:
613
2
    checkInt<27>(Loc, Val, Type);
614
2
    writeMicroRelocation32<E>(Loc, Val, 26, 1);
615
2
    break;
616
1
  case R_MICROMIPS_PC7_S1:
617
1
    checkInt<8>(Loc, Val, Type);
618
1
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
619
1
    break;
620
1
  case R_MICROMIPS_PC10_S1:
621
1
    checkInt<11>(Loc, Val, Type);
622
1
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
623
1
    break;
624
1
  case R_MICROMIPS_PC16_S1:
625
1
    checkInt<17>(Loc, Val, Type);
626
1
    writeMicroRelocation32<E>(Loc, Val, 16, 1);
627
1
    break;
628
0
  case R_MICROMIPS_PC18_S3:
629
0
    checkInt<21>(Loc, Val, Type);
630
0
    writeMicroRelocation32<E>(Loc, Val, 18, 3);
631
0
    break;
632
2
  case R_MICROMIPS_PC19_S2:
633
2
    checkInt<21>(Loc, Val, Type);
634
2
    writeMicroRelocation32<E>(Loc, Val, 19, 2);
635
2
    break;
636
0
  case R_MICROMIPS_PC21_S1:
637
0
    checkInt<22>(Loc, Val, Type);
638
0
    writeMicroRelocation32<E>(Loc, Val, 21, 1);
639
0
    break;
640
2
  case R_MICROMIPS_PC23_S2:
641
2
    checkInt<25>(Loc, Val, Type);
642
2
    writeMicroRelocation32<E>(Loc, Val, 23, 2);
643
2
    break;
644
0
  default:
645
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
646
293
  }
647
293
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
468
18
void MIPS<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
469
18
  const endianness E = ELFT::TargetEndianness;
470
18
  // Thread pointer and DRP offsets from the start of TLS data area.
471
18
  // https://www.linux-mips.org/wiki/NPTL
472
18
  if (
Type == R_MIPS_TLS_DTPREL_HI16 || 18
Type == R_MIPS_TLS_DTPREL_LO1618
||
473
18
      
Type == R_MIPS_TLS_DTPREL3218
||
Type == R_MIPS_TLS_DTPREL6418
||
474
18
      Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
475
18
      Type == R_MICROMIPS_TLS_DTPREL_LO16)
476
0
    Val -= 0x8000;
477
18
  else 
if (18
Type == R_MIPS_TLS_TPREL_HI16 || 18
Type == R_MIPS_TLS_TPREL_LO1618
||
478
18
           
Type == R_MIPS_TLS_TPREL3218
||
Type == R_MIPS_TLS_TPREL6418
||
479
18
           Type == R_MICROMIPS_TLS_TPREL_HI16 ||
480
18
           Type == R_MICROMIPS_TLS_TPREL_LO16)
481
0
    Val -= 0x7000;
482
18
  if (
ELFT::Is64Bits || 18
Config->MipsN32Abi18
)
483
0
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
484
18
  switch (Type) {
485
1
  case R_MIPS_32:
486
1
  case R_MIPS_GPREL32:
487
1
  case R_MIPS_TLS_DTPREL32:
488
1
  case R_MIPS_TLS_TPREL32:
489
1
    write32<E>(Loc, Val);
490
1
    break;
491
0
  case R_MIPS_64:
492
0
  case R_MIPS_TLS_DTPREL64:
493
0
  case R_MIPS_TLS_TPREL64:
494
0
    write64<E>(Loc, Val);
495
0
    break;
496
0
  case R_MIPS_26:
497
0
    writeRelocation<E>(Loc, Val, 26, 2);
498
0
    break;
499
4
  case R_MIPS_GOT16:
500
4
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
501
4
    // is updated addend (not a GOT index). In that case write high 16 bits
502
4
    // to store a correct addend value.
503
4
    if (
Config->Relocatable4
) {
504
0
      writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
505
4
    } else {
506
4
      checkInt<16>(Loc, Val, Type);
507
4
      writeRelocation<E>(Loc, Val, 16, 0);
508
4
    }
509
4
    break;
510
1
  case R_MICROMIPS_GOT16:
511
1
    if (
Config->Relocatable1
) {
512
0
      writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
513
1
    } else {
514
1
      checkInt<16>(Loc, Val, Type);
515
1
      writeMicroRelocation32<E>(Loc, Val, 16, 0);
516
1
    }
517
1
    break;
518
0
  case R_MIPS_GOT_DISP:
519
0
  case R_MIPS_GOT_PAGE:
520
0
  case R_MIPS_GPREL16:
521
0
  case R_MIPS_TLS_GD:
522
0
  case R_MIPS_TLS_LDM:
523
0
    checkInt<16>(Loc, Val, Type);
524
0
    LLVM_FALLTHROUGH;
525
0
  case R_MIPS_CALL16:
526
0
  case R_MIPS_CALL_LO16:
527
0
  case R_MIPS_GOT_LO16:
528
0
  case R_MIPS_GOT_OFST:
529
0
  case R_MIPS_LO16:
530
0
  case R_MIPS_PCLO16:
531
0
  case R_MIPS_TLS_DTPREL_LO16:
532
0
  case R_MIPS_TLS_GOTTPREL:
533
0
  case R_MIPS_TLS_TPREL_LO16:
534
0
    writeRelocation<E>(Loc, Val, 16, 0);
535
0
    break;
536
0
  case R_MICROMIPS_GOT_DISP:
537
0
  case R_MICROMIPS_GOT_PAGE:
538
0
  case R_MICROMIPS_GPREL16:
539
0
  case R_MICROMIPS_TLS_GD:
540
0
  case R_MICROMIPS_TLS_LDM:
541
0
    checkInt<16>(Loc, Val, Type);
542
0
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
543
0
    break;
544
2
  case R_MICROMIPS_CALL16:
545
2
  case R_MICROMIPS_CALL_LO16:
546
2
  case R_MICROMIPS_GOT_OFST:
547
2
  case R_MICROMIPS_LO16:
548
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
549
2
  case R_MICROMIPS_TLS_GOTTPREL:
550
2
  case R_MICROMIPS_TLS_TPREL_LO16:
551
2
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
552
2
    break;
553
0
  case R_MICROMIPS_GPREL7_S2:
554
0
    checkInt<7>(Loc, Val, Type);
555
0
    writeMicroRelocation32<E>(Loc, Val, 7, 2);
556
0
    break;
557
0
  case R_MIPS_CALL_HI16:
558
0
  case R_MIPS_GOT_HI16:
559
0
  case R_MIPS_HI16:
560
0
  case R_MIPS_PCHI16:
561
0
  case R_MIPS_TLS_DTPREL_HI16:
562
0
  case R_MIPS_TLS_TPREL_HI16:
563
0
    writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
564
0
    break;
565
1
  case R_MICROMIPS_CALL_HI16:
566
1
  case R_MICROMIPS_GOT_HI16:
567
1
  case R_MICROMIPS_HI16:
568
1
  case R_MICROMIPS_TLS_DTPREL_HI16:
569
1
  case R_MICROMIPS_TLS_TPREL_HI16:
570
1
    writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
571
1
    break;
572
0
  case R_MIPS_HIGHER:
573
0
    writeRelocation<E>(Loc, Val + 0x80008000, 16, 32);
574
0
    break;
575
0
  case R_MIPS_HIGHEST:
576
0
    writeRelocation<E>(Loc, Val + 0x800080008000, 16, 48);
577
0
    break;
578
0
  case R_MICROMIPS_HIGHER:
579
0
    writeMicroRelocation32<E>(Loc, Val + 0x80008000, 16, 32);
580
0
    break;
581
0
  case R_MICROMIPS_HIGHEST:
582
0
    writeMicroRelocation32<E>(Loc, Val + 0x800080008000, 16, 48);
583
0
    break;
584
0
  case R_MIPS_JALR:
585
0
  case R_MICROMIPS_JALR:
586
0
    // Ignore this optimization relocation for now
587
0
    break;
588
0
  case R_MIPS_PC16:
589
0
    checkAlignment<4>(Loc, Val, Type);
590
0
    checkInt<18>(Loc, Val, Type);
591
0
    writeRelocation<E>(Loc, Val, 16, 2);
592
0
    break;
593
0
  case R_MIPS_PC19_S2:
594
0
    checkAlignment<4>(Loc, Val, Type);
595
0
    checkInt<21>(Loc, Val, Type);
596
0
    writeRelocation<E>(Loc, Val, 19, 2);
597
0
    break;
598
0
  case R_MIPS_PC21_S2:
599
0
    checkAlignment<4>(Loc, Val, Type);
600
0
    checkInt<23>(Loc, Val, Type);
601
0
    writeRelocation<E>(Loc, Val, 21, 2);
602
0
    break;
603
0
  case R_MIPS_PC26_S2:
604
0
    checkAlignment<4>(Loc, Val, Type);
605
0
    checkInt<28>(Loc, Val, Type);
606
0
    writeRelocation<E>(Loc, Val, 26, 2);
607
0
    break;
608
0
  case R_MIPS_PC32:
609
0
    writeRelocation<E>(Loc, Val, 32, 0);
610
0
    break;
611
2
  case R_MICROMIPS_26_S1:
612
2
  case R_MICROMIPS_PC26_S1:
613
2
    checkInt<27>(Loc, Val, Type);
614
2
    writeMicroRelocation32<E>(Loc, Val, 26, 1);
615
2
    break;
616
1
  case R_MICROMIPS_PC7_S1:
617
1
    checkInt<8>(Loc, Val, Type);
618
1
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
619
1
    break;
620
1
  case R_MICROMIPS_PC10_S1:
621
1
    checkInt<11>(Loc, Val, Type);
622
1
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
623
1
    break;
624
1
  case R_MICROMIPS_PC16_S1:
625
1
    checkInt<17>(Loc, Val, Type);
626
1
    writeMicroRelocation32<E>(Loc, Val, 16, 1);
627
1
    break;
628
0
  case R_MICROMIPS_PC18_S3:
629
0
    checkInt<21>(Loc, Val, Type);
630
0
    writeMicroRelocation32<E>(Loc, Val, 18, 3);
631
0
    break;
632
2
  case R_MICROMIPS_PC19_S2:
633
2
    checkInt<21>(Loc, Val, Type);
634
2
    writeMicroRelocation32<E>(Loc, Val, 19, 2);
635
2
    break;
636
0
  case R_MICROMIPS_PC21_S1:
637
0
    checkInt<22>(Loc, Val, Type);
638
0
    writeMicroRelocation32<E>(Loc, Val, 21, 1);
639
0
    break;
640
2
  case R_MICROMIPS_PC23_S2:
641
2
    checkInt<25>(Loc, Val, Type);
642
2
    writeMicroRelocation32<E>(Loc, Val, 23, 2);
643
2
    break;
644
0
  default:
645
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
646
18
  }
647
18
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
468
47
void MIPS<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
469
47
  const endianness E = ELFT::TargetEndianness;
470
47
  // Thread pointer and DRP offsets from the start of TLS data area.
471
47
  // https://www.linux-mips.org/wiki/NPTL
472
47
  if (
Type == R_MIPS_TLS_DTPREL_HI16 || 47
Type == R_MIPS_TLS_DTPREL_LO1647
||
473
47
      
Type == R_MIPS_TLS_DTPREL3247
||
Type == R_MIPS_TLS_DTPREL6447
||
474
46
      Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
475
46
      Type == R_MICROMIPS_TLS_DTPREL_LO16)
476
1
    Val -= 0x8000;
477
46
  else 
if (46
Type == R_MIPS_TLS_TPREL_HI16 || 46
Type == R_MIPS_TLS_TPREL_LO1646
||
478
46
           
Type == R_MIPS_TLS_TPREL3246
||
Type == R_MIPS_TLS_TPREL6446
||
479
45
           Type == R_MICROMIPS_TLS_TPREL_HI16 ||
480
45
           Type == R_MICROMIPS_TLS_TPREL_LO16)
481
1
    Val -= 0x7000;
482
47
  if (
ELFT::Is64Bits || 47
Config->MipsN32Abi0
)
483
47
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
484
47
  switch (Type) {
485
2
  case R_MIPS_32:
486
2
  case R_MIPS_GPREL32:
487
2
  case R_MIPS_TLS_DTPREL32:
488
2
  case R_MIPS_TLS_TPREL32:
489
2
    write32<E>(Loc, Val);
490
2
    break;
491
3
  case R_MIPS_64:
492
3
  case R_MIPS_TLS_DTPREL64:
493
3
  case R_MIPS_TLS_TPREL64:
494
3
    write64<E>(Loc, Val);
495
3
    break;
496
0
  case R_MIPS_26:
497
0
    writeRelocation<E>(Loc, Val, 26, 2);
498
0
    break;
499
0
  case R_MIPS_GOT16:
500
0
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
501
0
    // is updated addend (not a GOT index). In that case write high 16 bits
502
0
    // to store a correct addend value.
503
0
    if (
Config->Relocatable0
) {
504
0
      writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
505
0
    } else {
506
0
      checkInt<16>(Loc, Val, Type);
507
0
      writeRelocation<E>(Loc, Val, 16, 0);
508
0
    }
509
0
    break;
510
0
  case R_MICROMIPS_GOT16:
511
0
    if (
Config->Relocatable0
) {
512
0
      writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
513
0
    } else {
514
0
      checkInt<16>(Loc, Val, Type);
515
0
      writeMicroRelocation32<E>(Loc, Val, 16, 0);
516
0
    }
517
0
    break;
518
18
  case R_MIPS_GOT_DISP:
519
18
  case R_MIPS_GOT_PAGE:
520
18
  case R_MIPS_GPREL16:
521
18
  case R_MIPS_TLS_GD:
522
18
  case R_MIPS_TLS_LDM:
523
18
    checkInt<16>(Loc, Val, Type);
524
18
    LLVM_FALLTHROUGH;
525
28
  case R_MIPS_CALL16:
526
28
  case R_MIPS_CALL_LO16:
527
28
  case R_MIPS_GOT_LO16:
528
28
  case R_MIPS_GOT_OFST:
529
28
  case R_MIPS_LO16:
530
28
  case R_MIPS_PCLO16:
531
28
  case R_MIPS_TLS_DTPREL_LO16:
532
28
  case R_MIPS_TLS_GOTTPREL:
533
28
  case R_MIPS_TLS_TPREL_LO16:
534
28
    writeRelocation<E>(Loc, Val, 16, 0);
535
28
    break;
536
1
  case R_MICROMIPS_GOT_DISP:
537
1
  case R_MICROMIPS_GOT_PAGE:
538
1
  case R_MICROMIPS_GPREL16:
539
1
  case R_MICROMIPS_TLS_GD:
540
1
  case R_MICROMIPS_TLS_LDM:
541
1
    checkInt<16>(Loc, Val, Type);
542
1
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
543
1
    break;
544
2
  case R_MICROMIPS_CALL16:
545
2
  case R_MICROMIPS_CALL_LO16:
546
2
  case R_MICROMIPS_GOT_OFST:
547
2
  case R_MICROMIPS_LO16:
548
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
549
2
  case R_MICROMIPS_TLS_GOTTPREL:
550
2
  case R_MICROMIPS_TLS_TPREL_LO16:
551
2
    writeMicroRelocation32<E>(Loc, Val, 16, 0);
552
2
    break;
553
0
  case R_MICROMIPS_GPREL7_S2:
554
0
    checkInt<7>(Loc, Val, Type);
555
0
    writeMicroRelocation32<E>(Loc, Val, 7, 2);
556
0
    break;
557
6
  case R_MIPS_CALL_HI16:
558
6
  case R_MIPS_GOT_HI16:
559
6
  case R_MIPS_HI16:
560
6
  case R_MIPS_PCHI16:
561
6
  case R_MIPS_TLS_DTPREL_HI16:
562
6
  case R_MIPS_TLS_TPREL_HI16:
563
6
    writeRelocation<E>(Loc, Val + 0x8000, 16, 16);
564
6
    break;
565
0
  case R_MICROMIPS_CALL_HI16:
566
0
  case R_MICROMIPS_GOT_HI16:
567
0
  case R_MICROMIPS_HI16:
568
0
  case R_MICROMIPS_TLS_DTPREL_HI16:
569
0
  case R_MICROMIPS_TLS_TPREL_HI16:
570
0
    writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16);
571
0
    break;
572
2
  case R_MIPS_HIGHER:
573
2
    writeRelocation<E>(Loc, Val + 0x80008000, 16, 32);
574
2
    break;
575
2
  case R_MIPS_HIGHEST:
576
2
    writeRelocation<E>(Loc, Val + 0x800080008000, 16, 48);
577
2
    break;
578
0
  case R_MICROMIPS_HIGHER:
579
0
    writeMicroRelocation32<E>(Loc, Val + 0x80008000, 16, 32);
580
0
    break;
581
0
  case R_MICROMIPS_HIGHEST:
582
0
    writeMicroRelocation32<E>(Loc, Val + 0x800080008000, 16, 48);
583
0
    break;
584
0
  case R_MIPS_JALR:
585
0
  case R_MICROMIPS_JALR:
586
0
    // Ignore this optimization relocation for now
587
0
    break;
588
0
  case R_MIPS_PC16:
589
0
    checkAlignment<4>(Loc, Val, Type);
590
0
    checkInt<18>(Loc, Val, Type);
591
0
    writeRelocation<E>(Loc, Val, 16, 2);
592
0
    break;
593
0
  case R_MIPS_PC19_S2:
594
0
    checkAlignment<4>(Loc, Val, Type);
595
0
    checkInt<21>(Loc, Val, Type);
596
0
    writeRelocation<E>(Loc, Val, 19, 2);
597
0
    break;
598
0
  case R_MIPS_PC21_S2:
599
0
    checkAlignment<4>(Loc, Val, Type);
600
0
    checkInt<23>(Loc, Val, Type);
601
0
    writeRelocation<E>(Loc, Val, 21, 2);
602
0
    break;
603
0
  case R_MIPS_PC26_S2:
604
0
    checkAlignment<4>(Loc, Val, Type);
605
0
    checkInt<28>(Loc, Val, Type);
606
0
    writeRelocation<E>(Loc, Val, 26, 2);
607
0
    break;
608
1
  case R_MIPS_PC32:
609
1
    writeRelocation<E>(Loc, Val, 32, 0);
610
1
    break;
611
0
  case R_MICROMIPS_26_S1:
612
0
  case R_MICROMIPS_PC26_S1:
613
0
    checkInt<27>(Loc, Val, Type);
614
0
    writeMicroRelocation32<E>(Loc, Val, 26, 1);
615
0
    break;
616
0
  case R_MICROMIPS_PC7_S1:
617
0
    checkInt<8>(Loc, Val, Type);
618
0
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
619
0
    break;
620
0
  case R_MICROMIPS_PC10_S1:
621
0
    checkInt<11>(Loc, Val, Type);
622
0
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
623
0
    break;
624
0
  case R_MICROMIPS_PC16_S1:
625
0
    checkInt<17>(Loc, Val, Type);
626
0
    writeMicroRelocation32<E>(Loc, Val, 16, 1);
627
0
    break;
628
0
  case R_MICROMIPS_PC18_S3:
629
0
    checkInt<21>(Loc, Val, Type);
630
0
    writeMicroRelocation32<E>(Loc, Val, 18, 3);
631
0
    break;
632
0
  case R_MICROMIPS_PC19_S2:
633
0
    checkInt<21>(Loc, Val, Type);
634
0
    writeMicroRelocation32<E>(Loc, Val, 19, 2);
635
0
    break;
636
0
  case R_MICROMIPS_PC21_S1:
637
0
    checkInt<22>(Loc, Val, Type);
638
0
    writeMicroRelocation32<E>(Loc, Val, 21, 1);
639
0
    break;
640
0
  case R_MICROMIPS_PC23_S2:
641
0
    checkInt<25>(Loc, Val, Type);
642
0
    writeMicroRelocation32<E>(Loc, Val, 23, 2);
643
0
    break;
644
0
  default:
645
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
646
47
  }
647
47
}
648
649
template <class ELFT>
650
48
bool MIPS<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
651
24
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
652
48
         
Type == R_MICROMIPS_LO1622
||
Type == R_MICROMIPS_GOT_OFST22
;
653
48
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
650
38
bool MIPS<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
651
14
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
652
38
         
Type == R_MICROMIPS_LO1614
||
Type == R_MICROMIPS_GOT_OFST14
;
653
38
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
650
5
bool MIPS<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
651
5
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
652
5
         
Type == R_MICROMIPS_LO165
||
Type == R_MICROMIPS_GOT_OFST5
;
653
5
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
650
5
bool MIPS<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
651
5
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
652
5
         
Type == R_MICROMIPS_LO163
||
Type == R_MICROMIPS_GOT_OFST3
;
653
5
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::usesOnlyLowPageBits(unsigned int) const
654
655
139
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
656
139
  static MIPS<ELFT> Target;
657
139
  return &Target;
658
139
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)0, false> >()
Line
Count
Source
655
95
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
656
95
  static MIPS<ELFT> Target;
657
95
  return &Target;
658
95
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)1, false> >()
Line
Count
Source
655
14
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
656
14
  static MIPS<ELFT> Target;
657
14
  return &Target;
658
14
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)0, true> >()
Line
Count
Source
655
28
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
656
28
  static MIPS<ELFT> Target;
657
28
  return &Target;
658
28
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)1, true> >()
Line
Count
Source
655
2
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
656
2
  static MIPS<ELFT> Target;
657
2
  return &Target;
658
2
}
659
660
template TargetInfo *elf::getMipsTargetInfo<ELF32LE>();
661
template TargetInfo *elf::getMipsTargetInfo<ELF32BE>();
662
template TargetInfo *elf::getMipsTargetInfo<ELF64LE>();
663
template TargetInfo *elf::getMipsTargetInfo<ELF64BE>();