Coverage Report

Created: 2019-05-22 02:55

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/COFF/Chunks.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- Chunks.cpp ---------------------------------------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "Chunks.h"
10
#include "InputFiles.h"
11
#include "Symbols.h"
12
#include "Writer.h"
13
#include "SymbolTable.h"
14
#include "lld/Common/ErrorHandler.h"
15
#include "llvm/ADT/Twine.h"
16
#include "llvm/BinaryFormat/COFF.h"
17
#include "llvm/Object/COFF.h"
18
#include "llvm/Support/Debug.h"
19
#include "llvm/Support/Endian.h"
20
#include "llvm/Support/raw_ostream.h"
21
#include <algorithm>
22
23
using namespace llvm;
24
using namespace llvm::object;
25
using namespace llvm::support::endian;
26
using namespace llvm::COFF;
27
using llvm::support::ulittle32_t;
28
29
namespace lld {
30
namespace coff {
31
32
SectionChunk::SectionChunk(ObjFile *F, const coff_section *H)
33
1.23k
    : Chunk(SectionKind), File(F), Header(H), Repl(this) {
34
1.23k
  // Initialize Relocs.
35
1.23k
  setRelocs(File->getCOFFObj()->getRelocations(Header));
36
1.23k
37
1.23k
  // Initialize SectionName.
38
1.23k
  StringRef SectionName;
39
1.23k
  if (Expected<StringRef> E = File->getCOFFObj()->getSectionName(Header))
40
1.23k
    SectionName = *E;
41
1.23k
  SectionNameData = SectionName.data();
42
1.23k
  SectionNameSize = SectionName.size();
43
1.23k
44
1.23k
  Alignment = Header->getAlignment();
45
1.23k
46
1.23k
  // If linker GC is disabled, every chunk starts out alive.  If linker GC is
47
1.23k
  // enabled, treat non-comdat sections as roots. Generally optimized object
48
1.23k
  // files will be built with -ffunction-sections or /Gy, so most things worth
49
1.23k
  // stripping will be in a comdat.
50
1.23k
  Live = !Config->DoGC || 
!isCOMDAT()955
;
51
1.23k
}
52
53
// SectionChunk is one of the most frequently allocated classes, so it is
54
// important to keep it as compact as possible. As of this writing, the number
55
// below is the size of this class on x64 platforms.
56
static_assert(sizeof(SectionChunk) <= 112, "SectionChunk grew unexpectedly");
57
58
120
static void add16(uint8_t *P, int16_t V) { write16le(P, read16le(P) + V); }
59
470
static void add32(uint8_t *P, int32_t V) { write32le(P, read32le(P) + V); }
60
95
static void add64(uint8_t *P, int64_t V) { write64le(P, read64le(P) + V); }
61
82
static void or16(uint8_t *P, uint16_t V) { write16le(P, read16le(P) | V); }
62
7
static void or32(uint8_t *P, uint32_t V) { write32le(P, read32le(P) | V); }
63
64
// Verify that given sections are appropriate targets for SECREL
65
// relocations. This check is relaxed because unfortunately debug
66
// sections have section-relative relocations against absolute symbols.
67
120
static bool checkSecRel(const SectionChunk *Sec, OutputSection *OS) {
68
120
  if (OS)
69
119
    return true;
70
1
  if (Sec->isCodeView())
71
1
    return false;
72
0
  error("SECREL relocation cannot be applied to absolute symbols");
73
0
  return false;
74
0
}
75
76
static void applySecRel(const SectionChunk *Sec, uint8_t *Off,
77
120
                        OutputSection *OS, uint64_t S) {
78
120
  if (!checkSecRel(Sec, OS))
79
1
    return;
80
119
  uint64_t SecRel = S - OS->getRVA();
81
119
  if (SecRel > UINT32_MAX) {
82
0
    error("overflow in SECREL relocation in section: " + Sec->getSectionName());
83
0
    return;
84
0
  }
85
119
  add32(Off, SecRel);
86
119
}
87
88
120
static void applySecIdx(uint8_t *Off, OutputSection *OS) {
89
120
  // Absolute symbol doesn't have section index, but section index relocation
90
120
  // against absolute symbol should be resolved to one plus the last output
91
120
  // section index. This is required for compatibility with MSVC.
92
120
  if (OS)
93
118
    add16(Off, OS->SectionIndex);
94
2
  else
95
2
    add16(Off, DefinedAbsolute::NumOutputSections + 1);
96
120
}
97
98
void SectionChunk::applyRelX64(uint8_t *Off, uint16_t Type, OutputSection *OS,
99
512
                               uint64_t S, uint64_t P) const {
100
512
  switch (Type) {
101
512
  
case IMAGE_REL_AMD64_ADDR32: add32(Off, S + Config->ImageBase); break21
;
102
512
  
case IMAGE_REL_AMD64_ADDR64: add64(Off, S + Config->ImageBase); break95
;
103
512
  
case IMAGE_REL_AMD64_ADDR32NB: add32(Off, S); break129
;
104
512
  
case IMAGE_REL_AMD64_REL32: add32(Off, S - P - 4); break124
;
105
512
  
case IMAGE_REL_AMD64_REL32_1: add32(Off, S - P - 5); break1
;
106
512
  
case IMAGE_REL_AMD64_REL32_2: add32(Off, S - P - 6); break1
;
107
512
  
case IMAGE_REL_AMD64_REL32_3: add32(Off, S - P - 7); break1
;
108
512
  
case IMAGE_REL_AMD64_REL32_4: add32(Off, S - P - 8); break1
;
109
512
  
case IMAGE_REL_AMD64_REL32_5: add32(Off, S - P - 9); break1
;
110
512
  
case IMAGE_REL_AMD64_SECTION: applySecIdx(Off, OS); break69
;
111
512
  
case IMAGE_REL_AMD64_SECREL: applySecRel(this, Off, OS, S); break68
;
112
512
  default:
113
0
    error("unsupported relocation type 0x" + Twine::utohexstr(Type) + " in " +
114
0
          toString(File));
115
512
  }
116
512
}
117
118
void SectionChunk::applyRelX86(uint8_t *Off, uint16_t Type, OutputSection *OS,
119
169
                               uint64_t S, uint64_t P) const {
120
169
  switch (Type) {
121
169
  
case IMAGE_REL_I386_ABSOLUTE: break0
;
122
169
  
case IMAGE_REL_I386_DIR32: add32(Off, S + Config->ImageBase); break30
;
123
169
  
case IMAGE_REL_I386_DIR32NB: add32(Off, S); break11
;
124
169
  
case IMAGE_REL_I386_REL32: add32(Off, S - P - 4); break26
;
125
169
  
case IMAGE_REL_I386_SECTION: applySecIdx(Off, OS); break51
;
126
169
  
case IMAGE_REL_I386_SECREL: applySecRel(this, Off, OS, S); break51
;
127
169
  default:
128
0
    error("unsupported relocation type 0x" + Twine::utohexstr(Type) + " in " +
129
0
          toString(File));
130
169
  }
131
169
}
132
133
74
static void applyMOV(uint8_t *Off, uint16_t V) {
134
74
  write16le(Off, (read16le(Off) & 0xfbf0) | ((V & 0x800) >> 1) | ((V >> 12) & 0xf));
135
74
  write16le(Off + 2, (read16le(Off + 2) & 0x8f00) | ((V & 0x700) << 4) | (V & 0xff));
136
74
}
137
138
74
static uint16_t readMOV(uint8_t *Off, bool MOVT) {
139
74
  uint16_t Op1 = read16le(Off);
140
74
  if ((Op1 & 0xfbf0) != (MOVT ? 
0xf2c037
:
0xf24037
))
141
1
    error("unexpected instruction in " + Twine(MOVT ? "MOVT" : 
"MOVW"0
) +
142
1
          " instruction in MOV32T relocation");
143
74
  uint16_t Op2 = read16le(Off + 2);
144
74
  if ((Op2 & 0x8000) != 0)
145
1
    error("unexpected instruction in " + Twine(MOVT ? "MOVT" : 
"MOVW"0
) +
146
1
          " instruction in MOV32T relocation");
147
74
  return (Op2 & 0x00ff) | ((Op2 >> 4) & 0x0700) | ((Op1 << 1) & 0x0800) |
148
74
         ((Op1 & 0x000f) << 12);
149
74
}
150
151
37
void applyMOV32T(uint8_t *Off, uint32_t V) {
152
37
  uint16_t ImmW = readMOV(Off, false);    // read MOVW operand
153
37
  uint16_t ImmT = readMOV(Off + 4, true); // read MOVT operand
154
37
  uint32_t Imm = ImmW | (ImmT << 16);
155
37
  V += Imm;                         // add the immediate offset
156
37
  applyMOV(Off, V);           // set MOVW operand
157
37
  applyMOV(Off + 4, V >> 16); // set MOVT operand
158
37
}
159
160
38
static void applyBranch20T(uint8_t *Off, int32_t V) {
161
38
  if (!isInt<21>(V))
162
0
    error("relocation out of range");
163
38
  uint32_t S = V < 0 ? 
10
: 0;
164
38
  uint32_t J1 = (V >> 19) & 1;
165
38
  uint32_t J2 = (V >> 18) & 1;
166
38
  or16(Off, (S << 10) | ((V >> 12) & 0x3f));
167
38
  or16(Off + 2, (J1 << 13) | (J2 << 11) | ((V >> 1) & 0x7ff));
168
38
}
169
170
6
void applyBranch24T(uint8_t *Off, int32_t V) {
171
6
  if (!isInt<25>(V))
172
0
    error("relocation out of range");
173
6
  uint32_t S = V < 0 ? 
12
:
04
;
174
6
  uint32_t J1 = ((~V >> 23) & 1) ^ S;
175
6
  uint32_t J2 = ((~V >> 22) & 1) ^ S;
176
6
  or16(Off, (S << 10) | ((V >> 12) & 0x3ff));
177
6
  // Clear out the J1 and J2 bits which may be set.
178
6
  write16le(Off + 2, (read16le(Off + 2) & 0xd000) | (J1 << 13) | (J2 << 11) | ((V >> 1) & 0x7ff));
179
6
}
180
181
void SectionChunk::applyRelARM(uint8_t *Off, uint16_t Type, OutputSection *OS,
182
52
                               uint64_t S, uint64_t P) const {
183
52
  // Pointer to thumb code must have the LSB set.
184
52
  uint64_t SX = S;
185
52
  if (OS && (OS->Header.Characteristics & IMAGE_SCN_MEM_EXECUTE))
186
48
    SX |= 1;
187
52
  switch (Type) {
188
52
  
case IMAGE_REL_ARM_ADDR32: add32(Off, SX + Config->ImageBase); break1
;
189
52
  
case IMAGE_REL_ARM_ADDR32NB: add32(Off, SX); break1
;
190
52
  
case IMAGE_REL_ARM_MOV32T: applyMOV32T(Off, SX + Config->ImageBase); break6
;
191
52
  
case IMAGE_REL_ARM_BRANCH20T: applyBranch20T(Off, SX - P - 4); break38
;
192
52
  
case IMAGE_REL_ARM_BRANCH24T: applyBranch24T(Off, SX - P - 4); break3
;
193
52
  
case IMAGE_REL_ARM_BLX23T: applyBranch24T(Off, SX - P - 4); break2
;
194
52
  
case IMAGE_REL_ARM_SECTION: applySecIdx(Off, OS); break0
;
195
52
  
case IMAGE_REL_ARM_SECREL: applySecRel(this, Off, OS, S); break1
;
196
52
  
case IMAGE_REL_ARM_REL32: add32(Off, SX - P - 4); break0
;
197
52
  default:
198
0
    error("unsupported relocation type 0x" + Twine::utohexstr(Type) + " in " +
199
0
          toString(File));
200
52
  }
201
52
}
202
203
// Interpret the existing immediate value as a byte offset to the
204
// target symbol, then update the instruction with the immediate as
205
// the page offset from the current instruction to the target.
206
3
void applyArm64Addr(uint8_t *Off, uint64_t S, uint64_t P, int Shift) {
207
3
  uint32_t Orig = read32le(Off);
208
3
  uint64_t Imm = ((Orig >> 29) & 0x3) | ((Orig >> 3) & 0x1FFFFC);
209
3
  S += Imm;
210
3
  Imm = (S >> Shift) - (P >> Shift);
211
3
  uint32_t ImmLo = (Imm & 0x3) << 29;
212
3
  uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
213
3
  uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
214
3
  write32le(Off, (Orig & ~Mask) | ImmLo | ImmHi);
215
3
}
216
217
// Update the immediate field in a AARCH64 ldr, str, and add instruction.
218
// Optionally limit the range of the written immediate by one or more bits
219
// (RangeLimit).
220
3
void applyArm64Imm(uint8_t *Off, uint64_t Imm, uint32_t RangeLimit) {
221
3
  uint32_t Orig = read32le(Off);
222
3
  Imm += (Orig >> 10) & 0xFFF;
223
3
  Orig &= ~(0xFFF << 10);
224
3
  write32le(Off, Orig | ((Imm & (0xFFF >> RangeLimit)) << 10));
225
3
}
226
227
// Add the 12 bit page offset to the existing immediate.
228
// Ldr/str instructions store the opcode immediate scaled
229
// by the load/store size (giving a larger range for larger
230
// loads/stores). The immediate is always (both before and after
231
// fixing up the relocation) stored scaled similarly.
232
// Even if larger loads/stores have a larger range, limit the
233
// effective offset to 12 bit, since it is intended to be a
234
// page offset.
235
3
static void applyArm64Ldr(uint8_t *Off, uint64_t Imm) {
236
3
  uint32_t Orig = read32le(Off);
237
3
  uint32_t Size = Orig >> 30;
238
3
  // 0x04000000 indicates SIMD/FP registers
239
3
  // 0x00800000 indicates 128 bit
240
3
  if ((Orig & 0x4800000) == 0x4800000)
241
0
    Size += 4;
242
3
  if ((Imm & ((1 << Size) - 1)) != 0)
243
0
    error("misaligned ldr/str offset");
244
3
  applyArm64Imm(Off, Imm >> Size, Size);
245
3
}
246
247
static void applySecRelLow12A(const SectionChunk *Sec, uint8_t *Off,
248
0
                              OutputSection *OS, uint64_t S) {
249
0
  if (checkSecRel(Sec, OS))
250
0
    applyArm64Imm(Off, (S - OS->getRVA()) & 0xfff, 0);
251
0
}
252
253
static void applySecRelHigh12A(const SectionChunk *Sec, uint8_t *Off,
254
0
                               OutputSection *OS, uint64_t S) {
255
0
  if (!checkSecRel(Sec, OS))
256
0
    return;
257
0
  uint64_t SecRel = (S - OS->getRVA()) >> 12;
258
0
  if (0xfff < SecRel) {
259
0
    error("overflow in SECREL_HIGH12A relocation in section: " +
260
0
          Sec->getSectionName());
261
0
    return;
262
0
  }
263
0
  applyArm64Imm(Off, SecRel & 0xfff, 0);
264
0
}
265
266
static void applySecRelLdr(const SectionChunk *Sec, uint8_t *Off,
267
0
                           OutputSection *OS, uint64_t S) {
268
0
  if (checkSecRel(Sec, OS))
269
0
    applyArm64Ldr(Off, (S - OS->getRVA()) & 0xfff);
270
0
}
271
272
7
void applyArm64Branch26(uint8_t *Off, int64_t V) {
273
7
  if (!isInt<28>(V))
274
0
    error("relocation out of range");
275
7
  or32(Off, (V & 0x0FFFFFFC) >> 2);
276
7
}
277
278
0
static void applyArm64Branch19(uint8_t *Off, int64_t V) {
279
0
  if (!isInt<21>(V))
280
0
    error("relocation out of range");
281
0
  or32(Off, (V & 0x001FFFFC) << 3);
282
0
}
283
284
0
static void applyArm64Branch14(uint8_t *Off, int64_t V) {
285
0
  if (!isInt<16>(V))
286
0
    error("relocation out of range");
287
0
  or32(Off, (V & 0x0000FFFC) << 3);
288
0
}
289
290
void SectionChunk::applyRelARM64(uint8_t *Off, uint16_t Type, OutputSection *OS,
291
11
                                 uint64_t S, uint64_t P) const {
292
11
  switch (Type) {
293
11
  
case IMAGE_REL_ARM64_PAGEBASE_REL21: applyArm64Addr(Off, S, P, 12); break1
;
294
11
  
case IMAGE_REL_ARM64_REL21: applyArm64Addr(Off, S, P, 0); break0
;
295
11
  
case IMAGE_REL_ARM64_PAGEOFFSET_12A: applyArm64Imm(Off, S & 0xfff, 0); break0
;
296
11
  
case IMAGE_REL_ARM64_PAGEOFFSET_12L: applyArm64Ldr(Off, S & 0xfff); break1
;
297
11
  
case IMAGE_REL_ARM64_BRANCH26: applyArm64Branch26(Off, S - P); break7
;
298
11
  
case IMAGE_REL_ARM64_BRANCH19: applyArm64Branch19(Off, S - P); break0
;
299
11
  
case IMAGE_REL_ARM64_BRANCH14: applyArm64Branch14(Off, S - P); break0
;
300
11
  
case IMAGE_REL_ARM64_ADDR32: add32(Off, S + Config->ImageBase); break0
;
301
11
  
case IMAGE_REL_ARM64_ADDR32NB: add32(Off, S); break2
;
302
11
  
case IMAGE_REL_ARM64_ADDR64: add64(Off, S + Config->ImageBase); break0
;
303
11
  
case IMAGE_REL_ARM64_SECREL: applySecRel(this, Off, OS, S); break0
;
304
11
  
case IMAGE_REL_ARM64_SECREL_LOW12A: applySecRelLow12A(this, Off, OS, S); break0
;
305
11
  
case IMAGE_REL_ARM64_SECREL_HIGH12A: applySecRelHigh12A(this, Off, OS, S); break0
;
306
11
  
case IMAGE_REL_ARM64_SECREL_LOW12L: applySecRelLdr(this, Off, OS, S); break0
;
307
11
  
case IMAGE_REL_ARM64_SECTION: applySecIdx(Off, OS); break0
;
308
11
  
case IMAGE_REL_ARM64_REL32: add32(Off, S - P - 4); break0
;
309
11
  default:
310
0
    error("unsupported relocation type 0x" + Twine::utohexstr(Type) + " in " +
311
0
          toString(File));
312
11
  }
313
11
}
314
315
static void maybeReportRelocationToDiscarded(const SectionChunk *FromChunk,
316
                                             Defined *Sym,
317
5
                                             const coff_relocation &Rel) {
318
5
  // Don't report these errors when the relocation comes from a debug info
319
5
  // section or in mingw mode. MinGW mode object files (built by GCC) can
320
5
  // have leftover sections with relocations against discarded comdat
321
5
  // sections. Such sections are left as is, with relocations untouched.
322
5
  if (FromChunk->isCodeView() || FromChunk->isDWARF() || 
Config->MinGW2
)
323
3
    return;
324
2
325
2
  // Get the name of the symbol. If it's null, it was discarded early, so we
326
2
  // have to go back to the object file.
327
2
  ObjFile *File = FromChunk->File;
328
2
  StringRef Name;
329
2
  if (Sym) {
330
0
    Name = Sym->getName();
331
2
  } else {
332
2
    COFFSymbolRef COFFSym =
333
2
        check(File->getCOFFObj()->getSymbol(Rel.SymbolTableIndex));
334
2
    File->getCOFFObj()->getSymbolName(COFFSym, Name);
335
2
  }
336
2
337
2
  error("relocation against symbol in discarded section: " + Name +
338
2
        getSymbolLocations(File, Rel.SymbolTableIndex));
339
2
}
340
341
727
void SectionChunk::writeTo(uint8_t *Buf) const {
342
727
  if (!hasData())
343
37
    return;
344
690
  // Copy section contents from source object file to output file.
345
690
  ArrayRef<uint8_t> A = getContents();
346
690
  if (!A.empty())
347
618
    memcpy(Buf, A.data(), A.size());
348
690
349
690
  // Apply relocations.
350
690
  size_t InputSize = getSize();
351
1.43k
  for (size_t I = 0, E = RelocsSize; I < E; 
I++749
) {
352
750
    const coff_relocation &Rel = RelocsData[I];
353
750
354
750
    // Check for an invalid relocation offset. This check isn't perfect, because
355
750
    // we don't have the relocation size, which is only known after checking the
356
750
    // machine and relocation type. As a result, a relocation may overwrite the
357
750
    // beginning of the following input section.
358
750
    if (Rel.VirtualAddress >= InputSize) {
359
1
      error("relocation points beyond the end of its parent section");
360
1
      continue;
361
1
    }
362
749
363
749
    uint8_t *Off = Buf + Rel.VirtualAddress;
364
749
365
749
    auto *Sym =
366
749
        dyn_cast_or_null<Defined>(File->getSymbol(Rel.SymbolTableIndex));
367
749
368
749
    // Get the output section of the symbol for this relocation.  The output
369
749
    // section is needed to compute SECREL and SECTION relocations used in debug
370
749
    // info.
371
749
    Chunk *C = Sym ? 
Sym->getChunk()744
:
nullptr5
;
372
749
    OutputSection *OS = C ? 
C->getOutputSection()695
:
nullptr54
;
373
749
374
749
    // Skip the relocation if it refers to a discarded section, and diagnose it
375
749
    // as an error if appropriate. If a symbol was discarded early, it may be
376
749
    // null. If it was discarded late, the output section will be null, unless
377
749
    // it was an absolute or synthetic symbol.
378
749
    if (!Sym ||
379
749
        
(744
!OS744
&&
!isa<DefinedAbsolute>(Sym)49
&&
!isa<DefinedSynthetic>(Sym)9
)) {
380
5
      maybeReportRelocationToDiscarded(this, Sym, Rel);
381
5
      continue;
382
5
    }
383
744
384
744
    uint64_t S = Sym->getRVA();
385
744
386
744
    // Compute the RVA of the relocation for relative relocations.
387
744
    uint64_t P = RVA + Rel.VirtualAddress;
388
744
    switch (Config->Machine) {
389
744
    case AMD64:
390
512
      applyRelX64(Off, Rel.Type, OS, S, P);
391
512
      break;
392
744
    case I386:
393
169
      applyRelX86(Off, Rel.Type, OS, S, P);
394
169
      break;
395
744
    case ARMNT:
396
52
      applyRelARM(Off, Rel.Type, OS, S, P);
397
52
      break;
398
744
    case ARM64:
399
11
      applyRelARM64(Off, Rel.Type, OS, S, P);
400
11
      break;
401
744
    default:
402
0
      llvm_unreachable("unknown machine type");
403
744
    }
404
744
  }
405
690
}
406
407
52
void SectionChunk::addAssociative(SectionChunk *Child) {
408
52
  // Insert this child at the head of the list.
409
52
  assert(Child->AssocChildren == nullptr &&
410
52
         "associated sections cannot have their own associated children");
411
52
  Child->AssocChildren = AssocChildren;
412
52
  AssocChildren = Child;
413
52
}
414
415
574
static uint8_t getBaserelType(const coff_relocation &Rel) {
416
574
  switch (Config->Machine) {
417
574
  case AMD64:
418
382
    if (Rel.Type == IMAGE_REL_AMD64_ADDR64)
419
95
      return IMAGE_REL_BASED_DIR64;
420
287
    return IMAGE_REL_BASED_ABSOLUTE;
421
287
  case I386:
422
54
    if (Rel.Type == IMAGE_REL_I386_DIR32)
423
29
      return IMAGE_REL_BASED_HIGHLOW;
424
25
    return IMAGE_REL_BASED_ABSOLUTE;
425
127
  case ARMNT:
426
127
    if (Rel.Type == IMAGE_REL_ARM_ADDR32)
427
1
      return IMAGE_REL_BASED_HIGHLOW;
428
126
    if (Rel.Type == IMAGE_REL_ARM_MOV32T)
429
6
      return IMAGE_REL_BASED_ARM_MOV32T;
430
120
    return IMAGE_REL_BASED_ABSOLUTE;
431
120
  case ARM64:
432
11
    if (Rel.Type == IMAGE_REL_ARM64_ADDR64)
433
0
      return IMAGE_REL_BASED_DIR64;
434
11
    return IMAGE_REL_BASED_ABSOLUTE;
435
11
  default:
436
0
    llvm_unreachable("unknown machine type");
437
574
  }
438
574
}
439
440
// Windows-specific.
441
// Collect all locations that contain absolute addresses, which need to be
442
// fixed by the loader if load-time relocation is needed.
443
// Only called when base relocation is enabled.
444
1.07k
void SectionChunk::getBaserels(std::vector<Baserel> *Res) {
445
1.64k
  for (size_t I = 0, E = RelocsSize; I < E; 
I++574
) {
446
574
    const coff_relocation &Rel = RelocsData[I];
447
574
    uint8_t Ty = getBaserelType(Rel);
448
574
    if (Ty == IMAGE_REL_BASED_ABSOLUTE)
449
443
      continue;
450
131
    Symbol *Target = File->getSymbol(Rel.SymbolTableIndex);
451
131
    if (!Target || 
isa<DefinedAbsolute>(Target)130
)
452
24
      continue;
453
107
    Res->emplace_back(RVA + Rel.VirtualAddress, Ty);
454
107
  }
455
1.07k
}
456
457
// MinGW specific.
458
// Check whether a static relocation of type Type can be deferred and
459
// handled at runtime as a pseudo relocation (for references to a module
460
// local variable, which turned out to actually need to be imported from
461
// another DLL) This returns the size the relocation is supposed to update,
462
// in bits, or 0 if the relocation cannot be handled as a runtime pseudo
463
// relocation.
464
5
static int getRuntimePseudoRelocSize(uint16_t Type) {
465
5
  // Relocations that either contain an absolute address, or a plain
466
5
  // relative offset, since the runtime pseudo reloc implementation
467
5
  // adds 8/16/32/64 bit values to a memory address.
468
5
  //
469
5
  // Given a pseudo relocation entry,
470
5
  //
471
5
  // typedef struct {
472
5
  //   DWORD sym;
473
5
  //   DWORD target;
474
5
  //   DWORD flags;
475
5
  // } runtime_pseudo_reloc_item_v2;
476
5
  //
477
5
  // the runtime relocation performs this adjustment:
478
5
  //     *(base + .target) += *(base + .sym) - (base + .sym)
479
5
  //
480
5
  // This works for both absolute addresses (IMAGE_REL_*_ADDR32/64,
481
5
  // IMAGE_REL_I386_DIR32, where the memory location initially contains
482
5
  // the address of the IAT slot, and for relative addresses (IMAGE_REL*_REL32),
483
5
  // where the memory location originally contains the relative offset to the
484
5
  // IAT slot.
485
5
  //
486
5
  // This requires the target address to be writable, either directly out of
487
5
  // the image, or temporarily changed at runtime with VirtualProtect.
488
5
  // Since this only operates on direct address values, it doesn't work for
489
5
  // ARM/ARM64 relocations, other than the plain ADDR32/ADDR64 relocations.
490
5
  switch (Config->Machine) {
491
5
  case AMD64:
492
2
    switch (Type) {
493
2
    case IMAGE_REL_AMD64_ADDR64:
494
1
      return 64;
495
2
    case IMAGE_REL_AMD64_ADDR32:
496
1
    case IMAGE_REL_AMD64_REL32:
497
1
    case IMAGE_REL_AMD64_REL32_1:
498
1
    case IMAGE_REL_AMD64_REL32_2:
499
1
    case IMAGE_REL_AMD64_REL32_3:
500
1
    case IMAGE_REL_AMD64_REL32_4:
501
1
    case IMAGE_REL_AMD64_REL32_5:
502
1
      return 32;
503
1
    default:
504
0
      return 0;
505
0
    }
506
0
  case I386:
507
0
    switch (Type) {
508
0
    case IMAGE_REL_I386_DIR32:
509
0
    case IMAGE_REL_I386_REL32:
510
0
      return 32;
511
0
    default:
512
0
      return 0;
513
0
    }
514
1
  case ARMNT:
515
1
    switch (Type) {
516
1
    case IMAGE_REL_ARM_ADDR32:
517
0
      return 32;
518
1
    default:
519
1
      return 0;
520
0
    }
521
2
  case ARM64:
522
2
    switch (Type) {
523
2
    case IMAGE_REL_ARM64_ADDR64:
524
0
      return 64;
525
2
    case IMAGE_REL_ARM64_ADDR32:
526
0
      return 32;
527
2
    default:
528
2
      return 0;
529
0
    }
530
0
  default:
531
0
    llvm_unreachable("unknown machine type");
532
5
  }
533
5
}
534
535
// MinGW specific.
536
// Append information to the provided vector about all relocations that
537
// need to be handled at runtime as runtime pseudo relocations (references
538
// to a module local variable, which turned out to actually need to be
539
// imported from another DLL).
540
void SectionChunk::getRuntimePseudoRelocs(
541
93
    std::vector<RuntimePseudoReloc> &Res) {
542
93
  for (const coff_relocation &Rel : getRelocs()) {
543
61
    auto *Target =
544
61
        dyn_cast_or_null<Defined>(File->getSymbol(Rel.SymbolTableIndex));
545
61
    if (!Target || !Target->IsRuntimePseudoReloc)
546
56
      continue;
547
5
    int SizeInBits = getRuntimePseudoRelocSize(Rel.Type);
548
5
    if (SizeInBits == 0) {
549
3
      error("unable to automatically import from " + Target->getName() +
550
3
            " with relocation type " +
551
3
            File->getCOFFObj()->getRelocationTypeName(Rel.Type) + " in " +
552
3
            toString(File));
553
3
      continue;
554
3
    }
555
2
    // SizeInBits is used to initialize the Flags field; currently no
556
2
    // other flags are defined.
557
2
    Res.emplace_back(
558
2
        RuntimePseudoReloc(Target, this, Rel.VirtualAddress, SizeInBits));
559
2
  }
560
93
}
561
562
1.82k
bool SectionChunk::hasData() const {
563
1.82k
  return !(Header->Characteristics & IMAGE_SCN_CNT_UNINITIALIZED_DATA);
564
1.82k
}
565
566
1.94k
uint32_t SectionChunk::getOutputCharacteristics() const {
567
1.94k
  return Header->Characteristics & (PermMask | TypeMask);
568
1.94k
}
569
570
1.75k
bool SectionChunk::isCOMDAT() const {
571
1.75k
  return Header->Characteristics & IMAGE_SCN_LNK_COMDAT;
572
1.75k
}
573
574
7
void SectionChunk::printDiscardedMessage() const {
575
7
  // Removed by dead-stripping. If it's removed by ICF, ICF already
576
7
  // printed out the name, so don't repeat that here.
577
7
  if (Sym && this == Repl)
578
2
    message("Discarded " + Sym->getName());
579
7
}
580
581
27
StringRef SectionChunk::getDebugName() {
582
27
  if (Sym)
583
23
    return Sym->getName();
584
4
  return "";
585
4
}
586
587
1.11k
ArrayRef<uint8_t> SectionChunk::getContents() const {
588
1.11k
  ArrayRef<uint8_t> A;
589
1.11k
  cantFail(File->getCOFFObj()->getSectionContents(Header, A));
590
1.11k
  return A;
591
1.11k
}
592
593
77
ArrayRef<uint8_t> SectionChunk::consumeDebugMagic() {
594
77
  assert(isCodeView());
595
77
  return consumeDebugMagic(getContents(), getSectionName());
596
77
}
597
598
ArrayRef<uint8_t> SectionChunk::consumeDebugMagic(ArrayRef<uint8_t> Data,
599
126
                                                  StringRef SectionName) {
600
126
  if (Data.empty())
601
1
    return {};
602
125
603
125
  // First 4 bytes are section magic.
604
125
  if (Data.size() < 4)
605
0
    fatal("the section is too short: " + SectionName);
606
125
607
125
  if (!SectionName.startswith(".debug$"))
608
0
    fatal("invalid section: " + SectionName);
609
125
610
125
  unsigned Magic = support::endian::read32le(Data.data());
611
125
  unsigned ExpectedMagic = SectionName == ".debug$H"
612
125
                               ? 
DEBUG_HASHES_SECTION_MAGIC0
613
125
                               : DEBUG_SECTION_MAGIC;
614
125
  if (Magic != ExpectedMagic)
615
0
    fatal("section: " + SectionName + " has an invalid magic: " + Twine(Magic));
616
125
  return Data.slice(4);
617
125
}
618
619
SectionChunk *SectionChunk::findByName(ArrayRef<SectionChunk *> Sections,
620
513
                                       StringRef Name) {
621
513
  for (SectionChunk *C : Sections)
622
189
    if (C->getSectionName() == Name)
623
80
      return C;
624
513
  
return nullptr433
;
625
513
}
626
627
14
void SectionChunk::replace(SectionChunk *Other) {
628
14
  Alignment = std::max(Alignment, Other->Alignment);
629
14
  Other->Repl = Repl;
630
14
  Other->Live = false;
631
14
}
632
633
24
uint32_t SectionChunk::getSectionNumber() const {
634
24
  DataRefImpl R;
635
24
  R.p = reinterpret_cast<uintptr_t>(Header);
636
24
  SectionRef S(R, File->getCOFFObj());
637
24
  return S.getIndex() + 1;
638
24
}
639
640
11
CommonChunk::CommonChunk(const COFFSymbolRef S) : Sym(S) {
641
11
  // Common symbols are aligned on natural boundaries up to 32 bytes.
642
11
  // This is what MSVC link.exe does.
643
11
  Alignment = std::min(uint64_t(32), PowerOf2Ceil(Sym.getValue()));
644
11
}
645
646
11
uint32_t CommonChunk::getOutputCharacteristics() const {
647
11
  return IMAGE_SCN_CNT_UNINITIALIZED_DATA | IMAGE_SCN_MEM_READ |
648
11
         IMAGE_SCN_MEM_WRITE;
649
11
}
650
651
180
void StringChunk::writeTo(uint8_t *Buf) const {
652
180
  memcpy(Buf, Str.data(), Str.size());
653
180
  Buf[Str.size()] = '\0';
654
180
}
655
656
32
ImportThunkChunkX64::ImportThunkChunkX64(Defined *S) : ImpSymbol(S) {
657
32
  // Intel Optimization Manual says that all branch targets
658
32
  // should be 16-byte aligned. MSVC linker does this too.
659
32
  Alignment = 16;
660
32
}
661
662
30
void ImportThunkChunkX64::writeTo(uint8_t *Buf) const {
663
30
  memcpy(Buf, ImportThunkX86, sizeof(ImportThunkX86));
664
30
  // The first two bytes is a JMP instruction. Fill its operand.
665
30
  write32le(Buf + 2, ImpSymbol->getRVA() - RVA - getSize());
666
30
}
667
668
14
void ImportThunkChunkX86::getBaserels(std::vector<Baserel> *Res) {
669
14
  Res->emplace_back(getRVA() + 2);
670
14
}
671
672
16
void ImportThunkChunkX86::writeTo(uint8_t *Buf) const {
673
16
  memcpy(Buf, ImportThunkX86, sizeof(ImportThunkX86));
674
16
  // The first two bytes is a JMP instruction. Fill its operand.
675
16
  write32le(Buf + 2,
676
16
            ImpSymbol->getRVA() + Config->ImageBase);
677
16
}
678
679
0
void ImportThunkChunkARM::getBaserels(std::vector<Baserel> *Res) {
680
0
  Res->emplace_back(getRVA(), IMAGE_REL_BASED_ARM_MOV32T);
681
0
}
682
683
0
void ImportThunkChunkARM::writeTo(uint8_t *Buf) const {
684
0
  memcpy(Buf, ImportThunkARM, sizeof(ImportThunkARM));
685
0
  // Fix mov.w and mov.t operands.
686
0
  applyMOV32T(Buf, ImpSymbol->getRVA() + Config->ImageBase);
687
0
}
688
689
2
void ImportThunkChunkARM64::writeTo(uint8_t *Buf) const {
690
2
  int64_t Off = ImpSymbol->getRVA() & 0xfff;
691
2
  memcpy(Buf, ImportThunkARM64, sizeof(ImportThunkARM64));
692
2
  applyArm64Addr(Buf, ImpSymbol->getRVA(), RVA, 12);
693
2
  applyArm64Ldr(Buf + 4, Off);
694
2
}
695
696
// A Thumb2, PIC, non-interworking range extension thunk.
697
const uint8_t ArmThunk[] = {
698
    0x40, 0xf2, 0x00, 0x0c, // P:  movw ip,:lower16:S - (P + (L1-P) + 4)
699
    0xc0, 0xf2, 0x00, 0x0c, //     movt ip,:upper16:S - (P + (L1-P) + 4)
700
    0xe7, 0x44,             // L1: add  pc, ip
701
};
702
703
142
size_t RangeExtensionThunkARM::getSize() const {
704
142
  assert(Config->Machine == ARMNT);
705
142
  return sizeof(ArmThunk);
706
142
}
707
708
29
void RangeExtensionThunkARM::writeTo(uint8_t *Buf) const {
709
29
  assert(Config->Machine == ARMNT);
710
29
  uint64_t Offset = Target->getRVA() - RVA - 12;
711
29
  memcpy(Buf, ArmThunk, sizeof(ArmThunk));
712
29
  applyMOV32T(Buf, uint32_t(Offset));
713
29
}
714
715
// A position independent ARM64 adrp+add thunk, with a maximum range of
716
// +/- 4 GB, which is enough for any PE-COFF.
717
const uint8_t Arm64Thunk[] = {
718
    0x10, 0x00, 0x00, 0x90, // adrp x16, Dest
719
    0x10, 0x02, 0x00, 0x91, // add  x16, x16, :lo12:Dest
720
    0x00, 0x02, 0x1f, 0xd6, // br   x16
721
};
722
723
0
size_t RangeExtensionThunkARM64::getSize() const {
724
0
  assert(Config->Machine == ARM64);
725
0
  return sizeof(Arm64Thunk);
726
0
}
727
728
0
void RangeExtensionThunkARM64::writeTo(uint8_t *Buf) const {
729
0
  assert(Config->Machine == ARM64);
730
0
  memcpy(Buf, Arm64Thunk, sizeof(Arm64Thunk));
731
0
  applyArm64Addr(Buf + 0, Target->getRVA(), RVA, 12);
732
0
  applyArm64Imm(Buf + 4, Target->getRVA() & 0xfff, 0);
733
0
}
734
735
3
void LocalImportChunk::getBaserels(std::vector<Baserel> *Res) {
736
3
  Res->emplace_back(getRVA());
737
3
}
738
739
4
size_t LocalImportChunk::getSize() const { return Config->Wordsize; }
740
741
3
void LocalImportChunk::writeTo(uint8_t *Buf) const {
742
3
  if (Config->is64()) {
743
2
    write64le(Buf, Sym->getRVA() + Config->ImageBase);
744
2
  } else {
745
1
    write32le(Buf, Sym->getRVA() + Config->ImageBase);
746
1
  }
747
3
}
748
749
11
void RVATableChunk::writeTo(uint8_t *Buf) const {
750
11
  ulittle32_t *Begin = reinterpret_cast<ulittle32_t *>(Buf);
751
11
  size_t Cnt = 0;
752
11
  for (const ChunkAndOffset &CO : Syms)
753
18
    Begin[Cnt++] = CO.InputChunk->getRVA() + CO.Offset;
754
11
  std::sort(Begin, Begin + Cnt);
755
11
  assert(std::unique(Begin, Begin + Cnt) == Begin + Cnt &&
756
11
         "RVA tables should be de-duplicated");
757
11
}
758
759
// MinGW specific, for the "automatic import of variables from DLLs" feature.
760
19
size_t PseudoRelocTableChunk::getSize() const {
761
19
  if (Relocs.empty())
762
18
    return 0;
763
1
  return 12 + 12 * Relocs.size();
764
1
}
765
766
// MinGW specific.
767
19
void PseudoRelocTableChunk::writeTo(uint8_t *Buf) const {
768
19
  if (Relocs.empty())
769
18
    return;
770
1
771
1
  ulittle32_t *Table = reinterpret_cast<ulittle32_t *>(Buf);
772
1
  // This is the list header, to signal the runtime pseudo relocation v2
773
1
  // format.
774
1
  Table[0] = 0;
775
1
  Table[1] = 0;
776
1
  Table[2] = 1;
777
1
778
1
  size_t Idx = 3;
779
2
  for (const RuntimePseudoReloc &RPR : Relocs) {
780
2
    Table[Idx + 0] = RPR.Sym->getRVA();
781
2
    Table[Idx + 1] = RPR.Target->getRVA() + RPR.TargetOffset;
782
2
    Table[Idx + 2] = RPR.Flags;
783
2
    Idx += 3;
784
2
  }
785
1
}
786
787
// Windows-specific. This class represents a block in .reloc section.
788
// The format is described here.
789
//
790
// On Windows, each DLL is linked against a fixed base address and
791
// usually loaded to that address. However, if there's already another
792
// DLL that overlaps, the loader has to relocate it. To do that, DLLs
793
// contain .reloc sections which contain offsets that need to be fixed
794
// up at runtime. If the loader finds that a DLL cannot be loaded to its
795
// desired base address, it loads it to somewhere else, and add <actual
796
// base address> - <desired base address> to each offset that is
797
// specified by the .reloc section. In ELF terms, .reloc sections
798
// contain relative relocations in REL format (as opposed to RELA.)
799
//
800
// This already significantly reduces the size of relocations compared
801
// to ELF .rel.dyn, but Windows does more to reduce it (probably because
802
// it was invented for PCs in the late '80s or early '90s.)  Offsets in
803
// .reloc are grouped by page where the page size is 12 bits, and
804
// offsets sharing the same page address are stored consecutively to
805
// represent them with less space. This is very similar to the page
806
// table which is grouped by (multiple stages of) pages.
807
//
808
// For example, let's say we have 0x00030, 0x00500, 0x00700, 0x00A00,
809
// 0x20004, and 0x20008 in a .reloc section for x64. The uppermost 4
810
// bits have a type IMAGE_REL_BASED_DIR64 or 0xA. In the section, they
811
// are represented like this:
812
//
813
//   0x00000  -- page address (4 bytes)
814
//   16       -- size of this block (4 bytes)
815
//     0xA030 -- entries (2 bytes each)
816
//     0xA500
817
//     0xA700
818
//     0xAA00
819
//   0x20000  -- page address (4 bytes)
820
//   12       -- size of this block (4 bytes)
821
//     0xA004 -- entries (2 bytes each)
822
//     0xA008
823
//
824
// Usually we have a lot of relocations for each page, so the number of
825
// bytes for one .reloc entry is close to 2 bytes on average.
826
60
BaserelChunk::BaserelChunk(uint32_t Page, Baserel *Begin, Baserel *End) {
827
60
  // Block header consists of 4 byte page RVA and 4 byte block size.
828
60
  // Each entry is 2 byte. Last entry may be padding.
829
60
  Data.resize(alignTo((End - Begin) * 2 + 8, 4));
830
60
  uint8_t *P = Data.data();
831
60
  write32le(P, Page);
832
60
  write32le(P + 4, Data.size());
833
60
  P += 8;
834
193
  for (Baserel *I = Begin; I != End; 
++I133
) {
835
133
    write16le(P, (I->Type << 12) | (I->RVA - Page));
836
133
    P += 2;
837
133
  }
838
60
}
839
840
60
void BaserelChunk::writeTo(uint8_t *Buf) const {
841
60
  memcpy(Buf, Data.data(), Data.size());
842
60
}
843
844
24
uint8_t Baserel::getDefaultType() {
845
24
  switch (Config->Machine) {
846
24
  case AMD64:
847
2
  case ARM64:
848
2
    return IMAGE_REL_BASED_DIR64;
849
22
  case I386:
850
22
  case ARMNT:
851
22
    return IMAGE_REL_BASED_HIGHLOW;
852
22
  default:
853
0
    llvm_unreachable("unknown machine type");
854
24
  }
855
24
}
856
857
std::map<uint32_t, MergeChunk *> MergeChunk::Instances;
858
859
MergeChunk::MergeChunk(uint32_t Alignment)
860
4
    : Builder(StringTableBuilder::RAW, Alignment) {
861
4
  this->Alignment = Alignment;
862
4
}
863
864
10
void MergeChunk::addSection(SectionChunk *C) {
865
10
  auto *&MC = Instances[C->Alignment];
866
10
  if (!MC)
867
4
    MC = make<MergeChunk>(C->Alignment);
868
10
  MC->Sections.push_back(C);
869
10
}
870
871
4
void MergeChunk::finalizeContents() {
872
4
  if (!Finalized) {
873
4
    for (SectionChunk *C : Sections)
874
10
      if (C->Live)
875
10
        Builder.add(toStringRef(C->getContents()));
876
4
    Builder.finalize();
877
4
    Finalized = true;
878
4
  }
879
4
880
10
  for (SectionChunk *C : Sections) {
881
10
    if (!C->Live)
882
0
      continue;
883
10
    size_t Off = Builder.getOffset(toStringRef(C->getContents()));
884
10
    C->setOutputSection(Out);
885
10
    C->setRVA(RVA + Off);
886
10
  }
887
4
}
888
889
0
uint32_t MergeChunk::getOutputCharacteristics() const {
890
0
  return IMAGE_SCN_MEM_READ | IMAGE_SCN_CNT_INITIALIZED_DATA;
891
0
}
892
893
4
size_t MergeChunk::getSize() const {
894
4
  return Builder.getSize();
895
4
}
896
897
4
void MergeChunk::writeTo(uint8_t *Buf) const {
898
4
  Builder.write(Buf);
899
4
}
900
901
// MinGW specific.
902
152
size_t AbsolutePointerChunk::getSize() const { return Config->Wordsize; }
903
904
76
void AbsolutePointerChunk::writeTo(uint8_t *Buf) const {
905
76
  if (Config->is64()) {
906
52
    write64le(Buf, Value);
907
52
  } else {
908
24
    write32le(Buf, Value);
909
24
  }
910
76
}
911
912
} // namespace coff
913
} // namespace lld