Coverage Report

Created: 2019-01-18 03:29

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/AArch64.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- AArch64.cpp --------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#include "Symbols.h"
11
#include "SyntheticSections.h"
12
#include "Target.h"
13
#include "Thunks.h"
14
#include "lld/Common/ErrorHandler.h"
15
#include "llvm/Object/ELF.h"
16
#include "llvm/Support/Endian.h"
17
18
using namespace llvm;
19
using namespace llvm::support::endian;
20
using namespace llvm::ELF;
21
using namespace lld;
22
using namespace lld::elf;
23
24
// Page(Expr) is the page address of the expression Expr, defined
25
// as (Expr & ~0xFFF). (This applies even if the machine page size
26
// supported by the platform has a different value.)
27
283
uint64_t elf::getAArch64Page(uint64_t Expr) {
28
283
  return Expr & ~static_cast<uint64_t>(0xFFF);
29
283
}
30
31
namespace {
32
class AArch64 final : public TargetInfo {
33
public:
34
  AArch64();
35
  RelExpr getRelExpr(RelType Type, const Symbol &S,
36
                     const uint8_t *Loc) const override;
37
  RelType getDynRel(RelType Type) const override;
38
  void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
39
  void writePltHeader(uint8_t *Buf) const override;
40
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
41
                int32_t Index, unsigned RelOff) const override;
42
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
43
                  uint64_t BranchAddr, const Symbol &S) const override;
44
  uint32_t getThunkSectionSpacing() const override;
45
  bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
46
  bool usesOnlyLowPageBits(RelType Type) const override;
47
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
48
  RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
49
                          RelExpr Expr) const override;
50
  void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
51
  void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
52
  void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
53
};
54
} // namespace
55
56
104
AArch64::AArch64() {
57
104
  CopyRel = R_AARCH64_COPY;
58
104
  RelativeRel = R_AARCH64_RELATIVE;
59
104
  IRelativeRel = R_AARCH64_IRELATIVE;
60
104
  GotRel = R_AARCH64_GLOB_DAT;
61
104
  NoneRel = R_AARCH64_NONE;
62
104
  PltRel = R_AARCH64_JUMP_SLOT;
63
104
  TlsDescRel = R_AARCH64_TLSDESC;
64
104
  TlsGotRel = R_AARCH64_TLS_TPREL64;
65
104
  GotEntrySize = 8;
66
104
  GotPltEntrySize = 8;
67
104
  PltEntrySize = 16;
68
104
  PltHeaderSize = 32;
69
104
  DefaultMaxPageSize = 65536;
70
104
71
104
  // Align to the 2 MiB page size (known as a superpage or huge page).
72
104
  // FreeBSD automatically promotes 2 MiB-aligned allocations.
73
104
  DefaultImageBase = 0x200000;
74
104
75
104
  NeedsThunks = true;
76
104
}
77
78
RelExpr AArch64::getRelExpr(RelType Type, const Symbol &S,
79
456
                            const uint8_t *Loc) const {
80
456
  switch (Type) {
81
456
  case R_AARCH64_TLSDESC_ADR_PAGE21:
82
7
    return R_AARCH64_TLSDESC_PAGE;
83
456
  case R_AARCH64_TLSDESC_LD64_LO12:
84
14
  case R_AARCH64_TLSDESC_ADD_LO12:
85
14
    return R_TLSDESC;
86
14
  case R_AARCH64_TLSDESC_CALL:
87
7
    return R_TLSDESC_CALL;
88
16
  case R_AARCH64_TLSLE_ADD_TPREL_HI12:
89
16
  case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
90
16
  case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
91
16
  case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
92
16
  case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
93
16
  case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
94
16
  case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
95
16
    return R_TLS;
96
51
  case R_AARCH64_CALL26:
97
51
  case R_AARCH64_CONDBR19:
98
51
  case R_AARCH64_JUMP26:
99
51
  case R_AARCH64_TSTBR14:
100
51
    return R_PLT_PC;
101
51
  case R_AARCH64_PREL16:
102
31
  case R_AARCH64_PREL32:
103
31
  case R_AARCH64_PREL64:
104
31
  case R_AARCH64_ADR_PREL_LO21:
105
31
  case R_AARCH64_LD_PREL_LO19:
106
31
    return R_PC;
107
91
  case R_AARCH64_ADR_PREL_PG_HI21:
108
91
    return R_AARCH64_PAGE_PC;
109
66
  case R_AARCH64_LD64_GOT_LO12_NC:
110
66
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
111
66
    return R_GOT;
112
66
  case R_AARCH64_ADR_GOT_PAGE:
113
16
  case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
114
16
    return R_AARCH64_GOT_PAGE_PC;
115
16
  case R_AARCH64_NONE:
116
1
    return R_NONE;
117
156
  default:
118
156
    return R_ABS;
119
456
  }
120
456
}
121
122
RelExpr AArch64::adjustRelaxExpr(RelType Type, const uint8_t *Data,
123
8
                                 RelExpr Expr) const {
124
8
  if (Expr == R_RELAX_TLS_GD_TO_IE) {
125
4
    if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
126
1
      return R_AARCH64_RELAX_TLS_GD_TO_IE_PAGE_PC;
127
3
    return R_RELAX_TLS_GD_TO_IE_ABS;
128
3
  }
129
4
  return Expr;
130
4
}
131
132
148
bool AArch64::usesOnlyLowPageBits(RelType Type) const {
133
148
  switch (Type) {
134
148
  default:
135
79
    return false;
136
148
  case R_AARCH64_ADD_ABS_LO12_NC:
137
69
  case R_AARCH64_LD64_GOT_LO12_NC:
138
69
  case R_AARCH64_LDST128_ABS_LO12_NC:
139
69
  case R_AARCH64_LDST16_ABS_LO12_NC:
140
69
  case R_AARCH64_LDST32_ABS_LO12_NC:
141
69
  case R_AARCH64_LDST64_ABS_LO12_NC:
142
69
  case R_AARCH64_LDST8_ABS_LO12_NC:
143
69
  case R_AARCH64_TLSDESC_ADD_LO12:
144
69
  case R_AARCH64_TLSDESC_LD64_LO12:
145
69
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
146
69
    return true;
147
148
  }
148
148
}
149
150
11
RelType AArch64::getDynRel(RelType Type) const {
151
11
  if (Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64)
152
7
    return Type;
153
4
  return R_AARCH64_NONE;
154
4
}
155
156
26
void AArch64::writeGotPlt(uint8_t *Buf, const Symbol &) const {
157
26
  write64le(Buf, In.Plt->getVA());
158
26
}
159
160
8
void AArch64::writePltHeader(uint8_t *Buf) const {
161
8
  const uint8_t PltData[] = {
162
8
      0xf0, 0x7b, 0xbf, 0xa9, // stp    x16, x30, [sp,#-16]!
163
8
      0x10, 0x00, 0x00, 0x90, // adrp   x16, Page(&(.plt.got[2]))
164
8
      0x11, 0x02, 0x40, 0xf9, // ldr    x17, [x16, Offset(&(.plt.got[2]))]
165
8
      0x10, 0x02, 0x00, 0x91, // add    x16, x16, Offset(&(.plt.got[2]))
166
8
      0x20, 0x02, 0x1f, 0xd6, // br     x17
167
8
      0x1f, 0x20, 0x03, 0xd5, // nop
168
8
      0x1f, 0x20, 0x03, 0xd5, // nop
169
8
      0x1f, 0x20, 0x03, 0xd5  // nop
170
8
  };
171
8
  memcpy(Buf, PltData, sizeof(PltData));
172
8
173
8
  uint64_t Got = In.GotPlt->getVA();
174
8
  uint64_t Plt = In.Plt->getVA();
175
8
  relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
176
8
              getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
177
8
  relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
178
8
  relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16);
179
8
}
180
181
void AArch64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
182
                       uint64_t PltEntryAddr, int32_t Index,
183
26
                       unsigned RelOff) const {
184
26
  const uint8_t Inst[] = {
185
26
      0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n]))
186
26
      0x11, 0x02, 0x40, 0xf9, // ldr  x17, [x16, Offset(&(.plt.got[n]))]
187
26
      0x10, 0x02, 0x00, 0x91, // add  x16, x16, Offset(&(.plt.got[n]))
188
26
      0x20, 0x02, 0x1f, 0xd6  // br   x17
189
26
  };
190
26
  memcpy(Buf, Inst, sizeof(Inst));
191
26
192
26
  relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21,
193
26
              getAArch64Page(GotPltEntryAddr) - getAArch64Page(PltEntryAddr));
194
26
  relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotPltEntryAddr);
195
26
  relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotPltEntryAddr);
196
26
}
197
198
bool AArch64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
199
471
                         uint64_t BranchAddr, const Symbol &S) const {
200
471
  // ELF for the ARM 64-bit architecture, section Call and Jump relocations
201
471
  // only permits range extension thunks for R_AARCH64_CALL26 and
202
471
  // R_AARCH64_JUMP26 relocation types.
203
471
  if (Type != R_AARCH64_CALL26 && 
Type != R_AARCH64_JUMP26446
)
204
389
    return false;
205
82
  uint64_t Dst = (Expr == R_PLT_PC) ? 
S.getPltVA()17
:
S.getVA()65
;
206
82
  return !inBranchRange(Type, BranchAddr, Dst);
207
82
}
208
209
197
uint32_t AArch64::getThunkSectionSpacing() const {
210
197
  // See comment in Arch/ARM.cpp for a more detailed explanation of
211
197
  // getThunkSectionSpacing(). For AArch64 the only branches we are permitted to
212
197
  // Thunk have a range of +/- 128 MiB
213
197
  return (128 * 1024 * 1024) - 0x30000;
214
197
}
215
216
100
bool AArch64::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
217
100
  if (Type != R_AARCH64_CALL26 && 
Type != R_AARCH64_JUMP2659
)
218
0
    return true;
219
100
  // The AArch64 call and unconditional branch instructions have a range of
220
100
  // +/- 128 MiB.
221
100
  uint64_t Range = 128 * 1024 * 1024;
222
100
  if (Dst > Src) {
223
90
    // Immediate of branch is signed.
224
90
    Range -= 4;
225
90
    return Dst - Src <= Range;
226
90
  }
227
10
  return Src - Dst <= Range;
228
10
}
229
230
147
static void write32AArch64Addr(uint8_t *L, uint64_t Imm) {
231
147
  uint32_t ImmLo = (Imm & 0x3) << 29;
232
147
  uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
233
147
  uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
234
147
  write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
235
147
}
236
237
// Return the bits [Start, End] from Val shifted Start bits.
238
// For instance, getBits(0xF0, 4, 8) returns 0xF.
239
144
static uint64_t getBits(uint64_t Val, int Start, int End) {
240
144
  uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
241
144
  return (Val >> Start) & Mask;
242
144
}
243
244
336
static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
245
246
// Update the immediate field in a AARCH64 ldr, str, and add instruction.
247
204
static void or32AArch64Imm(uint8_t *L, uint64_t Imm) {
248
204
  or32le(L, (Imm & 0xFFF) << 10);
249
204
}
250
251
557
void AArch64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
252
557
  switch (Type) {
253
557
  case R_AARCH64_ABS16:
254
13
  case R_AARCH64_PREL16:
255
13
    checkIntUInt(Loc, Val, 16, Type);
256
13
    write16le(Loc, Val);
257
13
    break;
258
16
  case R_AARCH64_ABS32:
259
16
  case R_AARCH64_PREL32:
260
16
    checkIntUInt(Loc, Val, 32, Type);
261
16
    write32le(Loc, Val);
262
16
    break;
263
47
  case R_AARCH64_ABS64:
264
47
  case R_AARCH64_GLOB_DAT:
265
47
  case R_AARCH64_PREL64:
266
47
    write64le(Loc, Val);
267
47
    break;
268
47
  case R_AARCH64_ADD_ABS_LO12_NC:
269
44
    or32AArch64Imm(Loc, Val);
270
44
    break;
271
143
  case R_AARCH64_ADR_GOT_PAGE:
272
143
  case R_AARCH64_ADR_PREL_PG_HI21:
273
143
  case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
274
143
  case R_AARCH64_TLSDESC_ADR_PAGE21:
275
143
    checkInt(Loc, Val, 33, Type);
276
143
    write32AArch64Addr(Loc, Val >> 12);
277
143
    break;
278
143
  case R_AARCH64_ADR_PREL_LO21:
279
4
    checkInt(Loc, Val, 21, Type);
280
4
    write32AArch64Addr(Loc, Val);
281
4
    break;
282
143
  case R_AARCH64_JUMP26:
283
84
    // Normally we would just write the bits of the immediate field, however
284
84
    // when patching instructions for the cpu errata fix -fix-cortex-a53-843419
285
84
    // we want to replace a non-branch instruction with a branch immediate
286
84
    // instruction. By writing all the bits of the instruction including the
287
84
    // opcode and the immediate (0 001 | 01 imm26) we can do this
288
84
    // transformation by placing a R_AARCH64_JUMP26 relocation at the offset of
289
84
    // the instruction we want to patch.
290
84
    write32le(Loc, 0x14000000);
291
84
    LLVM_FALLTHROUGH;
292
106
  case R_AARCH64_CALL26:
293
106
    checkInt(Loc, Val, 28, Type);
294
106
    or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
295
106
    break;
296
84
  case R_AARCH64_CONDBR19:
297
13
  case R_AARCH64_LD_PREL_LO19:
298
13
    checkAlignment(Loc, Val, 4, Type);
299
13
    checkInt(Loc, Val, 21, Type);
300
13
    or32le(Loc, (Val & 0x1FFFFC) << 3);
301
13
    break;
302
13
  case R_AARCH64_LDST8_ABS_LO12_NC:
303
4
  case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
304
4
    or32AArch64Imm(Loc, getBits(Val, 0, 11));
305
4
    break;
306
7
  case R_AARCH64_LDST16_ABS_LO12_NC:
307
7
  case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
308
7
    checkAlignment(Loc, Val, 2, Type);
309
7
    or32AArch64Imm(Loc, getBits(Val, 1, 11));
310
7
    break;
311
7
  case R_AARCH64_LDST32_ABS_LO12_NC:
312
5
  case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
313
5
    checkAlignment(Loc, Val, 4, Type);
314
5
    or32AArch64Imm(Loc, getBits(Val, 2, 11));
315
5
    break;
316
124
  case R_AARCH64_LDST64_ABS_LO12_NC:
317
124
  case R_AARCH64_LD64_GOT_LO12_NC:
318
124
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
319
124
  case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
320
124
  case R_AARCH64_TLSDESC_LD64_LO12:
321
124
    checkAlignment(Loc, Val, 8, Type);
322
124
    or32AArch64Imm(Loc, getBits(Val, 3, 11));
323
124
    break;
324
124
  case R_AARCH64_LDST128_ABS_LO12_NC:
325
5
  case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
326
5
    checkAlignment(Loc, Val, 16, Type);
327
5
    or32AArch64Imm(Loc, getBits(Val, 4, 11));
328
5
    break;
329
5
  case R_AARCH64_MOVW_UABS_G0_NC:
330
1
    or32le(Loc, (Val & 0xFFFF) << 5);
331
1
    break;
332
5
  case R_AARCH64_MOVW_UABS_G1_NC:
333
1
    or32le(Loc, (Val & 0xFFFF0000) >> 11);
334
1
    break;
335
5
  case R_AARCH64_MOVW_UABS_G2_NC:
336
1
    or32le(Loc, (Val & 0xFFFF00000000) >> 27);
337
1
    break;
338
5
  case R_AARCH64_MOVW_UABS_G3:
339
2
    or32le(Loc, (Val & 0xFFFF000000000000) >> 43);
340
2
    break;
341
8
  case R_AARCH64_TSTBR14:
342
8
    checkInt(Loc, Val, 16, Type);
343
8
    or32le(Loc, (Val & 0xFFFC) << 3);
344
8
    break;
345
8
  case R_AARCH64_TLSLE_ADD_TPREL_HI12:
346
8
    checkUInt(Loc, Val, 24, Type);
347
8
    or32AArch64Imm(Loc, Val >> 12);
348
8
    break;
349
8
  case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
350
8
  case R_AARCH64_TLSDESC_ADD_LO12:
351
8
    or32AArch64Imm(Loc, Val);
352
8
    break;
353
8
  default:
354
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
355
557
  }
356
557
}
357
358
4
void AArch64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
359
4
  // TLSDESC Global-Dynamic relocation are in the form:
360
4
  //   adrp    x0, :tlsdesc:v             [R_AARCH64_TLSDESC_ADR_PAGE21]
361
4
  //   ldr     x1, [x0, #:tlsdesc_lo12:v  [R_AARCH64_TLSDESC_LD64_LO12]
362
4
  //   add     x0, x0, :tlsdesc_los:v     [R_AARCH64_TLSDESC_ADD_LO12]
363
4
  //   .tlsdesccall                       [R_AARCH64_TLSDESC_CALL]
364
4
  //   blr     x1
365
4
  // And it can optimized to:
366
4
  //   movz    x0, #0x0, lsl #16
367
4
  //   movk    x0, #0x10
368
4
  //   nop
369
4
  //   nop
370
4
  checkUInt(Loc, Val, 32, Type);
371
4
372
4
  switch (Type) {
373
4
  case R_AARCH64_TLSDESC_ADD_LO12:
374
2
  case R_AARCH64_TLSDESC_CALL:
375
2
    write32le(Loc, 0xd503201f); // nop
376
2
    return;
377
2
  case R_AARCH64_TLSDESC_ADR_PAGE21:
378
1
    write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
379
1
    return;
380
2
  case R_AARCH64_TLSDESC_LD64_LO12:
381
1
    write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk
382
1
    return;
383
2
  default:
384
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
385
4
  }
386
4
}
387
388
4
void AArch64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
389
4
  // TLSDESC Global-Dynamic relocation are in the form:
390
4
  //   adrp    x0, :tlsdesc:v             [R_AARCH64_TLSDESC_ADR_PAGE21]
391
4
  //   ldr     x1, [x0, #:tlsdesc_lo12:v  [R_AARCH64_TLSDESC_LD64_LO12]
392
4
  //   add     x0, x0, :tlsdesc_los:v     [R_AARCH64_TLSDESC_ADD_LO12]
393
4
  //   .tlsdesccall                       [R_AARCH64_TLSDESC_CALL]
394
4
  //   blr     x1
395
4
  // And it can optimized to:
396
4
  //   adrp    x0, :gottprel:v
397
4
  //   ldr     x0, [x0, :gottprel_lo12:v]
398
4
  //   nop
399
4
  //   nop
400
4
401
4
  switch (Type) {
402
4
  case R_AARCH64_TLSDESC_ADD_LO12:
403
2
  case R_AARCH64_TLSDESC_CALL:
404
2
    write32le(Loc, 0xd503201f); // nop
405
2
    break;
406
2
  case R_AARCH64_TLSDESC_ADR_PAGE21:
407
1
    write32le(Loc, 0x90000000); // adrp
408
1
    relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val);
409
1
    break;
410
2
  case R_AARCH64_TLSDESC_LD64_LO12:
411
1
    write32le(Loc, 0xf9400000); // ldr
412
1
    relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val);
413
1
    break;
414
2
  default:
415
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
416
4
  }
417
4
}
418
419
11
void AArch64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
420
11
  checkUInt(Loc, Val, 32, Type);
421
11
422
11
  if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
423
6
    // Generate MOVZ.
424
6
    uint32_t RegNo = read32le(Loc) & 0x1f;
425
6
    write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
426
6
    return;
427
6
  }
428
5
  if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
429
5
    // Generate MOVK.
430
5
    uint32_t RegNo = read32le(Loc) & 0x1f;
431
5
    write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
432
5
    return;
433
5
  }
434
0
  llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
435
0
}
436
437
104
TargetInfo *elf::getAArch64TargetInfo() {
438
104
  static AArch64 Target;
439
104
  return &Target;
440
104
}