Coverage Report

Created: 2019-05-19 14:56

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/AArch64.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- AArch64.cpp --------------------------------------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "Symbols.h"
10
#include "SyntheticSections.h"
11
#include "Target.h"
12
#include "Thunks.h"
13
#include "lld/Common/ErrorHandler.h"
14
#include "llvm/Object/ELF.h"
15
#include "llvm/Support/Endian.h"
16
17
using namespace llvm;
18
using namespace llvm::support::endian;
19
using namespace llvm::ELF;
20
using namespace lld;
21
using namespace lld::elf;
22
23
// Page(Expr) is the page address of the expression Expr, defined
24
// as (Expr & ~0xFFF). (This applies even if the machine page size
25
// supported by the platform has a different value.)
26
279
uint64_t elf::getAArch64Page(uint64_t Expr) {
27
279
  return Expr & ~static_cast<uint64_t>(0xFFF);
28
279
}
29
30
namespace {
31
class AArch64 final : public TargetInfo {
32
public:
33
  AArch64();
34
  RelExpr getRelExpr(RelType Type, const Symbol &S,
35
                     const uint8_t *Loc) const override;
36
  RelType getDynRel(RelType Type) const override;
37
  void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
38
  void writePltHeader(uint8_t *Buf) const override;
39
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
40
                int32_t Index, unsigned RelOff) const override;
41
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
42
                  uint64_t BranchAddr, const Symbol &S) const override;
43
  uint32_t getThunkSectionSpacing() const override;
44
  bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
45
  bool usesOnlyLowPageBits(RelType Type) const override;
46
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
47
  RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
48
                          RelExpr Expr) const override;
49
  void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
50
  void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
51
  void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
52
};
53
} // namespace
54
55
107
AArch64::AArch64() {
56
107
  CopyRel = R_AARCH64_COPY;
57
107
  RelativeRel = R_AARCH64_RELATIVE;
58
107
  IRelativeRel = R_AARCH64_IRELATIVE;
59
107
  GotRel = R_AARCH64_GLOB_DAT;
60
107
  NoneRel = R_AARCH64_NONE;
61
107
  PltRel = R_AARCH64_JUMP_SLOT;
62
107
  TlsDescRel = R_AARCH64_TLSDESC;
63
107
  TlsGotRel = R_AARCH64_TLS_TPREL64;
64
107
  GotEntrySize = 8;
65
107
  GotPltEntrySize = 8;
66
107
  PltEntrySize = 16;
67
107
  PltHeaderSize = 32;
68
107
  DefaultMaxPageSize = 65536;
69
107
70
107
  // Align to the 2 MiB page size (known as a superpage or huge page).
71
107
  // FreeBSD automatically promotes 2 MiB-aligned allocations.
72
107
  DefaultImageBase = 0x200000;
73
107
74
107
  NeedsThunks = true;
75
107
}
76
77
RelExpr AArch64::getRelExpr(RelType Type, const Symbol &S,
78
456
                            const uint8_t *Loc) const {
79
456
  switch (Type) {
80
456
  case R_AARCH64_TLSDESC_ADR_PAGE21:
81
7
    return R_AARCH64_TLSDESC_PAGE;
82
456
  case R_AARCH64_TLSDESC_LD64_LO12:
83
14
  case R_AARCH64_TLSDESC_ADD_LO12:
84
14
    return R_TLSDESC;
85
14
  case R_AARCH64_TLSDESC_CALL:
86
7
    return R_TLSDESC_CALL;
87
16
  case R_AARCH64_TLSLE_ADD_TPREL_HI12:
88
16
  case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
89
16
  case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
90
16
  case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
91
16
  case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
92
16
  case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
93
16
  case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
94
16
    return R_TLS;
95
51
  case R_AARCH64_CALL26:
96
51
  case R_AARCH64_CONDBR19:
97
51
  case R_AARCH64_JUMP26:
98
51
  case R_AARCH64_TSTBR14:
99
51
    return R_PLT_PC;
100
51
  case R_AARCH64_PREL16:
101
31
  case R_AARCH64_PREL32:
102
31
  case R_AARCH64_PREL64:
103
31
  case R_AARCH64_ADR_PREL_LO21:
104
31
  case R_AARCH64_LD_PREL_LO19:
105
31
    return R_PC;
106
91
  case R_AARCH64_ADR_PREL_PG_HI21:
107
91
    return R_AARCH64_PAGE_PC;
108
66
  case R_AARCH64_LD64_GOT_LO12_NC:
109
66
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
110
66
    return R_GOT;
111
66
  case R_AARCH64_ADR_GOT_PAGE:
112
16
  case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
113
16
    return R_AARCH64_GOT_PAGE_PC;
114
16
  case R_AARCH64_NONE:
115
1
    return R_NONE;
116
156
  default:
117
156
    return R_ABS;
118
456
  }
119
456
}
120
121
RelExpr AArch64::adjustRelaxExpr(RelType Type, const uint8_t *Data,
122
8
                                 RelExpr Expr) const {
123
8
  if (Expr == R_RELAX_TLS_GD_TO_IE) {
124
4
    if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
125
1
      return R_AARCH64_RELAX_TLS_GD_TO_IE_PAGE_PC;
126
3
    return R_RELAX_TLS_GD_TO_IE_ABS;
127
3
  }
128
4
  return Expr;
129
4
}
130
131
147
bool AArch64::usesOnlyLowPageBits(RelType Type) const {
132
147
  switch (Type) {
133
147
  default:
134
79
    return false;
135
147
  case R_AARCH64_ADD_ABS_LO12_NC:
136
68
  case R_AARCH64_LD64_GOT_LO12_NC:
137
68
  case R_AARCH64_LDST128_ABS_LO12_NC:
138
68
  case R_AARCH64_LDST16_ABS_LO12_NC:
139
68
  case R_AARCH64_LDST32_ABS_LO12_NC:
140
68
  case R_AARCH64_LDST64_ABS_LO12_NC:
141
68
  case R_AARCH64_LDST8_ABS_LO12_NC:
142
68
  case R_AARCH64_TLSDESC_ADD_LO12:
143
68
  case R_AARCH64_TLSDESC_LD64_LO12:
144
68
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
145
68
    return true;
146
147
  }
147
147
}
148
149
11
RelType AArch64::getDynRel(RelType Type) const {
150
11
  if (Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64)
151
7
    return Type;
152
4
  return R_AARCH64_NONE;
153
4
}
154
155
25
void AArch64::writeGotPlt(uint8_t *Buf, const Symbol &) const {
156
25
  write64le(Buf, In.Plt->getVA());
157
25
}
158
159
7
void AArch64::writePltHeader(uint8_t *Buf) const {
160
7
  const uint8_t PltData[] = {
161
7
      0xf0, 0x7b, 0xbf, 0xa9, // stp    x16, x30, [sp,#-16]!
162
7
      0x10, 0x00, 0x00, 0x90, // adrp   x16, Page(&(.plt.got[2]))
163
7
      0x11, 0x02, 0x40, 0xf9, // ldr    x17, [x16, Offset(&(.plt.got[2]))]
164
7
      0x10, 0x02, 0x00, 0x91, // add    x16, x16, Offset(&(.plt.got[2]))
165
7
      0x20, 0x02, 0x1f, 0xd6, // br     x17
166
7
      0x1f, 0x20, 0x03, 0xd5, // nop
167
7
      0x1f, 0x20, 0x03, 0xd5, // nop
168
7
      0x1f, 0x20, 0x03, 0xd5  // nop
169
7
  };
170
7
  memcpy(Buf, PltData, sizeof(PltData));
171
7
172
7
  uint64_t Got = In.GotPlt->getVA();
173
7
  uint64_t Plt = In.Plt->getVA();
174
7
  relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
175
7
              getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
176
7
  relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
177
7
  relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16);
178
7
}
179
180
void AArch64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
181
                       uint64_t PltEntryAddr, int32_t Index,
182
25
                       unsigned RelOff) const {
183
25
  const uint8_t Inst[] = {
184
25
      0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n]))
185
25
      0x11, 0x02, 0x40, 0xf9, // ldr  x17, [x16, Offset(&(.plt.got[n]))]
186
25
      0x10, 0x02, 0x00, 0x91, // add  x16, x16, Offset(&(.plt.got[n]))
187
25
      0x20, 0x02, 0x1f, 0xd6  // br   x17
188
25
  };
189
25
  memcpy(Buf, Inst, sizeof(Inst));
190
25
191
25
  relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21,
192
25
              getAArch64Page(GotPltEntryAddr) - getAArch64Page(PltEntryAddr));
193
25
  relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotPltEntryAddr);
194
25
  relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotPltEntryAddr);
195
25
}
196
197
bool AArch64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
198
471
                         uint64_t BranchAddr, const Symbol &S) const {
199
471
  // ELF for the ARM 64-bit architecture, section Call and Jump relocations
200
471
  // only permits range extension thunks for R_AARCH64_CALL26 and
201
471
  // R_AARCH64_JUMP26 relocation types.
202
471
  if (Type != R_AARCH64_CALL26 && 
Type != R_AARCH64_JUMP26446
)
203
389
    return false;
204
82
  uint64_t Dst = (Expr == R_PLT_PC) ? 
S.getPltVA()17
:
S.getVA()65
;
205
82
  return !inBranchRange(Type, BranchAddr, Dst);
206
82
}
207
208
203
uint32_t AArch64::getThunkSectionSpacing() const {
209
203
  // See comment in Arch/ARM.cpp for a more detailed explanation of
210
203
  // getThunkSectionSpacing(). For AArch64 the only branches we are permitted to
211
203
  // Thunk have a range of +/- 128 MiB
212
203
  return (128 * 1024 * 1024) - 0x30000;
213
203
}
214
215
100
bool AArch64::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
216
100
  if (Type != R_AARCH64_CALL26 && 
Type != R_AARCH64_JUMP2659
)
217
0
    return true;
218
100
  // The AArch64 call and unconditional branch instructions have a range of
219
100
  // +/- 128 MiB.
220
100
  uint64_t Range = 128 * 1024 * 1024;
221
100
  if (Dst > Src) {
222
90
    // Immediate of branch is signed.
223
90
    Range -= 4;
224
90
    return Dst - Src <= Range;
225
90
  }
226
10
  return Src - Dst <= Range;
227
10
}
228
229
144
static void write32AArch64Addr(uint8_t *L, uint64_t Imm) {
230
144
  uint32_t ImmLo = (Imm & 0x3) << 29;
231
144
  uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
232
144
  uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
233
144
  write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
234
144
}
235
236
// Return the bits [Start, End] from Val shifted Start bits.
237
// For instance, getBits(0xF0, 4, 8) returns 0xF.
238
143
static uint64_t getBits(uint64_t Val, int Start, int End) {
239
143
  uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
240
143
  return (Val >> Start) & Mask;
241
143
}
242
243
332
static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
244
245
// Update the immediate field in a AARCH64 ldr, str, and add instruction.
246
201
static void or32AArch64Imm(uint8_t *L, uint64_t Imm) {
247
201
  or32le(L, (Imm & 0xFFF) << 10);
248
201
}
249
250
551
void AArch64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
251
551
  switch (Type) {
252
551
  case R_AARCH64_ABS16:
253
13
  case R_AARCH64_PREL16:
254
13
    checkIntUInt(Loc, Val, 16, Type);
255
13
    write16le(Loc, Val);
256
13
    break;
257
16
  case R_AARCH64_ABS32:
258
16
  case R_AARCH64_PREL32:
259
16
    checkIntUInt(Loc, Val, 32, Type);
260
16
    write32le(Loc, Val);
261
16
    break;
262
46
  case R_AARCH64_ABS64:
263
46
  case R_AARCH64_GLOB_DAT:
264
46
  case R_AARCH64_PREL64:
265
46
    write64le(Loc, Val);
266
46
    break;
267
46
  case R_AARCH64_ADD_ABS_LO12_NC:
268
42
    or32AArch64Imm(Loc, Val);
269
42
    break;
270
139
  case R_AARCH64_ADR_GOT_PAGE:
271
139
  case R_AARCH64_ADR_PREL_PG_HI21:
272
139
  case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
273
139
  case R_AARCH64_TLSDESC_ADR_PAGE21:
274
139
    checkInt(Loc, Val, 33, Type);
275
139
    write32AArch64Addr(Loc, Val >> 12);
276
139
    break;
277
139
  case R_AARCH64_ADR_PREL_LO21:
278
4
    checkInt(Loc, Val, 21, Type);
279
4
    write32AArch64Addr(Loc, Val);
280
4
    break;
281
139
  case R_AARCH64_JUMP26:
282
83
    // Normally we would just write the bits of the immediate field, however
283
83
    // when patching instructions for the cpu errata fix -fix-cortex-a53-843419
284
83
    // we want to replace a non-branch instruction with a branch immediate
285
83
    // instruction. By writing all the bits of the instruction including the
286
83
    // opcode and the immediate (0 001 | 01 imm26) we can do this
287
83
    // transformation by placing a R_AARCH64_JUMP26 relocation at the offset of
288
83
    // the instruction we want to patch.
289
83
    write32le(Loc, 0x14000000);
290
83
    LLVM_FALLTHROUGH;
291
105
  case R_AARCH64_CALL26:
292
105
    checkInt(Loc, Val, 28, Type);
293
105
    or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
294
105
    break;
295
83
  case R_AARCH64_CONDBR19:
296
13
  case R_AARCH64_LD_PREL_LO19:
297
13
    checkAlignment(Loc, Val, 4, Type);
298
13
    checkInt(Loc, Val, 21, Type);
299
13
    or32le(Loc, (Val & 0x1FFFFC) << 3);
300
13
    break;
301
13
  case R_AARCH64_LDST8_ABS_LO12_NC:
302
4
  case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
303
4
    or32AArch64Imm(Loc, getBits(Val, 0, 11));
304
4
    break;
305
7
  case R_AARCH64_LDST16_ABS_LO12_NC:
306
7
  case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
307
7
    checkAlignment(Loc, Val, 2, Type);
308
7
    or32AArch64Imm(Loc, getBits(Val, 1, 11));
309
7
    break;
310
7
  case R_AARCH64_LDST32_ABS_LO12_NC:
311
5
  case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
312
5
    checkAlignment(Loc, Val, 4, Type);
313
5
    or32AArch64Imm(Loc, getBits(Val, 2, 11));
314
5
    break;
315
122
  case R_AARCH64_LDST64_ABS_LO12_NC:
316
122
  case R_AARCH64_LD64_GOT_LO12_NC:
317
122
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
318
122
  case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
319
122
  case R_AARCH64_TLSDESC_LD64_LO12:
320
122
    checkAlignment(Loc, Val, 8, Type);
321
122
    or32AArch64Imm(Loc, getBits(Val, 3, 11));
322
122
    break;
323
122
  case R_AARCH64_LDST128_ABS_LO12_NC:
324
5
  case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
325
5
    checkAlignment(Loc, Val, 16, Type);
326
5
    or32AArch64Imm(Loc, getBits(Val, 4, 11));
327
5
    break;
328
5
  case R_AARCH64_MOVW_UABS_G0_NC:
329
1
    or32le(Loc, (Val & 0xFFFF) << 5);
330
1
    break;
331
5
  case R_AARCH64_MOVW_UABS_G1_NC:
332
1
    or32le(Loc, (Val & 0xFFFF0000) >> 11);
333
1
    break;
334
5
  case R_AARCH64_MOVW_UABS_G2_NC:
335
1
    or32le(Loc, (Val & 0xFFFF00000000) >> 27);
336
1
    break;
337
5
  case R_AARCH64_MOVW_UABS_G3:
338
2
    or32le(Loc, (Val & 0xFFFF000000000000) >> 43);
339
2
    break;
340
8
  case R_AARCH64_TSTBR14:
341
8
    checkInt(Loc, Val, 16, Type);
342
8
    or32le(Loc, (Val & 0xFFFC) << 3);
343
8
    break;
344
8
  case R_AARCH64_TLSLE_ADD_TPREL_HI12:
345
8
    checkUInt(Loc, Val, 24, Type);
346
8
    or32AArch64Imm(Loc, Val >> 12);
347
8
    break;
348
8
  case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
349
8
  case R_AARCH64_TLSDESC_ADD_LO12:
350
8
    or32AArch64Imm(Loc, Val);
351
8
    break;
352
8
  default:
353
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
354
551
  }
355
551
}
356
357
4
void AArch64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
358
4
  // TLSDESC Global-Dynamic relocation are in the form:
359
4
  //   adrp    x0, :tlsdesc:v             [R_AARCH64_TLSDESC_ADR_PAGE21]
360
4
  //   ldr     x1, [x0, #:tlsdesc_lo12:v  [R_AARCH64_TLSDESC_LD64_LO12]
361
4
  //   add     x0, x0, :tlsdesc_los:v     [R_AARCH64_TLSDESC_ADD_LO12]
362
4
  //   .tlsdesccall                       [R_AARCH64_TLSDESC_CALL]
363
4
  //   blr     x1
364
4
  // And it can optimized to:
365
4
  //   movz    x0, #0x0, lsl #16
366
4
  //   movk    x0, #0x10
367
4
  //   nop
368
4
  //   nop
369
4
  checkUInt(Loc, Val, 32, Type);
370
4
371
4
  switch (Type) {
372
4
  case R_AARCH64_TLSDESC_ADD_LO12:
373
2
  case R_AARCH64_TLSDESC_CALL:
374
2
    write32le(Loc, 0xd503201f); // nop
375
2
    return;
376
2
  case R_AARCH64_TLSDESC_ADR_PAGE21:
377
1
    write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
378
1
    return;
379
2
  case R_AARCH64_TLSDESC_LD64_LO12:
380
1
    write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk
381
1
    return;
382
2
  default:
383
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
384
4
  }
385
4
}
386
387
4
void AArch64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
388
4
  // TLSDESC Global-Dynamic relocation are in the form:
389
4
  //   adrp    x0, :tlsdesc:v             [R_AARCH64_TLSDESC_ADR_PAGE21]
390
4
  //   ldr     x1, [x0, #:tlsdesc_lo12:v  [R_AARCH64_TLSDESC_LD64_LO12]
391
4
  //   add     x0, x0, :tlsdesc_los:v     [R_AARCH64_TLSDESC_ADD_LO12]
392
4
  //   .tlsdesccall                       [R_AARCH64_TLSDESC_CALL]
393
4
  //   blr     x1
394
4
  // And it can optimized to:
395
4
  //   adrp    x0, :gottprel:v
396
4
  //   ldr     x0, [x0, :gottprel_lo12:v]
397
4
  //   nop
398
4
  //   nop
399
4
400
4
  switch (Type) {
401
4
  case R_AARCH64_TLSDESC_ADD_LO12:
402
2
  case R_AARCH64_TLSDESC_CALL:
403
2
    write32le(Loc, 0xd503201f); // nop
404
2
    break;
405
2
  case R_AARCH64_TLSDESC_ADR_PAGE21:
406
1
    write32le(Loc, 0x90000000); // adrp
407
1
    relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val);
408
1
    break;
409
2
  case R_AARCH64_TLSDESC_LD64_LO12:
410
1
    write32le(Loc, 0xf9400000); // ldr
411
1
    relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val);
412
1
    break;
413
2
  default:
414
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
415
4
  }
416
4
}
417
418
11
void AArch64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
419
11
  checkUInt(Loc, Val, 32, Type);
420
11
421
11
  if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
422
6
    // Generate MOVZ.
423
6
    uint32_t RegNo = read32le(Loc) & 0x1f;
424
6
    write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
425
6
    return;
426
6
  }
427
5
  if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
428
5
    // Generate MOVK.
429
5
    uint32_t RegNo = read32le(Loc) & 0x1f;
430
5
    write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
431
5
    return;
432
5
  }
433
0
  llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
434
0
}
435
436
107
TargetInfo *elf::getAArch64TargetInfo() {
437
107
  static AArch64 Target;
438
107
  return &Target;
439
107
}