Coverage Report

Created: 2018-10-23 15:26

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/AArch64.cpp
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//===- AArch64.cpp --------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#include "Symbols.h"
11
#include "SyntheticSections.h"
12
#include "Target.h"
13
#include "Thunks.h"
14
#include "lld/Common/ErrorHandler.h"
15
#include "llvm/Object/ELF.h"
16
#include "llvm/Support/Endian.h"
17
18
using namespace llvm;
19
using namespace llvm::support::endian;
20
using namespace llvm::ELF;
21
using namespace lld;
22
using namespace lld::elf;
23
24
// Page(Expr) is the page address of the expression Expr, defined
25
// as (Expr & ~0xFFF). (This applies even if the machine page size
26
// supported by the platform has a different value.)
27
266
uint64_t elf::getAArch64Page(uint64_t Expr) {
28
266
  return Expr & ~static_cast<uint64_t>(0xFFF);
29
266
}
30
31
namespace {
32
class AArch64 final : public TargetInfo {
33
public:
34
  AArch64();
35
  RelExpr getRelExpr(RelType Type, const Symbol &S,
36
                     const uint8_t *Loc) const override;
37
  RelType getDynRel(RelType Type) const override;
38
  void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
39
  void writePltHeader(uint8_t *Buf) const override;
40
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
41
                int32_t Index, unsigned RelOff) const override;
42
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
43
                  uint64_t BranchAddr, const Symbol &S) const override;
44
  uint32_t getThunkSectionSpacing() const override;
45
  bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
46
  bool usesOnlyLowPageBits(RelType Type) const override;
47
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
48
  RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
49
                          RelExpr Expr) const override;
50
  void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
51
  void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
52
  void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
53
};
54
} // namespace
55
56
98
AArch64::AArch64() {
57
98
  CopyRel = R_AARCH64_COPY;
58
98
  RelativeRel = R_AARCH64_RELATIVE;
59
98
  IRelativeRel = R_AARCH64_IRELATIVE;
60
98
  GotRel = R_AARCH64_GLOB_DAT;
61
98
  NoneRel = R_AARCH64_NONE;
62
98
  PltRel = R_AARCH64_JUMP_SLOT;
63
98
  TlsDescRel = R_AARCH64_TLSDESC;
64
98
  TlsGotRel = R_AARCH64_TLS_TPREL64;
65
98
  GotEntrySize = 8;
66
98
  GotPltEntrySize = 8;
67
98
  PltEntrySize = 16;
68
98
  PltHeaderSize = 32;
69
98
  DefaultMaxPageSize = 65536;
70
98
71
98
  // Align to the 2 MiB page size (known as a superpage or huge page).
72
98
  // FreeBSD automatically promotes 2 MiB-aligned allocations.
73
98
  DefaultImageBase = 0x200000;
74
98
75
98
  // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant
76
98
  // 1 of the tls structures and the tcb size is 16.
77
98
  TcbSize = 16;
78
98
  NeedsThunks = true;
79
98
}
80
81
RelExpr AArch64::getRelExpr(RelType Type, const Symbol &S,
82
442
                            const uint8_t *Loc) const {
83
442
  switch (Type) {
84
442
  case R_AARCH64_TLSDESC_ADR_PAGE21:
85
7
    return R_TLSDESC_PAGE;
86
442
  case R_AARCH64_TLSDESC_LD64_LO12:
87
14
  case R_AARCH64_TLSDESC_ADD_LO12:
88
14
    return R_TLSDESC;
89
14
  case R_AARCH64_TLSDESC_CALL:
90
7
    return R_TLSDESC_CALL;
91
16
  case R_AARCH64_TLSLE_ADD_TPREL_HI12:
92
16
  case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
93
16
  case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
94
16
  case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
95
16
  case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
96
16
  case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
97
16
  case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
98
16
    return R_TLS;
99
51
  case R_AARCH64_CALL26:
100
51
  case R_AARCH64_CONDBR19:
101
51
  case R_AARCH64_JUMP26:
102
51
  case R_AARCH64_TSTBR14:
103
51
    return R_PLT_PC;
104
51
  case R_AARCH64_PREL16:
105
31
  case R_AARCH64_PREL32:
106
31
  case R_AARCH64_PREL64:
107
31
  case R_AARCH64_ADR_PREL_LO21:
108
31
  case R_AARCH64_LD_PREL_LO19:
109
31
    return R_PC;
110
88
  case R_AARCH64_ADR_PREL_PG_HI21:
111
88
    return R_PAGE_PC;
112
61
  case R_AARCH64_LD64_GOT_LO12_NC:
113
61
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
114
61
    return R_GOT;
115
61
  case R_AARCH64_ADR_GOT_PAGE:
116
12
  case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
117
12
    return R_GOT_PAGE_PC;
118
12
  case R_AARCH64_NONE:
119
1
    return R_NONE;
120
154
  default:
121
154
    return R_ABS;
122
442
  }
123
442
}
124
125
RelExpr AArch64::adjustRelaxExpr(RelType Type, const uint8_t *Data,
126
8
                                 RelExpr Expr) const {
127
8
  if (Expr == R_RELAX_TLS_GD_TO_IE) {
128
4
    if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
129
1
      return R_RELAX_TLS_GD_TO_IE_PAGE_PC;
130
3
    return R_RELAX_TLS_GD_TO_IE_ABS;
131
3
  }
132
4
  return Expr;
133
4
}
134
135
143
bool AArch64::usesOnlyLowPageBits(RelType Type) const {
136
143
  switch (Type) {
137
143
  default:
138
79
    return false;
139
143
  case R_AARCH64_ADD_ABS_LO12_NC:
140
64
  case R_AARCH64_LD64_GOT_LO12_NC:
141
64
  case R_AARCH64_LDST128_ABS_LO12_NC:
142
64
  case R_AARCH64_LDST16_ABS_LO12_NC:
143
64
  case R_AARCH64_LDST32_ABS_LO12_NC:
144
64
  case R_AARCH64_LDST64_ABS_LO12_NC:
145
64
  case R_AARCH64_LDST8_ABS_LO12_NC:
146
64
  case R_AARCH64_TLSDESC_ADD_LO12:
147
64
  case R_AARCH64_TLSDESC_LD64_LO12:
148
64
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
149
64
    return true;
150
143
  }
151
143
}
152
153
11
RelType AArch64::getDynRel(RelType Type) const {
154
11
  if (Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64)
155
7
    return Type;
156
4
  return R_AARCH64_NONE;
157
4
}
158
159
22
void AArch64::writeGotPlt(uint8_t *Buf, const Symbol &) const {
160
22
  write64le(Buf, In.Plt->getVA());
161
22
}
162
163
7
void AArch64::writePltHeader(uint8_t *Buf) const {
164
7
  const uint8_t PltData[] = {
165
7
      0xf0, 0x7b, 0xbf, 0xa9, // stp    x16, x30, [sp,#-16]!
166
7
      0x10, 0x00, 0x00, 0x90, // adrp   x16, Page(&(.plt.got[2]))
167
7
      0x11, 0x02, 0x40, 0xf9, // ldr    x17, [x16, Offset(&(.plt.got[2]))]
168
7
      0x10, 0x02, 0x00, 0x91, // add    x16, x16, Offset(&(.plt.got[2]))
169
7
      0x20, 0x02, 0x1f, 0xd6, // br     x17
170
7
      0x1f, 0x20, 0x03, 0xd5, // nop
171
7
      0x1f, 0x20, 0x03, 0xd5, // nop
172
7
      0x1f, 0x20, 0x03, 0xd5  // nop
173
7
  };
174
7
  memcpy(Buf, PltData, sizeof(PltData));
175
7
176
7
  uint64_t Got = In.GotPlt->getVA();
177
7
  uint64_t Plt = In.Plt->getVA();
178
7
  relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
179
7
              getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
180
7
  relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
181
7
  relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16);
182
7
}
183
184
void AArch64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
185
                       uint64_t PltEntryAddr, int32_t Index,
186
22
                       unsigned RelOff) const {
187
22
  const uint8_t Inst[] = {
188
22
      0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n]))
189
22
      0x11, 0x02, 0x40, 0xf9, // ldr  x17, [x16, Offset(&(.plt.got[n]))]
190
22
      0x10, 0x02, 0x00, 0x91, // add  x16, x16, Offset(&(.plt.got[n]))
191
22
      0x20, 0x02, 0x1f, 0xd6  // br   x17
192
22
  };
193
22
  memcpy(Buf, Inst, sizeof(Inst));
194
22
195
22
  relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21,
196
22
              getAArch64Page(GotPltEntryAddr) - getAArch64Page(PltEntryAddr));
197
22
  relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotPltEntryAddr);
198
22
  relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotPltEntryAddr);
199
22
}
200
201
bool AArch64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
202
454
                         uint64_t BranchAddr, const Symbol &S) const {
203
454
  // ELF for the ARM 64-bit architecture, section Call and Jump relocations
204
454
  // only permits range extension thunks for R_AARCH64_CALL26 and
205
454
  // R_AARCH64_JUMP26 relocation types.
206
454
  if (Type != R_AARCH64_CALL26 && 
Type != R_AARCH64_JUMP26429
)
207
373
    return false;
208
81
  uint64_t Dst = (Expr == R_PLT_PC) ? 
S.getPltVA()17
:
S.getVA()64
;
209
81
  return !inBranchRange(Type, BranchAddr, Dst);
210
81
}
211
212
183
uint32_t AArch64::getThunkSectionSpacing() const {
213
183
  // See comment in Arch/ARM.cpp for a more detailed explanation of
214
183
  // getThunkSectionSpacing(). For AArch64 the only branches we are permitted to
215
183
  // Thunk have a range of +/- 128 MiB
216
183
  return (128 * 1024 * 1024) - 0x30000;
217
183
}
218
219
99
bool AArch64::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
220
99
  if (Type != R_AARCH64_CALL26 && 
Type != R_AARCH64_JUMP2658
)
221
0
    return true;
222
99
  // The AArch64 call and unconditional branch instructions have a range of
223
99
  // +/- 128 MiB.
224
99
  uint64_t Range = 128 * 1024 * 1024;
225
99
  if (Dst > Src) {
226
89
    // Immediate of branch is signed.
227
89
    Range -= 4;
228
89
    return Dst - Src <= Range;
229
89
  }
230
10
  return Src - Dst <= Range;
231
10
}
232
233
137
static void write32AArch64Addr(uint8_t *L, uint64_t Imm) {
234
137
  uint32_t ImmLo = (Imm & 0x3) << 29;
235
137
  uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
236
137
  uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
237
137
  write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
238
137
}
239
240
// Return the bits [Start, End] from Val shifted Start bits.
241
// For instance, getBits(0xF0, 4, 8) returns 0xF.
242
137
static uint64_t getBits(uint64_t Val, int Start, int End) {
243
137
  uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
244
137
  return (Val >> Start) & Mask;
245
137
}
246
247
320
static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
248
249
// Update the immediate field in a AARCH64 ldr, str, and add instruction.
250
190
static void or32AArch64Imm(uint8_t *L, uint64_t Imm) {
251
190
  or32le(L, (Imm & 0xFFF) << 10);
252
190
}
253
254
531
void AArch64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
255
531
  switch (Type) {
256
531
  case R_AARCH64_ABS16:
257
13
  case R_AARCH64_PREL16:
258
13
    checkIntUInt(Loc, Val, 16, Type);
259
13
    write16le(Loc, Val);
260
13
    break;
261
16
  case R_AARCH64_ABS32:
262
16
  case R_AARCH64_PREL32:
263
16
    checkIntUInt(Loc, Val, 32, Type);
264
16
    write32le(Loc, Val);
265
16
    break;
266
45
  case R_AARCH64_ABS64:
267
45
  case R_AARCH64_GLOB_DAT:
268
45
  case R_AARCH64_PREL64:
269
45
    write64le(Loc, Val);
270
45
    break;
271
45
  case R_AARCH64_ADD_ABS_LO12_NC:
272
37
    or32AArch64Imm(Loc, Val);
273
37
    break;
274
133
  case R_AARCH64_ADR_GOT_PAGE:
275
133
  case R_AARCH64_ADR_PREL_PG_HI21:
276
133
  case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
277
133
  case R_AARCH64_TLSDESC_ADR_PAGE21:
278
133
    checkInt(Loc, Val, 33, Type);
279
133
    write32AArch64Addr(Loc, Val >> 12);
280
133
    break;
281
133
  case R_AARCH64_ADR_PREL_LO21:
282
4
    checkInt(Loc, Val, 21, Type);
283
4
    write32AArch64Addr(Loc, Val);
284
4
    break;
285
133
  case R_AARCH64_JUMP26:
286
82
    // Normally we would just write the bits of the immediate field, however
287
82
    // when patching instructions for the cpu errata fix -fix-cortex-a53-843419
288
82
    // we want to replace a non-branch instruction with a branch immediate
289
82
    // instruction. By writing all the bits of the instruction including the
290
82
    // opcode and the immediate (0 001 | 01 imm26) we can do this
291
82
    // transformation by placing a R_AARCH64_JUMP26 relocation at the offset of
292
82
    // the instruction we want to patch.
293
82
    write32le(Loc, 0x14000000);
294
82
    LLVM_FALLTHROUGH;
295
104
  case R_AARCH64_CALL26:
296
104
    checkInt(Loc, Val, 28, Type);
297
104
    or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
298
104
    break;
299
82
  case R_AARCH64_CONDBR19:
300
13
  case R_AARCH64_LD_PREL_LO19:
301
13
    checkAlignment(Loc, Val, 4, Type);
302
13
    checkInt(Loc, Val, 21, Type);
303
13
    or32le(Loc, (Val & 0x1FFFFC) << 3);
304
13
    break;
305
13
  case R_AARCH64_LDST8_ABS_LO12_NC:
306
4
  case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
307
4
    or32AArch64Imm(Loc, getBits(Val, 0, 11));
308
4
    break;
309
7
  case R_AARCH64_LDST16_ABS_LO12_NC:
310
7
  case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
311
7
    checkAlignment(Loc, Val, 2, Type);
312
7
    or32AArch64Imm(Loc, getBits(Val, 1, 11));
313
7
    break;
314
7
  case R_AARCH64_LDST32_ABS_LO12_NC:
315
5
  case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
316
5
    checkAlignment(Loc, Val, 4, Type);
317
5
    or32AArch64Imm(Loc, getBits(Val, 2, 11));
318
5
    break;
319
116
  case R_AARCH64_LDST64_ABS_LO12_NC:
320
116
  case R_AARCH64_LD64_GOT_LO12_NC:
321
116
  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
322
116
  case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
323
116
  case R_AARCH64_TLSDESC_LD64_LO12:
324
116
    checkAlignment(Loc, Val, 8, Type);
325
116
    or32AArch64Imm(Loc, getBits(Val, 3, 11));
326
116
    break;
327
116
  case R_AARCH64_LDST128_ABS_LO12_NC:
328
5
  case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
329
5
    checkAlignment(Loc, Val, 16, Type);
330
5
    or32AArch64Imm(Loc, getBits(Val, 4, 11));
331
5
    break;
332
5
  case R_AARCH64_MOVW_UABS_G0_NC:
333
1
    or32le(Loc, (Val & 0xFFFF) << 5);
334
1
    break;
335
5
  case R_AARCH64_MOVW_UABS_G1_NC:
336
1
    or32le(Loc, (Val & 0xFFFF0000) >> 11);
337
1
    break;
338
5
  case R_AARCH64_MOVW_UABS_G2_NC:
339
1
    or32le(Loc, (Val & 0xFFFF00000000) >> 27);
340
1
    break;
341
5
  case R_AARCH64_MOVW_UABS_G3:
342
2
    or32le(Loc, (Val & 0xFFFF000000000000) >> 43);
343
2
    break;
344
8
  case R_AARCH64_TSTBR14:
345
8
    checkInt(Loc, Val, 16, Type);
346
8
    or32le(Loc, (Val & 0xFFFC) << 3);
347
8
    break;
348
8
  case R_AARCH64_TLSLE_ADD_TPREL_HI12:
349
8
    checkUInt(Loc, Val, 24, Type);
350
8
    or32AArch64Imm(Loc, Val >> 12);
351
8
    break;
352
8
  case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
353
8
  case R_AARCH64_TLSDESC_ADD_LO12:
354
8
    or32AArch64Imm(Loc, Val);
355
8
    break;
356
8
  default:
357
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
358
531
  }
359
531
}
360
361
4
void AArch64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
362
4
  // TLSDESC Global-Dynamic relocation are in the form:
363
4
  //   adrp    x0, :tlsdesc:v             [R_AARCH64_TLSDESC_ADR_PAGE21]
364
4
  //   ldr     x1, [x0, #:tlsdesc_lo12:v  [R_AARCH64_TLSDESC_LD64_LO12]
365
4
  //   add     x0, x0, :tlsdesc_los:v     [R_AARCH64_TLSDESC_ADD_LO12]
366
4
  //   .tlsdesccall                       [R_AARCH64_TLSDESC_CALL]
367
4
  //   blr     x1
368
4
  // And it can optimized to:
369
4
  //   movz    x0, #0x0, lsl #16
370
4
  //   movk    x0, #0x10
371
4
  //   nop
372
4
  //   nop
373
4
  checkUInt(Loc, Val, 32, Type);
374
4
375
4
  switch (Type) {
376
4
  case R_AARCH64_TLSDESC_ADD_LO12:
377
2
  case R_AARCH64_TLSDESC_CALL:
378
2
    write32le(Loc, 0xd503201f); // nop
379
2
    return;
380
2
  case R_AARCH64_TLSDESC_ADR_PAGE21:
381
1
    write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
382
1
    return;
383
2
  case R_AARCH64_TLSDESC_LD64_LO12:
384
1
    write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk
385
1
    return;
386
2
  default:
387
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
388
4
  }
389
4
}
390
391
4
void AArch64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
392
4
  // TLSDESC Global-Dynamic relocation are in the form:
393
4
  //   adrp    x0, :tlsdesc:v             [R_AARCH64_TLSDESC_ADR_PAGE21]
394
4
  //   ldr     x1, [x0, #:tlsdesc_lo12:v  [R_AARCH64_TLSDESC_LD64_LO12]
395
4
  //   add     x0, x0, :tlsdesc_los:v     [R_AARCH64_TLSDESC_ADD_LO12]
396
4
  //   .tlsdesccall                       [R_AARCH64_TLSDESC_CALL]
397
4
  //   blr     x1
398
4
  // And it can optimized to:
399
4
  //   adrp    x0, :gottprel:v
400
4
  //   ldr     x0, [x0, :gottprel_lo12:v]
401
4
  //   nop
402
4
  //   nop
403
4
404
4
  switch (Type) {
405
4
  case R_AARCH64_TLSDESC_ADD_LO12:
406
2
  case R_AARCH64_TLSDESC_CALL:
407
2
    write32le(Loc, 0xd503201f); // nop
408
2
    break;
409
2
  case R_AARCH64_TLSDESC_ADR_PAGE21:
410
1
    write32le(Loc, 0x90000000); // adrp
411
1
    relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val);
412
1
    break;
413
2
  case R_AARCH64_TLSDESC_LD64_LO12:
414
1
    write32le(Loc, 0xf9400000); // ldr
415
1
    relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val);
416
1
    break;
417
2
  default:
418
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
419
4
  }
420
4
}
421
422
7
void AArch64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
423
7
  checkUInt(Loc, Val, 32, Type);
424
7
425
7
  if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
426
4
    // Generate MOVZ.
427
4
    uint32_t RegNo = read32le(Loc) & 0x1f;
428
4
    write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
429
4
    return;
430
4
  }
431
3
  if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
432
3
    // Generate MOVK.
433
3
    uint32_t RegNo = read32le(Loc) & 0x1f;
434
3
    write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
435
3
    return;
436
3
  }
437
0
  llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
438
0
}
439
440
98
TargetInfo *elf::getAArch64TargetInfo() {
441
98
  static AArch64 Target;
442
98
  return &Target;
443
98
}