Coverage Report

Created: 2018-06-25 02:00

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/ARM.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- ARM.cpp ------------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#include "InputFiles.h"
11
#include "Symbols.h"
12
#include "SyntheticSections.h"
13
#include "Target.h"
14
#include "Thunks.h"
15
#include "lld/Common/ErrorHandler.h"
16
#include "llvm/Object/ELF.h"
17
#include "llvm/Support/Endian.h"
18
19
using namespace llvm;
20
using namespace llvm::support::endian;
21
using namespace llvm::ELF;
22
using namespace lld;
23
using namespace lld::elf;
24
25
namespace {
26
class ARM final : public TargetInfo {
27
public:
28
  ARM();
29
  uint32_t calcEFlags() const override;
30
  RelExpr getRelExpr(RelType Type, const Symbol &S,
31
                     const uint8_t *Loc) const override;
32
  RelType getDynRel(RelType Type) const override;
33
  int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
34
  void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
35
  void writeIgotPlt(uint8_t *Buf, const Symbol &S) const override;
36
  void writePltHeader(uint8_t *Buf) const override;
37
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
38
                int32_t Index, unsigned RelOff) const override;
39
  void addPltSymbols(InputSection &IS, uint64_t Off) const override;
40
  void addPltHeaderSymbols(InputSection &ISD) const override;
41
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
42
                  uint64_t BranchAddr, const Symbol &S) const override;
43
  bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
44
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
45
};
46
} // namespace
47
48
120
ARM::ARM() {
49
120
  CopyRel = R_ARM_COPY;
50
120
  RelativeRel = R_ARM_RELATIVE;
51
120
  IRelativeRel = R_ARM_IRELATIVE;
52
120
  GotRel = R_ARM_GLOB_DAT;
53
120
  PltRel = R_ARM_JUMP_SLOT;
54
120
  TlsGotRel = R_ARM_TLS_TPOFF32;
55
120
  TlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
56
120
  TlsOffsetRel = R_ARM_TLS_DTPOFF32;
57
120
  GotBaseSymInGotPlt = false;
58
120
  GotEntrySize = 4;
59
120
  GotPltEntrySize = 4;
60
120
  PltEntrySize = 16;
61
120
  PltHeaderSize = 32;
62
120
  TrapInstr = 0xd4d4d4d4;
63
120
  // ARM uses Variant 1 TLS
64
120
  TcbSize = 8;
65
120
  NeedsThunks = true;
66
120
67
120
  // The placing of pre-created ThunkSections is controlled by the
68
120
  // ThunkSectionSpacing parameter. The aim is to place the
69
120
  // ThunkSection such that all branches from the InputSections prior to the
70
120
  // ThunkSection can reach a Thunk placed at the end of the ThunkSection.
71
120
  // Graphically:
72
120
  // | up to ThunkSectionSpacing .text input sections |
73
120
  // | ThunkSection                                   |
74
120
  // | up to ThunkSectionSpacing .text input sections |
75
120
  // | ThunkSection                                   |
76
120
77
120
  // Pre-created ThunkSections are spaced roughly 16MiB apart on ARM. This is to
78
120
  // match the most common expected case of a Thumb 2 encoded BL, BLX or B.W
79
120
  // ARM B, BL, BLX range +/- 32MiB
80
120
  // Thumb B.W, BL, BLX range +/- 16MiB
81
120
  // Thumb B<cc>.W range +/- 1MiB
82
120
  // If a branch cannot reach a pre-created ThunkSection a new one will be
83
120
  // created so we can handle the rare cases of a Thumb 2 conditional branch.
84
120
  // We intentionally use a lower size for ThunkSectionSpacing than the maximum
85
120
  // branch range so the end of the ThunkSection is more likely to be within
86
120
  // range of the branch instruction that is furthest away. The value we shorten
87
120
  // ThunkSectionSpacing by is set conservatively to allow us to create 16,384
88
120
  // 12 byte Thunks at any offset in a ThunkSection without risk of a branch to
89
120
  // one of the Thunks going out of range.
90
120
91
120
  // FIXME: lld assumes that the Thumb BL and BLX encoding permits the J1 and
92
120
  // J2 bits to be used to extend the branch range. On earlier Architectures
93
120
  // such as ARMv4, ARMv5 and ARMv6 (except ARMv6T2) the range is +/- 4MiB. If
94
120
  // support for the earlier encodings is added then when they are used the
95
120
  // ThunkSectionSpacing will need lowering.
96
120
  ThunkSectionSpacing = 0x1000000 - 0x30000;
97
120
}
98
99
120
uint32_t ARM::calcEFlags() const {
100
120
  // We don't currently use any features incompatible with EF_ARM_EABI_VER5,
101
120
  // but we don't have any firm guarantees of conformance. Linux AArch64
102
120
  // kernels (as of 2016) require an EABI version to be set.
103
120
  return EF_ARM_EABI_VER5;
104
120
}
105
106
RelExpr ARM::getRelExpr(RelType Type, const Symbol &S,
107
524
                        const uint8_t *Loc) const {
108
524
  switch (Type) {
109
524
  case R_ARM_THM_JUMP11:
110
4
    return R_PC;
111
524
  case R_ARM_CALL:
112
346
  case R_ARM_JUMP24:
113
346
  case R_ARM_PC24:
114
346
  case R_ARM_PLT32:
115
346
  case R_ARM_PREL31:
116
346
  case R_ARM_THM_JUMP19:
117
346
  case R_ARM_THM_JUMP24:
118
346
  case R_ARM_THM_CALL:
119
346
    return R_PLT_PC;
120
346
  case R_ARM_GOTOFF32:
121
3
    // (S + A) - GOT_ORG
122
3
    return R_GOTREL;
123
346
  case R_ARM_GOT_BREL:
124
5
    // GOT(S) + A - GOT_ORG
125
5
    return R_GOT_OFF;
126
346
  case R_ARM_GOT_PREL:
127
6
  case R_ARM_TLS_IE32:
128
6
    // GOT(S) + A - P
129
6
    return R_GOT_PC;
130
6
  case R_ARM_SBREL32:
131
4
    return R_ARM_SBREL;
132
6
  case R_ARM_TARGET1:
133
4
    return Config->Target1Rel ? 
R_PC2
:
R_ABS2
;
134
6
  case R_ARM_TARGET2:
135
4
    if (Config->Target2 == Target2Policy::Rel)
136
1
      return R_PC;
137
3
    if (Config->Target2 == Target2Policy::Abs)
138
1
      return R_ABS;
139
2
    return R_GOT_PC;
140
14
  case R_ARM_TLS_GD32:
141
14
    return R_TLSGD_PC;
142
2
  case R_ARM_TLS_LDM32:
143
2
    return R_TLSLD_PC;
144
2
  case R_ARM_BASE_PREL:
145
0
    // B(S) + A - P
146
0
    // FIXME: currently B(S) assumed to be .got, this may not hold for all
147
0
    // platforms.
148
0
    return R_GOTONLY_PC;
149
27
  case R_ARM_MOVW_PREL_NC:
150
27
  case R_ARM_MOVT_PREL:
151
27
  case R_ARM_REL32:
152
27
  case R_ARM_THM_MOVW_PREL_NC:
153
27
  case R_ARM_THM_MOVT_PREL:
154
27
    return R_PC;
155
27
  case R_ARM_NONE:
156
13
    return R_NONE;
157
27
  case R_ARM_TLS_LE32:
158
3
    return R_TLS;
159
89
  default:
160
89
    return R_ABS;
161
524
  }
162
524
}
163
164
5
RelType ARM::getDynRel(RelType Type) const {
165
5
  if ((Type == R_ARM_ABS32) || 
(0
Type == R_ARM_TARGET10
&&
!Config->Target1Rel0
))
166
5
    return R_ARM_ABS32;
167
0
  return R_ARM_NONE;
168
0
}
169
170
43
void ARM::writeGotPlt(uint8_t *Buf, const Symbol &) const {
171
43
  write32le(Buf, InX::Plt->getVA());
172
43
}
173
174
6
void ARM::writeIgotPlt(uint8_t *Buf, const Symbol &S) const {
175
6
  // An ARM entry is the address of the ifunc resolver function.
176
6
  write32le(Buf, S.getVA());
177
6
}
178
179
// Long form PLT Header that does not have any restrictions on the displacement
180
// of the .plt from the .plt.got.
181
2
static void writePltHeaderLong(uint8_t *Buf) {
182
2
  const uint8_t PltData[] = {
183
2
      0x04, 0xe0, 0x2d, 0xe5, //     str lr, [sp,#-4]!
184
2
      0x04, 0xe0, 0x9f, 0xe5, //     ldr lr, L2
185
2
      0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr
186
2
      0x08, 0xf0, 0xbe, 0xe5, //     ldr pc, [lr, #8]
187
2
      0x00, 0x00, 0x00, 0x00, // L2: .word   &(.got.plt) - L1 - 8
188
2
      0xd4, 0xd4, 0xd4, 0xd4, //     Pad to 32-byte boundary
189
2
      0xd4, 0xd4, 0xd4, 0xd4, //     Pad to 32-byte boundary
190
2
      0xd4, 0xd4, 0xd4, 0xd4};
191
2
  memcpy(Buf, PltData, sizeof(PltData));
192
2
  uint64_t GotPlt = InX::GotPlt->getVA();
193
2
  uint64_t L1 = InX::Plt->getVA() + 8;
194
2
  write32le(Buf + 16, GotPlt - L1 - 8);
195
2
}
196
197
// The default PLT header requires the .plt.got to be within 128 Mb of the
198
// .plt in the positive direction.
199
19
void ARM::writePltHeader(uint8_t *Buf) const {
200
19
  // Use a similar sequence to that in writePlt(), the difference is the calling
201
19
  // conventions mean we use lr instead of ip. The PLT entry is responsible for
202
19
  // saving lr on the stack, the dynamic loader is responsible for reloading
203
19
  // it.
204
19
  const uint32_t PltData[] = {
205
19
      0xe52de004, // L1: str lr, [sp,#-4]!
206
19
      0xe28fe600, //     add lr, pc,  #0x0NN00000 &(.got.plt - L1 - 4)
207
19
      0xe28eea00, //     add lr, lr,  #0x000NN000 &(.got.plt - L1 - 4)
208
19
      0xe5bef000, //     ldr pc, [lr, #0x00000NNN] &(.got.plt -L1 - 4)
209
19
  };
210
19
211
19
  uint64_t Offset = InX::GotPlt->getVA() - InX::Plt->getVA() - 4;
212
19
  if (!llvm::isUInt<27>(Offset)) {
213
2
    // We cannot encode the Offset, use the long form.
214
2
    writePltHeaderLong(Buf);
215
2
    return;
216
2
  }
217
17
  write32le(Buf + 0, PltData[0]);
218
17
  write32le(Buf + 4, PltData[1] | ((Offset >> 20) & 0xff));
219
17
  write32le(Buf + 8, PltData[2] | ((Offset >> 12) & 0xff));
220
17
  write32le(Buf + 12, PltData[3] | (Offset & 0xfff));
221
17
  write32le(Buf + 16, TrapInstr); // Pad to 32-byte boundary
222
17
  write32le(Buf + 20, TrapInstr);
223
17
  write32le(Buf + 24, TrapInstr);
224
17
  write32le(Buf + 28, TrapInstr);
225
17
}
226
227
19
void ARM::addPltHeaderSymbols(InputSection &IS) const {
228
19
  addSyntheticLocal("$a", STT_NOTYPE, 0, 0, IS);
229
19
  addSyntheticLocal("$d", STT_NOTYPE, 16, 0, IS);
230
19
}
231
232
// Long form PLT entries that do not have any restrictions on the displacement
233
// of the .plt from the .plt.got.
234
static void writePltLong(uint8_t *Buf, uint64_t GotPltEntryAddr,
235
                         uint64_t PltEntryAddr, int32_t Index,
236
4
                         unsigned RelOff) {
237
4
  const uint8_t PltData[] = {
238
4
      0x04, 0xc0, 0x9f, 0xe5, //     ldr ip, L2
239
4
      0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc
240
4
      0x00, 0xf0, 0x9c, 0xe5, //     ldr pc, [ip]
241
4
      0x00, 0x00, 0x00, 0x00, // L2: .word   Offset(&(.plt.got) - L1 - 8
242
4
  };
243
4
  memcpy(Buf, PltData, sizeof(PltData));
244
4
  uint64_t L1 = PltEntryAddr + 4;
245
4
  write32le(Buf + 12, GotPltEntryAddr - L1 - 8);
246
4
}
247
248
// The default PLT entries require the .plt.got to be within 128 Mb of the
249
// .plt in the positive direction.
250
void ARM::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
251
                   uint64_t PltEntryAddr, int32_t Index,
252
49
                   unsigned RelOff) const {
253
49
  // The PLT entry is similar to the example given in Appendix A of ELF for
254
49
  // the Arm Architecture. Instead of using the Group Relocations to find the
255
49
  // optimal rotation for the 8-bit immediate used in the add instructions we
256
49
  // hard code the most compact rotations for simplicity. This saves a load
257
49
  // instruction over the long plt sequences.
258
49
  const uint32_t PltData[] = {
259
49
      0xe28fc600, // L1: add ip, pc,  #0x0NN00000  Offset(&(.plt.got) - L1 - 8
260
49
      0xe28cca00, //     add ip, ip,  #0x000NN000  Offset(&(.plt.got) - L1 - 8
261
49
      0xe5bcf000, //     ldr pc, [ip, #0x00000NNN] Offset(&(.plt.got) - L1 - 8
262
49
  };
263
49
264
49
  uint64_t Offset = GotPltEntryAddr - PltEntryAddr - 8;
265
49
  if (!llvm::isUInt<27>(Offset)) {
266
4
    // We cannot encode the Offset, use the long form.
267
4
    writePltLong(Buf, GotPltEntryAddr, PltEntryAddr, Index, RelOff);
268
4
    return;
269
4
  }
270
45
  write32le(Buf + 0, PltData[0] | ((Offset >> 20) & 0xff));
271
45
  write32le(Buf + 4, PltData[1] | ((Offset >> 12) & 0xff));
272
45
  write32le(Buf + 8, PltData[2] | (Offset & 0xfff));
273
45
  write32le(Buf + 12, TrapInstr); // Pad to 16-byte boundary
274
45
}
275
276
49
void ARM::addPltSymbols(InputSection &IS, uint64_t Off) const {
277
49
  addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS);
278
49
  addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS);
279
49
}
280
281
bool ARM::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
282
424
                     uint64_t BranchAddr, const Symbol &S) const {
283
424
  // If S is an undefined weak symbol and does not have a PLT entry then it
284
424
  // will be resolved as a branch to the next instruction.
285
424
  if (S.isUndefWeak() && 
!S.isInPlt()17
)
286
15
    return false;
287
409
  // A state change from ARM to Thumb and vice versa must go through an
288
409
  // interworking thunk if the relocation type is not R_ARM_CALL or
289
409
  // R_ARM_THM_CALL.
290
409
  switch (Type) {
291
409
  case R_ARM_PC24:
292
67
  case R_ARM_PLT32:
293
67
  case R_ARM_JUMP24:
294
67
    // Source is ARM, all PLT entries are ARM so no interworking required.
295
67
    // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
296
67
    if (Expr == R_PC && 
((S.getVA() & 1) == 1)42
)
297
14
      return true;
298
53
    LLVM_FALLTHROUGH;
299
133
  case R_ARM_CALL: {
300
133
    uint64_t Dst = (Expr == R_PLT_PC) ? 
S.getPltVA()52
:
S.getVA()81
;
301
133
    return !inBranchRange(Type, BranchAddr, Dst);
302
53
  }
303
53
  case R_ARM_THM_JUMP19:
304
48
  case R_ARM_THM_JUMP24:
305
48
    // Source is Thumb, all PLT entries are ARM so interworking is required.
306
48
    // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
307
48
    if (Expr == R_PLT_PC || 
((S.getVA() & 1) == 0)35
)
308
31
      return true;
309
17
    LLVM_FALLTHROUGH;
310
133
  case R_ARM_THM_CALL: {
311
133
    uint64_t Dst = (Expr == R_PLT_PC) ? 
S.getPltVA()12
:
S.getVA()121
;
312
133
    return !inBranchRange(Type, BranchAddr, Dst);
313
98
  }
314
98
  }
315
98
  return false;
316
98
}
317
318
533
bool ARM::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
319
533
  uint64_t Range;
320
533
  uint64_t InstrSize;
321
533
322
533
  switch (Type) {
323
533
  case R_ARM_PC24:
324
186
  case R_ARM_PLT32:
325
186
  case R_ARM_JUMP24:
326
186
  case R_ARM_CALL:
327
186
    Range = 0x2000000;
328
186
    InstrSize = 4;
329
186
    break;
330
186
  case R_ARM_THM_JUMP19:
331
51
    Range = 0x100000;
332
51
    InstrSize = 2;
333
51
    break;
334
296
  case R_ARM_THM_JUMP24:
335
296
  case R_ARM_THM_CALL:
336
296
    Range = 0x1000000;
337
296
    InstrSize = 2;
338
296
    break;
339
296
  default:
340
0
    return true;
341
533
  }
342
533
  // PC at Src is 2 instructions ahead, immediate of branch is signed
343
533
  if (Src > Dst)
344
181
    Range -= 2 * InstrSize;
345
352
  else
346
352
    Range += InstrSize;
347
533
348
533
  if ((Dst & 0x1) == 0)
349
274
    // Destination is ARM, if ARM caller then Src is already 4-byte aligned.
350
274
    // If Thumb Caller (BLX) the Src address has bottom 2 bits cleared to ensure
351
274
    // destination will be 4 byte aligned.
352
274
    Src &= ~0x3;
353
259
  else
354
259
    // Bit 0 == 1 denotes Thumb state, it is not part of the range
355
259
    Dst &= ~0x1;
356
533
357
533
  uint64_t Distance = (Src > Dst) ? 
Src - Dst180
:
Dst - Src353
;
358
533
  return Distance <= Range;
359
533
}
360
361
701
void ARM::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
362
701
  switch (Type) {
363
701
  case R_ARM_ABS32:
364
120
  case R_ARM_BASE_PREL:
365
120
  case R_ARM_GLOB_DAT:
366
120
  case R_ARM_GOTOFF32:
367
120
  case R_ARM_GOT_BREL:
368
120
  case R_ARM_GOT_PREL:
369
120
  case R_ARM_REL32:
370
120
  case R_ARM_RELATIVE:
371
120
  case R_ARM_SBREL32:
372
120
  case R_ARM_TARGET1:
373
120
  case R_ARM_TARGET2:
374
120
  case R_ARM_TLS_GD32:
375
120
  case R_ARM_TLS_IE32:
376
120
  case R_ARM_TLS_LDM32:
377
120
  case R_ARM_TLS_LDO32:
378
120
  case R_ARM_TLS_LE32:
379
120
  case R_ARM_TLS_TPOFF32:
380
120
  case R_ARM_TLS_DTPOFF32:
381
120
    write32le(Loc, Val);
382
120
    break;
383
120
  case R_ARM_TLS_DTPMOD32:
384
6
    write32le(Loc, 1);
385
6
    break;
386
120
  case R_ARM_PREL31:
387
109
    checkInt(Loc, Val, 31, Type);
388
109
    write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000));
389
109
    break;
390
120
  case R_ARM_CALL:
391
66
    // R_ARM_CALL is used for BL and BLX instructions, depending on the
392
66
    // value of bit 0 of Val, we must select a BL or BLX instruction
393
66
    if (Val & 1) {
394
20
      // If bit 0 of Val is 1 the target is Thumb, we must select a BLX.
395
20
      // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
396
20
      checkInt(Loc, Val, 26, Type);
397
20
      write32le(Loc, 0xfa000000 |                    // opcode
398
20
                         ((Val & 2) << 23) |         // H
399
20
                         ((Val >> 2) & 0x00ffffff)); // imm24
400
20
      break;
401
20
    }
402
46
    if ((read32le(Loc) & 0xfe000000) == 0xfa000000)
403
4
      // BLX (always unconditional) instruction to an ARM Target, select an
404
4
      // unconditional BL.
405
4
      write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff));
406
46
    // fall through as BL encoding is shared with B
407
46
    LLVM_FALLTHROUGH;
408
101
  case R_ARM_JUMP24:
409
101
  case R_ARM_PC24:
410
101
  case R_ARM_PLT32:
411
101
    checkInt(Loc, Val, 26, Type);
412
101
    write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff));
413
101
    break;
414
101
  case R_ARM_THM_JUMP11:
415
4
    checkInt(Loc, Val, 12, Type);
416
4
    write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff));
417
4
    break;
418
101
  case R_ARM_THM_JUMP19:
419
19
    // Encoding T3: Val = S:J2:J1:imm6:imm11:0
420
19
    checkInt(Loc, Val, 21, Type);
421
19
    write16le(Loc,
422
19
              (read16le(Loc) & 0xfbc0) |   // opcode cond
423
19
                  ((Val >> 10) & 0x0400) | // S
424
19
                  ((Val >> 12) & 0x003f)); // imm6
425
19
    write16le(Loc + 2,
426
19
              0x8000 |                    // opcode
427
19
                  ((Val >> 8) & 0x0800) | // J2
428
19
                  ((Val >> 5) & 0x2000) | // J1
429
19
                  ((Val >> 1) & 0x07ff)); // imm11
430
19
    break;
431
101
  case R_ARM_THM_CALL:
432
93
    // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
433
93
    // value of bit 0 of Val, we must select a BL or BLX instruction
434
93
    if ((Val & 1) == 0) {
435
17
      // Ensure BLX destination is 4-byte aligned. As BLX instruction may
436
17
      // only be two byte aligned. This must be done before overflow check
437
17
      Val = alignTo(Val, 4);
438
17
    }
439
93
    // Bit 12 is 0 for BLX, 1 for BL
440
93
    write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12);
441
93
    // Fall through as rest of encoding is the same as B.W
442
93
    LLVM_FALLTHROUGH;
443
143
  case R_ARM_THM_JUMP24:
444
143
    // Encoding B  T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
445
143
    // FIXME: Use of I1 and I2 require v6T2ops
446
143
    checkInt(Loc, Val, 25, Type);
447
143
    write16le(Loc,
448
143
              0xf000 |                     // opcode
449
143
                  ((Val >> 14) & 0x0400) | // S
450
143
                  ((Val >> 12) & 0x03ff)); // imm10
451
143
    write16le(Loc + 2,
452
143
              (read16le(Loc + 2) & 0xd000) |                  // opcode
453
143
                  (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1
454
143
                  (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2
455
143
                  ((Val >> 1) & 0x07ff));                     // imm11
456
143
    break;
457
93
  case R_ARM_MOVW_ABS_NC:
458
32
  case R_ARM_MOVW_PREL_NC:
459
32
    write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) |
460
32
                       (Val & 0x0fff));
461
32
    break;
462
32
  case R_ARM_MOVT_ABS:
463
32
  case R_ARM_MOVT_PREL:
464
32
    checkInt(Loc, Val, 32, Type);
465
32
    write32le(Loc, (read32le(Loc) & ~0x000f0fff) |
466
32
                       (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff));
467
32
    break;
468
57
  case R_ARM_THM_MOVT_ABS:
469
57
  case R_ARM_THM_MOVT_PREL:
470
57
    // Encoding T1: A = imm4:i:imm3:imm8
471
57
    checkInt(Loc, Val, 32, Type);
472
57
    write16le(Loc,
473
57
              0xf2c0 |                     // opcode
474
57
                  ((Val >> 17) & 0x0400) | // i
475
57
                  ((Val >> 28) & 0x000f)); // imm4
476
57
    write16le(Loc + 2,
477
57
              (read16le(Loc + 2) & 0x8f00) | // opcode
478
57
                  ((Val >> 12) & 0x7000) |   // imm3
479
57
                  ((Val >> 16) & 0x00ff));   // imm8
480
57
    break;
481
57
  case R_ARM_THM_MOVW_ABS_NC:
482
57
  case R_ARM_THM_MOVW_PREL_NC:
483
57
    // Encoding T3: A = imm4:i:imm3:imm8
484
57
    write16le(Loc,
485
57
              0xf240 |                     // opcode
486
57
                  ((Val >> 1) & 0x0400) |  // i
487
57
                  ((Val >> 12) & 0x000f)); // imm4
488
57
    write16le(Loc + 2,
489
57
              (read16le(Loc + 2) & 0x8f00) | // opcode
490
57
                  ((Val << 4) & 0x7000) |    // imm3
491
57
                  (Val & 0x00ff));           // imm8
492
57
    break;
493
57
  default:
494
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
495
701
  }
496
701
}
497
498
527
int64_t ARM::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
499
527
  switch (Type) {
500
527
  default:
501
4
    return 0;
502
527
  case R_ARM_ABS32:
503
107
  case R_ARM_BASE_PREL:
504
107
  case R_ARM_GOTOFF32:
505
107
  case R_ARM_GOT_BREL:
506
107
  case R_ARM_GOT_PREL:
507
107
  case R_ARM_REL32:
508
107
  case R_ARM_TARGET1:
509
107
  case R_ARM_TARGET2:
510
107
  case R_ARM_TLS_GD32:
511
107
  case R_ARM_TLS_LDM32:
512
107
  case R_ARM_TLS_LDO32:
513
107
  case R_ARM_TLS_IE32:
514
107
  case R_ARM_TLS_LE32:
515
107
    return SignExtend64<32>(read32le(Buf));
516
107
  case R_ARM_PREL31:
517
101
    return SignExtend64<31>(read32le(Buf));
518
118
  case R_ARM_CALL:
519
118
  case R_ARM_JUMP24:
520
118
  case R_ARM_PC24:
521
118
  case R_ARM_PLT32:
522
118
    return SignExtend64<26>(read32le(Buf) << 2);
523
118
  case R_ARM_THM_JUMP11:
524
4
    return SignExtend64<12>(read16le(Buf) << 1);
525
118
  case R_ARM_THM_JUMP19: {
526
20
    // Encoding T3: A = S:J2:J1:imm10:imm6:0
527
20
    uint16_t Hi = read16le(Buf);
528
20
    uint16_t Lo = read16le(Buf + 2);
529
20
    return SignExtend64<20>(((Hi & 0x0400) << 10) | // S
530
20
                            ((Lo & 0x0800) << 8) |  // J2
531
20
                            ((Lo & 0x2000) << 5) |  // J1
532
20
                            ((Hi & 0x003f) << 12) | // imm6
533
20
                            ((Lo & 0x07ff) << 1));  // imm11:0
534
118
  }
535
123
  case R_ARM_THM_CALL:
536
123
  case R_ARM_THM_JUMP24: {
537
123
    // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
538
123
    // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
539
123
    // FIXME: I1 and I2 require v6T2ops
540
123
    uint16_t Hi = read16le(Buf);
541
123
    uint16_t Lo = read16le(Buf + 2);
542
123
    return SignExtend64<24>(((Hi & 0x0400) << 14) |                    // S
543
123
                            (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1
544
123
                            (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2
545
123
                            ((Hi & 0x003ff) << 12) |                   // imm0
546
123
                            ((Lo & 0x007ff) << 1)); // imm11:0
547
123
  }
548
123
  // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and
549
123
  // MOVT is in the range -32768 <= A < 32768
550
123
  case R_ARM_MOVW_ABS_NC:
551
28
  case R_ARM_MOVT_ABS:
552
28
  case R_ARM_MOVW_PREL_NC:
553
28
  case R_ARM_MOVT_PREL: {
554
28
    uint64_t Val = read32le(Buf) & 0x000f0fff;
555
28
    return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff));
556
28
  }
557
28
  case R_ARM_THM_MOVW_ABS_NC:
558
22
  case R_ARM_THM_MOVT_ABS:
559
22
  case R_ARM_THM_MOVW_PREL_NC:
560
22
  case R_ARM_THM_MOVT_PREL: {
561
22
    // Encoding T3: A = imm4:i:imm3:imm8
562
22
    uint16_t Hi = read16le(Buf);
563
22
    uint16_t Lo = read16le(Buf + 2);
564
22
    return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4
565
22
                            ((Hi & 0x0400) << 1) |  // i
566
22
                            ((Lo & 0x7000) >> 4) |  // imm3
567
22
                            (Lo & 0x00ff));         // imm8
568
22
  }
569
527
  }
570
527
}
571
572
120
TargetInfo *elf::getARMTargetInfo() {
573
120
  static ARM Target;
574
120
  return &Target;
575
120
}