Coverage Report

Created: 2018-10-23 15:26

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/ARM.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- ARM.cpp ------------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#include "InputFiles.h"
11
#include "Symbols.h"
12
#include "SyntheticSections.h"
13
#include "Target.h"
14
#include "Thunks.h"
15
#include "lld/Common/ErrorHandler.h"
16
#include "llvm/Object/ELF.h"
17
#include "llvm/Support/Endian.h"
18
19
using namespace llvm;
20
using namespace llvm::support::endian;
21
using namespace llvm::ELF;
22
using namespace lld;
23
using namespace lld::elf;
24
25
namespace {
26
class ARM final : public TargetInfo {
27
public:
28
  ARM();
29
  uint32_t calcEFlags() const override;
30
  RelExpr getRelExpr(RelType Type, const Symbol &S,
31
                     const uint8_t *Loc) const override;
32
  RelType getDynRel(RelType Type) const override;
33
  int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
34
  void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
35
  void writeIgotPlt(uint8_t *Buf, const Symbol &S) const override;
36
  void writePltHeader(uint8_t *Buf) const override;
37
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
38
                int32_t Index, unsigned RelOff) const override;
39
  void addPltSymbols(InputSection &IS, uint64_t Off) const override;
40
  void addPltHeaderSymbols(InputSection &ISD) const override;
41
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
42
                  uint64_t BranchAddr, const Symbol &S) const override;
43
  uint32_t getThunkSectionSpacing() const override;
44
  bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
45
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
46
};
47
} // namespace
48
49
145
ARM::ARM() {
50
145
  CopyRel = R_ARM_COPY;
51
145
  RelativeRel = R_ARM_RELATIVE;
52
145
  IRelativeRel = R_ARM_IRELATIVE;
53
145
  GotRel = R_ARM_GLOB_DAT;
54
145
  NoneRel = R_ARM_NONE;
55
145
  PltRel = R_ARM_JUMP_SLOT;
56
145
  TlsGotRel = R_ARM_TLS_TPOFF32;
57
145
  TlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
58
145
  TlsOffsetRel = R_ARM_TLS_DTPOFF32;
59
145
  GotBaseSymInGotPlt = false;
60
145
  GotEntrySize = 4;
61
145
  GotPltEntrySize = 4;
62
145
  PltEntrySize = 16;
63
145
  PltHeaderSize = 32;
64
145
  TrapInstr = 0xd4d4d4d4;
65
145
  // ARM uses Variant 1 TLS
66
145
  TcbSize = 8;
67
145
  NeedsThunks = true;
68
145
}
69
70
138
uint32_t ARM::calcEFlags() const {
71
138
  // The ABIFloatType is used by loaders to detect the floating point calling
72
138
  // convention.
73
138
  uint32_t ABIFloatType = 0;
74
138
  if (Config->ARMVFPArgs == ARMVFPArgKind::Base ||
75
138
      
Config->ARMVFPArgs == ARMVFPArgKind::Default136
)
76
134
    ABIFloatType = EF_ARM_ABI_FLOAT_SOFT;
77
4
  else if (Config->ARMVFPArgs == ARMVFPArgKind::VFP)
78
2
    ABIFloatType = EF_ARM_ABI_FLOAT_HARD;
79
138
80
138
  // We don't currently use any features incompatible with EF_ARM_EABI_VER5,
81
138
  // but we don't have any firm guarantees of conformance. Linux AArch64
82
138
  // kernels (as of 2016) require an EABI version to be set.
83
138
  return EF_ARM_EABI_VER5 | ABIFloatType;
84
138
}
85
86
RelExpr ARM::getRelExpr(RelType Type, const Symbol &S,
87
596
                        const uint8_t *Loc) const {
88
596
  switch (Type) {
89
596
  case R_ARM_THM_JUMP11:
90
5
    return R_PC;
91
596
  case R_ARM_CALL:
92
354
  case R_ARM_JUMP24:
93
354
  case R_ARM_PC24:
94
354
  case R_ARM_PLT32:
95
354
  case R_ARM_PREL31:
96
354
  case R_ARM_THM_JUMP19:
97
354
  case R_ARM_THM_JUMP24:
98
354
  case R_ARM_THM_CALL:
99
354
    return R_PLT_PC;
100
354
  case R_ARM_GOTOFF32:
101
3
    // (S + A) - GOT_ORG
102
3
    return R_GOTREL;
103
354
  case R_ARM_GOT_BREL:
104
5
    // GOT(S) + A - GOT_ORG
105
5
    return R_GOT_OFF;
106
354
  case R_ARM_GOT_PREL:
107
6
  case R_ARM_TLS_IE32:
108
6
    // GOT(S) + A - P
109
6
    return R_GOT_PC;
110
6
  case R_ARM_SBREL32:
111
4
    return R_ARM_SBREL;
112
6
  case R_ARM_TARGET1:
113
4
    return Config->Target1Rel ? 
R_PC2
:
R_ABS2
;
114
6
  case R_ARM_TARGET2:
115
4
    if (Config->Target2 == Target2Policy::Rel)
116
1
      return R_PC;
117
3
    if (Config->Target2 == Target2Policy::Abs)
118
1
      return R_ABS;
119
2
    return R_GOT_PC;
120
14
  case R_ARM_TLS_GD32:
121
14
    return R_TLSGD_PC;
122
2
  case R_ARM_TLS_LDM32:
123
2
    return R_TLSLD_PC;
124
2
  case R_ARM_BASE_PREL:
125
0
    // B(S) + A - P
126
0
    // FIXME: currently B(S) assumed to be .got, this may not hold for all
127
0
    // platforms.
128
0
    return R_GOTONLY_PC;
129
27
  case R_ARM_MOVW_PREL_NC:
130
27
  case R_ARM_MOVT_PREL:
131
27
  case R_ARM_REL32:
132
27
  case R_ARM_THM_MOVW_PREL_NC:
133
27
  case R_ARM_THM_MOVT_PREL:
134
27
    return R_PC;
135
27
  case R_ARM_NONE:
136
13
    return R_NONE;
137
27
  case R_ARM_TLS_LE32:
138
3
    return R_TLS;
139
152
  default:
140
152
    return R_ABS;
141
596
  }
142
596
}
143
144
7
RelType ARM::getDynRel(RelType Type) const {
145
7
  if ((Type == R_ARM_ABS32) || 
(0
Type == R_ARM_TARGET10
&&
!Config->Target1Rel0
))
146
7
    return R_ARM_ABS32;
147
0
  return R_ARM_NONE;
148
0
}
149
150
43
void ARM::writeGotPlt(uint8_t *Buf, const Symbol &) const {
151
43
  write32le(Buf, In.Plt->getVA());
152
43
}
153
154
6
void ARM::writeIgotPlt(uint8_t *Buf, const Symbol &S) const {
155
6
  // An ARM entry is the address of the ifunc resolver function.
156
6
  write32le(Buf, S.getVA());
157
6
}
158
159
// Long form PLT Header that does not have any restrictions on the displacement
160
// of the .plt from the .plt.got.
161
2
static void writePltHeaderLong(uint8_t *Buf) {
162
2
  const uint8_t PltData[] = {
163
2
      0x04, 0xe0, 0x2d, 0xe5, //     str lr, [sp,#-4]!
164
2
      0x04, 0xe0, 0x9f, 0xe5, //     ldr lr, L2
165
2
      0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr
166
2
      0x08, 0xf0, 0xbe, 0xe5, //     ldr pc, [lr, #8]
167
2
      0x00, 0x00, 0x00, 0x00, // L2: .word   &(.got.plt) - L1 - 8
168
2
      0xd4, 0xd4, 0xd4, 0xd4, //     Pad to 32-byte boundary
169
2
      0xd4, 0xd4, 0xd4, 0xd4, //     Pad to 32-byte boundary
170
2
      0xd4, 0xd4, 0xd4, 0xd4};
171
2
  memcpy(Buf, PltData, sizeof(PltData));
172
2
  uint64_t GotPlt = In.GotPlt->getVA();
173
2
  uint64_t L1 = In.Plt->getVA() + 8;
174
2
  write32le(Buf + 16, GotPlt - L1 - 8);
175
2
}
176
177
// The default PLT header requires the .plt.got to be within 128 Mb of the
178
// .plt in the positive direction.
179
19
void ARM::writePltHeader(uint8_t *Buf) const {
180
19
  // Use a similar sequence to that in writePlt(), the difference is the calling
181
19
  // conventions mean we use lr instead of ip. The PLT entry is responsible for
182
19
  // saving lr on the stack, the dynamic loader is responsible for reloading
183
19
  // it.
184
19
  const uint32_t PltData[] = {
185
19
      0xe52de004, // L1: str lr, [sp,#-4]!
186
19
      0xe28fe600, //     add lr, pc,  #0x0NN00000 &(.got.plt - L1 - 4)
187
19
      0xe28eea00, //     add lr, lr,  #0x000NN000 &(.got.plt - L1 - 4)
188
19
      0xe5bef000, //     ldr pc, [lr, #0x00000NNN] &(.got.plt -L1 - 4)
189
19
  };
190
19
191
19
  uint64_t Offset = In.GotPlt->getVA() - In.Plt->getVA() - 4;
192
19
  if (!llvm::isUInt<27>(Offset)) {
193
2
    // We cannot encode the Offset, use the long form.
194
2
    writePltHeaderLong(Buf);
195
2
    return;
196
2
  }
197
17
  write32le(Buf + 0, PltData[0]);
198
17
  write32le(Buf + 4, PltData[1] | ((Offset >> 20) & 0xff));
199
17
  write32le(Buf + 8, PltData[2] | ((Offset >> 12) & 0xff));
200
17
  write32le(Buf + 12, PltData[3] | (Offset & 0xfff));
201
17
  write32le(Buf + 16, TrapInstr); // Pad to 32-byte boundary
202
17
  write32le(Buf + 20, TrapInstr);
203
17
  write32le(Buf + 24, TrapInstr);
204
17
  write32le(Buf + 28, TrapInstr);
205
17
}
206
207
19
void ARM::addPltHeaderSymbols(InputSection &IS) const {
208
19
  addSyntheticLocal("$a", STT_NOTYPE, 0, 0, IS);
209
19
  addSyntheticLocal("$d", STT_NOTYPE, 16, 0, IS);
210
19
}
211
212
// Long form PLT entries that do not have any restrictions on the displacement
213
// of the .plt from the .plt.got.
214
static void writePltLong(uint8_t *Buf, uint64_t GotPltEntryAddr,
215
                         uint64_t PltEntryAddr, int32_t Index,
216
4
                         unsigned RelOff) {
217
4
  const uint8_t PltData[] = {
218
4
      0x04, 0xc0, 0x9f, 0xe5, //     ldr ip, L2
219
4
      0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc
220
4
      0x00, 0xf0, 0x9c, 0xe5, //     ldr pc, [ip]
221
4
      0x00, 0x00, 0x00, 0x00, // L2: .word   Offset(&(.plt.got) - L1 - 8
222
4
  };
223
4
  memcpy(Buf, PltData, sizeof(PltData));
224
4
  uint64_t L1 = PltEntryAddr + 4;
225
4
  write32le(Buf + 12, GotPltEntryAddr - L1 - 8);
226
4
}
227
228
// The default PLT entries require the .plt.got to be within 128 Mb of the
229
// .plt in the positive direction.
230
void ARM::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
231
                   uint64_t PltEntryAddr, int32_t Index,
232
49
                   unsigned RelOff) const {
233
49
  // The PLT entry is similar to the example given in Appendix A of ELF for
234
49
  // the Arm Architecture. Instead of using the Group Relocations to find the
235
49
  // optimal rotation for the 8-bit immediate used in the add instructions we
236
49
  // hard code the most compact rotations for simplicity. This saves a load
237
49
  // instruction over the long plt sequences.
238
49
  const uint32_t PltData[] = {
239
49
      0xe28fc600, // L1: add ip, pc,  #0x0NN00000  Offset(&(.plt.got) - L1 - 8
240
49
      0xe28cca00, //     add ip, ip,  #0x000NN000  Offset(&(.plt.got) - L1 - 8
241
49
      0xe5bcf000, //     ldr pc, [ip, #0x00000NNN] Offset(&(.plt.got) - L1 - 8
242
49
  };
243
49
244
49
  uint64_t Offset = GotPltEntryAddr - PltEntryAddr - 8;
245
49
  if (!llvm::isUInt<27>(Offset)) {
246
4
    // We cannot encode the Offset, use the long form.
247
4
    writePltLong(Buf, GotPltEntryAddr, PltEntryAddr, Index, RelOff);
248
4
    return;
249
4
  }
250
45
  write32le(Buf + 0, PltData[0] | ((Offset >> 20) & 0xff));
251
45
  write32le(Buf + 4, PltData[1] | ((Offset >> 12) & 0xff));
252
45
  write32le(Buf + 8, PltData[2] | (Offset & 0xfff));
253
45
  write32le(Buf + 12, TrapInstr); // Pad to 16-byte boundary
254
45
}
255
256
49
void ARM::addPltSymbols(InputSection &IS, uint64_t Off) const {
257
49
  addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS);
258
49
  addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS);
259
49
}
260
261
bool ARM::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
262
444
                     uint64_t BranchAddr, const Symbol &S) const {
263
444
  // If S is an undefined weak symbol and does not have a PLT entry then it
264
444
  // will be resolved as a branch to the next instruction.
265
444
  if (S.isUndefWeak() && 
!S.isInPlt()18
)
266
16
    return false;
267
428
  // A state change from ARM to Thumb and vice versa must go through an
268
428
  // interworking thunk if the relocation type is not R_ARM_CALL or
269
428
  // R_ARM_THM_CALL.
270
428
  switch (Type) {
271
428
  case R_ARM_PC24:
272
69
  case R_ARM_PLT32:
273
69
  case R_ARM_JUMP24:
274
69
    // Source is ARM, all PLT entries are ARM so no interworking required.
275
69
    // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
276
69
    if (Expr == R_PC && 
((S.getVA() & 1) == 1)44
)
277
16
      return true;
278
53
    LLVM_FALLTHROUGH;
279
142
  case R_ARM_CALL: {
280
142
    uint64_t Dst = (Expr == R_PLT_PC) ? 
S.getPltVA()52
:
S.getVA()90
;
281
142
    return !inBranchRange(Type, BranchAddr, Dst);
282
53
  }
283
53
  case R_ARM_THM_JUMP19:
284
48
  case R_ARM_THM_JUMP24:
285
48
    // Source is Thumb, all PLT entries are ARM so interworking is required.
286
48
    // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
287
48
    if (Expr == R_PLT_PC || 
((S.getVA() & 1) == 0)35
)
288
31
      return true;
289
17
    LLVM_FALLTHROUGH;
290
141
  case R_ARM_THM_CALL: {
291
141
    uint64_t Dst = (Expr == R_PLT_PC) ? 
S.getPltVA()12
:
S.getVA()129
;
292
141
    return !inBranchRange(Type, BranchAddr, Dst);
293
98
  }
294
98
  }
295
98
  return false;
296
98
}
297
298
276
uint32_t ARM::getThunkSectionSpacing() const {
299
276
  // The placing of pre-created ThunkSections is controlled by the value
300
276
  // ThunkSectionSpacing returned by getThunkSectionSpacing(). The aim is to
301
276
  // place the ThunkSection such that all branches from the InputSections
302
276
  // prior to the ThunkSection can reach a Thunk placed at the end of the
303
276
  // ThunkSection. Graphically:
304
276
  // | up to ThunkSectionSpacing .text input sections |
305
276
  // | ThunkSection                                   |
306
276
  // | up to ThunkSectionSpacing .text input sections |
307
276
  // | ThunkSection                                   |
308
276
309
276
  // Pre-created ThunkSections are spaced roughly 16MiB apart on ARMv7. This
310
276
  // is to match the most common expected case of a Thumb 2 encoded BL, BLX or
311
276
  // B.W:
312
276
  // ARM B, BL, BLX range +/- 32MiB
313
276
  // Thumb B.W, BL, BLX range +/- 16MiB
314
276
  // Thumb B<cc>.W range +/- 1MiB
315
276
  // If a branch cannot reach a pre-created ThunkSection a new one will be
316
276
  // created so we can handle the rare cases of a Thumb 2 conditional branch.
317
276
  // We intentionally use a lower size for ThunkSectionSpacing than the maximum
318
276
  // branch range so the end of the ThunkSection is more likely to be within
319
276
  // range of the branch instruction that is furthest away. The value we shorten
320
276
  // ThunkSectionSpacing by is set conservatively to allow us to create 16,384
321
276
  // 12 byte Thunks at any offset in a ThunkSection without risk of a branch to
322
276
  // one of the Thunks going out of range.
323
276
324
276
  // On Arm the ThunkSectionSpacing depends on the range of the Thumb Branch
325
276
  // range. On earlier Architectures such as ARMv4, ARMv5 and ARMv6 (except
326
276
  // ARMv6T2) the range is +/- 4MiB.
327
276
328
276
  return (Config->ARMJ1J2BranchEncoding) ? 
0x1000000 - 0x3000082
329
276
                                         : 
0x400000 - 0x7500194
;
330
276
}
331
332
560
bool ARM::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
333
560
  uint64_t Range;
334
560
  uint64_t InstrSize;
335
560
336
560
  switch (Type) {
337
560
  case R_ARM_PC24:
338
199
  case R_ARM_PLT32:
339
199
  case R_ARM_JUMP24:
340
199
  case R_ARM_CALL:
341
199
    Range = 0x2000000;
342
199
    InstrSize = 4;
343
199
    break;
344
199
  case R_ARM_THM_JUMP19:
345
51
    Range = 0x100000;
346
51
    InstrSize = 2;
347
51
    break;
348
310
  case R_ARM_THM_JUMP24:
349
310
  case R_ARM_THM_CALL:
350
310
    Range = Config->ARMJ1J2BranchEncoding ? 
0x1000000281
:
0x40000029
;
351
310
    InstrSize = 2;
352
310
    break;
353
310
  default:
354
0
    return true;
355
560
  }
356
560
  // PC at Src is 2 instructions ahead, immediate of branch is signed
357
560
  if (Src > Dst)
358
185
    Range -= 2 * InstrSize;
359
375
  else
360
375
    Range += InstrSize;
361
560
362
560
  if ((Dst & 0x1) == 0)
363
289
    // Destination is ARM, if ARM caller then Src is already 4-byte aligned.
364
289
    // If Thumb Caller (BLX) the Src address has bottom 2 bits cleared to ensure
365
289
    // destination will be 4 byte aligned.
366
289
    Src &= ~0x3;
367
271
  else
368
271
    // Bit 0 == 1 denotes Thumb state, it is not part of the range
369
271
    Dst &= ~0x1;
370
560
371
560
  uint64_t Distance = (Src > Dst) ? 
Src - Dst184
:
Dst - Src376
;
372
560
  return Distance <= Range;
373
560
}
374
375
777
void ARM::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
376
777
  switch (Type) {
377
777
  case R_ARM_ABS32:
378
185
  case R_ARM_BASE_PREL:
379
185
  case R_ARM_GLOB_DAT:
380
185
  case R_ARM_GOTOFF32:
381
185
  case R_ARM_GOT_BREL:
382
185
  case R_ARM_GOT_PREL:
383
185
  case R_ARM_REL32:
384
185
  case R_ARM_RELATIVE:
385
185
  case R_ARM_SBREL32:
386
185
  case R_ARM_TARGET1:
387
185
  case R_ARM_TARGET2:
388
185
  case R_ARM_TLS_GD32:
389
185
  case R_ARM_TLS_IE32:
390
185
  case R_ARM_TLS_LDM32:
391
185
  case R_ARM_TLS_LDO32:
392
185
  case R_ARM_TLS_LE32:
393
185
  case R_ARM_TLS_TPOFF32:
394
185
  case R_ARM_TLS_DTPOFF32:
395
185
    write32le(Loc, Val);
396
185
    break;
397
185
  case R_ARM_TLS_DTPMOD32:
398
6
    write32le(Loc, 1);
399
6
    break;
400
185
  case R_ARM_PREL31:
401
110
    checkInt(Loc, Val, 31, Type);
402
110
    write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000));
403
110
    break;
404
185
  case R_ARM_CALL:
405
70
    // R_ARM_CALL is used for BL and BLX instructions, depending on the
406
70
    // value of bit 0 of Val, we must select a BL or BLX instruction
407
70
    if (Val & 1) {
408
24
      // If bit 0 of Val is 1 the target is Thumb, we must select a BLX.
409
24
      // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
410
24
      checkInt(Loc, Val, 26, Type);
411
24
      write32le(Loc, 0xfa000000 |                    // opcode
412
24
                         ((Val & 2) << 23) |         // H
413
24
                         ((Val >> 2) & 0x00ffffff)); // imm24
414
24
      break;
415
24
    }
416
46
    if ((read32le(Loc) & 0xfe000000) == 0xfa000000)
417
4
      // BLX (always unconditional) instruction to an ARM Target, select an
418
4
      // unconditional BL.
419
4
      write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff));
420
46
    // fall through as BL encoding is shared with B
421
46
    LLVM_FALLTHROUGH;
422
104
  case R_ARM_JUMP24:
423
104
  case R_ARM_PC24:
424
104
  case R_ARM_PLT32:
425
104
    checkInt(Loc, Val, 26, Type);
426
104
    write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff));
427
104
    break;
428
104
  case R_ARM_THM_JUMP11:
429
5
    checkInt(Loc, Val, 12, Type);
430
5
    write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff));
431
5
    break;
432
104
  case R_ARM_THM_JUMP19:
433
20
    // Encoding T3: Val = S:J2:J1:imm6:imm11:0
434
20
    checkInt(Loc, Val, 21, Type);
435
20
    write16le(Loc,
436
20
              (read16le(Loc) & 0xfbc0) |   // opcode cond
437
20
                  ((Val >> 10) & 0x0400) | // S
438
20
                  ((Val >> 12) & 0x003f)); // imm6
439
20
    write16le(Loc + 2,
440
20
              0x8000 |                    // opcode
441
20
                  ((Val >> 8) & 0x0800) | // J2
442
20
                  ((Val >> 5) & 0x2000) | // J1
443
20
                  ((Val >> 1) & 0x07ff)); // imm11
444
20
    break;
445
104
  case R_ARM_THM_CALL:
446
95
    // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
447
95
    // value of bit 0 of Val, we must select a BL or BLX instruction
448
95
    if ((Val & 1) == 0) {
449
19
      // Ensure BLX destination is 4-byte aligned. As BLX instruction may
450
19
      // only be two byte aligned. This must be done before overflow check
451
19
      Val = alignTo(Val, 4);
452
19
    }
453
95
    // Bit 12 is 0 for BLX, 1 for BL
454
95
    write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12);
455
95
    if (!Config->ARMJ1J2BranchEncoding) {
456
20
      // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
457
20
      // different encoding rules and range due to J1 and J2 always being 1.
458
20
      checkInt(Loc, Val, 23, Type);
459
20
      write16le(Loc,
460
20
                0xf000 |                     // opcode
461
20
                    ((Val >> 12) & 0x07ff)); // imm11
462
20
      write16le(Loc + 2,
463
20
                (read16le(Loc + 2) & 0xd000) | // opcode
464
20
                    0x2800 |                   // J1 == J2 == 1
465
20
                    ((Val >> 1) & 0x07ff));    // imm11
466
20
      break;
467
20
    }
468
75
    // Fall through as rest of encoding is the same as B.W
469
75
    LLVM_FALLTHROUGH;
470
125
  case R_ARM_THM_JUMP24:
471
125
    // Encoding B  T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
472
125
    checkInt(Loc, Val, 25, Type);
473
125
    write16le(Loc,
474
125
              0xf000 |                     // opcode
475
125
                  ((Val >> 14) & 0x0400) | // S
476
125
                  ((Val >> 12) & 0x03ff)); // imm10
477
125
    write16le(Loc + 2,
478
125
              (read16le(Loc + 2) & 0xd000) |                  // opcode
479
125
                  (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1
480
125
                  (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2
481
125
                  ((Val >> 1) & 0x07ff));                     // imm11
482
125
    break;
483
75
  case R_ARM_MOVW_ABS_NC:
484
32
  case R_ARM_MOVW_PREL_NC:
485
32
    write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) |
486
32
                       (Val & 0x0fff));
487
32
    break;
488
32
  case R_ARM_MOVT_ABS:
489
32
  case R_ARM_MOVT_PREL:
490
32
    checkInt(Loc, Val, 32, Type);
491
32
    write32le(Loc, (read32le(Loc) & ~0x000f0fff) |
492
32
                       (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff));
493
32
    break;
494
57
  case R_ARM_THM_MOVT_ABS:
495
57
  case R_ARM_THM_MOVT_PREL:
496
57
    // Encoding T1: A = imm4:i:imm3:imm8
497
57
    checkInt(Loc, Val, 32, Type);
498
57
    write16le(Loc,
499
57
              0xf2c0 |                     // opcode
500
57
                  ((Val >> 17) & 0x0400) | // i
501
57
                  ((Val >> 28) & 0x000f)); // imm4
502
57
    write16le(Loc + 2,
503
57
              (read16le(Loc + 2) & 0x8f00) | // opcode
504
57
                  ((Val >> 12) & 0x7000) |   // imm3
505
57
                  ((Val >> 16) & 0x00ff));   // imm8
506
57
    break;
507
57
  case R_ARM_THM_MOVW_ABS_NC:
508
57
  case R_ARM_THM_MOVW_PREL_NC:
509
57
    // Encoding T3: A = imm4:i:imm3:imm8
510
57
    write16le(Loc,
511
57
              0xf240 |                     // opcode
512
57
                  ((Val >> 1) & 0x0400) |  // i
513
57
                  ((Val >> 12) & 0x000f)); // imm4
514
57
    write16le(Loc + 2,
515
57
              (read16le(Loc + 2) & 0x8f00) | // opcode
516
57
                  ((Val << 4) & 0x7000) |    // imm3
517
57
                  (Val & 0x00ff));           // imm8
518
57
    break;
519
57
  default:
520
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
521
777
  }
522
777
}
523
524
599
int64_t ARM::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
525
599
  switch (Type) {
526
599
  default:
527
4
    return 0;
528
599
  case R_ARM_ABS32:
529
170
  case R_ARM_BASE_PREL:
530
170
  case R_ARM_GOTOFF32:
531
170
  case R_ARM_GOT_BREL:
532
170
  case R_ARM_GOT_PREL:
533
170
  case R_ARM_REL32:
534
170
  case R_ARM_TARGET1:
535
170
  case R_ARM_TARGET2:
536
170
  case R_ARM_TLS_GD32:
537
170
  case R_ARM_TLS_LDM32:
538
170
  case R_ARM_TLS_LDO32:
539
170
  case R_ARM_TLS_IE32:
540
170
  case R_ARM_TLS_LE32:
541
170
    return SignExtend64<32>(read32le(Buf));
542
170
  case R_ARM_PREL31:
543
101
    return SignExtend64<31>(read32le(Buf));
544
170
  case R_ARM_CALL:
545
124
  case R_ARM_JUMP24:
546
124
  case R_ARM_PC24:
547
124
  case R_ARM_PLT32:
548
124
    return SignExtend64<26>(read32le(Buf) << 2);
549
124
  case R_ARM_THM_JUMP11:
550
5
    return SignExtend64<12>(read16le(Buf) << 1);
551
124
  case R_ARM_THM_JUMP19: {
552
20
    // Encoding T3: A = S:J2:J1:imm10:imm6:0
553
20
    uint16_t Hi = read16le(Buf);
554
20
    uint16_t Lo = read16le(Buf + 2);
555
20
    return SignExtend64<20>(((Hi & 0x0400) << 10) | // S
556
20
                            ((Lo & 0x0800) << 8) |  // J2
557
20
                            ((Lo & 0x2000) << 5) |  // J1
558
20
                            ((Hi & 0x003f) << 12) | // imm6
559
20
                            ((Lo & 0x07ff) << 1));  // imm11:0
560
124
  }
561
124
  case R_ARM_THM_CALL:
562
95
    if (!Config->ARMJ1J2BranchEncoding) {
563
20
      // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
564
20
      // different encoding rules and range due to J1 and J2 always being 1.
565
20
      uint16_t Hi = read16le(Buf);
566
20
      uint16_t Lo = read16le(Buf + 2);
567
20
      return SignExtend64<22>(((Hi & 0x7ff) << 12) | // imm11
568
20
                              ((Lo & 0x7ff) << 1));  // imm11:0
569
20
      
break0
;
570
75
    }
571
75
    LLVM_FALLTHROUGH;
572
105
  case R_ARM_THM_JUMP24: {
573
105
    // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
574
105
    // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
575
105
    uint16_t Hi = read16le(Buf);
576
105
    uint16_t Lo = read16le(Buf + 2);
577
105
    return SignExtend64<24>(((Hi & 0x0400) << 14) |                    // S
578
105
                            (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1
579
105
                            (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2
580
105
                            ((Hi & 0x003ff) << 12) |                   // imm0
581
105
                            ((Lo & 0x007ff) << 1)); // imm11:0
582
75
  }
583
75
  // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and
584
75
  // MOVT is in the range -32768 <= A < 32768
585
75
  case R_ARM_MOVW_ABS_NC:
586
28
  case R_ARM_MOVT_ABS:
587
28
  case R_ARM_MOVW_PREL_NC:
588
28
  case R_ARM_MOVT_PREL: {
589
28
    uint64_t Val = read32le(Buf) & 0x000f0fff;
590
28
    return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff));
591
28
  }
592
28
  case R_ARM_THM_MOVW_ABS_NC:
593
22
  case R_ARM_THM_MOVT_ABS:
594
22
  case R_ARM_THM_MOVW_PREL_NC:
595
22
  case R_ARM_THM_MOVT_PREL: {
596
22
    // Encoding T3: A = imm4:i:imm3:imm8
597
22
    uint16_t Hi = read16le(Buf);
598
22
    uint16_t Lo = read16le(Buf + 2);
599
22
    return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4
600
22
                            ((Hi & 0x0400) << 1) |  // i
601
22
                            ((Lo & 0x7000) >> 4) |  // imm3
602
22
                            (Lo & 0x00ff));         // imm8
603
22
  }
604
599
  }
605
599
}
606
607
145
TargetInfo *elf::getARMTargetInfo() {
608
145
  static ARM Target;
609
145
  return &Target;
610
145
}