Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/ARM.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- ARM.cpp ------------------------------------------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "InputFiles.h"
10
#include "Symbols.h"
11
#include "SyntheticSections.h"
12
#include "Target.h"
13
#include "Thunks.h"
14
#include "lld/Common/ErrorHandler.h"
15
#include "llvm/Object/ELF.h"
16
#include "llvm/Support/Endian.h"
17
18
using namespace llvm;
19
using namespace llvm::support::endian;
20
using namespace llvm::ELF;
21
using namespace lld;
22
using namespace lld::elf;
23
24
namespace {
25
class ARM final : public TargetInfo {
26
public:
27
  ARM();
28
  uint32_t calcEFlags() const override;
29
  RelExpr getRelExpr(RelType type, const Symbol &s,
30
                     const uint8_t *loc) const override;
31
  RelType getDynRel(RelType type) const override;
32
  int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
33
  void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
34
  void writeIgotPlt(uint8_t *buf, const Symbol &s) const override;
35
  void writePltHeader(uint8_t *buf) const override;
36
  void writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, uint64_t pltEntryAddr,
37
                int32_t index, unsigned relOff) const override;
38
  void addPltSymbols(InputSection &isec, uint64_t off) const override;
39
  void addPltHeaderSymbols(InputSection &isd) const override;
40
  bool needsThunk(RelExpr expr, RelType type, const InputFile *file,
41
                  uint64_t branchAddr, const Symbol &s) const override;
42
  uint32_t getThunkSectionSpacing() const override;
43
  bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override;
44
  void relocateOne(uint8_t *loc, RelType type, uint64_t val) const override;
45
};
46
} // namespace
47
48
166
ARM::ARM() {
49
166
  copyRel = R_ARM_COPY;
50
166
  relativeRel = R_ARM_RELATIVE;
51
166
  iRelativeRel = R_ARM_IRELATIVE;
52
166
  gotRel = R_ARM_GLOB_DAT;
53
166
  noneRel = R_ARM_NONE;
54
166
  pltRel = R_ARM_JUMP_SLOT;
55
166
  symbolicRel = R_ARM_ABS32;
56
166
  tlsGotRel = R_ARM_TLS_TPOFF32;
57
166
  tlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
58
166
  tlsOffsetRel = R_ARM_TLS_DTPOFF32;
59
166
  gotBaseSymInGotPlt = false;
60
166
  pltEntrySize = 16;
61
166
  pltHeaderSize = 32;
62
166
  trapInstr = {0xd4, 0xd4, 0xd4, 0xd4};
63
166
  needsThunks = true;
64
166
}
65
66
159
uint32_t ARM::calcEFlags() const {
67
159
  // The ABIFloatType is used by loaders to detect the floating point calling
68
159
  // convention.
69
159
  uint32_t abiFloatType = 0;
70
159
  if (config->armVFPArgs == ARMVFPArgKind::Base ||
71
159
      
config->armVFPArgs == ARMVFPArgKind::Default157
)
72
155
    abiFloatType = EF_ARM_ABI_FLOAT_SOFT;
73
4
  else if (config->armVFPArgs == ARMVFPArgKind::VFP)
74
2
    abiFloatType = EF_ARM_ABI_FLOAT_HARD;
75
159
76
159
  // We don't currently use any features incompatible with EF_ARM_EABI_VER5,
77
159
  // but we don't have any firm guarantees of conformance. Linux AArch64
78
159
  // kernels (as of 2016) require an EABI version to be set.
79
159
  return EF_ARM_EABI_VER5 | abiFloatType;
80
159
}
81
82
RelExpr ARM::getRelExpr(RelType type, const Symbol &s,
83
645
                        const uint8_t *loc) const {
84
645
  switch (type) {
85
645
  case R_ARM_THM_JUMP11:
86
5
    return R_PC;
87
645
  case R_ARM_CALL:
88
392
  case R_ARM_JUMP24:
89
392
  case R_ARM_PC24:
90
392
  case R_ARM_PLT32:
91
392
  case R_ARM_PREL31:
92
392
  case R_ARM_THM_JUMP19:
93
392
  case R_ARM_THM_JUMP24:
94
392
  case R_ARM_THM_CALL:
95
392
    return R_PLT_PC;
96
392
  case R_ARM_GOTOFF32:
97
3
    // (S + A) - GOT_ORG
98
3
    return R_GOTREL;
99
392
  case R_ARM_GOT_BREL:
100
7
    // GOT(S) + A - GOT_ORG
101
7
    return R_GOT_OFF;
102
392
  case R_ARM_GOT_PREL:
103
6
  case R_ARM_TLS_IE32:
104
6
    // GOT(S) + A - P
105
6
    return R_GOT_PC;
106
6
  case R_ARM_SBREL32:
107
4
    return R_ARM_SBREL;
108
6
  case R_ARM_TARGET1:
109
5
    return config->target1Rel ? 
R_PC2
:
R_ABS3
;
110
6
  case R_ARM_TARGET2:
111
4
    if (config->target2 == Target2Policy::Rel)
112
1
      return R_PC;
113
3
    if (config->target2 == Target2Policy::Abs)
114
1
      return R_ABS;
115
2
    return R_GOT_PC;
116
14
  case R_ARM_TLS_GD32:
117
14
    return R_TLSGD_PC;
118
2
  case R_ARM_TLS_LDM32:
119
2
    return R_TLSLD_PC;
120
2
  case R_ARM_BASE_PREL:
121
0
    // B(S) + A - P
122
0
    // FIXME: currently B(S) assumed to be .got, this may not hold for all
123
0
    // platforms.
124
0
    return R_GOTONLY_PC;
125
27
  case R_ARM_MOVW_PREL_NC:
126
27
  case R_ARM_MOVT_PREL:
127
27
  case R_ARM_REL32:
128
27
  case R_ARM_THM_MOVW_PREL_NC:
129
27
  case R_ARM_THM_MOVT_PREL:
130
27
    return R_PC;
131
27
  case R_ARM_NONE:
132
19
    return R_NONE;
133
27
  case R_ARM_TLS_LE32:
134
3
    return R_TLS;
135
27
  case R_ARM_V4BX:
136
2
    // V4BX is just a marker to indicate there's a "bx rN" instruction at the
137
2
    // given address. It can be used to implement a special linker mode which
138
2
    // rewrites ARMv4T inputs to ARMv4. Since we support only ARMv4 input and
139
2
    // not ARMv4 output, we can just ignore it.
140
2
    return R_HINT;
141
152
  default:
142
152
    return R_ABS;
143
645
  }
144
645
}
145
146
118
RelType ARM::getDynRel(RelType type) const {
147
118
  if ((type == R_ARM_ABS32) || 
(1
type == R_ARM_TARGET11
&&
!config->target1Rel1
))
148
118
    return R_ARM_ABS32;
149
0
  return R_ARM_NONE;
150
0
}
151
152
46
void ARM::writeGotPlt(uint8_t *buf, const Symbol &) const {
153
46
  write32le(buf, in.plt->getVA());
154
46
}
155
156
7
void ARM::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
157
7
  // An ARM entry is the address of the ifunc resolver function.
158
7
  write32le(buf, s.getVA());
159
7
}
160
161
// Long form PLT Header that does not have any restrictions on the displacement
162
// of the .plt from the .plt.got.
163
2
static void writePltHeaderLong(uint8_t *buf) {
164
2
  const uint8_t pltData[] = {
165
2
      0x04, 0xe0, 0x2d, 0xe5, //     str lr, [sp,#-4]!
166
2
      0x04, 0xe0, 0x9f, 0xe5, //     ldr lr, L2
167
2
      0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr
168
2
      0x08, 0xf0, 0xbe, 0xe5, //     ldr pc, [lr, #8]
169
2
      0x00, 0x00, 0x00, 0x00, // L2: .word   &(.got.plt) - L1 - 8
170
2
      0xd4, 0xd4, 0xd4, 0xd4, //     Pad to 32-byte boundary
171
2
      0xd4, 0xd4, 0xd4, 0xd4, //     Pad to 32-byte boundary
172
2
      0xd4, 0xd4, 0xd4, 0xd4};
173
2
  memcpy(buf, pltData, sizeof(pltData));
174
2
  uint64_t gotPlt = in.gotPlt->getVA();
175
2
  uint64_t l1 = in.plt->getVA() + 8;
176
2
  write32le(buf + 16, gotPlt - l1 - 8);
177
2
}
178
179
// The default PLT header requires the .plt.got to be within 128 Mb of the
180
// .plt in the positive direction.
181
21
void ARM::writePltHeader(uint8_t *buf) const {
182
21
  // Use a similar sequence to that in writePlt(), the difference is the calling
183
21
  // conventions mean we use lr instead of ip. The PLT entry is responsible for
184
21
  // saving lr on the stack, the dynamic loader is responsible for reloading
185
21
  // it.
186
21
  const uint32_t pltData[] = {
187
21
      0xe52de004, // L1: str lr, [sp,#-4]!
188
21
      0xe28fe600, //     add lr, pc,  #0x0NN00000 &(.got.plt - L1 - 4)
189
21
      0xe28eea00, //     add lr, lr,  #0x000NN000 &(.got.plt - L1 - 4)
190
21
      0xe5bef000, //     ldr pc, [lr, #0x00000NNN] &(.got.plt -L1 - 4)
191
21
  };
192
21
193
21
  uint64_t offset = in.gotPlt->getVA() - in.plt->getVA() - 4;
194
21
  if (!llvm::isUInt<27>(offset)) {
195
2
    // We cannot encode the Offset, use the long form.
196
2
    writePltHeaderLong(buf);
197
2
    return;
198
2
  }
199
19
  write32le(buf + 0, pltData[0]);
200
19
  write32le(buf + 4, pltData[1] | ((offset >> 20) & 0xff));
201
19
  write32le(buf + 8, pltData[2] | ((offset >> 12) & 0xff));
202
19
  write32le(buf + 12, pltData[3] | (offset & 0xfff));
203
19
  memcpy(buf + 16, trapInstr.data(), 4); // Pad to 32-byte boundary
204
19
  memcpy(buf + 20, trapInstr.data(), 4);
205
19
  memcpy(buf + 24, trapInstr.data(), 4);
206
19
  memcpy(buf + 28, trapInstr.data(), 4);
207
19
}
208
209
21
void ARM::addPltHeaderSymbols(InputSection &isec) const {
210
21
  addSyntheticLocal("$a", STT_NOTYPE, 0, 0, isec);
211
21
  addSyntheticLocal("$d", STT_NOTYPE, 16, 0, isec);
212
21
}
213
214
// Long form PLT entries that do not have any restrictions on the displacement
215
// of the .plt from the .plt.got.
216
static void writePltLong(uint8_t *buf, uint64_t gotPltEntryAddr,
217
                         uint64_t pltEntryAddr, int32_t index,
218
4
                         unsigned relOff) {
219
4
  const uint8_t pltData[] = {
220
4
      0x04, 0xc0, 0x9f, 0xe5, //     ldr ip, L2
221
4
      0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc
222
4
      0x00, 0xf0, 0x9c, 0xe5, //     ldr pc, [ip]
223
4
      0x00, 0x00, 0x00, 0x00, // L2: .word   Offset(&(.plt.got) - L1 - 8
224
4
  };
225
4
  memcpy(buf, pltData, sizeof(pltData));
226
4
  uint64_t l1 = pltEntryAddr + 4;
227
4
  write32le(buf + 12, gotPltEntryAddr - l1 - 8);
228
4
}
229
230
// The default PLT entries require the .plt.got to be within 128 Mb of the
231
// .plt in the positive direction.
232
void ARM::writePlt(uint8_t *buf, uint64_t gotPltEntryAddr,
233
                   uint64_t pltEntryAddr, int32_t index,
234
53
                   unsigned relOff) const {
235
53
  // The PLT entry is similar to the example given in Appendix A of ELF for
236
53
  // the Arm Architecture. Instead of using the Group Relocations to find the
237
53
  // optimal rotation for the 8-bit immediate used in the add instructions we
238
53
  // hard code the most compact rotations for simplicity. This saves a load
239
53
  // instruction over the long plt sequences.
240
53
  const uint32_t pltData[] = {
241
53
      0xe28fc600, // L1: add ip, pc,  #0x0NN00000  Offset(&(.plt.got) - L1 - 8
242
53
      0xe28cca00, //     add ip, ip,  #0x000NN000  Offset(&(.plt.got) - L1 - 8
243
53
      0xe5bcf000, //     ldr pc, [ip, #0x00000NNN] Offset(&(.plt.got) - L1 - 8
244
53
  };
245
53
246
53
  uint64_t offset = gotPltEntryAddr - pltEntryAddr - 8;
247
53
  if (!llvm::isUInt<27>(offset)) {
248
4
    // We cannot encode the Offset, use the long form.
249
4
    writePltLong(buf, gotPltEntryAddr, pltEntryAddr, index, relOff);
250
4
    return;
251
4
  }
252
49
  write32le(buf + 0, pltData[0] | ((offset >> 20) & 0xff));
253
49
  write32le(buf + 4, pltData[1] | ((offset >> 12) & 0xff));
254
49
  write32le(buf + 8, pltData[2] | (offset & 0xfff));
255
49
  memcpy(buf + 12, trapInstr.data(), 4); // Pad to 16-byte boundary
256
49
}
257
258
53
void ARM::addPltSymbols(InputSection &isec, uint64_t off) const {
259
53
  addSyntheticLocal("$a", STT_NOTYPE, off, 0, isec);
260
53
  addSyntheticLocal("$d", STT_NOTYPE, off + 12, 0, isec);
261
53
}
262
263
bool ARM::needsThunk(RelExpr expr, RelType type, const InputFile *file,
264
473
                     uint64_t branchAddr, const Symbol &s) const {
265
473
  // If S is an undefined weak symbol and does not have a PLT entry then it
266
473
  // will be resolved as a branch to the next instruction.
267
473
  if (s.isUndefWeak() && 
!s.isInPlt()18
)
268
16
    return false;
269
457
  // A state change from ARM to Thumb and vice versa must go through an
270
457
  // interworking thunk if the relocation type is not R_ARM_CALL or
271
457
  // R_ARM_THM_CALL.
272
457
  switch (type) {
273
457
  case R_ARM_PC24:
274
69
  case R_ARM_PLT32:
275
69
  case R_ARM_JUMP24:
276
69
    // Source is ARM, all PLT entries are ARM so no interworking required.
277
69
    // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
278
69
    if (expr == R_PC && 
((s.getVA() & 1) == 1)44
)
279
16
      return true;
280
53
    LLVM_FALLTHROUGH;
281
146
  case R_ARM_CALL: {
282
146
    uint64_t dst = (expr == R_PLT_PC) ? 
s.getPltVA()54
:
s.getVA()92
;
283
146
    return !inBranchRange(type, branchAddr, dst);
284
53
  }
285
55
  case R_ARM_THM_JUMP19:
286
55
  case R_ARM_THM_JUMP24:
287
55
    // Source is Thumb, all PLT entries are ARM so interworking is required.
288
55
    // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
289
55
    if (expr == R_PLT_PC || 
((s.getVA() & 1) == 0)42
)
290
37
      return true;
291
18
    LLVM_FALLTHROUGH;
292
158
  case R_ARM_THM_CALL: {
293
158
    uint64_t dst = (expr == R_PLT_PC) ? 
s.getPltVA()16
:
s.getVA()142
;
294
158
    return !inBranchRange(type, branchAddr, dst);
295
100
  }
296
100
  }
297
100
  return false;
298
100
}
299
300
318
uint32_t ARM::getThunkSectionSpacing() const {
301
318
  // The placing of pre-created ThunkSections is controlled by the value
302
318
  // thunkSectionSpacing returned by getThunkSectionSpacing(). The aim is to
303
318
  // place the ThunkSection such that all branches from the InputSections
304
318
  // prior to the ThunkSection can reach a Thunk placed at the end of the
305
318
  // ThunkSection. Graphically:
306
318
  // | up to thunkSectionSpacing .text input sections |
307
318
  // | ThunkSection                                   |
308
318
  // | up to thunkSectionSpacing .text input sections |
309
318
  // | ThunkSection                                   |
310
318
311
318
  // Pre-created ThunkSections are spaced roughly 16MiB apart on ARMv7. This
312
318
  // is to match the most common expected case of a Thumb 2 encoded BL, BLX or
313
318
  // B.W:
314
318
  // ARM B, BL, BLX range +/- 32MiB
315
318
  // Thumb B.W, BL, BLX range +/- 16MiB
316
318
  // Thumb B<cc>.W range +/- 1MiB
317
318
  // If a branch cannot reach a pre-created ThunkSection a new one will be
318
318
  // created so we can handle the rare cases of a Thumb 2 conditional branch.
319
318
  // We intentionally use a lower size for thunkSectionSpacing than the maximum
320
318
  // branch range so the end of the ThunkSection is more likely to be within
321
318
  // range of the branch instruction that is furthest away. The value we shorten
322
318
  // thunkSectionSpacing by is set conservatively to allow us to create 16,384
323
318
  // 12 byte Thunks at any offset in a ThunkSection without risk of a branch to
324
318
  // one of the Thunks going out of range.
325
318
326
318
  // On Arm the thunkSectionSpacing depends on the range of the Thumb Branch
327
318
  // range. On earlier Architectures such as ARMv4, ARMv5 and ARMv6 (except
328
318
  // ARMv6T2) the range is +/- 4MiB.
329
318
330
318
  return (config->armJ1J2BranchEncoding) ? 
0x1000000 - 0x30000120
331
318
                                         : 
0x400000 - 0x7500198
;
332
318
}
333
334
639
bool ARM::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
335
639
  uint64_t range;
336
639
  uint64_t instrSize;
337
639
338
639
  switch (type) {
339
639
  case R_ARM_PC24:
340
207
  case R_ARM_PLT32:
341
207
  case R_ARM_JUMP24:
342
207
  case R_ARM_CALL:
343
207
    range = 0x2000000;
344
207
    instrSize = 4;
345
207
    break;
346
207
  case R_ARM_THM_JUMP19:
347
56
    range = 0x100000;
348
56
    instrSize = 2;
349
56
    break;
350
376
  case R_ARM_THM_JUMP24:
351
376
  case R_ARM_THM_CALL:
352
376
    range = config->armJ1J2BranchEncoding ? 
0x1000000330
:
0x40000046
;
353
376
    instrSize = 2;
354
376
    break;
355
376
  default:
356
0
    return true;
357
639
  }
358
639
  // PC at Src is 2 instructions ahead, immediate of branch is signed
359
639
  if (src > dst)
360
214
    range -= 2 * instrSize;
361
425
  else
362
425
    range += instrSize;
363
639
364
639
  if ((dst & 0x1) == 0)
365
330
    // Destination is ARM, if ARM caller then Src is already 4-byte aligned.
366
330
    // If Thumb Caller (BLX) the Src address has bottom 2 bits cleared to ensure
367
330
    // destination will be 4 byte aligned.
368
330
    src &= ~0x3;
369
309
  else
370
309
    // Bit 0 == 1 denotes Thumb state, it is not part of the range
371
309
    dst &= ~0x1;
372
639
373
639
  uint64_t distance = (src > dst) ? 
src - dst212
:
dst - src427
;
374
639
  return distance <= range;
375
639
}
376
377
859
void ARM::relocateOne(uint8_t *loc, RelType type, uint64_t val) const {
378
859
  switch (type) {
379
859
  case R_ARM_ABS32:
380
196
  case R_ARM_BASE_PREL:
381
196
  case R_ARM_GOTOFF32:
382
196
  case R_ARM_GOT_BREL:
383
196
  case R_ARM_GOT_PREL:
384
196
  case R_ARM_REL32:
385
196
  case R_ARM_RELATIVE:
386
196
  case R_ARM_SBREL32:
387
196
  case R_ARM_TARGET1:
388
196
  case R_ARM_TARGET2:
389
196
  case R_ARM_TLS_GD32:
390
196
  case R_ARM_TLS_IE32:
391
196
  case R_ARM_TLS_LDM32:
392
196
  case R_ARM_TLS_LDO32:
393
196
  case R_ARM_TLS_LE32:
394
196
  case R_ARM_TLS_TPOFF32:
395
196
  case R_ARM_TLS_DTPOFF32:
396
196
    write32le(loc, val);
397
196
    break;
398
196
  case R_ARM_PREL31:
399
133
    checkInt(loc, val, 31, type);
400
133
    write32le(loc, (read32le(loc) & 0x80000000) | (val & ~0x80000000));
401
133
    break;
402
196
  case R_ARM_CALL:
403
74
    // R_ARM_CALL is used for BL and BLX instructions, depending on the
404
74
    // value of bit 0 of Val, we must select a BL or BLX instruction
405
74
    if (val & 1) {
406
24
      // If bit 0 of Val is 1 the target is Thumb, we must select a BLX.
407
24
      // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
408
24
      checkInt(loc, val, 26, type);
409
24
      write32le(loc, 0xfa000000 |                    // opcode
410
24
                         ((val & 2) << 23) |         // H
411
24
                         ((val >> 2) & 0x00ffffff)); // imm24
412
24
      break;
413
24
    }
414
50
    if ((read32le(loc) & 0xfe000000) == 0xfa000000)
415
4
      // BLX (always unconditional) instruction to an ARM Target, select an
416
4
      // unconditional BL.
417
4
      write32le(loc, 0xeb000000 | (read32le(loc) & 0x00ffffff));
418
50
    // fall through as BL encoding is shared with B
419
50
    LLVM_FALLTHROUGH;
420
111
  case R_ARM_JUMP24:
421
111
  case R_ARM_PC24:
422
111
  case R_ARM_PLT32:
423
111
    checkInt(loc, val, 26, type);
424
111
    write32le(loc, (read32le(loc) & ~0x00ffffff) | ((val >> 2) & 0x00ffffff));
425
111
    break;
426
111
  case R_ARM_THM_JUMP11:
427
5
    checkInt(loc, val, 12, type);
428
5
    write16le(loc, (read32le(loc) & 0xf800) | ((val >> 1) & 0x07ff));
429
5
    break;
430
111
  case R_ARM_THM_JUMP19:
431
21
    // Encoding T3: Val = S:J2:J1:imm6:imm11:0
432
21
    checkInt(loc, val, 21, type);
433
21
    write16le(loc,
434
21
              (read16le(loc) & 0xfbc0) |   // opcode cond
435
21
                  ((val >> 10) & 0x0400) | // S
436
21
                  ((val >> 12) & 0x003f)); // imm6
437
21
    write16le(loc + 2,
438
21
              0x8000 |                    // opcode
439
21
                  ((val >> 8) & 0x0800) | // J2
440
21
                  ((val >> 5) & 0x2000) | // J1
441
21
                  ((val >> 1) & 0x07ff)); // imm11
442
21
    break;
443
111
  case R_ARM_THM_CALL:
444
110
    // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
445
110
    // value of bit 0 of Val, we must select a BL or BLX instruction
446
110
    if ((val & 1) == 0) {
447
22
      // Ensure BLX destination is 4-byte aligned. As BLX instruction may
448
22
      // only be two byte aligned. This must be done before overflow check
449
22
      val = alignTo(val, 4);
450
22
    }
451
110
    // Bit 12 is 0 for BLX, 1 for BL
452
110
    write16le(loc + 2, (read16le(loc + 2) & ~0x1000) | (val & 1) << 12);
453
110
    if (!config->armJ1J2BranchEncoding) {
454
23
      // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
455
23
      // different encoding rules and range due to J1 and J2 always being 1.
456
23
      checkInt(loc, val, 23, type);
457
23
      write16le(loc,
458
23
                0xf000 |                     // opcode
459
23
                    ((val >> 12) & 0x07ff)); // imm11
460
23
      write16le(loc + 2,
461
23
                (read16le(loc + 2) & 0xd000) | // opcode
462
23
                    0x2800 |                   // J1 == J2 == 1
463
23
                    ((val >> 1) & 0x07ff));    // imm11
464
23
      break;
465
23
    }
466
87
    // Fall through as rest of encoding is the same as B.W
467
87
    LLVM_FALLTHROUGH;
468
144
  case R_ARM_THM_JUMP24:
469
144
    // Encoding B  T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
470
144
    checkInt(loc, val, 25, type);
471
144
    write16le(loc,
472
144
              0xf000 |                     // opcode
473
144
                  ((val >> 14) & 0x0400) | // S
474
144
                  ((val >> 12) & 0x03ff)); // imm10
475
144
    write16le(loc + 2,
476
144
              (read16le(loc + 2) & 0xd000) |                  // opcode
477
144
                  (((~(val >> 10)) ^ (val >> 11)) & 0x2000) | // J1
478
144
                  (((~(val >> 11)) ^ (val >> 13)) & 0x0800) | // J2
479
144
                  ((val >> 1) & 0x07ff));                     // imm11
480
144
    break;
481
87
  case R_ARM_MOVW_ABS_NC:
482
34
  case R_ARM_MOVW_PREL_NC:
483
34
    write32le(loc, (read32le(loc) & ~0x000f0fff) | ((val & 0xf000) << 4) |
484
34
                       (val & 0x0fff));
485
34
    break;
486
34
  case R_ARM_MOVT_ABS:
487
34
  case R_ARM_MOVT_PREL:
488
34
    write32le(loc, (read32le(loc) & ~0x000f0fff) |
489
34
                       (((val >> 16) & 0xf000) << 4) | ((val >> 16) & 0xfff));
490
34
    break;
491
67
  case R_ARM_THM_MOVT_ABS:
492
67
  case R_ARM_THM_MOVT_PREL:
493
67
    // Encoding T1: A = imm4:i:imm3:imm8
494
67
    write16le(loc,
495
67
              0xf2c0 |                     // opcode
496
67
                  ((val >> 17) & 0x0400) | // i
497
67
                  ((val >> 28) & 0x000f)); // imm4
498
67
    write16le(loc + 2,
499
67
              (read16le(loc + 2) & 0x8f00) | // opcode
500
67
                  ((val >> 12) & 0x7000) |   // imm3
501
67
                  ((val >> 16) & 0x00ff));   // imm8
502
67
    break;
503
67
  case R_ARM_THM_MOVW_ABS_NC:
504
67
  case R_ARM_THM_MOVW_PREL_NC:
505
67
    // Encoding T3: A = imm4:i:imm3:imm8
506
67
    write16le(loc,
507
67
              0xf240 |                     // opcode
508
67
                  ((val >> 1) & 0x0400) |  // i
509
67
                  ((val >> 12) & 0x000f)); // imm4
510
67
    write16le(loc + 2,
511
67
              (read16le(loc + 2) & 0x8f00) | // opcode
512
67
                  ((val << 4) & 0x7000) |    // imm3
513
67
                  (val & 0x00ff));           // imm8
514
67
    break;
515
67
  default:
516
0
    error(getErrorLocation(loc) + "unrecognized relocation " + toString(type));
517
859
  }
518
859
}
519
520
644
int64_t ARM::getImplicitAddend(const uint8_t *buf, RelType type) const {
521
644
  switch (type) {
522
644
  default:
523
6
    return 0;
524
644
  case R_ARM_ABS32:
525
173
  case R_ARM_BASE_PREL:
526
173
  case R_ARM_GOTOFF32:
527
173
  case R_ARM_GOT_BREL:
528
173
  case R_ARM_GOT_PREL:
529
173
  case R_ARM_REL32:
530
173
  case R_ARM_TARGET1:
531
173
  case R_ARM_TARGET2:
532
173
  case R_ARM_TLS_GD32:
533
173
  case R_ARM_TLS_LDM32:
534
173
  case R_ARM_TLS_LDO32:
535
173
  case R_ARM_TLS_IE32:
536
173
  case R_ARM_TLS_LE32:
537
173
    return SignExtend64<32>(read32le(buf));
538
173
  case R_ARM_PREL31:
539
115
    return SignExtend64<31>(read32le(buf));
540
173
  case R_ARM_CALL:
541
128
  case R_ARM_JUMP24:
542
128
  case R_ARM_PC24:
543
128
  case R_ARM_PLT32:
544
128
    return SignExtend64<26>(read32le(buf) << 2);
545
128
  case R_ARM_THM_JUMP11:
546
5
    return SignExtend64<12>(read16le(buf) << 1);
547
128
  case R_ARM_THM_JUMP19: {
548
21
    // Encoding T3: A = S:J2:J1:imm10:imm6:0
549
21
    uint16_t hi = read16le(buf);
550
21
    uint16_t lo = read16le(buf + 2);
551
21
    return SignExtend64<20>(((hi & 0x0400) << 10) | // S
552
21
                            ((lo & 0x0800) << 8) |  // J2
553
21
                            ((lo & 0x2000) << 5) |  // J1
554
21
                            ((hi & 0x003f) << 12) | // imm6
555
21
                            ((lo & 0x07ff) << 1));  // imm11:0
556
128
  }
557
128
  case R_ARM_THM_CALL:
558
110
    if (!config->armJ1J2BranchEncoding) {
559
23
      // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
560
23
      // different encoding rules and range due to J1 and J2 always being 1.
561
23
      uint16_t hi = read16le(buf);
562
23
      uint16_t lo = read16le(buf + 2);
563
23
      return SignExtend64<22>(((hi & 0x7ff) << 12) | // imm11
564
23
                              ((lo & 0x7ff) << 1));  // imm11:0
565
23
      
break0
;
566
87
    }
567
87
    LLVM_FALLTHROUGH;
568
123
  case R_ARM_THM_JUMP24: {
569
123
    // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
570
123
    // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
571
123
    uint16_t hi = read16le(buf);
572
123
    uint16_t lo = read16le(buf + 2);
573
123
    return SignExtend64<24>(((hi & 0x0400) << 14) |                    // S
574
123
                            (~((lo ^ (hi << 3)) << 10) & 0x00800000) | // I1
575
123
                            (~((lo ^ (hi << 1)) << 11) & 0x00400000) | // I2
576
123
                            ((hi & 0x003ff) << 12) |                   // imm0
577
123
                            ((lo & 0x007ff) << 1)); // imm11:0
578
87
  }
579
87
  // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and
580
87
  // MOVT is in the range -32768 <= A < 32768
581
87
  case R_ARM_MOVW_ABS_NC:
582
28
  case R_ARM_MOVT_ABS:
583
28
  case R_ARM_MOVW_PREL_NC:
584
28
  case R_ARM_MOVT_PREL: {
585
28
    uint64_t val = read32le(buf) & 0x000f0fff;
586
28
    return SignExtend64<16>(((val & 0x000f0000) >> 4) | (val & 0x00fff));
587
28
  }
588
28
  case R_ARM_THM_MOVW_ABS_NC:
589
22
  case R_ARM_THM_MOVT_ABS:
590
22
  case R_ARM_THM_MOVW_PREL_NC:
591
22
  case R_ARM_THM_MOVT_PREL: {
592
22
    // Encoding T3: A = imm4:i:imm3:imm8
593
22
    uint16_t hi = read16le(buf);
594
22
    uint16_t lo = read16le(buf + 2);
595
22
    return SignExtend64<16>(((hi & 0x000f) << 12) | // imm4
596
22
                            ((hi & 0x0400) << 1) |  // i
597
22
                            ((lo & 0x7000) >> 4) |  // imm3
598
22
                            (lo & 0x00ff));         // imm8
599
22
  }
600
644
  }
601
644
}
602
603
325
TargetInfo *elf::getARMTargetInfo() {
604
325
  static ARM target;
605
325
  return &target;
606
325
}