Coverage Report

Created: 2019-05-22 02:55

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/ARM.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- ARM.cpp ------------------------------------------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "InputFiles.h"
10
#include "Symbols.h"
11
#include "SyntheticSections.h"
12
#include "Target.h"
13
#include "Thunks.h"
14
#include "lld/Common/ErrorHandler.h"
15
#include "llvm/Object/ELF.h"
16
#include "llvm/Support/Endian.h"
17
18
using namespace llvm;
19
using namespace llvm::support::endian;
20
using namespace llvm::ELF;
21
using namespace lld;
22
using namespace lld::elf;
23
24
namespace {
25
class ARM final : public TargetInfo {
26
public:
27
  ARM();
28
  uint32_t calcEFlags() const override;
29
  RelExpr getRelExpr(RelType Type, const Symbol &S,
30
                     const uint8_t *Loc) const override;
31
  RelType getDynRel(RelType Type) const override;
32
  int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
33
  void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
34
  void writeIgotPlt(uint8_t *Buf, const Symbol &S) const override;
35
  void writePltHeader(uint8_t *Buf) const override;
36
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
37
                int32_t Index, unsigned RelOff) const override;
38
  void addPltSymbols(InputSection &IS, uint64_t Off) const override;
39
  void addPltHeaderSymbols(InputSection &ISD) const override;
40
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
41
                  uint64_t BranchAddr, const Symbol &S) const override;
42
  uint32_t getThunkSectionSpacing() const override;
43
  bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
44
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
45
};
46
} // namespace
47
48
79
ARM::ARM() {
49
79
  CopyRel = R_ARM_COPY;
50
79
  RelativeRel = R_ARM_RELATIVE;
51
79
  IRelativeRel = R_ARM_IRELATIVE;
52
79
  GotRel = R_ARM_GLOB_DAT;
53
79
  NoneRel = R_ARM_NONE;
54
79
  PltRel = R_ARM_JUMP_SLOT;
55
79
  TlsGotRel = R_ARM_TLS_TPOFF32;
56
79
  TlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
57
79
  TlsOffsetRel = R_ARM_TLS_DTPOFF32;
58
79
  GotBaseSymInGotPlt = false;
59
79
  GotEntrySize = 4;
60
79
  GotPltEntrySize = 4;
61
79
  PltEntrySize = 16;
62
79
  PltHeaderSize = 32;
63
79
  TrapInstr = {0xd4, 0xd4, 0xd4, 0xd4};
64
79
  NeedsThunks = true;
65
79
}
66
67
75
uint32_t ARM::calcEFlags() const {
68
75
  // The ABIFloatType is used by loaders to detect the floating point calling
69
75
  // convention.
70
75
  uint32_t ABIFloatType = 0;
71
75
  if (Config->ARMVFPArgs == ARMVFPArgKind::Base ||
72
75
      Config->ARMVFPArgs == ARMVFPArgKind::Default)
73
74
    ABIFloatType = EF_ARM_ABI_FLOAT_SOFT;
74
1
  else if (Config->ARMVFPArgs == ARMVFPArgKind::VFP)
75
1
    ABIFloatType = EF_ARM_ABI_FLOAT_HARD;
76
75
77
75
  // We don't currently use any features incompatible with EF_ARM_EABI_VER5,
78
75
  // but we don't have any firm guarantees of conformance. Linux AArch64
79
75
  // kernels (as of 2016) require an EABI version to be set.
80
75
  return EF_ARM_EABI_VER5 | ABIFloatType;
81
75
}
82
83
RelExpr ARM::getRelExpr(RelType Type, const Symbol &S,
84
313
                        const uint8_t *Loc) const {
85
313
  switch (Type) {
86
313
  case R_ARM_THM_JUMP11:
87
4
    return R_PC;
88
313
  case R_ARM_CALL:
89
189
  case R_ARM_JUMP24:
90
189
  case R_ARM_PC24:
91
189
  case R_ARM_PLT32:
92
189
  case R_ARM_PREL31:
93
189
  case R_ARM_THM_JUMP19:
94
189
  case R_ARM_THM_JUMP24:
95
189
  case R_ARM_THM_CALL:
96
189
    return R_PLT_PC;
97
189
  case R_ARM_GOTOFF32:
98
0
    // (S + A) - GOT_ORG
99
0
    return R_GOTREL;
100
189
  case R_ARM_GOT_BREL:
101
6
    // GOT(S) + A - GOT_ORG
102
6
    return R_GOT_OFF;
103
189
  case R_ARM_GOT_PREL:
104
2
  case R_ARM_TLS_IE32:
105
2
    // GOT(S) + A - P
106
2
    return R_GOT_PC;
107
2
  case R_ARM_SBREL32:
108
0
    return R_ARM_SBREL;
109
2
  case R_ARM_TARGET1:
110
2
    return Config->Target1Rel ? 
R_PC1
:
R_ABS1
;
111
2
  case R_ARM_TARGET2:
112
1
    if (Config->Target2 == Target2Policy::Rel)
113
0
      return R_PC;
114
1
    if (Config->Target2 == Target2Policy::Abs)
115
0
      return R_ABS;
116
1
    return R_GOT_PC;
117
11
  case R_ARM_TLS_GD32:
118
11
    return R_TLSGD_PC;
119
1
  case R_ARM_TLS_LDM32:
120
0
    return R_TLSLD_PC;
121
1
  case R_ARM_BASE_PREL:
122
0
    // B(S) + A - P
123
0
    // FIXME: currently B(S) assumed to be .got, this may not hold for all
124
0
    // platforms.
125
0
    return R_GOTONLY_PC;
126
16
  case R_ARM_MOVW_PREL_NC:
127
16
  case R_ARM_MOVT_PREL:
128
16
  case R_ARM_REL32:
129
16
  case R_ARM_THM_MOVW_PREL_NC:
130
16
  case R_ARM_THM_MOVT_PREL:
131
16
    return R_PC;
132
16
  case R_ARM_NONE:
133
8
    return R_NONE;
134
16
  case R_ARM_TLS_LE32:
135
3
    return R_TLS;
136
16
  case R_ARM_V4BX:
137
1
    // V4BX is just a marker to indicate there's a "bx rN" instruction at the
138
1
    // given address. It can be used to implement a special linker mode which
139
1
    // rewrites ARMv4T inputs to ARMv4. Since we support only ARMv4 input and
140
1
    // not ARMv4 output, we can just ignore it.
141
1
    return R_HINT;
142
70
  default:
143
70
    return R_ABS;
144
313
  }
145
313
}
146
147
5
RelType ARM::getDynRel(RelType Type) const {
148
5
  if ((Type == R_ARM_ABS32) || 
(0
Type == R_ARM_TARGET10
&&
!Config->Target1Rel0
))
149
5
    return R_ARM_ABS32;
150
0
  return R_ARM_NONE;
151
0
}
152
153
22
void ARM::writeGotPlt(uint8_t *Buf, const Symbol &) const {
154
22
  write32le(Buf, In.Plt->getVA());
155
22
}
156
157
5
void ARM::writeIgotPlt(uint8_t *Buf, const Symbol &S) const {
158
5
  // An ARM entry is the address of the ifunc resolver function.
159
5
  write32le(Buf, S.getVA());
160
5
}
161
162
// Long form PLT Header that does not have any restrictions on the displacement
163
// of the .plt from the .plt.got.
164
0
static void writePltHeaderLong(uint8_t *Buf) {
165
0
  const uint8_t PltData[] = {
166
0
      0x04, 0xe0, 0x2d, 0xe5, //     str lr, [sp,#-4]!
167
0
      0x04, 0xe0, 0x9f, 0xe5, //     ldr lr, L2
168
0
      0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr
169
0
      0x08, 0xf0, 0xbe, 0xe5, //     ldr pc, [lr, #8]
170
0
      0x00, 0x00, 0x00, 0x00, // L2: .word   &(.got.plt) - L1 - 8
171
0
      0xd4, 0xd4, 0xd4, 0xd4, //     Pad to 32-byte boundary
172
0
      0xd4, 0xd4, 0xd4, 0xd4, //     Pad to 32-byte boundary
173
0
      0xd4, 0xd4, 0xd4, 0xd4};
174
0
  memcpy(Buf, PltData, sizeof(PltData));
175
0
  uint64_t GotPlt = In.GotPlt->getVA();
176
0
  uint64_t L1 = In.Plt->getVA() + 8;
177
0
  write32le(Buf + 16, GotPlt - L1 - 8);
178
0
}
179
180
// The default PLT header requires the .plt.got to be within 128 Mb of the
181
// .plt in the positive direction.
182
12
void ARM::writePltHeader(uint8_t *Buf) const {
183
12
  // Use a similar sequence to that in writePlt(), the difference is the calling
184
12
  // conventions mean we use lr instead of ip. The PLT entry is responsible for
185
12
  // saving lr on the stack, the dynamic loader is responsible for reloading
186
12
  // it.
187
12
  const uint32_t PltData[] = {
188
12
      0xe52de004, // L1: str lr, [sp,#-4]!
189
12
      0xe28fe600, //     add lr, pc,  #0x0NN00000 &(.got.plt - L1 - 4)
190
12
      0xe28eea00, //     add lr, lr,  #0x000NN000 &(.got.plt - L1 - 4)
191
12
      0xe5bef000, //     ldr pc, [lr, #0x00000NNN] &(.got.plt -L1 - 4)
192
12
  };
193
12
194
12
  uint64_t Offset = In.GotPlt->getVA() - In.Plt->getVA() - 4;
195
12
  if (!llvm::isUInt<27>(Offset)) {
196
0
    // We cannot encode the Offset, use the long form.
197
0
    writePltHeaderLong(Buf);
198
0
    return;
199
0
  }
200
12
  write32le(Buf + 0, PltData[0]);
201
12
  write32le(Buf + 4, PltData[1] | ((Offset >> 20) & 0xff));
202
12
  write32le(Buf + 8, PltData[2] | ((Offset >> 12) & 0xff));
203
12
  write32le(Buf + 12, PltData[3] | (Offset & 0xfff));
204
12
  memcpy(Buf + 16, TrapInstr.data(), 4); // Pad to 32-byte boundary
205
12
  memcpy(Buf + 20, TrapInstr.data(), 4);
206
12
  memcpy(Buf + 24, TrapInstr.data(), 4);
207
12
  memcpy(Buf + 28, TrapInstr.data(), 4);
208
12
}
209
210
12
void ARM::addPltHeaderSymbols(InputSection &IS) const {
211
12
  addSyntheticLocal("$a", STT_NOTYPE, 0, 0, IS);
212
12
  addSyntheticLocal("$d", STT_NOTYPE, 16, 0, IS);
213
12
}
214
215
// Long form PLT entries that do not have any restrictions on the displacement
216
// of the .plt from the .plt.got.
217
static void writePltLong(uint8_t *Buf, uint64_t GotPltEntryAddr,
218
                         uint64_t PltEntryAddr, int32_t Index,
219
0
                         unsigned RelOff) {
220
0
  const uint8_t PltData[] = {
221
0
      0x04, 0xc0, 0x9f, 0xe5, //     ldr ip, L2
222
0
      0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc
223
0
      0x00, 0xf0, 0x9c, 0xe5, //     ldr pc, [ip]
224
0
      0x00, 0x00, 0x00, 0x00, // L2: .word   Offset(&(.plt.got) - L1 - 8
225
0
  };
226
0
  memcpy(Buf, PltData, sizeof(PltData));
227
0
  uint64_t L1 = PltEntryAddr + 4;
228
0
  write32le(Buf + 12, GotPltEntryAddr - L1 - 8);
229
0
}
230
231
// The default PLT entries require the .plt.got to be within 128 Mb of the
232
// .plt in the positive direction.
233
void ARM::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
234
                   uint64_t PltEntryAddr, int32_t Index,
235
27
                   unsigned RelOff) const {
236
27
  // The PLT entry is similar to the example given in Appendix A of ELF for
237
27
  // the Arm Architecture. Instead of using the Group Relocations to find the
238
27
  // optimal rotation for the 8-bit immediate used in the add instructions we
239
27
  // hard code the most compact rotations for simplicity. This saves a load
240
27
  // instruction over the long plt sequences.
241
27
  const uint32_t PltData[] = {
242
27
      0xe28fc600, // L1: add ip, pc,  #0x0NN00000  Offset(&(.plt.got) - L1 - 8
243
27
      0xe28cca00, //     add ip, ip,  #0x000NN000  Offset(&(.plt.got) - L1 - 8
244
27
      0xe5bcf000, //     ldr pc, [ip, #0x00000NNN] Offset(&(.plt.got) - L1 - 8
245
27
  };
246
27
247
27
  uint64_t Offset = GotPltEntryAddr - PltEntryAddr - 8;
248
27
  if (!llvm::isUInt<27>(Offset)) {
249
0
    // We cannot encode the Offset, use the long form.
250
0
    writePltLong(Buf, GotPltEntryAddr, PltEntryAddr, Index, RelOff);
251
0
    return;
252
0
  }
253
27
  write32le(Buf + 0, PltData[0] | ((Offset >> 20) & 0xff));
254
27
  write32le(Buf + 4, PltData[1] | ((Offset >> 12) & 0xff));
255
27
  write32le(Buf + 8, PltData[2] | (Offset & 0xfff));
256
27
  memcpy(Buf + 12, TrapInstr.data(), 4); // Pad to 16-byte boundary
257
27
}
258
259
27
void ARM::addPltSymbols(InputSection &IS, uint64_t Off) const {
260
27
  addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS);
261
27
  addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS);
262
27
}
263
264
bool ARM::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
265
224
                     uint64_t BranchAddr, const Symbol &S) const {
266
224
  // If S is an undefined weak symbol and does not have a PLT entry then it
267
224
  // will be resolved as a branch to the next instruction.
268
224
  if (S.isUndefWeak() && 
!S.isInPlt()15
)
269
15
    return false;
270
209
  // A state change from ARM to Thumb and vice versa must go through an
271
209
  // interworking thunk if the relocation type is not R_ARM_CALL or
272
209
  // R_ARM_THM_CALL.
273
209
  switch (Type) {
274
209
  case R_ARM_PC24:
275
10
  case R_ARM_PLT32:
276
10
  case R_ARM_JUMP24:
277
10
    // Source is ARM, all PLT entries are ARM so no interworking required.
278
10
    // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
279
10
    if (Expr == R_PC && 
((S.getVA() & 1) == 1)6
)
280
2
      return true;
281
8
    LLVM_FALLTHROUGH;
282
51
  case R_ARM_CALL: {
283
51
    uint64_t Dst = (Expr == R_PLT_PC) ? 
S.getPltVA()18
:
S.getVA()33
;
284
51
    return !inBranchRange(Type, BranchAddr, Dst);
285
8
  }
286
12
  case R_ARM_THM_JUMP19:
287
12
  case R_ARM_THM_JUMP24:
288
12
    // Source is Thumb, all PLT entries are ARM so interworking is required.
289
12
    // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
290
12
    if (Expr == R_PLT_PC || ((S.getVA() & 1) == 0))
291
2
      return true;
292
10
    LLVM_FALLTHROUGH;
293
103
  case R_ARM_THM_CALL: {
294
103
    uint64_t Dst = (Expr == R_PLT_PC) ? 
S.getPltVA()12
:
S.getVA()91
;
295
103
    return !inBranchRange(Type, BranchAddr, Dst);
296
51
  }
297
51
  }
298
51
  return false;
299
51
}
300
301
152
uint32_t ARM::getThunkSectionSpacing() const {
302
152
  // The placing of pre-created ThunkSections is controlled by the value
303
152
  // ThunkSectionSpacing returned by getThunkSectionSpacing(). The aim is to
304
152
  // place the ThunkSection such that all branches from the InputSections
305
152
  // prior to the ThunkSection can reach a Thunk placed at the end of the
306
152
  // ThunkSection. Graphically:
307
152
  // | up to ThunkSectionSpacing .text input sections |
308
152
  // | ThunkSection                                   |
309
152
  // | up to ThunkSectionSpacing .text input sections |
310
152
  // | ThunkSection                                   |
311
152
312
152
  // Pre-created ThunkSections are spaced roughly 16MiB apart on ARMv7. This
313
152
  // is to match the most common expected case of a Thumb 2 encoded BL, BLX or
314
152
  // B.W:
315
152
  // ARM B, BL, BLX range +/- 32MiB
316
152
  // Thumb B.W, BL, BLX range +/- 16MiB
317
152
  // Thumb B<cc>.W range +/- 1MiB
318
152
  // If a branch cannot reach a pre-created ThunkSection a new one will be
319
152
  // created so we can handle the rare cases of a Thumb 2 conditional branch.
320
152
  // We intentionally use a lower size for ThunkSectionSpacing than the maximum
321
152
  // branch range so the end of the ThunkSection is more likely to be within
322
152
  // range of the branch instruction that is furthest away. The value we shorten
323
152
  // ThunkSectionSpacing by is set conservatively to allow us to create 16,384
324
152
  // 12 byte Thunks at any offset in a ThunkSection without risk of a branch to
325
152
  // one of the Thunks going out of range.
326
152
327
152
  // On Arm the ThunkSectionSpacing depends on the range of the Thumb Branch
328
152
  // range. On earlier Architectures such as ARMv4, ARMv5 and ARMv6 (except
329
152
  // ARMv6T2) the range is +/- 4MiB.
330
152
331
152
  return (Config->ARMJ1J2BranchEncoding) ? 
0x1000000 - 0x3000054
332
152
                                         : 
0x400000 - 0x750098
;
333
152
}
334
335
324
bool ARM::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
336
324
  uint64_t Range;
337
324
  uint64_t InstrSize;
338
324
339
324
  switch (Type) {
340
324
  case R_ARM_PC24:
341
71
  case R_ARM_PLT32:
342
71
  case R_ARM_JUMP24:
343
71
  case R_ARM_CALL:
344
71
    Range = 0x2000000;
345
71
    InstrSize = 4;
346
71
    break;
347
71
  case R_ARM_THM_JUMP19:
348
26
    Range = 0x100000;
349
26
    InstrSize = 2;
350
26
    break;
351
227
  case R_ARM_THM_JUMP24:
352
227
  case R_ARM_THM_CALL:
353
227
    Range = Config->ARMJ1J2BranchEncoding ? 
0x1000000186
:
0x40000041
;
354
227
    InstrSize = 2;
355
227
    break;
356
227
  default:
357
0
    return true;
358
324
  }
359
324
  // PC at Src is 2 instructions ahead, immediate of branch is signed
360
324
  if (Src > Dst)
361
113
    Range -= 2 * InstrSize;
362
211
  else
363
211
    Range += InstrSize;
364
324
365
324
  if ((Dst & 0x1) == 0)
366
146
    // Destination is ARM, if ARM caller then Src is already 4-byte aligned.
367
146
    // If Thumb Caller (BLX) the Src address has bottom 2 bits cleared to ensure
368
146
    // destination will be 4 byte aligned.
369
146
    Src &= ~0x3;
370
178
  else
371
178
    // Bit 0 == 1 denotes Thumb state, it is not part of the range
372
178
    Dst &= ~0x1;
373
324
374
324
  uint64_t Distance = (Src > Dst) ? 
Src - Dst112
:
Dst - Src212
;
375
324
  return Distance <= Range;
376
324
}
377
378
424
void ARM::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
379
424
  switch (Type) {
380
424
  case R_ARM_ABS32:
381
92
  case R_ARM_BASE_PREL:
382
92
  case R_ARM_GLOB_DAT:
383
92
  case R_ARM_GOTOFF32:
384
92
  case R_ARM_GOT_BREL:
385
92
  case R_ARM_GOT_PREL:
386
92
  case R_ARM_REL32:
387
92
  case R_ARM_RELATIVE:
388
92
  case R_ARM_SBREL32:
389
92
  case R_ARM_TARGET1:
390
92
  case R_ARM_TARGET2:
391
92
  case R_ARM_TLS_GD32:
392
92
  case R_ARM_TLS_IE32:
393
92
  case R_ARM_TLS_LDM32:
394
92
  case R_ARM_TLS_LDO32:
395
92
  case R_ARM_TLS_LE32:
396
92
  case R_ARM_TLS_TPOFF32:
397
92
  case R_ARM_TLS_DTPOFF32:
398
92
    write32le(Loc, Val);
399
92
    break;
400
92
  case R_ARM_TLS_DTPMOD32:
401
5
    write32le(Loc, 1);
402
5
    break;
403
92
  case R_ARM_PREL31:
404
69
    checkInt(Loc, Val, 31, Type);
405
69
    write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000));
406
69
    break;
407
92
  case R_ARM_CALL:
408
42
    // R_ARM_CALL is used for BL and BLX instructions, depending on the
409
42
    // value of bit 0 of Val, we must select a BL or BLX instruction
410
42
    if (Val & 1) {
411
14
      // If bit 0 of Val is 1 the target is Thumb, we must select a BLX.
412
14
      // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
413
14
      checkInt(Loc, Val, 26, Type);
414
14
      write32le(Loc, 0xfa000000 |                    // opcode
415
14
                         ((Val & 2) << 23) |         // H
416
14
                         ((Val >> 2) & 0x00ffffff)); // imm24
417
14
      break;
418
14
    }
419
28
    if ((read32le(Loc) & 0xfe000000) == 0xfa000000)
420
3
      // BLX (always unconditional) instruction to an ARM Target, select an
421
3
      // unconditional BL.
422
3
      write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff));
423
28
    // fall through as BL encoding is shared with B
424
28
    LLVM_FALLTHROUGH;
425
46
  case R_ARM_JUMP24:
426
46
  case R_ARM_PC24:
427
46
  case R_ARM_PLT32:
428
46
    checkInt(Loc, Val, 26, Type);
429
46
    write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff));
430
46
    break;
431
46
  case R_ARM_THM_JUMP11:
432
4
    checkInt(Loc, Val, 12, Type);
433
4
    write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff));
434
4
    break;
435
46
  case R_ARM_THM_JUMP19:
436
7
    // Encoding T3: Val = S:J2:J1:imm6:imm11:0
437
7
    checkInt(Loc, Val, 21, Type);
438
7
    write16le(Loc,
439
7
              (read16le(Loc) & 0xfbc0) |   // opcode cond
440
7
                  ((Val >> 10) & 0x0400) | // S
441
7
                  ((Val >> 12) & 0x003f)); // imm6
442
7
    write16le(Loc + 2,
443
7
              0x8000 |                    // opcode
444
7
                  ((Val >> 8) & 0x0800) | // J2
445
7
                  ((Val >> 5) & 0x2000) | // J1
446
7
                  ((Val >> 1) & 0x07ff)); // imm11
447
7
    break;
448
76
  case R_ARM_THM_CALL:
449
76
    // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
450
76
    // value of bit 0 of Val, we must select a BL or BLX instruction
451
76
    if ((Val & 1) == 0) {
452
14
      // Ensure BLX destination is 4-byte aligned. As BLX instruction may
453
14
      // only be two byte aligned. This must be done before overflow check
454
14
      Val = alignTo(Val, 4);
455
14
    }
456
76
    // Bit 12 is 0 for BLX, 1 for BL
457
76
    write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12);
458
76
    if (!Config->ARMJ1J2BranchEncoding) {
459
18
      // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
460
18
      // different encoding rules and range due to J1 and J2 always being 1.
461
18
      checkInt(Loc, Val, 23, Type);
462
18
      write16le(Loc,
463
18
                0xf000 |                     // opcode
464
18
                    ((Val >> 12) & 0x07ff)); // imm11
465
18
      write16le(Loc + 2,
466
18
                (read16le(Loc + 2) & 0xd000) | // opcode
467
18
                    0x2800 |                   // J1 == J2 == 1
468
18
                    ((Val >> 1) & 0x07ff));    // imm11
469
18
      break;
470
18
    }
471
58
    // Fall through as rest of encoding is the same as B.W
472
58
    LLVM_FALLTHROUGH;
473
79
  case R_ARM_THM_JUMP24:
474
79
    // Encoding B  T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
475
79
    checkInt(Loc, Val, 25, Type);
476
79
    write16le(Loc,
477
79
              0xf000 |                     // opcode
478
79
                  ((Val >> 14) & 0x0400) | // S
479
79
                  ((Val >> 12) & 0x03ff)); // imm10
480
79
    write16le(Loc + 2,
481
79
              (read16le(Loc + 2) & 0xd000) |                  // opcode
482
79
                  (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1
483
79
                  (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2
484
79
                  ((Val >> 1) & 0x07ff));                     // imm11
485
79
    break;
486
58
  case R_ARM_MOVW_ABS_NC:
487
9
  case R_ARM_MOVW_PREL_NC:
488
9
    write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) |
489
9
                       (Val & 0x0fff));
490
9
    break;
491
9
  case R_ARM_MOVT_ABS:
492
9
  case R_ARM_MOVT_PREL:
493
9
    write32le(Loc, (read32le(Loc) & ~0x000f0fff) |
494
9
                       (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff));
495
9
    break;
496
36
  case R_ARM_THM_MOVT_ABS:
497
36
  case R_ARM_THM_MOVT_PREL:
498
36
    // Encoding T1: A = imm4:i:imm3:imm8
499
36
    write16le(Loc,
500
36
              0xf2c0 |                     // opcode
501
36
                  ((Val >> 17) & 0x0400) | // i
502
36
                  ((Val >> 28) & 0x000f)); // imm4
503
36
    write16le(Loc + 2,
504
36
              (read16le(Loc + 2) & 0x8f00) | // opcode
505
36
                  ((Val >> 12) & 0x7000) |   // imm3
506
36
                  ((Val >> 16) & 0x00ff));   // imm8
507
36
    break;
508
36
  case R_ARM_THM_MOVW_ABS_NC:
509
36
  case R_ARM_THM_MOVW_PREL_NC:
510
36
    // Encoding T3: A = imm4:i:imm3:imm8
511
36
    write16le(Loc,
512
36
              0xf240 |                     // opcode
513
36
                  ((Val >> 1) & 0x0400) |  // i
514
36
                  ((Val >> 12) & 0x000f)); // imm4
515
36
    write16le(Loc + 2,
516
36
              (read16le(Loc + 2) & 0x8f00) | // opcode
517
36
                  ((Val << 4) & 0x7000) |    // imm3
518
36
                  (Val & 0x00ff));           // imm8
519
36
    break;
520
36
  default:
521
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
522
424
  }
523
424
}
524
525
320
int64_t ARM::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
526
320
  switch (Type) {
527
320
  default:
528
1
    return 0;
529
320
  case R_ARM_ABS32:
530
83
  case R_ARM_BASE_PREL:
531
83
  case R_ARM_GOTOFF32:
532
83
  case R_ARM_GOT_BREL:
533
83
  case R_ARM_GOT_PREL:
534
83
  case R_ARM_REL32:
535
83
  case R_ARM_TARGET1:
536
83
  case R_ARM_TARGET2:
537
83
  case R_ARM_TLS_GD32:
538
83
  case R_ARM_TLS_LDM32:
539
83
  case R_ARM_TLS_LDO32:
540
83
  case R_ARM_TLS_IE32:
541
83
  case R_ARM_TLS_LE32:
542
83
    return SignExtend64<32>(read32le(Buf));
543
83
  case R_ARM_PREL31:
544
60
    return SignExtend64<31>(read32le(Buf));
545
83
  case R_ARM_CALL:
546
53
  case R_ARM_JUMP24:
547
53
  case R_ARM_PC24:
548
53
  case R_ARM_PLT32:
549
53
    return SignExtend64<26>(read32le(Buf) << 2);
550
53
  case R_ARM_THM_JUMP11:
551
4
    return SignExtend64<12>(read16le(Buf) << 1);
552
53
  case R_ARM_THM_JUMP19: {
553
7
    // Encoding T3: A = S:J2:J1:imm10:imm6:0
554
7
    uint16_t Hi = read16le(Buf);
555
7
    uint16_t Lo = read16le(Buf + 2);
556
7
    return SignExtend64<20>(((Hi & 0x0400) << 10) | // S
557
7
                            ((Lo & 0x0800) << 8) |  // J2
558
7
                            ((Lo & 0x2000) << 5) |  // J1
559
7
                            ((Hi & 0x003f) << 12) | // imm6
560
7
                            ((Lo & 0x07ff) << 1));  // imm11:0
561
53
  }
562
76
  case R_ARM_THM_CALL:
563
76
    if (!Config->ARMJ1J2BranchEncoding) {
564
18
      // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
565
18
      // different encoding rules and range due to J1 and J2 always being 1.
566
18
      uint16_t Hi = read16le(Buf);
567
18
      uint16_t Lo = read16le(Buf + 2);
568
18
      return SignExtend64<22>(((Hi & 0x7ff) << 12) | // imm11
569
18
                              ((Lo & 0x7ff) << 1));  // imm11:0
570
18
      
break0
;
571
58
    }
572
58
    LLVM_FALLTHROUGH;
573
66
  case R_ARM_THM_JUMP24: {
574
66
    // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
575
66
    // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
576
66
    uint16_t Hi = read16le(Buf);
577
66
    uint16_t Lo = read16le(Buf + 2);
578
66
    return SignExtend64<24>(((Hi & 0x0400) << 14) |                    // S
579
66
                            (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1
580
66
                            (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2
581
66
                            ((Hi & 0x003ff) << 12) |                   // imm0
582
66
                            ((Lo & 0x007ff) << 1)); // imm11:0
583
58
  }
584
58
  // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and
585
58
  // MOVT is in the range -32768 <= A < 32768
586
58
  case R_ARM_MOVW_ABS_NC:
587
6
  case R_ARM_MOVT_ABS:
588
6
  case R_ARM_MOVW_PREL_NC:
589
6
  case R_ARM_MOVT_PREL: {
590
6
    uint64_t Val = read32le(Buf) & 0x000f0fff;
591
6
    return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff));
592
6
  }
593
22
  case R_ARM_THM_MOVW_ABS_NC:
594
22
  case R_ARM_THM_MOVT_ABS:
595
22
  case R_ARM_THM_MOVW_PREL_NC:
596
22
  case R_ARM_THM_MOVT_PREL: {
597
22
    // Encoding T3: A = imm4:i:imm3:imm8
598
22
    uint16_t Hi = read16le(Buf);
599
22
    uint16_t Lo = read16le(Buf + 2);
600
22
    return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4
601
22
                            ((Hi & 0x0400) << 1) |  // i
602
22
                            ((Lo & 0x7000) >> 4) |  // imm3
603
22
                            (Lo & 0x00ff));         // imm8
604
22
  }
605
320
  }
606
320
}
607
608
79
TargetInfo *elf::getARMTargetInfo() {
609
79
  static ARM Target;
610
79
  return &Target;
611
79
}