Coverage Report

Created: 2019-01-21 03:01

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/ARM.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- ARM.cpp ------------------------------------------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "InputFiles.h"
10
#include "Symbols.h"
11
#include "SyntheticSections.h"
12
#include "Target.h"
13
#include "Thunks.h"
14
#include "lld/Common/ErrorHandler.h"
15
#include "llvm/Object/ELF.h"
16
#include "llvm/Support/Endian.h"
17
18
using namespace llvm;
19
using namespace llvm::support::endian;
20
using namespace llvm::ELF;
21
using namespace lld;
22
using namespace lld::elf;
23
24
namespace {
25
class ARM final : public TargetInfo {
26
public:
27
  ARM();
28
  uint32_t calcEFlags() const override;
29
  RelExpr getRelExpr(RelType Type, const Symbol &S,
30
                     const uint8_t *Loc) const override;
31
  RelType getDynRel(RelType Type) const override;
32
  int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
33
  void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
34
  void writeIgotPlt(uint8_t *Buf, const Symbol &S) const override;
35
  void writePltHeader(uint8_t *Buf) const override;
36
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
37
                int32_t Index, unsigned RelOff) const override;
38
  void addPltSymbols(InputSection &IS, uint64_t Off) const override;
39
  void addPltHeaderSymbols(InputSection &ISD) const override;
40
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
41
                  uint64_t BranchAddr, const Symbol &S) const override;
42
  uint32_t getThunkSectionSpacing() const override;
43
  bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
44
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
45
};
46
} // namespace
47
48
155
ARM::ARM() {
49
155
  CopyRel = R_ARM_COPY;
50
155
  RelativeRel = R_ARM_RELATIVE;
51
155
  IRelativeRel = R_ARM_IRELATIVE;
52
155
  GotRel = R_ARM_GLOB_DAT;
53
155
  NoneRel = R_ARM_NONE;
54
155
  PltRel = R_ARM_JUMP_SLOT;
55
155
  TlsGotRel = R_ARM_TLS_TPOFF32;
56
155
  TlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
57
155
  TlsOffsetRel = R_ARM_TLS_DTPOFF32;
58
155
  GotBaseSymInGotPlt = false;
59
155
  GotEntrySize = 4;
60
155
  GotPltEntrySize = 4;
61
155
  PltEntrySize = 16;
62
155
  PltHeaderSize = 32;
63
155
  TrapInstr = {0xd4, 0xd4, 0xd4, 0xd4};
64
155
  NeedsThunks = true;
65
155
}
66
67
148
uint32_t ARM::calcEFlags() const {
68
148
  // The ABIFloatType is used by loaders to detect the floating point calling
69
148
  // convention.
70
148
  uint32_t ABIFloatType = 0;
71
148
  if (Config->ARMVFPArgs == ARMVFPArgKind::Base ||
72
148
      
Config->ARMVFPArgs == ARMVFPArgKind::Default146
)
73
144
    ABIFloatType = EF_ARM_ABI_FLOAT_SOFT;
74
4
  else if (Config->ARMVFPArgs == ARMVFPArgKind::VFP)
75
2
    ABIFloatType = EF_ARM_ABI_FLOAT_HARD;
76
148
77
148
  // We don't currently use any features incompatible with EF_ARM_EABI_VER5,
78
148
  // but we don't have any firm guarantees of conformance. Linux AArch64
79
148
  // kernels (as of 2016) require an EABI version to be set.
80
148
  return EF_ARM_EABI_VER5 | ABIFloatType;
81
148
}
82
83
RelExpr ARM::getRelExpr(RelType Type, const Symbol &S,
84
617
                        const uint8_t *Loc) const {
85
617
  switch (Type) {
86
617
  case R_ARM_THM_JUMP11:
87
5
    return R_PC;
88
617
  case R_ARM_CALL:
89
371
  case R_ARM_JUMP24:
90
371
  case R_ARM_PC24:
91
371
  case R_ARM_PLT32:
92
371
  case R_ARM_PREL31:
93
371
  case R_ARM_THM_JUMP19:
94
371
  case R_ARM_THM_JUMP24:
95
371
  case R_ARM_THM_CALL:
96
371
    return R_PLT_PC;
97
371
  case R_ARM_GOTOFF32:
98
3
    // (S + A) - GOT_ORG
99
3
    return R_GOTREL;
100
371
  case R_ARM_GOT_BREL:
101
7
    // GOT(S) + A - GOT_ORG
102
7
    return R_GOT_OFF;
103
371
  case R_ARM_GOT_PREL:
104
6
  case R_ARM_TLS_IE32:
105
6
    // GOT(S) + A - P
106
6
    return R_GOT_PC;
107
6
  case R_ARM_SBREL32:
108
4
    return R_ARM_SBREL;
109
6
  case R_ARM_TARGET1:
110
4
    return Config->Target1Rel ? 
R_PC2
:
R_ABS2
;
111
6
  case R_ARM_TARGET2:
112
4
    if (Config->Target2 == Target2Policy::Rel)
113
1
      return R_PC;
114
3
    if (Config->Target2 == Target2Policy::Abs)
115
1
      return R_ABS;
116
2
    return R_GOT_PC;
117
14
  case R_ARM_TLS_GD32:
118
14
    return R_TLSGD_PC;
119
2
  case R_ARM_TLS_LDM32:
120
2
    return R_TLSLD_PC;
121
2
  case R_ARM_BASE_PREL:
122
0
    // B(S) + A - P
123
0
    // FIXME: currently B(S) assumed to be .got, this may not hold for all
124
0
    // platforms.
125
0
    return R_GOTONLY_PC;
126
27
  case R_ARM_MOVW_PREL_NC:
127
27
  case R_ARM_MOVT_PREL:
128
27
  case R_ARM_REL32:
129
27
  case R_ARM_THM_MOVW_PREL_NC:
130
27
  case R_ARM_THM_MOVT_PREL:
131
27
    return R_PC;
132
27
  case R_ARM_NONE:
133
13
    return R_NONE;
134
27
  case R_ARM_TLS_LE32:
135
3
    return R_TLS;
136
27
  case R_ARM_V4BX:
137
2
    // V4BX is just a marker to indicate there's a "bx rN" instruction at the
138
2
    // given address. It can be used to implement a special linker mode which
139
2
    // rewrites ARMv4T inputs to ARMv4. Since we support only ARMv4 input and
140
2
    // not ARMv4 output, we can just ignore it.
141
2
    return R_HINT;
142
152
  default:
143
152
    return R_ABS;
144
617
  }
145
617
}
146
147
7
RelType ARM::getDynRel(RelType Type) const {
148
7
  if ((Type == R_ARM_ABS32) || 
(0
Type == R_ARM_TARGET10
&&
!Config->Target1Rel0
))
149
7
    return R_ARM_ABS32;
150
0
  return R_ARM_NONE;
151
0
}
152
153
44
void ARM::writeGotPlt(uint8_t *Buf, const Symbol &) const {
154
44
  write32le(Buf, In.Plt->getVA());
155
44
}
156
157
7
void ARM::writeIgotPlt(uint8_t *Buf, const Symbol &S) const {
158
7
  // An ARM entry is the address of the ifunc resolver function.
159
7
  write32le(Buf, S.getVA());
160
7
}
161
162
// Long form PLT Header that does not have any restrictions on the displacement
163
// of the .plt from the .plt.got.
164
2
static void writePltHeaderLong(uint8_t *Buf) {
165
2
  const uint8_t PltData[] = {
166
2
      0x04, 0xe0, 0x2d, 0xe5, //     str lr, [sp,#-4]!
167
2
      0x04, 0xe0, 0x9f, 0xe5, //     ldr lr, L2
168
2
      0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr
169
2
      0x08, 0xf0, 0xbe, 0xe5, //     ldr pc, [lr, #8]
170
2
      0x00, 0x00, 0x00, 0x00, // L2: .word   &(.got.plt) - L1 - 8
171
2
      0xd4, 0xd4, 0xd4, 0xd4, //     Pad to 32-byte boundary
172
2
      0xd4, 0xd4, 0xd4, 0xd4, //     Pad to 32-byte boundary
173
2
      0xd4, 0xd4, 0xd4, 0xd4};
174
2
  memcpy(Buf, PltData, sizeof(PltData));
175
2
  uint64_t GotPlt = In.GotPlt->getVA();
176
2
  uint64_t L1 = In.Plt->getVA() + 8;
177
2
  write32le(Buf + 16, GotPlt - L1 - 8);
178
2
}
179
180
// The default PLT header requires the .plt.got to be within 128 Mb of the
181
// .plt in the positive direction.
182
20
void ARM::writePltHeader(uint8_t *Buf) const {
183
20
  // Use a similar sequence to that in writePlt(), the difference is the calling
184
20
  // conventions mean we use lr instead of ip. The PLT entry is responsible for
185
20
  // saving lr on the stack, the dynamic loader is responsible for reloading
186
20
  // it.
187
20
  const uint32_t PltData[] = {
188
20
      0xe52de004, // L1: str lr, [sp,#-4]!
189
20
      0xe28fe600, //     add lr, pc,  #0x0NN00000 &(.got.plt - L1 - 4)
190
20
      0xe28eea00, //     add lr, lr,  #0x000NN000 &(.got.plt - L1 - 4)
191
20
      0xe5bef000, //     ldr pc, [lr, #0x00000NNN] &(.got.plt -L1 - 4)
192
20
  };
193
20
194
20
  uint64_t Offset = In.GotPlt->getVA() - In.Plt->getVA() - 4;
195
20
  if (!llvm::isUInt<27>(Offset)) {
196
2
    // We cannot encode the Offset, use the long form.
197
2
    writePltHeaderLong(Buf);
198
2
    return;
199
2
  }
200
18
  write32le(Buf + 0, PltData[0]);
201
18
  write32le(Buf + 4, PltData[1] | ((Offset >> 20) & 0xff));
202
18
  write32le(Buf + 8, PltData[2] | ((Offset >> 12) & 0xff));
203
18
  write32le(Buf + 12, PltData[3] | (Offset & 0xfff));
204
18
  memcpy(Buf + 16, TrapInstr.data(), 4); // Pad to 32-byte boundary
205
18
  memcpy(Buf + 20, TrapInstr.data(), 4);
206
18
  memcpy(Buf + 24, TrapInstr.data(), 4);
207
18
  memcpy(Buf + 28, TrapInstr.data(), 4);
208
18
}
209
210
20
void ARM::addPltHeaderSymbols(InputSection &IS) const {
211
20
  addSyntheticLocal("$a", STT_NOTYPE, 0, 0, IS);
212
20
  addSyntheticLocal("$d", STT_NOTYPE, 16, 0, IS);
213
20
}
214
215
// Long form PLT entries that do not have any restrictions on the displacement
216
// of the .plt from the .plt.got.
217
static void writePltLong(uint8_t *Buf, uint64_t GotPltEntryAddr,
218
                         uint64_t PltEntryAddr, int32_t Index,
219
4
                         unsigned RelOff) {
220
4
  const uint8_t PltData[] = {
221
4
      0x04, 0xc0, 0x9f, 0xe5, //     ldr ip, L2
222
4
      0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc
223
4
      0x00, 0xf0, 0x9c, 0xe5, //     ldr pc, [ip]
224
4
      0x00, 0x00, 0x00, 0x00, // L2: .word   Offset(&(.plt.got) - L1 - 8
225
4
  };
226
4
  memcpy(Buf, PltData, sizeof(PltData));
227
4
  uint64_t L1 = PltEntryAddr + 4;
228
4
  write32le(Buf + 12, GotPltEntryAddr - L1 - 8);
229
4
}
230
231
// The default PLT entries require the .plt.got to be within 128 Mb of the
232
// .plt in the positive direction.
233
void ARM::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
234
                   uint64_t PltEntryAddr, int32_t Index,
235
51
                   unsigned RelOff) const {
236
51
  // The PLT entry is similar to the example given in Appendix A of ELF for
237
51
  // the Arm Architecture. Instead of using the Group Relocations to find the
238
51
  // optimal rotation for the 8-bit immediate used in the add instructions we
239
51
  // hard code the most compact rotations for simplicity. This saves a load
240
51
  // instruction over the long plt sequences.
241
51
  const uint32_t PltData[] = {
242
51
      0xe28fc600, // L1: add ip, pc,  #0x0NN00000  Offset(&(.plt.got) - L1 - 8
243
51
      0xe28cca00, //     add ip, ip,  #0x000NN000  Offset(&(.plt.got) - L1 - 8
244
51
      0xe5bcf000, //     ldr pc, [ip, #0x00000NNN] Offset(&(.plt.got) - L1 - 8
245
51
  };
246
51
247
51
  uint64_t Offset = GotPltEntryAddr - PltEntryAddr - 8;
248
51
  if (!llvm::isUInt<27>(Offset)) {
249
4
    // We cannot encode the Offset, use the long form.
250
4
    writePltLong(Buf, GotPltEntryAddr, PltEntryAddr, Index, RelOff);
251
4
    return;
252
4
  }
253
47
  write32le(Buf + 0, PltData[0] | ((Offset >> 20) & 0xff));
254
47
  write32le(Buf + 4, PltData[1] | ((Offset >> 12) & 0xff));
255
47
  write32le(Buf + 8, PltData[2] | (Offset & 0xfff));
256
47
  memcpy(Buf + 12, TrapInstr.data(), 4); // Pad to 16-byte boundary
257
47
}
258
259
51
void ARM::addPltSymbols(InputSection &IS, uint64_t Off) const {
260
51
  addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS);
261
51
  addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS);
262
51
}
263
264
bool ARM::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
265
463
                     uint64_t BranchAddr, const Symbol &S) const {
266
463
  // If S is an undefined weak symbol and does not have a PLT entry then it
267
463
  // will be resolved as a branch to the next instruction.
268
463
  if (S.isUndefWeak() && 
!S.isInPlt()18
)
269
16
    return false;
270
447
  // A state change from ARM to Thumb and vice versa must go through an
271
447
  // interworking thunk if the relocation type is not R_ARM_CALL or
272
447
  // R_ARM_THM_CALL.
273
447
  switch (Type) {
274
447
  case R_ARM_PC24:
275
69
  case R_ARM_PLT32:
276
69
  case R_ARM_JUMP24:
277
69
    // Source is ARM, all PLT entries are ARM so no interworking required.
278
69
    // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
279
69
    if (Expr == R_PC && 
((S.getVA() & 1) == 1)44
)
280
16
      return true;
281
53
    LLVM_FALLTHROUGH;
282
146
  case R_ARM_CALL: {
283
146
    uint64_t Dst = (Expr == R_PLT_PC) ? 
S.getPltVA()54
:
S.getVA()92
;
284
146
    return !inBranchRange(Type, BranchAddr, Dst);
285
53
  }
286
53
  case R_ARM_THM_JUMP19:
287
49
  case R_ARM_THM_JUMP24:
288
49
    // Source is Thumb, all PLT entries are ARM so interworking is required.
289
49
    // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
290
49
    if (Expr == R_PLT_PC || 
((S.getVA() & 1) == 0)36
)
291
31
      return true;
292
18
    LLVM_FALLTHROUGH;
293
154
  case R_ARM_THM_CALL: {
294
154
    uint64_t Dst = (Expr == R_PLT_PC) ? 
S.getPltVA()12
:
S.getVA()142
;
295
154
    return !inBranchRange(Type, BranchAddr, Dst);
296
100
  }
297
100
  }
298
100
  return false;
299
100
}
300
301
296
uint32_t ARM::getThunkSectionSpacing() const {
302
296
  // The placing of pre-created ThunkSections is controlled by the value
303
296
  // ThunkSectionSpacing returned by getThunkSectionSpacing(). The aim is to
304
296
  // place the ThunkSection such that all branches from the InputSections
305
296
  // prior to the ThunkSection can reach a Thunk placed at the end of the
306
296
  // ThunkSection. Graphically:
307
296
  // | up to ThunkSectionSpacing .text input sections |
308
296
  // | ThunkSection                                   |
309
296
  // | up to ThunkSectionSpacing .text input sections |
310
296
  // | ThunkSection                                   |
311
296
312
296
  // Pre-created ThunkSections are spaced roughly 16MiB apart on ARMv7. This
313
296
  // is to match the most common expected case of a Thumb 2 encoded BL, BLX or
314
296
  // B.W:
315
296
  // ARM B, BL, BLX range +/- 32MiB
316
296
  // Thumb B.W, BL, BLX range +/- 16MiB
317
296
  // Thumb B<cc>.W range +/- 1MiB
318
296
  // If a branch cannot reach a pre-created ThunkSection a new one will be
319
296
  // created so we can handle the rare cases of a Thumb 2 conditional branch.
320
296
  // We intentionally use a lower size for ThunkSectionSpacing than the maximum
321
296
  // branch range so the end of the ThunkSection is more likely to be within
322
296
  // range of the branch instruction that is furthest away. The value we shorten
323
296
  // ThunkSectionSpacing by is set conservatively to allow us to create 16,384
324
296
  // 12 byte Thunks at any offset in a ThunkSection without risk of a branch to
325
296
  // one of the Thunks going out of range.
326
296
327
296
  // On Arm the ThunkSectionSpacing depends on the range of the Thumb Branch
328
296
  // range. On earlier Architectures such as ARMv4, ARMv5 and ARMv6 (except
329
296
  // ARMv6T2) the range is +/- 4MiB.
330
296
331
296
  return (Config->ARMJ1J2BranchEncoding) ? 
0x1000000 - 0x3000098
332
296
                                         : 
0x400000 - 0x7500198
;
333
296
}
334
335
609
bool ARM::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
336
609
  uint64_t Range;
337
609
  uint64_t InstrSize;
338
609
339
609
  switch (Type) {
340
609
  case R_ARM_PC24:
341
207
  case R_ARM_PLT32:
342
207
  case R_ARM_JUMP24:
343
207
  case R_ARM_CALL:
344
207
    Range = 0x2000000;
345
207
    InstrSize = 4;
346
207
    break;
347
207
  case R_ARM_THM_JUMP19:
348
56
    Range = 0x100000;
349
56
    InstrSize = 2;
350
56
    break;
351
346
  case R_ARM_THM_JUMP24:
352
346
  case R_ARM_THM_CALL:
353
346
    Range = Config->ARMJ1J2BranchEncoding ? 
0x1000000317
:
0x40000029
;
354
346
    InstrSize = 2;
355
346
    break;
356
346
  default:
357
0
    return true;
358
609
  }
359
609
  // PC at Src is 2 instructions ahead, immediate of branch is signed
360
609
  if (Src > Dst)
361
196
    Range -= 2 * InstrSize;
362
413
  else
363
413
    Range += InstrSize;
364
609
365
609
  if ((Dst & 0x1) == 0)
366
308
    // Destination is ARM, if ARM caller then Src is already 4-byte aligned.
367
308
    // If Thumb Caller (BLX) the Src address has bottom 2 bits cleared to ensure
368
308
    // destination will be 4 byte aligned.
369
308
    Src &= ~0x3;
370
301
  else
371
301
    // Bit 0 == 1 denotes Thumb state, it is not part of the range
372
301
    Dst &= ~0x1;
373
609
374
609
  uint64_t Distance = (Src > Dst) ? 
Src - Dst195
:
Dst - Src414
;
375
609
  return Distance <= Range;
376
609
}
377
378
814
void ARM::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
379
814
  switch (Type) {
380
814
  case R_ARM_ABS32:
381
190
  case R_ARM_BASE_PREL:
382
190
  case R_ARM_GLOB_DAT:
383
190
  case R_ARM_GOTOFF32:
384
190
  case R_ARM_GOT_BREL:
385
190
  case R_ARM_GOT_PREL:
386
190
  case R_ARM_REL32:
387
190
  case R_ARM_RELATIVE:
388
190
  case R_ARM_SBREL32:
389
190
  case R_ARM_TARGET1:
390
190
  case R_ARM_TARGET2:
391
190
  case R_ARM_TLS_GD32:
392
190
  case R_ARM_TLS_IE32:
393
190
  case R_ARM_TLS_LDM32:
394
190
  case R_ARM_TLS_LDO32:
395
190
  case R_ARM_TLS_LE32:
396
190
  case R_ARM_TLS_TPOFF32:
397
190
  case R_ARM_TLS_DTPOFF32:
398
190
    write32le(Loc, Val);
399
190
    break;
400
190
  case R_ARM_TLS_DTPMOD32:
401
6
    write32le(Loc, 1);
402
6
    break;
403
190
  case R_ARM_PREL31:
404
109
    checkInt(Loc, Val, 31, Type);
405
109
    write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000));
406
109
    break;
407
190
  case R_ARM_CALL:
408
74
    // R_ARM_CALL is used for BL and BLX instructions, depending on the
409
74
    // value of bit 0 of Val, we must select a BL or BLX instruction
410
74
    if (Val & 1) {
411
24
      // If bit 0 of Val is 1 the target is Thumb, we must select a BLX.
412
24
      // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
413
24
      checkInt(Loc, Val, 26, Type);
414
24
      write32le(Loc, 0xfa000000 |                    // opcode
415
24
                         ((Val & 2) << 23) |         // H
416
24
                         ((Val >> 2) & 0x00ffffff)); // imm24
417
24
      break;
418
24
    }
419
50
    if ((read32le(Loc) & 0xfe000000) == 0xfa000000)
420
4
      // BLX (always unconditional) instruction to an ARM Target, select an
421
4
      // unconditional BL.
422
4
      write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff));
423
50
    // fall through as BL encoding is shared with B
424
50
    LLVM_FALLTHROUGH;
425
108
  case R_ARM_JUMP24:
426
108
  case R_ARM_PC24:
427
108
  case R_ARM_PLT32:
428
108
    checkInt(Loc, Val, 26, Type);
429
108
    write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff));
430
108
    break;
431
108
  case R_ARM_THM_JUMP11:
432
5
    checkInt(Loc, Val, 12, Type);
433
5
    write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff));
434
5
    break;
435
108
  case R_ARM_THM_JUMP19:
436
21
    // Encoding T3: Val = S:J2:J1:imm6:imm11:0
437
21
    checkInt(Loc, Val, 21, Type);
438
21
    write16le(Loc,
439
21
              (read16le(Loc) & 0xfbc0) |   // opcode cond
440
21
                  ((Val >> 10) & 0x0400) | // S
441
21
                  ((Val >> 12) & 0x003f)); // imm6
442
21
    write16le(Loc + 2,
443
21
              0x8000 |                    // opcode
444
21
                  ((Val >> 8) & 0x0800) | // J2
445
21
                  ((Val >> 5) & 0x2000) | // J1
446
21
                  ((Val >> 1) & 0x07ff)); // imm11
447
21
    break;
448
108
  case R_ARM_THM_CALL:
449
107
    // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
450
107
    // value of bit 0 of Val, we must select a BL or BLX instruction
451
107
    if ((Val & 1) == 0) {
452
19
      // Ensure BLX destination is 4-byte aligned. As BLX instruction may
453
19
      // only be two byte aligned. This must be done before overflow check
454
19
      Val = alignTo(Val, 4);
455
19
    }
456
107
    // Bit 12 is 0 for BLX, 1 for BL
457
107
    write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12);
458
107
    if (!Config->ARMJ1J2BranchEncoding) {
459
20
      // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
460
20
      // different encoding rules and range due to J1 and J2 always being 1.
461
20
      checkInt(Loc, Val, 23, Type);
462
20
      write16le(Loc,
463
20
                0xf000 |                     // opcode
464
20
                    ((Val >> 12) & 0x07ff)); // imm11
465
20
      write16le(Loc + 2,
466
20
                (read16le(Loc + 2) & 0xd000) | // opcode
467
20
                    0x2800 |                   // J1 == J2 == 1
468
20
                    ((Val >> 1) & 0x07ff));    // imm11
469
20
      break;
470
20
    }
471
87
    // Fall through as rest of encoding is the same as B.W
472
87
    LLVM_FALLTHROUGH;
473
138
  case R_ARM_THM_JUMP24:
474
138
    // Encoding B  T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
475
138
    checkInt(Loc, Val, 25, Type);
476
138
    write16le(Loc,
477
138
              0xf000 |                     // opcode
478
138
                  ((Val >> 14) & 0x0400) | // S
479
138
                  ((Val >> 12) & 0x03ff)); // imm10
480
138
    write16le(Loc + 2,
481
138
              (read16le(Loc + 2) & 0xd000) |                  // opcode
482
138
                  (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1
483
138
                  (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2
484
138
                  ((Val >> 1) & 0x07ff));                     // imm11
485
138
    break;
486
87
  case R_ARM_MOVW_ABS_NC:
487
34
  case R_ARM_MOVW_PREL_NC:
488
34
    write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) |
489
34
                       (Val & 0x0fff));
490
34
    break;
491
34
  case R_ARM_MOVT_ABS:
492
34
  case R_ARM_MOVT_PREL:
493
34
    write32le(Loc, (read32le(Loc) & ~0x000f0fff) |
494
34
                       (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff));
495
34
    break;
496
63
  case R_ARM_THM_MOVT_ABS:
497
63
  case R_ARM_THM_MOVT_PREL:
498
63
    // Encoding T1: A = imm4:i:imm3:imm8
499
63
    write16le(Loc,
500
63
              0xf2c0 |                     // opcode
501
63
                  ((Val >> 17) & 0x0400) | // i
502
63
                  ((Val >> 28) & 0x000f)); // imm4
503
63
    write16le(Loc + 2,
504
63
              (read16le(Loc + 2) & 0x8f00) | // opcode
505
63
                  ((Val >> 12) & 0x7000) |   // imm3
506
63
                  ((Val >> 16) & 0x00ff));   // imm8
507
63
    break;
508
63
  case R_ARM_THM_MOVW_ABS_NC:
509
63
  case R_ARM_THM_MOVW_PREL_NC:
510
63
    // Encoding T3: A = imm4:i:imm3:imm8
511
63
    write16le(Loc,
512
63
              0xf240 |                     // opcode
513
63
                  ((Val >> 1) & 0x0400) |  // i
514
63
                  ((Val >> 12) & 0x000f)); // imm4
515
63
    write16le(Loc + 2,
516
63
              (read16le(Loc + 2) & 0x8f00) | // opcode
517
63
                  ((Val << 4) & 0x7000) |    // imm3
518
63
                  (Val & 0x00ff));           // imm8
519
63
    break;
520
63
  default:
521
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
522
814
  }
523
814
}
524
525
618
int64_t ARM::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
526
618
  switch (Type) {
527
618
  default:
528
4
    return 0;
529
618
  case R_ARM_ABS32:
530
172
  case R_ARM_BASE_PREL:
531
172
  case R_ARM_GOTOFF32:
532
172
  case R_ARM_GOT_BREL:
533
172
  case R_ARM_GOT_PREL:
534
172
  case R_ARM_REL32:
535
172
  case R_ARM_TARGET1:
536
172
  case R_ARM_TARGET2:
537
172
  case R_ARM_TLS_GD32:
538
172
  case R_ARM_TLS_LDM32:
539
172
  case R_ARM_TLS_LDO32:
540
172
  case R_ARM_TLS_IE32:
541
172
  case R_ARM_TLS_LE32:
542
172
    return SignExtend64<32>(read32le(Buf));
543
172
  case R_ARM_PREL31:
544
101
    return SignExtend64<31>(read32le(Buf));
545
172
  case R_ARM_CALL:
546
128
  case R_ARM_JUMP24:
547
128
  case R_ARM_PC24:
548
128
  case R_ARM_PLT32:
549
128
    return SignExtend64<26>(read32le(Buf) << 2);
550
128
  case R_ARM_THM_JUMP11:
551
5
    return SignExtend64<12>(read16le(Buf) << 1);
552
128
  case R_ARM_THM_JUMP19: {
553
21
    // Encoding T3: A = S:J2:J1:imm10:imm6:0
554
21
    uint16_t Hi = read16le(Buf);
555
21
    uint16_t Lo = read16le(Buf + 2);
556
21
    return SignExtend64<20>(((Hi & 0x0400) << 10) | // S
557
21
                            ((Lo & 0x0800) << 8) |  // J2
558
21
                            ((Lo & 0x2000) << 5) |  // J1
559
21
                            ((Hi & 0x003f) << 12) | // imm6
560
21
                            ((Lo & 0x07ff) << 1));  // imm11:0
561
128
  }
562
128
  case R_ARM_THM_CALL:
563
107
    if (!Config->ARMJ1J2BranchEncoding) {
564
20
      // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
565
20
      // different encoding rules and range due to J1 and J2 always being 1.
566
20
      uint16_t Hi = read16le(Buf);
567
20
      uint16_t Lo = read16le(Buf + 2);
568
20
      return SignExtend64<22>(((Hi & 0x7ff) << 12) | // imm11
569
20
                              ((Lo & 0x7ff) << 1));  // imm11:0
570
20
      
break0
;
571
87
    }
572
87
    LLVM_FALLTHROUGH;
573
117
  case R_ARM_THM_JUMP24: {
574
117
    // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
575
117
    // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
576
117
    uint16_t Hi = read16le(Buf);
577
117
    uint16_t Lo = read16le(Buf + 2);
578
117
    return SignExtend64<24>(((Hi & 0x0400) << 14) |                    // S
579
117
                            (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1
580
117
                            (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2
581
117
                            ((Hi & 0x003ff) << 12) |                   // imm0
582
117
                            ((Lo & 0x007ff) << 1)); // imm11:0
583
87
  }
584
87
  // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and
585
87
  // MOVT is in the range -32768 <= A < 32768
586
87
  case R_ARM_MOVW_ABS_NC:
587
28
  case R_ARM_MOVT_ABS:
588
28
  case R_ARM_MOVW_PREL_NC:
589
28
  case R_ARM_MOVT_PREL: {
590
28
    uint64_t Val = read32le(Buf) & 0x000f0fff;
591
28
    return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff));
592
28
  }
593
28
  case R_ARM_THM_MOVW_ABS_NC:
594
22
  case R_ARM_THM_MOVT_ABS:
595
22
  case R_ARM_THM_MOVW_PREL_NC:
596
22
  case R_ARM_THM_MOVT_PREL: {
597
22
    // Encoding T3: A = imm4:i:imm3:imm8
598
22
    uint16_t Hi = read16le(Buf);
599
22
    uint16_t Lo = read16le(Buf + 2);
600
22
    return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4
601
22
                            ((Hi & 0x0400) << 1) |  // i
602
22
                            ((Lo & 0x7000) >> 4) |  // imm3
603
22
                            (Lo & 0x00ff));         // imm8
604
22
  }
605
618
  }
606
618
}
607
608
155
TargetInfo *elf::getARMTargetInfo() {
609
155
  static ARM Target;
610
155
  return &Target;
611
155
}