Coverage Report

Created: 2018-08-19 21:11

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/ARM.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- ARM.cpp ------------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#include "InputFiles.h"
11
#include "Symbols.h"
12
#include "SyntheticSections.h"
13
#include "Target.h"
14
#include "Thunks.h"
15
#include "lld/Common/ErrorHandler.h"
16
#include "llvm/Object/ELF.h"
17
#include "llvm/Support/Endian.h"
18
19
using namespace llvm;
20
using namespace llvm::support::endian;
21
using namespace llvm::ELF;
22
using namespace lld;
23
using namespace lld::elf;
24
25
namespace {
26
class ARM final : public TargetInfo {
27
public:
28
  ARM();
29
  uint32_t calcEFlags() const override;
30
  RelExpr getRelExpr(RelType Type, const Symbol &S,
31
                     const uint8_t *Loc) const override;
32
  RelType getDynRel(RelType Type) const override;
33
  int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
34
  void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
35
  void writeIgotPlt(uint8_t *Buf, const Symbol &S) const override;
36
  void writePltHeader(uint8_t *Buf) const override;
37
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
38
                int32_t Index, unsigned RelOff) const override;
39
  void addPltSymbols(InputSection &IS, uint64_t Off) const override;
40
  void addPltHeaderSymbols(InputSection &ISD) const override;
41
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
42
                  uint64_t BranchAddr, const Symbol &S) const override;
43
  bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
44
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
45
};
46
} // namespace
47
48
138
ARM::ARM() {
49
138
  CopyRel = R_ARM_COPY;
50
138
  RelativeRel = R_ARM_RELATIVE;
51
138
  IRelativeRel = R_ARM_IRELATIVE;
52
138
  GotRel = R_ARM_GLOB_DAT;
53
138
  PltRel = R_ARM_JUMP_SLOT;
54
138
  TlsGotRel = R_ARM_TLS_TPOFF32;
55
138
  TlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
56
138
  TlsOffsetRel = R_ARM_TLS_DTPOFF32;
57
138
  GotBaseSymInGotPlt = false;
58
138
  GotEntrySize = 4;
59
138
  GotPltEntrySize = 4;
60
138
  PltEntrySize = 16;
61
138
  PltHeaderSize = 32;
62
138
  TrapInstr = 0xd4d4d4d4;
63
138
  // ARM uses Variant 1 TLS
64
138
  TcbSize = 8;
65
138
  NeedsThunks = true;
66
138
67
138
  // The placing of pre-created ThunkSections is controlled by the
68
138
  // ThunkSectionSpacing parameter. The aim is to place the
69
138
  // ThunkSection such that all branches from the InputSections prior to the
70
138
  // ThunkSection can reach a Thunk placed at the end of the ThunkSection.
71
138
  // Graphically:
72
138
  // | up to ThunkSectionSpacing .text input sections |
73
138
  // | ThunkSection                                   |
74
138
  // | up to ThunkSectionSpacing .text input sections |
75
138
  // | ThunkSection                                   |
76
138
77
138
  // Pre-created ThunkSections are spaced roughly 16MiB apart on ARM. This is to
78
138
  // match the most common expected case of a Thumb 2 encoded BL, BLX or B.W
79
138
  // ARM B, BL, BLX range +/- 32MiB
80
138
  // Thumb B.W, BL, BLX range +/- 16MiB
81
138
  // Thumb B<cc>.W range +/- 1MiB
82
138
  // If a branch cannot reach a pre-created ThunkSection a new one will be
83
138
  // created so we can handle the rare cases of a Thumb 2 conditional branch.
84
138
  // We intentionally use a lower size for ThunkSectionSpacing than the maximum
85
138
  // branch range so the end of the ThunkSection is more likely to be within
86
138
  // range of the branch instruction that is furthest away. The value we shorten
87
138
  // ThunkSectionSpacing by is set conservatively to allow us to create 16,384
88
138
  // 12 byte Thunks at any offset in a ThunkSection without risk of a branch to
89
138
  // one of the Thunks going out of range.
90
138
91
138
  // FIXME: lld assumes that the Thumb BL and BLX encoding permits the J1 and
92
138
  // J2 bits to be used to extend the branch range. On earlier Architectures
93
138
  // such as ARMv4, ARMv5 and ARMv6 (except ARMv6T2) the range is +/- 4MiB. If
94
138
  // support for the earlier encodings is added then when they are used the
95
138
  // ThunkSectionSpacing will need lowering.
96
138
  ThunkSectionSpacing = 0x1000000 - 0x30000;
97
138
}
98
99
131
uint32_t ARM::calcEFlags() const {
100
131
  // The ABIFloatType is used by loaders to detect the floating point calling
101
131
  // convention.
102
131
  uint32_t ABIFloatType = 0;
103
131
  if (Config->ARMVFPArgs == ARMVFPArgKind::Base ||
104
131
      
Config->ARMVFPArgs == ARMVFPArgKind::Default129
)
105
127
    ABIFloatType = EF_ARM_ABI_FLOAT_SOFT;
106
4
  else if (Config->ARMVFPArgs == ARMVFPArgKind::VFP)
107
2
    ABIFloatType = EF_ARM_ABI_FLOAT_HARD;
108
131
109
131
  // We don't currently use any features incompatible with EF_ARM_EABI_VER5,
110
131
  // but we don't have any firm guarantees of conformance. Linux AArch64
111
131
  // kernels (as of 2016) require an EABI version to be set.
112
131
  return EF_ARM_EABI_VER5 | ABIFloatType;
113
131
}
114
115
RelExpr ARM::getRelExpr(RelType Type, const Symbol &S,
116
588
                        const uint8_t *Loc) const {
117
588
  switch (Type) {
118
588
  case R_ARM_THM_JUMP11:
119
5
    return R_PC;
120
588
  case R_ARM_CALL:
121
346
  case R_ARM_JUMP24:
122
346
  case R_ARM_PC24:
123
346
  case R_ARM_PLT32:
124
346
  case R_ARM_PREL31:
125
346
  case R_ARM_THM_JUMP19:
126
346
  case R_ARM_THM_JUMP24:
127
346
  case R_ARM_THM_CALL:
128
346
    return R_PLT_PC;
129
346
  case R_ARM_GOTOFF32:
130
3
    // (S + A) - GOT_ORG
131
3
    return R_GOTREL;
132
346
  case R_ARM_GOT_BREL:
133
5
    // GOT(S) + A - GOT_ORG
134
5
    return R_GOT_OFF;
135
346
  case R_ARM_GOT_PREL:
136
6
  case R_ARM_TLS_IE32:
137
6
    // GOT(S) + A - P
138
6
    return R_GOT_PC;
139
6
  case R_ARM_SBREL32:
140
4
    return R_ARM_SBREL;
141
6
  case R_ARM_TARGET1:
142
4
    return Config->Target1Rel ? 
R_PC2
:
R_ABS2
;
143
6
  case R_ARM_TARGET2:
144
4
    if (Config->Target2 == Target2Policy::Rel)
145
1
      return R_PC;
146
3
    if (Config->Target2 == Target2Policy::Abs)
147
1
      return R_ABS;
148
2
    return R_GOT_PC;
149
14
  case R_ARM_TLS_GD32:
150
14
    return R_TLSGD_PC;
151
2
  case R_ARM_TLS_LDM32:
152
2
    return R_TLSLD_PC;
153
2
  case R_ARM_BASE_PREL:
154
0
    // B(S) + A - P
155
0
    // FIXME: currently B(S) assumed to be .got, this may not hold for all
156
0
    // platforms.
157
0
    return R_GOTONLY_PC;
158
27
  case R_ARM_MOVW_PREL_NC:
159
27
  case R_ARM_MOVT_PREL:
160
27
  case R_ARM_REL32:
161
27
  case R_ARM_THM_MOVW_PREL_NC:
162
27
  case R_ARM_THM_MOVT_PREL:
163
27
    return R_PC;
164
27
  case R_ARM_NONE:
165
13
    return R_NONE;
166
27
  case R_ARM_TLS_LE32:
167
3
    return R_TLS;
168
152
  default:
169
152
    return R_ABS;
170
588
  }
171
588
}
172
173
7
RelType ARM::getDynRel(RelType Type) const {
174
7
  if ((Type == R_ARM_ABS32) || 
(0
Type == R_ARM_TARGET10
&&
!Config->Target1Rel0
))
175
7
    return R_ARM_ABS32;
176
0
  return R_ARM_NONE;
177
0
}
178
179
43
void ARM::writeGotPlt(uint8_t *Buf, const Symbol &) const {
180
43
  write32le(Buf, InX::Plt->getVA());
181
43
}
182
183
6
void ARM::writeIgotPlt(uint8_t *Buf, const Symbol &S) const {
184
6
  // An ARM entry is the address of the ifunc resolver function.
185
6
  write32le(Buf, S.getVA());
186
6
}
187
188
// Long form PLT Header that does not have any restrictions on the displacement
189
// of the .plt from the .plt.got.
190
2
static void writePltHeaderLong(uint8_t *Buf) {
191
2
  const uint8_t PltData[] = {
192
2
      0x04, 0xe0, 0x2d, 0xe5, //     str lr, [sp,#-4]!
193
2
      0x04, 0xe0, 0x9f, 0xe5, //     ldr lr, L2
194
2
      0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr
195
2
      0x08, 0xf0, 0xbe, 0xe5, //     ldr pc, [lr, #8]
196
2
      0x00, 0x00, 0x00, 0x00, // L2: .word   &(.got.plt) - L1 - 8
197
2
      0xd4, 0xd4, 0xd4, 0xd4, //     Pad to 32-byte boundary
198
2
      0xd4, 0xd4, 0xd4, 0xd4, //     Pad to 32-byte boundary
199
2
      0xd4, 0xd4, 0xd4, 0xd4};
200
2
  memcpy(Buf, PltData, sizeof(PltData));
201
2
  uint64_t GotPlt = InX::GotPlt->getVA();
202
2
  uint64_t L1 = InX::Plt->getVA() + 8;
203
2
  write32le(Buf + 16, GotPlt - L1 - 8);
204
2
}
205
206
// The default PLT header requires the .plt.got to be within 128 Mb of the
207
// .plt in the positive direction.
208
19
void ARM::writePltHeader(uint8_t *Buf) const {
209
19
  // Use a similar sequence to that in writePlt(), the difference is the calling
210
19
  // conventions mean we use lr instead of ip. The PLT entry is responsible for
211
19
  // saving lr on the stack, the dynamic loader is responsible for reloading
212
19
  // it.
213
19
  const uint32_t PltData[] = {
214
19
      0xe52de004, // L1: str lr, [sp,#-4]!
215
19
      0xe28fe600, //     add lr, pc,  #0x0NN00000 &(.got.plt - L1 - 4)
216
19
      0xe28eea00, //     add lr, lr,  #0x000NN000 &(.got.plt - L1 - 4)
217
19
      0xe5bef000, //     ldr pc, [lr, #0x00000NNN] &(.got.plt -L1 - 4)
218
19
  };
219
19
220
19
  uint64_t Offset = InX::GotPlt->getVA() - InX::Plt->getVA() - 4;
221
19
  if (!llvm::isUInt<27>(Offset)) {
222
2
    // We cannot encode the Offset, use the long form.
223
2
    writePltHeaderLong(Buf);
224
2
    return;
225
2
  }
226
17
  write32le(Buf + 0, PltData[0]);
227
17
  write32le(Buf + 4, PltData[1] | ((Offset >> 20) & 0xff));
228
17
  write32le(Buf + 8, PltData[2] | ((Offset >> 12) & 0xff));
229
17
  write32le(Buf + 12, PltData[3] | (Offset & 0xfff));
230
17
  write32le(Buf + 16, TrapInstr); // Pad to 32-byte boundary
231
17
  write32le(Buf + 20, TrapInstr);
232
17
  write32le(Buf + 24, TrapInstr);
233
17
  write32le(Buf + 28, TrapInstr);
234
17
}
235
236
19
void ARM::addPltHeaderSymbols(InputSection &IS) const {
237
19
  addSyntheticLocal("$a", STT_NOTYPE, 0, 0, IS);
238
19
  addSyntheticLocal("$d", STT_NOTYPE, 16, 0, IS);
239
19
}
240
241
// Long form PLT entries that do not have any restrictions on the displacement
242
// of the .plt from the .plt.got.
243
static void writePltLong(uint8_t *Buf, uint64_t GotPltEntryAddr,
244
                         uint64_t PltEntryAddr, int32_t Index,
245
4
                         unsigned RelOff) {
246
4
  const uint8_t PltData[] = {
247
4
      0x04, 0xc0, 0x9f, 0xe5, //     ldr ip, L2
248
4
      0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc
249
4
      0x00, 0xf0, 0x9c, 0xe5, //     ldr pc, [ip]
250
4
      0x00, 0x00, 0x00, 0x00, // L2: .word   Offset(&(.plt.got) - L1 - 8
251
4
  };
252
4
  memcpy(Buf, PltData, sizeof(PltData));
253
4
  uint64_t L1 = PltEntryAddr + 4;
254
4
  write32le(Buf + 12, GotPltEntryAddr - L1 - 8);
255
4
}
256
257
// The default PLT entries require the .plt.got to be within 128 Mb of the
258
// .plt in the positive direction.
259
void ARM::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
260
                   uint64_t PltEntryAddr, int32_t Index,
261
49
                   unsigned RelOff) const {
262
49
  // The PLT entry is similar to the example given in Appendix A of ELF for
263
49
  // the Arm Architecture. Instead of using the Group Relocations to find the
264
49
  // optimal rotation for the 8-bit immediate used in the add instructions we
265
49
  // hard code the most compact rotations for simplicity. This saves a load
266
49
  // instruction over the long plt sequences.
267
49
  const uint32_t PltData[] = {
268
49
      0xe28fc600, // L1: add ip, pc,  #0x0NN00000  Offset(&(.plt.got) - L1 - 8
269
49
      0xe28cca00, //     add ip, ip,  #0x000NN000  Offset(&(.plt.got) - L1 - 8
270
49
      0xe5bcf000, //     ldr pc, [ip, #0x00000NNN] Offset(&(.plt.got) - L1 - 8
271
49
  };
272
49
273
49
  uint64_t Offset = GotPltEntryAddr - PltEntryAddr - 8;
274
49
  if (!llvm::isUInt<27>(Offset)) {
275
4
    // We cannot encode the Offset, use the long form.
276
4
    writePltLong(Buf, GotPltEntryAddr, PltEntryAddr, Index, RelOff);
277
4
    return;
278
4
  }
279
45
  write32le(Buf + 0, PltData[0] | ((Offset >> 20) & 0xff));
280
45
  write32le(Buf + 4, PltData[1] | ((Offset >> 12) & 0xff));
281
45
  write32le(Buf + 8, PltData[2] | (Offset & 0xfff));
282
45
  write32le(Buf + 12, TrapInstr); // Pad to 16-byte boundary
283
45
}
284
285
49
void ARM::addPltSymbols(InputSection &IS, uint64_t Off) const {
286
49
  addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS);
287
49
  addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS);
288
49
}
289
290
bool ARM::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
291
425
                     uint64_t BranchAddr, const Symbol &S) const {
292
425
  // If S is an undefined weak symbol and does not have a PLT entry then it
293
425
  // will be resolved as a branch to the next instruction.
294
425
  if (S.isUndefWeak() && 
!S.isInPlt()18
)
295
16
    return false;
296
409
  // A state change from ARM to Thumb and vice versa must go through an
297
409
  // interworking thunk if the relocation type is not R_ARM_CALL or
298
409
  // R_ARM_THM_CALL.
299
409
  switch (Type) {
300
409
  case R_ARM_PC24:
301
67
  case R_ARM_PLT32:
302
67
  case R_ARM_JUMP24:
303
67
    // Source is ARM, all PLT entries are ARM so no interworking required.
304
67
    // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
305
67
    if (Expr == R_PC && 
((S.getVA() & 1) == 1)42
)
306
14
      return true;
307
53
    LLVM_FALLTHROUGH;
308
133
  case R_ARM_CALL: {
309
133
    uint64_t Dst = (Expr == R_PLT_PC) ? 
S.getPltVA()52
:
S.getVA()81
;
310
133
    return !inBranchRange(Type, BranchAddr, Dst);
311
53
  }
312
53
  case R_ARM_THM_JUMP19:
313
48
  case R_ARM_THM_JUMP24:
314
48
    // Source is Thumb, all PLT entries are ARM so interworking is required.
315
48
    // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
316
48
    if (Expr == R_PLT_PC || 
((S.getVA() & 1) == 0)35
)
317
31
      return true;
318
17
    LLVM_FALLTHROUGH;
319
133
  case R_ARM_THM_CALL: {
320
133
    uint64_t Dst = (Expr == R_PLT_PC) ? 
S.getPltVA()12
:
S.getVA()121
;
321
133
    return !inBranchRange(Type, BranchAddr, Dst);
322
98
  }
323
98
  }
324
98
  return false;
325
98
}
326
327
533
bool ARM::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
328
533
  uint64_t Range;
329
533
  uint64_t InstrSize;
330
533
331
533
  switch (Type) {
332
533
  case R_ARM_PC24:
333
186
  case R_ARM_PLT32:
334
186
  case R_ARM_JUMP24:
335
186
  case R_ARM_CALL:
336
186
    Range = 0x2000000;
337
186
    InstrSize = 4;
338
186
    break;
339
186
  case R_ARM_THM_JUMP19:
340
51
    Range = 0x100000;
341
51
    InstrSize = 2;
342
51
    break;
343
296
  case R_ARM_THM_JUMP24:
344
296
  case R_ARM_THM_CALL:
345
296
    Range = 0x1000000;
346
296
    InstrSize = 2;
347
296
    break;
348
296
  default:
349
0
    return true;
350
533
  }
351
533
  // PC at Src is 2 instructions ahead, immediate of branch is signed
352
533
  if (Src > Dst)
353
181
    Range -= 2 * InstrSize;
354
352
  else
355
352
    Range += InstrSize;
356
533
357
533
  if ((Dst & 0x1) == 0)
358
274
    // Destination is ARM, if ARM caller then Src is already 4-byte aligned.
359
274
    // If Thumb Caller (BLX) the Src address has bottom 2 bits cleared to ensure
360
274
    // destination will be 4 byte aligned.
361
274
    Src &= ~0x3;
362
259
  else
363
259
    // Bit 0 == 1 denotes Thumb state, it is not part of the range
364
259
    Dst &= ~0x1;
365
533
366
533
  uint64_t Distance = (Src > Dst) ? 
Src - Dst180
:
Dst - Src353
;
367
533
  return Distance <= Range;
368
533
}
369
370
765
void ARM::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
371
765
  switch (Type) {
372
765
  case R_ARM_ABS32:
373
182
  case R_ARM_BASE_PREL:
374
182
  case R_ARM_GLOB_DAT:
375
182
  case R_ARM_GOTOFF32:
376
182
  case R_ARM_GOT_BREL:
377
182
  case R_ARM_GOT_PREL:
378
182
  case R_ARM_REL32:
379
182
  case R_ARM_RELATIVE:
380
182
  case R_ARM_SBREL32:
381
182
  case R_ARM_TARGET1:
382
182
  case R_ARM_TARGET2:
383
182
  case R_ARM_TLS_GD32:
384
182
  case R_ARM_TLS_IE32:
385
182
  case R_ARM_TLS_LDM32:
386
182
  case R_ARM_TLS_LDO32:
387
182
  case R_ARM_TLS_LE32:
388
182
  case R_ARM_TLS_TPOFF32:
389
182
  case R_ARM_TLS_DTPOFF32:
390
182
    write32le(Loc, Val);
391
182
    break;
392
182
  case R_ARM_TLS_DTPMOD32:
393
6
    write32le(Loc, 1);
394
6
    break;
395
182
  case R_ARM_PREL31:
396
110
    checkInt(Loc, Val, 31, Type);
397
110
    write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000));
398
110
    break;
399
182
  case R_ARM_CALL:
400
66
    // R_ARM_CALL is used for BL and BLX instructions, depending on the
401
66
    // value of bit 0 of Val, we must select a BL or BLX instruction
402
66
    if (Val & 1) {
403
20
      // If bit 0 of Val is 1 the target is Thumb, we must select a BLX.
404
20
      // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
405
20
      checkInt(Loc, Val, 26, Type);
406
20
      write32le(Loc, 0xfa000000 |                    // opcode
407
20
                         ((Val & 2) << 23) |         // H
408
20
                         ((Val >> 2) & 0x00ffffff)); // imm24
409
20
      break;
410
20
    }
411
46
    if ((read32le(Loc) & 0xfe000000) == 0xfa000000)
412
4
      // BLX (always unconditional) instruction to an ARM Target, select an
413
4
      // unconditional BL.
414
4
      write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff));
415
46
    // fall through as BL encoding is shared with B
416
46
    LLVM_FALLTHROUGH;
417
101
  case R_ARM_JUMP24:
418
101
  case R_ARM_PC24:
419
101
  case R_ARM_PLT32:
420
101
    checkInt(Loc, Val, 26, Type);
421
101
    write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff));
422
101
    break;
423
101
  case R_ARM_THM_JUMP11:
424
5
    checkInt(Loc, Val, 12, Type);
425
5
    write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff));
426
5
    break;
427
101
  case R_ARM_THM_JUMP19:
428
20
    // Encoding T3: Val = S:J2:J1:imm6:imm11:0
429
20
    checkInt(Loc, Val, 21, Type);
430
20
    write16le(Loc,
431
20
              (read16le(Loc) & 0xfbc0) |   // opcode cond
432
20
                  ((Val >> 10) & 0x0400) | // S
433
20
                  ((Val >> 12) & 0x003f)); // imm6
434
20
    write16le(Loc + 2,
435
20
              0x8000 |                    // opcode
436
20
                  ((Val >> 8) & 0x0800) | // J2
437
20
                  ((Val >> 5) & 0x2000) | // J1
438
20
                  ((Val >> 1) & 0x07ff)); // imm11
439
20
    break;
440
101
  case R_ARM_THM_CALL:
441
93
    // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
442
93
    // value of bit 0 of Val, we must select a BL or BLX instruction
443
93
    if ((Val & 1) == 0) {
444
17
      // Ensure BLX destination is 4-byte aligned. As BLX instruction may
445
17
      // only be two byte aligned. This must be done before overflow check
446
17
      Val = alignTo(Val, 4);
447
17
    }
448
93
    // Bit 12 is 0 for BLX, 1 for BL
449
93
    write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12);
450
93
    // Fall through as rest of encoding is the same as B.W
451
93
    LLVM_FALLTHROUGH;
452
143
  case R_ARM_THM_JUMP24:
453
143
    // Encoding B  T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
454
143
    // FIXME: Use of I1 and I2 require v6T2ops
455
143
    checkInt(Loc, Val, 25, Type);
456
143
    write16le(Loc,
457
143
              0xf000 |                     // opcode
458
143
                  ((Val >> 14) & 0x0400) | // S
459
143
                  ((Val >> 12) & 0x03ff)); // imm10
460
143
    write16le(Loc + 2,
461
143
              (read16le(Loc + 2) & 0xd000) |                  // opcode
462
143
                  (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1
463
143
                  (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2
464
143
                  ((Val >> 1) & 0x07ff));                     // imm11
465
143
    break;
466
93
  case R_ARM_MOVW_ABS_NC:
467
32
  case R_ARM_MOVW_PREL_NC:
468
32
    write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) |
469
32
                       (Val & 0x0fff));
470
32
    break;
471
32
  case R_ARM_MOVT_ABS:
472
32
  case R_ARM_MOVT_PREL:
473
32
    checkInt(Loc, Val, 32, Type);
474
32
    write32le(Loc, (read32le(Loc) & ~0x000f0fff) |
475
32
                       (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff));
476
32
    break;
477
57
  case R_ARM_THM_MOVT_ABS:
478
57
  case R_ARM_THM_MOVT_PREL:
479
57
    // Encoding T1: A = imm4:i:imm3:imm8
480
57
    checkInt(Loc, Val, 32, Type);
481
57
    write16le(Loc,
482
57
              0xf2c0 |                     // opcode
483
57
                  ((Val >> 17) & 0x0400) | // i
484
57
                  ((Val >> 28) & 0x000f)); // imm4
485
57
    write16le(Loc + 2,
486
57
              (read16le(Loc + 2) & 0x8f00) | // opcode
487
57
                  ((Val >> 12) & 0x7000) |   // imm3
488
57
                  ((Val >> 16) & 0x00ff));   // imm8
489
57
    break;
490
57
  case R_ARM_THM_MOVW_ABS_NC:
491
57
  case R_ARM_THM_MOVW_PREL_NC:
492
57
    // Encoding T3: A = imm4:i:imm3:imm8
493
57
    write16le(Loc,
494
57
              0xf240 |                     // opcode
495
57
                  ((Val >> 1) & 0x0400) |  // i
496
57
                  ((Val >> 12) & 0x000f)); // imm4
497
57
    write16le(Loc + 2,
498
57
              (read16le(Loc + 2) & 0x8f00) | // opcode
499
57
                  ((Val << 4) & 0x7000) |    // imm3
500
57
                  (Val & 0x00ff));           // imm8
501
57
    break;
502
57
  default:
503
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
504
765
  }
505
765
}
506
507
591
int64_t ARM::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
508
591
  switch (Type) {
509
591
  default:
510
4
    return 0;
511
591
  case R_ARM_ABS32:
512
170
  case R_ARM_BASE_PREL:
513
170
  case R_ARM_GOTOFF32:
514
170
  case R_ARM_GOT_BREL:
515
170
  case R_ARM_GOT_PREL:
516
170
  case R_ARM_REL32:
517
170
  case R_ARM_TARGET1:
518
170
  case R_ARM_TARGET2:
519
170
  case R_ARM_TLS_GD32:
520
170
  case R_ARM_TLS_LDM32:
521
170
  case R_ARM_TLS_LDO32:
522
170
  case R_ARM_TLS_IE32:
523
170
  case R_ARM_TLS_LE32:
524
170
    return SignExtend64<32>(read32le(Buf));
525
170
  case R_ARM_PREL31:
526
101
    return SignExtend64<31>(read32le(Buf));
527
170
  case R_ARM_CALL:
528
118
  case R_ARM_JUMP24:
529
118
  case R_ARM_PC24:
530
118
  case R_ARM_PLT32:
531
118
    return SignExtend64<26>(read32le(Buf) << 2);
532
118
  case R_ARM_THM_JUMP11:
533
5
    return SignExtend64<12>(read16le(Buf) << 1);
534
118
  case R_ARM_THM_JUMP19: {
535
20
    // Encoding T3: A = S:J2:J1:imm10:imm6:0
536
20
    uint16_t Hi = read16le(Buf);
537
20
    uint16_t Lo = read16le(Buf + 2);
538
20
    return SignExtend64<20>(((Hi & 0x0400) << 10) | // S
539
20
                            ((Lo & 0x0800) << 8) |  // J2
540
20
                            ((Lo & 0x2000) << 5) |  // J1
541
20
                            ((Hi & 0x003f) << 12) | // imm6
542
20
                            ((Lo & 0x07ff) << 1));  // imm11:0
543
118
  }
544
123
  case R_ARM_THM_CALL:
545
123
  case R_ARM_THM_JUMP24: {
546
123
    // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
547
123
    // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
548
123
    // FIXME: I1 and I2 require v6T2ops
549
123
    uint16_t Hi = read16le(Buf);
550
123
    uint16_t Lo = read16le(Buf + 2);
551
123
    return SignExtend64<24>(((Hi & 0x0400) << 14) |                    // S
552
123
                            (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1
553
123
                            (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2
554
123
                            ((Hi & 0x003ff) << 12) |                   // imm0
555
123
                            ((Lo & 0x007ff) << 1)); // imm11:0
556
123
  }
557
123
  // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and
558
123
  // MOVT is in the range -32768 <= A < 32768
559
123
  case R_ARM_MOVW_ABS_NC:
560
28
  case R_ARM_MOVT_ABS:
561
28
  case R_ARM_MOVW_PREL_NC:
562
28
  case R_ARM_MOVT_PREL: {
563
28
    uint64_t Val = read32le(Buf) & 0x000f0fff;
564
28
    return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff));
565
28
  }
566
28
  case R_ARM_THM_MOVW_ABS_NC:
567
22
  case R_ARM_THM_MOVT_ABS:
568
22
  case R_ARM_THM_MOVW_PREL_NC:
569
22
  case R_ARM_THM_MOVT_PREL: {
570
22
    // Encoding T3: A = imm4:i:imm3:imm8
571
22
    uint16_t Hi = read16le(Buf);
572
22
    uint16_t Lo = read16le(Buf + 2);
573
22
    return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4
574
22
                            ((Hi & 0x0400) << 1) |  // i
575
22
                            ((Lo & 0x7000) >> 4) |  // imm3
576
22
                            (Lo & 0x00ff));         // imm8
577
22
  }
578
591
  }
579
591
}
580
581
138
TargetInfo *elf::getARMTargetInfo() {
582
138
  static ARM Target;
583
138
  return &Target;
584
138
}