Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/Hexagon.cpp
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//===-- Hexagon.cpp -------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "InputFiles.h"
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#include "Symbols.h"
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#include "SyntheticSections.h"
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#include "Target.h"
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#include "lld/Common/ErrorHandler.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/Object/ELF.h"
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#include "llvm/Support/Endian.h"
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using namespace llvm;
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using namespace llvm::object;
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using namespace llvm::support::endian;
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using namespace llvm::ELF;
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using namespace lld;
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using namespace lld::elf;
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namespace {
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class Hexagon final : public TargetInfo {
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public:
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  Hexagon();
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  uint32_t calcEFlags() const override;
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  RelExpr getRelExpr(RelType type, const Symbol &s,
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                     const uint8_t *loc) const override;
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  void relocateOne(uint8_t *loc, RelType type, uint64_t val) const override;
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  void writePltHeader(uint8_t *buf) const override;
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  void writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, uint64_t pltEntryAddr,
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                int32_t index, unsigned relOff) const override;
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};
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} // namespace
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Hexagon::Hexagon() {
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4
  pltRel = R_HEX_JMP_SLOT;
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4
  relativeRel = R_HEX_RELATIVE;
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  gotRel = R_HEX_GLOB_DAT;
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  symbolicRel = R_HEX_32;
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  // The zero'th GOT entry is reserved for the address of _DYNAMIC.  The
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  // next 3 are reserved for the dynamic loader.
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  gotPltHeaderEntriesNum = 4;
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  pltEntrySize = 16;
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4
  pltHeaderSize = 32;
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4
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  // Hexagon Linux uses 64K pages by default.
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4
  defaultMaxPageSize = 0x10000;
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  noneRel = R_HEX_NONE;
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4
}
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4
uint32_t Hexagon::calcEFlags() const {
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4
  assert(!objectFiles.empty());
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4
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  // The architecture revision must always be equal to or greater than
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  // greatest revision in the list of inputs.
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  uint32_t ret = 0;
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6
  for (InputFile *f : objectFiles) {
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    uint32_t eflags = cast<ObjFile<ELF32LE>>(f)->getObj().getHeader()->e_flags;
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    if (eflags > ret)
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5
      ret = eflags;
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  }
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  return ret;
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}
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static uint32_t applyMask(uint32_t mask, uint32_t data) {
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  uint32_t result = 0;
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103
  size_t off = 0;
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103
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3.39k
  for (size_t bit = 0; bit != 32; 
++bit3.29k
) {
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3.29k
    uint32_t valBit = (data >> off) & 1;
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3.29k
    uint32_t maskBit = (mask >> bit) & 1;
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3.29k
    if (maskBit) {
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1.78k
      result |= (valBit << bit);
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1.78k
      ++off;
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1.78k
    }
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3.29k
  }
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  return result;
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}
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RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s,
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101
                            const uint8_t *loc) const {
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  switch (type) {
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  case R_HEX_B9_PCREL:
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7
  case R_HEX_B9_PCREL_X:
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  case R_HEX_B13_PCREL:
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  case R_HEX_B15_PCREL:
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  case R_HEX_B15_PCREL_X:
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  case R_HEX_6_PCREL_X:
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  case R_HEX_32_PCREL:
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    return R_PC;
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  case R_HEX_B22_PCREL:
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  case R_HEX_PLT_B22_PCREL:
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  case R_HEX_B22_PCREL_X:
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  case R_HEX_B32_PCREL_X:
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    return R_PLT_PC;
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  case R_HEX_GOT_11_X:
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4
  case R_HEX_GOT_16_X:
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  case R_HEX_GOT_32_6_X:
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    return R_HEXAGON_GOT;
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  default:
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    return R_ABS;
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  }
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}
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static uint32_t findMaskR6(uint32_t insn) {
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  // There are (arguably too) many relocation masks for the DSP's
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  // R_HEX_6_X type.  The table below is used to select the correct mask
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  // for the given instruction.
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  struct InstructionMask {
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    uint32_t cmpMask;
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    uint32_t relocMask;
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  };
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  static const InstructionMask r6[] = {
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      {0x38000000, 0x0000201f}, {0x39000000, 0x0000201f},
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      {0x3e000000, 0x00001f80}, {0x3f000000, 0x00001f80},
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      {0x40000000, 0x000020f8}, {0x41000000, 0x000007e0},
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      {0x42000000, 0x000020f8}, {0x43000000, 0x000007e0},
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      {0x44000000, 0x000020f8}, {0x45000000, 0x000007e0},
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      {0x46000000, 0x000020f8}, {0x47000000, 0x000007e0},
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      {0x6a000000, 0x00001f80}, {0x7c000000, 0x001f2000},
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      {0x9a000000, 0x00000f60}, {0x9b000000, 0x00000f60},
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      {0x9c000000, 0x00000f60}, {0x9d000000, 0x00000f60},
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      {0x9f000000, 0x001f0100}, {0xab000000, 0x0000003f},
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      {0xad000000, 0x0000003f}, {0xaf000000, 0x00030078},
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      {0xd7000000, 0x006020e0}, {0xd8000000, 0x006020e0},
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      {0xdb000000, 0x006020e0}, {0xdf000000, 0x006020e0}};
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  // Duplex forms have a fixed mask and parse bits 15:14 are always
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  // zero.  Non-duplex insns will always have at least one bit set in the
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  // parse field.
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  if ((0xC000 & insn) == 0x0)
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1
    return 0x03f00000;
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  for (InstructionMask i : r6)
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    if ((0xff000000 & insn) == i.cmpMask)
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      return i.relocMask;
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  error("unrecognized instruction for R_HEX_6 relocation: 0x" +
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0
        utohexstr(insn));
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0
  return 0;
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}
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static uint32_t findMaskR8(uint32_t insn) {
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3
  if ((0xff000000 & insn) == 0xde000000)
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1
    return 0x00e020e8;
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2
  if ((0xff000000 & insn) == 0x3c000000)
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1
    return 0x0000207f;
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1
  return 0x00001fe0;
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1
}
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3
static uint32_t findMaskR11(uint32_t insn) {
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3
  if ((0xff000000 & insn) == 0xa1000000)
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1
    return 0x060020ff;
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2
  return 0x06003fe0;
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2
}
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static uint32_t findMaskR16(uint32_t insn) {
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  if ((0xff000000 & insn) == 0x48000000)
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1
    return 0x061f20ff;
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4
  if ((0xff000000 & insn) == 0x49000000)
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1
    return 0x061f3fe0;
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3
  if ((0xff000000 & insn) == 0x78000000)
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1
    return 0x00df3fe0;
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2
  if ((0xff000000 & insn) == 0xb0000000)
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2
    return 0x0fe03fe0;
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0
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0
  error("unrecognized instruction for R_HEX_16_X relocation: 0x" +
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0
        utohexstr(insn));
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0
  return 0;
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0
}
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static void or32le(uint8_t *p, int32_t v) { write32le(p, read32le(p) | v); }
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void Hexagon::relocateOne(uint8_t *loc, RelType type, uint64_t val) const {
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  switch (type) {
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  case R_HEX_NONE:
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0
    break;
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  case R_HEX_6_PCREL_X:
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30
  case R_HEX_6_X:
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30
    or32le(loc, applyMask(findMaskR6(read32le(loc)), val));
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30
    break;
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30
  case R_HEX_8_X:
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3
    or32le(loc, applyMask(findMaskR8(read32le(loc)), val));
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3
    break;
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30
  case R_HEX_9_X:
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1
    or32le(loc, applyMask(0x00003fe0, val & 0x3f));
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1
    break;
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30
  case R_HEX_10_X:
196
1
    or32le(loc, applyMask(0x00203fe0, val & 0x3f));
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1
    break;
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30
  case R_HEX_11_X:
199
3
  case R_HEX_GOT_11_X:
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3
    or32le(loc, applyMask(findMaskR11(read32le(loc)), val & 0x3f));
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3
    break;
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3
  case R_HEX_12_X:
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1
    or32le(loc, applyMask(0x000007e0, val));
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1
    break;
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5
  case R_HEX_16_X: // These relocs only have 6 effective bits.
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5
  case R_HEX_GOT_16_X:
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5
    or32le(loc, applyMask(findMaskR16(read32le(loc)), val & 0x3f));
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5
    break;
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5
  case R_HEX_32:
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2
  case R_HEX_32_PCREL:
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2
    or32le(loc, val);
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2
    break;
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40
  case R_HEX_32_6_X:
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40
  case R_HEX_GOT_32_6_X:
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40
    or32le(loc, applyMask(0x0fff3fff, val >> 6));
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40
    break;
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40
  case R_HEX_B9_PCREL:
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1
    or32le(loc, applyMask(0x003000fe, val >> 2));
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1
    break;
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40
  case R_HEX_B9_PCREL_X:
221
0
    or32le(loc, applyMask(0x003000fe, val & 0x3f));
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0
    break;
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40
  case R_HEX_B13_PCREL:
224
1
    or32le(loc, applyMask(0x00202ffe, val >> 2));
225
1
    break;
226
40
  case R_HEX_B15_PCREL:
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1
    or32le(loc, applyMask(0x00df20fe, val >> 2));
228
1
    break;
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40
  case R_HEX_B15_PCREL_X:
230
1
    or32le(loc, applyMask(0x00df20fe, val & 0x3f));
231
1
    break;
232
40
  case R_HEX_B22_PCREL:
233
2
  case R_HEX_PLT_B22_PCREL:
234
2
    or32le(loc, applyMask(0x1ff3ffe, val >> 2));
235
2
    break;
236
3
  case R_HEX_B22_PCREL_X:
237
3
    or32le(loc, applyMask(0x1ff3ffe, val & 0x3f));
238
3
    break;
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8
  case R_HEX_B32_PCREL_X:
240
8
    or32le(loc, applyMask(0x0fff3fff, val >> 6));
241
8
    break;
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2
  case R_HEX_HI16:
243
1
    or32le(loc, applyMask(0x00c03fff, val >> 16));
244
1
    break;
245
2
  case R_HEX_LO16:
246
1
    or32le(loc, applyMask(0x00c03fff, val));
247
1
    break;
248
2
  default:
249
0
    error(getErrorLocation(loc) + "unrecognized relocation " + toString(type));
250
0
    break;
251
105
  }
252
105
}
253
254
1
void Hexagon::writePltHeader(uint8_t *buf) const {
255
1
  const uint8_t pltData[] = {
256
1
      0x00, 0x40, 0x00, 0x00, // { immext (#0)
257
1
      0x1c, 0xc0, 0x49, 0x6a, //   r28 = add (pc, ##GOT0@PCREL) } # @GOT0
258
1
      0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16)  # offset of GOTn
259
1
      0x4f, 0x40, 0x9c, 0x91, //   r15 = memw (r28 + #8)  # object ID at GOT2
260
1
      0x3c, 0xc0, 0x9c, 0x91, //   r28 = memw (r28 + #4) }# dynamic link at GOT1
261
1
      0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2)    # index of PLTn
262
1
      0x00, 0xc0, 0x9c, 0x52, //   jumpr r28 }            # call dynamic linker
263
1
      0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment
264
1
  };
265
1
  memcpy(buf, pltData, sizeof(pltData));
266
1
267
1
  // Offset from PLT0 to the GOT.
268
1
  uint64_t off = in.gotPlt->getVA() - in.plt->getVA();
269
1
  relocateOne(buf, R_HEX_B32_PCREL_X, off);
270
1
  relocateOne(buf + 4, R_HEX_6_PCREL_X, off);
271
1
}
272
273
void Hexagon::writePlt(uint8_t *buf, uint64_t gotPltEntryAddr,
274
                       uint64_t pltEntryAddr, int32_t index,
275
1
                       unsigned relOff) const {
276
1
  const uint8_t inst[] = {
277
1
      0x00, 0x40, 0x00, 0x00, // { immext (#0)
278
1
      0x0e, 0xc0, 0x49, 0x6a, //   r14 = add (pc, ##GOTn@PCREL) }
279
1
      0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14)
280
1
      0x00, 0xc0, 0x9c, 0x52, // jumpr r28
281
1
  };
282
1
  memcpy(buf, inst, sizeof(inst));
283
1
284
1
  relocateOne(buf, R_HEX_B32_PCREL_X, gotPltEntryAddr - pltEntryAddr);
285
1
  relocateOne(buf + 4, R_HEX_6_PCREL_X, gotPltEntryAddr - pltEntryAddr);
286
1
}
287
288
8
TargetInfo *elf::getHexagonTargetInfo() {
289
8
  static Hexagon target;
290
8
  return &target;
291
8
}