Coverage Report

Created: 2018-10-23 15:26

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/Mips.cpp
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Source (jump to first uncovered line)
1
//===- MIPS.cpp -----------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
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//===----------------------------------------------------------------------===//
9
10
#include "InputFiles.h"
11
#include "OutputSections.h"
12
#include "Symbols.h"
13
#include "SyntheticSections.h"
14
#include "Target.h"
15
#include "Thunks.h"
16
#include "lld/Common/ErrorHandler.h"
17
#include "llvm/Object/ELF.h"
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#include "llvm/Support/Endian.h"
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20
using namespace llvm;
21
using namespace llvm::object;
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using namespace llvm::support::endian;
23
using namespace llvm::ELF;
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using namespace lld;
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using namespace lld::elf;
26
27
namespace {
28
template <class ELFT> class MIPS final : public TargetInfo {
29
public:
30
  MIPS();
31
  uint32_t calcEFlags() const override;
32
  RelExpr getRelExpr(RelType Type, const Symbol &S,
33
                     const uint8_t *Loc) const override;
34
  int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
35
  RelType getDynRel(RelType Type) const override;
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  void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
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  void writePltHeader(uint8_t *Buf) const override;
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  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
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                int32_t Index, unsigned RelOff) const override;
40
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
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                  uint64_t BranchAddr, const Symbol &S) const override;
42
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
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  bool usesOnlyLowPageBits(RelType Type) const override;
44
};
45
} // namespace
46
47
181
template <class ELFT> MIPS<ELFT>::MIPS() {
48
181
  GotPltHeaderEntriesNum = 2;
49
181
  DefaultMaxPageSize = 65536;
50
181
  GotEntrySize = sizeof(typename ELFT::uint);
51
181
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
181
  GotBaseSymInGotPlt = false;
53
181
  PltEntrySize = 16;
54
181
  PltHeaderSize = 32;
55
181
  CopyRel = R_MIPS_COPY;
56
181
  NoneRel = R_MIPS_NONE;
57
181
  PltRel = R_MIPS_JUMP_SLOT;
58
181
  NeedsThunks = true;
59
181
  TrapInstr = 0xefefefef;
60
181
61
181
  if (ELFT::Is64Bits) {
62
47
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
63
47
    TlsGotRel = R_MIPS_TLS_TPREL64;
64
47
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
65
47
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
66
134
  } else {
67
134
    RelativeRel = R_MIPS_REL32;
68
134
    TlsGotRel = R_MIPS_TLS_TPREL32;
69
134
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
70
134
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
71
134
  }
72
181
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::MIPS()
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47
17
template <class ELFT> MIPS<ELFT>::MIPS() {
48
17
  GotPltHeaderEntriesNum = 2;
49
17
  DefaultMaxPageSize = 65536;
50
17
  GotEntrySize = sizeof(typename ELFT::uint);
51
17
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
17
  GotBaseSymInGotPlt = false;
53
17
  PltEntrySize = 16;
54
17
  PltHeaderSize = 32;
55
17
  CopyRel = R_MIPS_COPY;
56
17
  NoneRel = R_MIPS_NONE;
57
17
  PltRel = R_MIPS_JUMP_SLOT;
58
17
  NeedsThunks = true;
59
17
  TrapInstr = 0xefefefef;
60
17
61
17
  if (ELFT::Is64Bits) {
62
0
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
63
0
    TlsGotRel = R_MIPS_TLS_TPREL64;
64
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
65
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
66
17
  } else {
67
17
    RelativeRel = R_MIPS_REL32;
68
17
    TlsGotRel = R_MIPS_TLS_TPREL32;
69
17
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
70
17
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
71
17
  }
72
17
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::MIPS()
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47
117
template <class ELFT> MIPS<ELFT>::MIPS() {
48
117
  GotPltHeaderEntriesNum = 2;
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117
  DefaultMaxPageSize = 65536;
50
117
  GotEntrySize = sizeof(typename ELFT::uint);
51
117
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
117
  GotBaseSymInGotPlt = false;
53
117
  PltEntrySize = 16;
54
117
  PltHeaderSize = 32;
55
117
  CopyRel = R_MIPS_COPY;
56
117
  NoneRel = R_MIPS_NONE;
57
117
  PltRel = R_MIPS_JUMP_SLOT;
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117
  NeedsThunks = true;
59
117
  TrapInstr = 0xefefefef;
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117
61
117
  if (ELFT::Is64Bits) {
62
0
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
63
0
    TlsGotRel = R_MIPS_TLS_TPREL64;
64
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
65
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
66
117
  } else {
67
117
    RelativeRel = R_MIPS_REL32;
68
117
    TlsGotRel = R_MIPS_TLS_TPREL32;
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117
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
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117
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
71
117
  }
72
117
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::MIPS()
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47
2
template <class ELFT> MIPS<ELFT>::MIPS() {
48
2
  GotPltHeaderEntriesNum = 2;
49
2
  DefaultMaxPageSize = 65536;
50
2
  GotEntrySize = sizeof(typename ELFT::uint);
51
2
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
2
  GotBaseSymInGotPlt = false;
53
2
  PltEntrySize = 16;
54
2
  PltHeaderSize = 32;
55
2
  CopyRel = R_MIPS_COPY;
56
2
  NoneRel = R_MIPS_NONE;
57
2
  PltRel = R_MIPS_JUMP_SLOT;
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2
  NeedsThunks = true;
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2
  TrapInstr = 0xefefefef;
60
2
61
2
  if (ELFT::Is64Bits) {
62
2
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
63
2
    TlsGotRel = R_MIPS_TLS_TPREL64;
64
2
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
65
2
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
66
2
  } else {
67
0
    RelativeRel = R_MIPS_REL32;
68
0
    TlsGotRel = R_MIPS_TLS_TPREL32;
69
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
70
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
71
0
  }
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2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::MIPS()
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47
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template <class ELFT> MIPS<ELFT>::MIPS() {
48
45
  GotPltHeaderEntriesNum = 2;
49
45
  DefaultMaxPageSize = 65536;
50
45
  GotEntrySize = sizeof(typename ELFT::uint);
51
45
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
45
  GotBaseSymInGotPlt = false;
53
45
  PltEntrySize = 16;
54
45
  PltHeaderSize = 32;
55
45
  CopyRel = R_MIPS_COPY;
56
45
  NoneRel = R_MIPS_NONE;
57
45
  PltRel = R_MIPS_JUMP_SLOT;
58
45
  NeedsThunks = true;
59
45
  TrapInstr = 0xefefefef;
60
45
61
45
  if (ELFT::Is64Bits) {
62
45
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
63
45
    TlsGotRel = R_MIPS_TLS_TPREL64;
64
45
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
65
45
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
66
45
  } else {
67
0
    RelativeRel = R_MIPS_REL32;
68
0
    TlsGotRel = R_MIPS_TLS_TPREL32;
69
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
70
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
71
0
  }
72
45
}
73
74
179
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
75
179
  return calcMipsEFlags<ELFT>();
76
179
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::calcEFlags() const
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74
17
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
75
17
  return calcMipsEFlags<ELFT>();
76
17
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::calcEFlags() const
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116
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
75
116
  return calcMipsEFlags<ELFT>();
76
116
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::calcEFlags() const
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74
2
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
75
2
  return calcMipsEFlags<ELFT>();
76
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::calcEFlags() const
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74
44
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
75
44
  return calcMipsEFlags<ELFT>();
76
44
}
77
78
template <class ELFT>
79
RelExpr MIPS<ELFT>::getRelExpr(RelType Type, const Symbol &S,
80
10.3k
                               const uint8_t *Loc) const {
81
10.3k
  // See comment in the calculateMipsRelChain.
82
10.3k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi293
)
83
10.0k
    Type &= 0xff;
84
10.3k
85
10.3k
  switch (Type) {
86
10.3k
  case R_MIPS_JALR:
87
1
  case R_MICROMIPS_JALR:
88
1
    return R_HINT;
89
26
  case R_MIPS_GPREL16:
90
26
  case R_MIPS_GPREL32:
91
26
  case R_MICROMIPS_GPREL16:
92
26
  case R_MICROMIPS_GPREL7_S2:
93
26
    return R_MIPS_GOTREL;
94
60
  case R_MIPS_26:
95
60
  case R_MICROMIPS_26_S1:
96
60
    return R_PLT;
97
60
  case R_MICROMIPS_PC26_S1:
98
6
    return R_PLT_PC;
99
77
  case R_MIPS_HI16:
100
77
  case R_MIPS_LO16:
101
77
  case R_MIPS_HIGHER:
102
77
  case R_MIPS_HIGHEST:
103
77
  case R_MICROMIPS_HI16:
104
77
  case R_MICROMIPS_LO16:
105
77
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
106
77
    // offset between start of function and 'gp' value which by default
107
77
    // equal to the start of .got section. In that case we consider these
108
77
    // relocations as relative.
109
77
    if (&S == ElfSym::MipsGpDisp)
110
20
      return R_MIPS_GOT_GP_PC;
111
57
    if (&S == ElfSym::MipsLocalGp)
112
2
      return R_MIPS_GOT_GP;
113
55
    LLVM_FALLTHROUGH;
114
90
  case R_MIPS_32:
115
90
  case R_MIPS_64:
116
90
  case R_MIPS_GOT_OFST:
117
90
  case R_MIPS_SUB:
118
90
  case R_MIPS_TLS_DTPREL_HI16:
119
90
  case R_MIPS_TLS_DTPREL_LO16:
120
90
  case R_MIPS_TLS_DTPREL32:
121
90
  case R_MIPS_TLS_DTPREL64:
122
90
  case R_MIPS_TLS_TPREL_HI16:
123
90
  case R_MIPS_TLS_TPREL_LO16:
124
90
  case R_MIPS_TLS_TPREL32:
125
90
  case R_MIPS_TLS_TPREL64:
126
90
  case R_MICROMIPS_TLS_DTPREL_HI16:
127
90
  case R_MICROMIPS_TLS_DTPREL_LO16:
128
90
  case R_MICROMIPS_TLS_TPREL_HI16:
129
90
  case R_MICROMIPS_TLS_TPREL_LO16:
130
90
    return R_ABS;
131
90
  case R_MIPS_PC32:
132
19
  case R_MIPS_PC16:
133
19
  case R_MIPS_PC19_S2:
134
19
  case R_MIPS_PC21_S2:
135
19
  case R_MIPS_PC26_S2:
136
19
  case R_MIPS_PCHI16:
137
19
  case R_MIPS_PCLO16:
138
19
  case R_MICROMIPS_PC7_S1:
139
19
  case R_MICROMIPS_PC10_S1:
140
19
  case R_MICROMIPS_PC16_S1:
141
19
  case R_MICROMIPS_PC18_S3:
142
19
  case R_MICROMIPS_PC19_S2:
143
19
  case R_MICROMIPS_PC23_S2:
144
19
  case R_MICROMIPS_PC21_S1:
145
19
    return R_PC;
146
46
  case R_MIPS_GOT16:
147
46
  case R_MICROMIPS_GOT16:
148
46
    if (S.isLocal())
149
19
      return R_MIPS_GOT_LOCAL_PAGE;
150
27
    LLVM_FALLTHROUGH;
151
10.0k
  case R_MIPS_CALL16:
152
10.0k
  case R_MIPS_GOT_DISP:
153
10.0k
  case R_MIPS_TLS_GOTTPREL:
154
10.0k
  case R_MICROMIPS_CALL16:
155
10.0k
  case R_MICROMIPS_TLS_GOTTPREL:
156
10.0k
    return R_MIPS_GOT_OFF;
157
10.0k
  case R_MIPS_CALL_HI16:
158
16
  case R_MIPS_CALL_LO16:
159
16
  case R_MIPS_GOT_HI16:
160
16
  case R_MIPS_GOT_LO16:
161
16
  case R_MICROMIPS_CALL_HI16:
162
16
  case R_MICROMIPS_CALL_LO16:
163
16
  case R_MICROMIPS_GOT_HI16:
164
16
  case R_MICROMIPS_GOT_LO16:
165
16
    return R_MIPS_GOT_OFF32;
166
16
  case R_MIPS_GOT_PAGE:
167
12
    return R_MIPS_GOT_LOCAL_PAGE;
168
16
  case R_MIPS_TLS_GD:
169
12
  case R_MICROMIPS_TLS_GD:
170
12
    return R_MIPS_TLSGD;
171
12
  case R_MIPS_TLS_LDM:
172
6
  case R_MICROMIPS_TLS_LDM:
173
6
    return R_MIPS_TLSLD;
174
6
  case R_MIPS_NONE:
175
0
    return R_NONE;
176
6
  default:
177
0
    return R_INVALID;
178
10.3k
  }
179
10.3k
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Line
Count
Source
80
21
                               const uint8_t *Loc) const {
81
21
  // See comment in the calculateMipsRelChain.
82
21
  if (ELFT::Is64Bits || Config->MipsN32Abi)
83
0
    Type &= 0xff;
84
21
85
21
  switch (Type) {
86
21
  case R_MIPS_JALR:
87
1
  case R_MICROMIPS_JALR:
88
1
    return R_HINT;
89
1
  case R_MIPS_GPREL16:
90
0
  case R_MIPS_GPREL32:
91
0
  case R_MICROMIPS_GPREL16:
92
0
  case R_MICROMIPS_GPREL7_S2:
93
0
    return R_MIPS_GOTREL;
94
2
  case R_MIPS_26:
95
2
  case R_MICROMIPS_26_S1:
96
2
    return R_PLT;
97
3
  case R_MICROMIPS_PC26_S1:
98
3
    return R_PLT_PC;
99
2
  case R_MIPS_HI16:
100
2
  case R_MIPS_LO16:
101
2
  case R_MIPS_HIGHER:
102
2
  case R_MIPS_HIGHEST:
103
2
  case R_MICROMIPS_HI16:
104
2
  case R_MICROMIPS_LO16:
105
2
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
106
2
    // offset between start of function and 'gp' value which by default
107
2
    // equal to the start of .got section. In that case we consider these
108
2
    // relocations as relative.
109
2
    if (&S == ElfSym::MipsGpDisp)
110
2
      return R_MIPS_GOT_GP_PC;
111
0
    if (&S == ElfSym::MipsLocalGp)
112
0
      return R_MIPS_GOT_GP;
113
0
    LLVM_FALLTHROUGH;
114
2
  case R_MIPS_32:
115
2
  case R_MIPS_64:
116
2
  case R_MIPS_GOT_OFST:
117
2
  case R_MIPS_SUB:
118
2
  case R_MIPS_TLS_DTPREL_HI16:
119
2
  case R_MIPS_TLS_DTPREL_LO16:
120
2
  case R_MIPS_TLS_DTPREL32:
121
2
  case R_MIPS_TLS_DTPREL64:
122
2
  case R_MIPS_TLS_TPREL_HI16:
123
2
  case R_MIPS_TLS_TPREL_LO16:
124
2
  case R_MIPS_TLS_TPREL32:
125
2
  case R_MIPS_TLS_TPREL64:
126
2
  case R_MICROMIPS_TLS_DTPREL_HI16:
127
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
128
2
  case R_MICROMIPS_TLS_TPREL_HI16:
129
2
  case R_MICROMIPS_TLS_TPREL_LO16:
130
2
    return R_ABS;
131
5
  case R_MIPS_PC32:
132
5
  case R_MIPS_PC16:
133
5
  case R_MIPS_PC19_S2:
134
5
  case R_MIPS_PC21_S2:
135
5
  case R_MIPS_PC26_S2:
136
5
  case R_MIPS_PCHI16:
137
5
  case R_MIPS_PCLO16:
138
5
  case R_MICROMIPS_PC7_S1:
139
5
  case R_MICROMIPS_PC10_S1:
140
5
  case R_MICROMIPS_PC16_S1:
141
5
  case R_MICROMIPS_PC18_S3:
142
5
  case R_MICROMIPS_PC19_S2:
143
5
  case R_MICROMIPS_PC23_S2:
144
5
  case R_MICROMIPS_PC21_S1:
145
5
    return R_PC;
146
5
  case R_MIPS_GOT16:
147
5
  case R_MICROMIPS_GOT16:
148
5
    if (S.isLocal())
149
0
      return R_MIPS_GOT_LOCAL_PAGE;
150
5
    LLVM_FALLTHROUGH;
151
6
  case R_MIPS_CALL16:
152
6
  case R_MIPS_GOT_DISP:
153
6
  case R_MIPS_TLS_GOTTPREL:
154
6
  case R_MICROMIPS_CALL16:
155
6
  case R_MICROMIPS_TLS_GOTTPREL:
156
6
    return R_MIPS_GOT_OFF;
157
6
  case R_MIPS_CALL_HI16:
158
0
  case R_MIPS_CALL_LO16:
159
0
  case R_MIPS_GOT_HI16:
160
0
  case R_MIPS_GOT_LO16:
161
0
  case R_MICROMIPS_CALL_HI16:
162
0
  case R_MICROMIPS_CALL_LO16:
163
0
  case R_MICROMIPS_GOT_HI16:
164
0
  case R_MICROMIPS_GOT_LO16:
165
0
    return R_MIPS_GOT_OFF32;
166
0
  case R_MIPS_GOT_PAGE:
167
0
    return R_MIPS_GOT_LOCAL_PAGE;
168
0
  case R_MIPS_TLS_GD:
169
0
  case R_MICROMIPS_TLS_GD:
170
0
    return R_MIPS_TLSGD;
171
0
  case R_MIPS_TLS_LDM:
172
0
  case R_MICROMIPS_TLS_LDM:
173
0
    return R_MIPS_TLSLD;
174
0
  case R_MIPS_NONE:
175
0
    return R_NONE;
176
0
  default:
177
0
    return R_INVALID;
178
21
  }
179
21
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Line
Count
Source
80
272
                               const uint8_t *Loc) const {
81
272
  // See comment in the calculateMipsRelChain.
82
272
  if (ELFT::Is64Bits || Config->MipsN32Abi)
83
5
    Type &= 0xff;
84
272
85
272
  switch (Type) {
86
272
  case R_MIPS_JALR:
87
0
  case R_MICROMIPS_JALR:
88
0
    return R_HINT;
89
15
  case R_MIPS_GPREL16:
90
15
  case R_MIPS_GPREL32:
91
15
  case R_MICROMIPS_GPREL16:
92
15
  case R_MICROMIPS_GPREL7_S2:
93
15
    return R_MIPS_GOTREL;
94
56
  case R_MIPS_26:
95
56
  case R_MICROMIPS_26_S1:
96
56
    return R_PLT;
97
56
  case R_MICROMIPS_PC26_S1:
98
3
    return R_PLT_PC;
99
71
  case R_MIPS_HI16:
100
71
  case R_MIPS_LO16:
101
71
  case R_MIPS_HIGHER:
102
71
  case R_MIPS_HIGHEST:
103
71
  case R_MICROMIPS_HI16:
104
71
  case R_MICROMIPS_LO16:
105
71
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
106
71
    // offset between start of function and 'gp' value which by default
107
71
    // equal to the start of .got section. In that case we consider these
108
71
    // relocations as relative.
109
71
    if (&S == ElfSym::MipsGpDisp)
110
18
      return R_MIPS_GOT_GP_PC;
111
53
    if (&S == ElfSym::MipsLocalGp)
112
2
      return R_MIPS_GOT_GP;
113
51
    LLVM_FALLTHROUGH;
114
72
  case R_MIPS_32:
115
72
  case R_MIPS_64:
116
72
  case R_MIPS_GOT_OFST:
117
72
  case R_MIPS_SUB:
118
72
  case R_MIPS_TLS_DTPREL_HI16:
119
72
  case R_MIPS_TLS_DTPREL_LO16:
120
72
  case R_MIPS_TLS_DTPREL32:
121
72
  case R_MIPS_TLS_DTPREL64:
122
72
  case R_MIPS_TLS_TPREL_HI16:
123
72
  case R_MIPS_TLS_TPREL_LO16:
124
72
  case R_MIPS_TLS_TPREL32:
125
72
  case R_MIPS_TLS_TPREL64:
126
72
  case R_MICROMIPS_TLS_DTPREL_HI16:
127
72
  case R_MICROMIPS_TLS_DTPREL_LO16:
128
72
  case R_MICROMIPS_TLS_TPREL_HI16:
129
72
  case R_MICROMIPS_TLS_TPREL_LO16:
130
72
    return R_ABS;
131
72
  case R_MIPS_PC32:
132
13
  case R_MIPS_PC16:
133
13
  case R_MIPS_PC19_S2:
134
13
  case R_MIPS_PC21_S2:
135
13
  case R_MIPS_PC26_S2:
136
13
  case R_MIPS_PCHI16:
137
13
  case R_MIPS_PCLO16:
138
13
  case R_MICROMIPS_PC7_S1:
139
13
  case R_MICROMIPS_PC10_S1:
140
13
  case R_MICROMIPS_PC16_S1:
141
13
  case R_MICROMIPS_PC18_S3:
142
13
  case R_MICROMIPS_PC19_S2:
143
13
  case R_MICROMIPS_PC23_S2:
144
13
  case R_MICROMIPS_PC21_S1:
145
13
    return R_PC;
146
41
  case R_MIPS_GOT16:
147
41
  case R_MICROMIPS_GOT16:
148
41
    if (S.isLocal())
149
19
      return R_MIPS_GOT_LOCAL_PAGE;
150
22
    LLVM_FALLTHROUGH;
151
47
  case R_MIPS_CALL16:
152
47
  case R_MIPS_GOT_DISP:
153
47
  case R_MIPS_TLS_GOTTPREL:
154
47
  case R_MICROMIPS_CALL16:
155
47
  case R_MICROMIPS_TLS_GOTTPREL:
156
47
    return R_MIPS_GOT_OFF;
157
47
  case R_MIPS_CALL_HI16:
158
16
  case R_MIPS_CALL_LO16:
159
16
  case R_MIPS_GOT_HI16:
160
16
  case R_MIPS_GOT_LO16:
161
16
  case R_MICROMIPS_CALL_HI16:
162
16
  case R_MICROMIPS_CALL_LO16:
163
16
  case R_MICROMIPS_GOT_HI16:
164
16
  case R_MICROMIPS_GOT_LO16:
165
16
    return R_MIPS_GOT_OFF32;
166
16
  case R_MIPS_GOT_PAGE:
167
0
    return R_MIPS_GOT_LOCAL_PAGE;
168
16
  case R_MIPS_TLS_GD:
169
7
  case R_MICROMIPS_TLS_GD:
170
7
    return R_MIPS_TLSGD;
171
7
  case R_MIPS_TLS_LDM:
172
4
  case R_MICROMIPS_TLS_LDM:
173
4
    return R_MIPS_TLSLD;
174
4
  case R_MIPS_NONE:
175
0
    return R_NONE;
176
4
  default:
177
0
    return R_INVALID;
178
272
  }
179
272
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Line
Count
Source
80
10.0k
                               const uint8_t *Loc) const {
81
10.0k
  // See comment in the calculateMipsRelChain.
82
10.0k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi0
)
83
10.0k
    Type &= 0xff;
84
10.0k
85
10.0k
  switch (Type) {
86
10.0k
  case R_MIPS_JALR:
87
0
  case R_MICROMIPS_JALR:
88
0
    return R_HINT;
89
11
  case R_MIPS_GPREL16:
90
11
  case R_MIPS_GPREL32:
91
11
  case R_MICROMIPS_GPREL16:
92
11
  case R_MICROMIPS_GPREL7_S2:
93
11
    return R_MIPS_GOTREL;
94
11
  case R_MIPS_26:
95
2
  case R_MICROMIPS_26_S1:
96
2
    return R_PLT;
97
2
  case R_MICROMIPS_PC26_S1:
98
0
    return R_PLT_PC;
99
4
  case R_MIPS_HI16:
100
4
  case R_MIPS_LO16:
101
4
  case R_MIPS_HIGHER:
102
4
  case R_MIPS_HIGHEST:
103
4
  case R_MICROMIPS_HI16:
104
4
  case R_MICROMIPS_LO16:
105
4
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
106
4
    // offset between start of function and 'gp' value which by default
107
4
    // equal to the start of .got section. In that case we consider these
108
4
    // relocations as relative.
109
4
    if (&S == ElfSym::MipsGpDisp)
110
0
      return R_MIPS_GOT_GP_PC;
111
4
    if (&S == ElfSym::MipsLocalGp)
112
0
      return R_MIPS_GOT_GP;
113
4
    LLVM_FALLTHROUGH;
114
16
  case R_MIPS_32:
115
16
  case R_MIPS_64:
116
16
  case R_MIPS_GOT_OFST:
117
16
  case R_MIPS_SUB:
118
16
  case R_MIPS_TLS_DTPREL_HI16:
119
16
  case R_MIPS_TLS_DTPREL_LO16:
120
16
  case R_MIPS_TLS_DTPREL32:
121
16
  case R_MIPS_TLS_DTPREL64:
122
16
  case R_MIPS_TLS_TPREL_HI16:
123
16
  case R_MIPS_TLS_TPREL_LO16:
124
16
  case R_MIPS_TLS_TPREL32:
125
16
  case R_MIPS_TLS_TPREL64:
126
16
  case R_MICROMIPS_TLS_DTPREL_HI16:
127
16
  case R_MICROMIPS_TLS_DTPREL_LO16:
128
16
  case R_MICROMIPS_TLS_TPREL_HI16:
129
16
  case R_MICROMIPS_TLS_TPREL_LO16:
130
16
    return R_ABS;
131
16
  case R_MIPS_PC32:
132
1
  case R_MIPS_PC16:
133
1
  case R_MIPS_PC19_S2:
134
1
  case R_MIPS_PC21_S2:
135
1
  case R_MIPS_PC26_S2:
136
1
  case R_MIPS_PCHI16:
137
1
  case R_MIPS_PCLO16:
138
1
  case R_MICROMIPS_PC7_S1:
139
1
  case R_MICROMIPS_PC10_S1:
140
1
  case R_MICROMIPS_PC16_S1:
141
1
  case R_MICROMIPS_PC18_S3:
142
1
  case R_MICROMIPS_PC19_S2:
143
1
  case R_MICROMIPS_PC23_S2:
144
1
  case R_MICROMIPS_PC21_S1:
145
1
    return R_PC;
146
1
  case R_MIPS_GOT16:
147
0
  case R_MICROMIPS_GOT16:
148
0
    if (S.isLocal())
149
0
      return R_MIPS_GOT_LOCAL_PAGE;
150
0
    LLVM_FALLTHROUGH;
151
10.0k
  case R_MIPS_CALL16:
152
10.0k
  case R_MIPS_GOT_DISP:
153
10.0k
  case R_MIPS_TLS_GOTTPREL:
154
10.0k
  case R_MICROMIPS_CALL16:
155
10.0k
  case R_MICROMIPS_TLS_GOTTPREL:
156
10.0k
    return R_MIPS_GOT_OFF;
157
10.0k
  case R_MIPS_CALL_HI16:
158
0
  case R_MIPS_CALL_LO16:
159
0
  case R_MIPS_GOT_HI16:
160
0
  case R_MIPS_GOT_LO16:
161
0
  case R_MICROMIPS_CALL_HI16:
162
0
  case R_MICROMIPS_CALL_LO16:
163
0
  case R_MICROMIPS_GOT_HI16:
164
0
  case R_MICROMIPS_GOT_LO16:
165
0
    return R_MIPS_GOT_OFF32;
166
12
  case R_MIPS_GOT_PAGE:
167
12
    return R_MIPS_GOT_LOCAL_PAGE;
168
5
  case R_MIPS_TLS_GD:
169
5
  case R_MICROMIPS_TLS_GD:
170
5
    return R_MIPS_TLSGD;
171
5
  case R_MIPS_TLS_LDM:
172
2
  case R_MICROMIPS_TLS_LDM:
173
2
    return R_MIPS_TLSLD;
174
2
  case R_MIPS_NONE:
175
0
    return R_NONE;
176
2
  default:
177
0
    return R_INVALID;
178
10.0k
  }
179
10.0k
}
180
181
4
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
182
4
  if (Type == R_MIPS_32 || 
Type == R_MIPS_642
)
183
4
    return RelativeRel;
184
0
  return R_MIPS_NONE;
185
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getDynRel(unsigned int) const
Line
Count
Source
181
1
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
182
1
  if (Type == R_MIPS_32 || 
Type == R_MIPS_640
)
183
1
    return RelativeRel;
184
0
  return R_MIPS_NONE;
185
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getDynRel(unsigned int) const
Line
Count
Source
181
1
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
182
1
  if (Type == R_MIPS_32 || 
Type == R_MIPS_640
)
183
1
    return RelativeRel;
184
0
  return R_MIPS_NONE;
185
0
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getDynRel(unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getDynRel(unsigned int) const
Line
Count
Source
181
2
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
182
2
  if (Type == R_MIPS_32 || Type == R_MIPS_64)
183
2
    return RelativeRel;
184
0
  return R_MIPS_NONE;
185
0
}
186
187
template <class ELFT>
188
17
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
189
17
  uint64_t VA = In.Plt->getVA();
190
17
  if (isMicroMips())
191
6
    VA |= 1;
192
17
  write32<ELFT::TargetEndianness>(Buf, VA);
193
17
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Line
Count
Source
188
2
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
189
2
  uint64_t VA = In.Plt->getVA();
190
2
  if (isMicroMips())
191
2
    VA |= 1;
192
2
  write32<ELFT::TargetEndianness>(Buf, VA);
193
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Line
Count
Source
188
13
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
189
13
  uint64_t VA = In.Plt->getVA();
190
13
  if (isMicroMips())
191
4
    VA |= 1;
192
13
  write32<ELFT::TargetEndianness>(Buf, VA);
193
13
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Line
Count
Source
188
2
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
189
2
  uint64_t VA = In.Plt->getVA();
190
2
  if (isMicroMips())
191
0
    VA |= 1;
192
2
  write32<ELFT::TargetEndianness>(Buf, VA);
193
2
}
194
195
34
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
196
34
  // The major opcode of a microMIPS instruction needs to appear
197
34
  // in the first 16-bit word (lowest address) for efficient hardware
198
34
  // decode so that it knows if the instruction is 16-bit or 32-bit
199
34
  // as early as possible. To do so, little-endian binaries keep 16-bit
200
34
  // words in a big-endian order. That is why we have to swap these
201
34
  // words to get a correct value.
202
34
  uint32_t V = read32<E>(Loc);
203
34
  if (E == support::little)
204
12
    return (V << 16) | (V >> 16);
205
22
  return V;
206
22
}
Mips.cpp:unsigned int readShuffle<(llvm::support::endianness)1>(unsigned char const*)
Line
Count
Source
195
12
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
196
12
  // The major opcode of a microMIPS instruction needs to appear
197
12
  // in the first 16-bit word (lowest address) for efficient hardware
198
12
  // decode so that it knows if the instruction is 16-bit or 32-bit
199
12
  // as early as possible. To do so, little-endian binaries keep 16-bit
200
12
  // words in a big-endian order. That is why we have to swap these
201
12
  // words to get a correct value.
202
12
  uint32_t V = read32<E>(Loc);
203
12
  if (E == support::little)
204
12
    return (V << 16) | (V >> 16);
205
0
  return V;
206
0
}
Mips.cpp:unsigned int readShuffle<(llvm::support::endianness)0>(unsigned char const*)
Line
Count
Source
195
22
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
196
22
  // The major opcode of a microMIPS instruction needs to appear
197
22
  // in the first 16-bit word (lowest address) for efficient hardware
198
22
  // decode so that it knows if the instruction is 16-bit or 32-bit
199
22
  // as early as possible. To do so, little-endian binaries keep 16-bit
200
22
  // words in a big-endian order. That is why we have to swap these
201
22
  // words to get a correct value.
202
22
  uint32_t V = read32<E>(Loc);
203
22
  if (E == support::little)
204
0
    return (V << 16) | (V >> 16);
205
22
  return V;
206
22
}
207
208
template <endianness E>
209
static void writeValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
210
10.4k
                       uint8_t Shift) {
211
10.4k
  uint32_t Instr = read32<E>(Loc);
212
10.4k
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
213
10.4k
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
214
10.4k
  write32<E>(Loc, Data);
215
10.4k
}
Mips.cpp:void writeValue<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
210
26
                       uint8_t Shift) {
211
26
  uint32_t Instr = read32<E>(Loc);
212
26
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
213
26
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
214
26
  write32<E>(Loc, Data);
215
26
}
Mips.cpp:void writeValue<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
210
10.4k
                       uint8_t Shift) {
211
10.4k
  uint32_t Instr = read32<E>(Loc);
212
10.4k
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
213
10.4k
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
214
10.4k
  write32<E>(Loc, Data);
215
10.4k
}
216
217
template <endianness E>
218
static void writeShuffleValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
219
57
                              uint8_t Shift) {
220
57
  // See comments in readShuffle for purpose of this code.
221
57
  uint16_t *Words = (uint16_t *)Loc;
222
57
  if (E == support::little)
223
22
    std::swap(Words[0], Words[1]);
224
57
225
57
  writeValue<E>(Loc, V, BitsSize, Shift);
226
57
227
57
  if (E == support::little)
228
22
    std::swap(Words[0], Words[1]);
229
57
}
Mips.cpp:void writeShuffleValue<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
219
22
                              uint8_t Shift) {
220
22
  // See comments in readShuffle for purpose of this code.
221
22
  uint16_t *Words = (uint16_t *)Loc;
222
22
  if (E == support::little)
223
22
    std::swap(Words[0], Words[1]);
224
22
225
22
  writeValue<E>(Loc, V, BitsSize, Shift);
226
22
227
22
  if (E == support::little)
228
22
    std::swap(Words[0], Words[1]);
229
22
}
Mips.cpp:void writeShuffleValue<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
219
35
                              uint8_t Shift) {
220
35
  // See comments in readShuffle for purpose of this code.
221
35
  uint16_t *Words = (uint16_t *)Loc;
222
35
  if (E == support::little)
223
0
    std::swap(Words[0], Words[1]);
224
35
225
35
  writeValue<E>(Loc, V, BitsSize, Shift);
226
35
227
35
  if (E == support::little)
228
0
    std::swap(Words[0], Words[1]);
229
35
}
230
231
template <endianness E>
232
static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
233
4
                                   uint8_t Shift) {
234
4
  uint16_t Instr = read16<E>(Loc);
235
4
  uint16_t Mask = 0xffff >> (16 - BitsSize);
236
4
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
237
4
  write16<E>(Loc, Data);
238
4
}
Mips.cpp:void writeMicroRelocation16<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
233
2
                                   uint8_t Shift) {
234
2
  uint16_t Instr = read16<E>(Loc);
235
2
  uint16_t Mask = 0xffff >> (16 - BitsSize);
236
2
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
237
2
  write16<E>(Loc, Data);
238
2
}
Mips.cpp:void writeMicroRelocation16<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
233
2
                                   uint8_t Shift) {
234
2
  uint16_t Instr = read16<E>(Loc);
235
2
  uint16_t Mask = 0xffff >> (16 - BitsSize);
236
2
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
237
2
  write16<E>(Loc, Data);
238
2
}
239
240
15
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
241
15
  const endianness E = ELFT::TargetEndianness;
242
15
  if (isMicroMips()) {
243
6
    uint64_t GotPlt = In.GotPlt->getVA();
244
6
    uint64_t Plt = In.Plt->getVA();
245
6
    // Overwrite trap instructions written by Writer::writeTrapInstr.
246
6
    memset(Buf, 0, PltHeaderSize);
247
6
248
6
    write16<E>(Buf, isMipsR6() ? 
0x78602
:
0x79804
); // addiupc v1, (GOTPLT) - .
249
6
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
250
6
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
251
6
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
252
6
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
253
6
    write16<E>(Buf + 14, 0xfffe);
254
6
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
255
6
    if (isMipsR6()) {
256
2
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
257
2
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
258
2
      write16<E>(Buf + 22, 0x0c00); // nop
259
2
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
260
4
    } else {
261
4
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
262
4
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
263
4
      write16<E>(Buf + 22, 0x0c00); // nop
264
4
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
265
4
    }
266
6
    return;
267
6
  }
268
9
269
9
  if (Config->MipsN32Abi) {
270
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
271
2
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
272
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
273
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
274
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
275
2
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
276
7
  } else if (ELFT::Is64Bits) {
277
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
278
2
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
279
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
280
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
281
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
282
2
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
283
5
  } else {
284
5
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
285
5
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
286
5
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
287
5
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
288
5
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
289
5
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
290
5
  }
291
9
292
9
  uint32_t JalrInst = Config->ZHazardplt ? 
0x0320fc093
:
0x0320f8096
;
293
9
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
294
9
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
295
9
296
9
  uint64_t GotPlt = In.GotPlt->getVA();
297
9
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
298
9
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
299
9
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
300
9
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writePltHeader(unsigned char*) const
Line
Count
Source
240
2
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
241
2
  const endianness E = ELFT::TargetEndianness;
242
2
  if (isMicroMips()) {
243
2
    uint64_t GotPlt = In.GotPlt->getVA();
244
2
    uint64_t Plt = In.Plt->getVA();
245
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
246
2
    memset(Buf, 0, PltHeaderSize);
247
2
248
2
    write16<E>(Buf, isMipsR6() ? 
0x78601
:
0x79801
); // addiupc v1, (GOTPLT) - .
249
2
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
250
2
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
251
2
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
252
2
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
253
2
    write16<E>(Buf + 14, 0xfffe);
254
2
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
255
2
    if (isMipsR6()) {
256
1
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
257
1
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
258
1
      write16<E>(Buf + 22, 0x0c00); // nop
259
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
260
1
    } else {
261
1
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
262
1
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
263
1
      write16<E>(Buf + 22, 0x0c00); // nop
264
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
265
1
    }
266
2
    return;
267
2
  }
268
0
269
0
  if (Config->MipsN32Abi) {
270
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
271
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
272
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
273
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
274
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
275
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
276
0
  } else if (ELFT::Is64Bits) {
277
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
278
0
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
279
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
280
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
281
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
282
0
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
283
0
  } else {
284
0
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
285
0
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
286
0
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
287
0
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
288
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
289
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
290
0
  }
291
0
292
0
  uint32_t JalrInst = Config->ZHazardplt ? 0x0320fc09 : 0x0320f809;
293
0
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
294
0
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
295
0
296
0
  uint64_t GotPlt = In.GotPlt->getVA();
297
0
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
298
0
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
299
0
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
300
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writePltHeader(unsigned char*) const
Line
Count
Source
240
11
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
241
11
  const endianness E = ELFT::TargetEndianness;
242
11
  if (isMicroMips()) {
243
4
    uint64_t GotPlt = In.GotPlt->getVA();
244
4
    uint64_t Plt = In.Plt->getVA();
245
4
    // Overwrite trap instructions written by Writer::writeTrapInstr.
246
4
    memset(Buf, 0, PltHeaderSize);
247
4
248
4
    write16<E>(Buf, isMipsR6() ? 
0x78601
:
0x79803
); // addiupc v1, (GOTPLT) - .
249
4
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
250
4
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
251
4
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
252
4
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
253
4
    write16<E>(Buf + 14, 0xfffe);
254
4
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
255
4
    if (isMipsR6()) {
256
1
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
257
1
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
258
1
      write16<E>(Buf + 22, 0x0c00); // nop
259
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
260
3
    } else {
261
3
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
262
3
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
263
3
      write16<E>(Buf + 22, 0x0c00); // nop
264
3
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
265
3
    }
266
4
    return;
267
4
  }
268
7
269
7
  if (Config->MipsN32Abi) {
270
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
271
2
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
272
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
273
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
274
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
275
2
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
276
5
  } else if (ELFT::Is64Bits) {
277
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
278
0
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
279
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
280
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
281
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
282
0
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
283
5
  } else {
284
5
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
285
5
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
286
5
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
287
5
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
288
5
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
289
5
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
290
5
  }
291
7
292
7
  uint32_t JalrInst = Config->ZHazardplt ? 
0x0320fc092
:
0x0320f8095
;
293
7
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
294
7
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
295
7
296
7
  uint64_t GotPlt = In.GotPlt->getVA();
297
7
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
298
7
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
299
7
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
300
7
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writePltHeader(unsigned char*) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writePltHeader(unsigned char*) const
Line
Count
Source
240
2
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
241
2
  const endianness E = ELFT::TargetEndianness;
242
2
  if (isMicroMips()) {
243
0
    uint64_t GotPlt = In.GotPlt->getVA();
244
0
    uint64_t Plt = In.Plt->getVA();
245
0
    // Overwrite trap instructions written by Writer::writeTrapInstr.
246
0
    memset(Buf, 0, PltHeaderSize);
247
0
248
0
    write16<E>(Buf, isMipsR6() ? 0x7860 : 0x7980);  // addiupc v1, (GOTPLT) - .
249
0
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
250
0
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
251
0
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
252
0
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
253
0
    write16<E>(Buf + 14, 0xfffe);
254
0
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
255
0
    if (isMipsR6()) {
256
0
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
257
0
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
258
0
      write16<E>(Buf + 22, 0x0c00); // nop
259
0
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
260
0
    } else {
261
0
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
262
0
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
263
0
      write16<E>(Buf + 22, 0x0c00); // nop
264
0
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
265
0
    }
266
0
    return;
267
0
  }
268
2
269
2
  if (Config->MipsN32Abi) {
270
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
271
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
272
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
273
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
274
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
275
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
276
2
  } else if (ELFT::Is64Bits) {
277
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
278
2
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
279
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
280
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
281
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
282
2
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
283
2
  } else {
284
0
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
285
0
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
286
0
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
287
0
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
288
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
289
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
290
0
  }
291
2
292
2
  uint32_t JalrInst = Config->ZHazardplt ? 
0x0320fc091
:
0x0320f8091
;
293
2
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
294
2
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
295
2
296
2
  uint64_t GotPlt = In.GotPlt->getVA();
297
2
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
298
2
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
299
2
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
300
2
}
301
302
template <class ELFT>
303
void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
304
                          uint64_t PltEntryAddr, int32_t Index,
305
17
                          unsigned RelOff) const {
306
17
  const endianness E = ELFT::TargetEndianness;
307
17
  if (isMicroMips()) {
308
6
    // Overwrite trap instructions written by Writer::writeTrapInstr.
309
6
    memset(Buf, 0, PltEntrySize);
310
6
311
6
    if (isMipsR6()) {
312
2
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
313
2
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
314
2
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
315
2
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
316
2
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
317
4
    } else {
318
4
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
319
4
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
320
4
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
321
4
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
322
4
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
323
4
    }
324
6
    return;
325
6
  }
326
11
327
11
  uint32_t JrInst = isMipsR6() ? 
(Config->ZHazardplt 2
?
0x032004091
:
0x032000091
)
328
11
                               : 
(Config->ZHazardplt 9
?
0x032004082
:
0x032000087
);
329
11
330
11
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
331
11
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
332
11
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
333
11
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
334
11
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
335
11
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
336
11
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
337
11
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
305
2
                          unsigned RelOff) const {
306
2
  const endianness E = ELFT::TargetEndianness;
307
2
  if (isMicroMips()) {
308
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
309
2
    memset(Buf, 0, PltEntrySize);
310
2
311
2
    if (isMipsR6()) {
312
1
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
313
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
314
1
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
315
1
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
316
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
317
1
    } else {
318
1
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
319
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
320
1
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
321
1
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
322
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
323
1
    }
324
2
    return;
325
2
  }
326
0
327
0
  uint32_t JrInst = isMipsR6() ? (Config->ZHazardplt ? 0x03200409 : 0x03200009)
328
0
                               : (Config->ZHazardplt ? 0x03200408 : 0x03200008);
329
0
330
0
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
331
0
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
332
0
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
333
0
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
334
0
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
335
0
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
336
0
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
337
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
305
13
                          unsigned RelOff) const {
306
13
  const endianness E = ELFT::TargetEndianness;
307
13
  if (isMicroMips()) {
308
4
    // Overwrite trap instructions written by Writer::writeTrapInstr.
309
4
    memset(Buf, 0, PltEntrySize);
310
4
311
4
    if (isMipsR6()) {
312
1
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
313
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
314
1
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
315
1
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
316
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
317
3
    } else {
318
3
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
319
3
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
320
3
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
321
3
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
322
3
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
323
3
    }
324
4
    return;
325
4
  }
326
9
327
9
  uint32_t JrInst = isMipsR6() ? 
(Config->ZHazardplt 2
?
0x032004091
:
0x032000091
)
328
9
                               : 
(Config->ZHazardplt 7
?
0x032004081
:
0x032000086
);
329
9
330
9
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
331
9
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
332
9
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
333
9
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
334
9
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
335
9
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
336
9
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
337
9
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
305
2
                          unsigned RelOff) const {
306
2
  const endianness E = ELFT::TargetEndianness;
307
2
  if (isMicroMips()) {
308
0
    // Overwrite trap instructions written by Writer::writeTrapInstr.
309
0
    memset(Buf, 0, PltEntrySize);
310
0
311
0
    if (isMipsR6()) {
312
0
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
313
0
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
314
0
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
315
0
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
316
0
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
317
0
    } else {
318
0
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
319
0
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
320
0
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
321
0
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
322
0
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
323
0
    }
324
0
    return;
325
0
  }
326
2
327
2
  uint32_t JrInst = isMipsR6() ? 
(Config->ZHazardplt 0
?
0x032004090
:
0x032000090
)
328
2
                               : (Config->ZHazardplt ? 
0x032004081
:
0x032000081
);
329
2
330
2
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
331
2
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
332
2
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
333
2
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
334
2
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
335
2
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
336
2
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
337
2
}
338
339
template <class ELFT>
340
bool MIPS<ELFT>::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
341
10.3k
                            uint64_t BranchAddr, const Symbol &S) const {
342
10.3k
  // Any MIPS PIC code function is invoked with its address in register $t9.
343
10.3k
  // So if we have a branch instruction from non-PIC code to the PIC one
344
10.3k
  // we cannot make the jump directly and need to create a small stubs
345
10.3k
  // to save the target function address.
346
10.3k
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
347
10.3k
  if (Type != R_MIPS_26 && 
Type != R_MICROMIPS_26_S110.2k
&&
348
10.3k
      
Type != R_MICROMIPS_PC26_S110.2k
)
349
10.2k
    return false;
350
73
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
351
73
  if (!F)
352
0
    return false;
353
73
  // If current file has PIC code, LA25 stub is not required.
354
73
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
355
0
    return false;
356
73
  auto *D = dyn_cast<Defined>(&S);
357
73
  // LA25 is required if target file has PIC code
358
73
  // or target symbol is a PIC symbol.
359
73
  return D && 
isMipsPIC<ELFT>(D)60
;
360
73
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Line
Count
Source
341
18
                            uint64_t BranchAddr, const Symbol &S) const {
342
18
  // Any MIPS PIC code function is invoked with its address in register $t9.
343
18
  // So if we have a branch instruction from non-PIC code to the PIC one
344
18
  // we cannot make the jump directly and need to create a small stubs
345
18
  // to save the target function address.
346
18
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
347
18
  if (Type != R_MIPS_26 && Type != R_MICROMIPS_26_S1 &&
348
18
      
Type != R_MICROMIPS_PC26_S116
)
349
13
    return false;
350
5
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
351
5
  if (!F)
352
0
    return false;
353
5
  // If current file has PIC code, LA25 stub is not required.
354
5
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
355
0
    return false;
356
5
  auto *D = dyn_cast<Defined>(&S);
357
5
  // LA25 is required if target file has PIC code
358
5
  // or target symbol is a PIC symbol.
359
5
  return D && 
isMipsPIC<ELFT>(D)3
;
360
5
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Line
Count
Source
341
248
                            uint64_t BranchAddr, const Symbol &S) const {
342
248
  // Any MIPS PIC code function is invoked with its address in register $t9.
343
248
  // So if we have a branch instruction from non-PIC code to the PIC one
344
248
  // we cannot make the jump directly and need to create a small stubs
345
248
  // to save the target function address.
346
248
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
347
248
  if (Type != R_MIPS_26 && 
Type != R_MICROMIPS_26_S1189
&&
348
248
      
Type != R_MICROMIPS_PC26_S1185
)
349
182
    return false;
350
66
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
351
66
  if (!F)
352
0
    return false;
353
66
  // If current file has PIC code, LA25 stub is not required.
354
66
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
355
0
    return false;
356
66
  auto *D = dyn_cast<Defined>(&S);
357
66
  // LA25 is required if target file has PIC code
358
66
  // or target symbol is a PIC symbol.
359
66
  return D && 
isMipsPIC<ELFT>(D)57
;
360
66
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Line
Count
Source
341
10.0k
                            uint64_t BranchAddr, const Symbol &S) const {
342
10.0k
  // Any MIPS PIC code function is invoked with its address in register $t9.
343
10.0k
  // So if we have a branch instruction from non-PIC code to the PIC one
344
10.0k
  // we cannot make the jump directly and need to create a small stubs
345
10.0k
  // to save the target function address.
346
10.0k
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
347
10.0k
  if (Type != R_MIPS_26 && 
Type != R_MICROMIPS_26_S110.0k
&&
348
10.0k
      
Type != R_MICROMIPS_PC26_S110.0k
)
349
10.0k
    return false;
350
2
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
351
2
  if (!F)
352
0
    return false;
353
2
  // If current file has PIC code, LA25 stub is not required.
354
2
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
355
0
    return false;
356
2
  auto *D = dyn_cast<Defined>(&S);
357
2
  // LA25 is required if target file has PIC code
358
2
  // or target symbol is a PIC symbol.
359
2
  return D && 
isMipsPIC<ELFT>(D)0
;
360
2
}
361
362
template <class ELFT>
363
330
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
364
330
  const endianness E = ELFT::TargetEndianness;
365
330
  switch (Type) {
366
330
  case R_MIPS_32:
367
27
  case R_MIPS_GPREL32:
368
27
  case R_MIPS_TLS_DTPREL32:
369
27
  case R_MIPS_TLS_TPREL32:
370
27
    return SignExtend64<32>(read32<E>(Buf));
371
50
  case R_MIPS_26:
372
50
    // FIXME (simon): If the relocation target symbol is not a PLT entry
373
50
    // we should use another expression for calculation:
374
50
    // ((A << 2) | (P & 0xf0000000)) >> 2
375
50
    return SignExtend64<28>(read32<E>(Buf) << 2);
376
66
  case R_MIPS_GOT16:
377
66
  case R_MIPS_HI16:
378
66
  case R_MIPS_PCHI16:
379
66
    return SignExtend64<16>(read32<E>(Buf)) << 16;
380
90
  case R_MIPS_GPREL16:
381
90
  case R_MIPS_LO16:
382
90
  case R_MIPS_PCLO16:
383
90
  case R_MIPS_TLS_DTPREL_HI16:
384
90
  case R_MIPS_TLS_DTPREL_LO16:
385
90
  case R_MIPS_TLS_TPREL_HI16:
386
90
  case R_MIPS_TLS_TPREL_LO16:
387
90
    return SignExtend64<16>(read32<E>(Buf));
388
90
  case R_MICROMIPS_GOT16:
389
7
  case R_MICROMIPS_HI16:
390
7
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
391
9
  case R_MICROMIPS_GPREL16:
392
9
  case R_MICROMIPS_LO16:
393
9
  case R_MICROMIPS_TLS_DTPREL_HI16:
394
9
  case R_MICROMIPS_TLS_DTPREL_LO16:
395
9
  case R_MICROMIPS_TLS_TPREL_HI16:
396
9
  case R_MICROMIPS_TLS_TPREL_LO16:
397
9
    return SignExtend64<16>(readShuffle<E>(Buf));
398
9
  case R_MICROMIPS_GPREL7_S2:
399
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
400
9
  case R_MIPS_PC16:
401
2
    return SignExtend64<18>(read32<E>(Buf) << 2);
402
9
  case R_MIPS_PC19_S2:
403
1
    return SignExtend64<21>(read32<E>(Buf) << 2);
404
9
  case R_MIPS_PC21_S2:
405
1
    return SignExtend64<23>(read32<E>(Buf) << 2);
406
9
  case R_MIPS_PC26_S2:
407
1
    return SignExtend64<28>(read32<E>(Buf) << 2);
408
9
  case R_MIPS_PC32:
409
1
    return SignExtend64<32>(read32<E>(Buf));
410
9
  case R_MICROMIPS_26_S1:
411
6
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
412
9
  case R_MICROMIPS_PC7_S1:
413
2
    return SignExtend64<8>(read16<E>(Buf) << 1);
414
9
  case R_MICROMIPS_PC10_S1:
415
2
    return SignExtend64<11>(read16<E>(Buf) << 1);
416
9
  case R_MICROMIPS_PC16_S1:
417
2
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
418
9
  case R_MICROMIPS_PC18_S3:
419
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
420
9
  case R_MICROMIPS_PC19_S2:
421
2
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
422
9
  case R_MICROMIPS_PC21_S1:
423
2
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
424
9
  case R_MICROMIPS_PC23_S2:
425
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
426
9
  case R_MICROMIPS_PC26_S1:
427
6
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
428
53
  default:
429
53
    return 0;
430
330
  }
431
330
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getImplicitAddend(unsigned char const*, unsigned int) const
Line
Count
Source
363
21
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
364
21
  const endianness E = ELFT::TargetEndianness;
365
21
  switch (Type) {
366
21
  case R_MIPS_32:
367
2
  case R_MIPS_GPREL32:
368
2
  case R_MIPS_TLS_DTPREL32:
369
2
  case R_MIPS_TLS_TPREL32:
370
2
    return SignExtend64<32>(read32<E>(Buf));
371
2
  case R_MIPS_26:
372
0
    // FIXME (simon): If the relocation target symbol is not a PLT entry
373
0
    // we should use another expression for calculation:
374
0
    // ((A << 2) | (P & 0xf0000000)) >> 2
375
0
    return SignExtend64<28>(read32<E>(Buf) << 2);
376
4
  case R_MIPS_GOT16:
377
4
  case R_MIPS_HI16:
378
4
  case R_MIPS_PCHI16:
379
4
    return SignExtend64<16>(read32<E>(Buf)) << 16;
380
4
  case R_MIPS_GPREL16:
381
0
  case R_MIPS_LO16:
382
0
  case R_MIPS_PCLO16:
383
0
  case R_MIPS_TLS_DTPREL_HI16:
384
0
  case R_MIPS_TLS_DTPREL_LO16:
385
0
  case R_MIPS_TLS_TPREL_HI16:
386
0
  case R_MIPS_TLS_TPREL_LO16:
387
0
    return SignExtend64<16>(read32<E>(Buf));
388
2
  case R_MICROMIPS_GOT16:
389
2
  case R_MICROMIPS_HI16:
390
2
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
391
2
  case R_MICROMIPS_GPREL16:
392
2
  case R_MICROMIPS_LO16:
393
2
  case R_MICROMIPS_TLS_DTPREL_HI16:
394
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
395
2
  case R_MICROMIPS_TLS_TPREL_HI16:
396
2
  case R_MICROMIPS_TLS_TPREL_LO16:
397
2
    return SignExtend64<16>(readShuffle<E>(Buf));
398
2
  case R_MICROMIPS_GPREL7_S2:
399
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
400
2
  case R_MIPS_PC16:
401
0
    return SignExtend64<18>(read32<E>(Buf) << 2);
402
2
  case R_MIPS_PC19_S2:
403
0
    return SignExtend64<21>(read32<E>(Buf) << 2);
404
2
  case R_MIPS_PC21_S2:
405
0
    return SignExtend64<23>(read32<E>(Buf) << 2);
406
2
  case R_MIPS_PC26_S2:
407
0
    return SignExtend64<28>(read32<E>(Buf) << 2);
408
2
  case R_MIPS_PC32:
409
0
    return SignExtend64<32>(read32<E>(Buf));
410
2
  case R_MICROMIPS_26_S1:
411
2
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
412
2
  case R_MICROMIPS_PC7_S1:
413
1
    return SignExtend64<8>(read16<E>(Buf) << 1);
414
2
  case R_MICROMIPS_PC10_S1:
415
1
    return SignExtend64<11>(read16<E>(Buf) << 1);
416
2
  case R_MICROMIPS_PC16_S1:
417
1
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
418
2
  case R_MICROMIPS_PC18_S3:
419
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
420
2
  case R_MICROMIPS_PC19_S2:
421
1
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
422
2
  case R_MICROMIPS_PC21_S1:
423
1
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
424
2
  case R_MICROMIPS_PC23_S2:
425
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
426
3
  case R_MICROMIPS_PC26_S1:
427
3
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
428
2
  default:
429
1
    return 0;
430
21
  }
431
21
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getImplicitAddend(unsigned char const*, unsigned int) const
Line
Count
Source
363
309
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
364
309
  const endianness E = ELFT::TargetEndianness;
365
309
  switch (Type) {
366
309
  case R_MIPS_32:
367
25
  case R_MIPS_GPREL32:
368
25
  case R_MIPS_TLS_DTPREL32:
369
25
  case R_MIPS_TLS_TPREL32:
370
25
    return SignExtend64<32>(read32<E>(Buf));
371
50
  case R_MIPS_26:
372
50
    // FIXME (simon): If the relocation target symbol is not a PLT entry
373
50
    // we should use another expression for calculation:
374
50
    // ((A << 2) | (P & 0xf0000000)) >> 2
375
50
    return SignExtend64<28>(read32<E>(Buf) << 2);
376
62
  case R_MIPS_GOT16:
377
62
  case R_MIPS_HI16:
378
62
  case R_MIPS_PCHI16:
379
62
    return SignExtend64<16>(read32<E>(Buf)) << 16;
380
90
  case R_MIPS_GPREL16:
381
90
  case R_MIPS_LO16:
382
90
  case R_MIPS_PCLO16:
383
90
  case R_MIPS_TLS_DTPREL_HI16:
384
90
  case R_MIPS_TLS_DTPREL_LO16:
385
90
  case R_MIPS_TLS_TPREL_HI16:
386
90
  case R_MIPS_TLS_TPREL_LO16:
387
90
    return SignExtend64<16>(read32<E>(Buf));
388
90
  case R_MICROMIPS_GOT16:
389
5
  case R_MICROMIPS_HI16:
390
5
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
391
7
  case R_MICROMIPS_GPREL16:
392
7
  case R_MICROMIPS_LO16:
393
7
  case R_MICROMIPS_TLS_DTPREL_HI16:
394
7
  case R_MICROMIPS_TLS_DTPREL_LO16:
395
7
  case R_MICROMIPS_TLS_TPREL_HI16:
396
7
  case R_MICROMIPS_TLS_TPREL_LO16:
397
7
    return SignExtend64<16>(readShuffle<E>(Buf));
398
7
  case R_MICROMIPS_GPREL7_S2:
399
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
400
7
  case R_MIPS_PC16:
401
2
    return SignExtend64<18>(read32<E>(Buf) << 2);
402
7
  case R_MIPS_PC19_S2:
403
1
    return SignExtend64<21>(read32<E>(Buf) << 2);
404
7
  case R_MIPS_PC21_S2:
405
1
    return SignExtend64<23>(read32<E>(Buf) << 2);
406
7
  case R_MIPS_PC26_S2:
407
1
    return SignExtend64<28>(read32<E>(Buf) << 2);
408
7
  case R_MIPS_PC32:
409
1
    return SignExtend64<32>(read32<E>(Buf));
410
7
  case R_MICROMIPS_26_S1:
411
4
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
412
7
  case R_MICROMIPS_PC7_S1:
413
1
    return SignExtend64<8>(read16<E>(Buf) << 1);
414
7
  case R_MICROMIPS_PC10_S1:
415
1
    return SignExtend64<11>(read16<E>(Buf) << 1);
416
7
  case R_MICROMIPS_PC16_S1:
417
1
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
418
7
  case R_MICROMIPS_PC18_S3:
419
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
420
7
  case R_MICROMIPS_PC19_S2:
421
1
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
422
7
  case R_MICROMIPS_PC21_S1:
423
1
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
424
7
  case R_MICROMIPS_PC23_S2:
425
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
426
7
  case R_MICROMIPS_PC26_S1:
427
3
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
428
52
  default:
429
52
    return 0;
430
309
  }
431
309
}
432
433
static std::pair<uint32_t, uint64_t>
434
10.0k
calculateMipsRelChain(uint8_t *Loc, RelType Type, uint64_t Val) {
435
10.0k
  // MIPS N64 ABI packs multiple relocations into the single relocation
436
10.0k
  // record. In general, all up to three relocations can have arbitrary
437
10.0k
  // types. In fact, Clang and GCC uses only a few combinations. For now,
438
10.0k
  // we support two of them. That is allow to pass at least all LLVM
439
10.0k
  // test suite cases.
440
10.0k
  // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
441
10.0k
  // <any relocation> / R_MIPS_64 / R_MIPS_NONE
442
10.0k
  // The first relocation is a 'real' relocation which is calculated
443
10.0k
  // using the corresponding symbol's value. The second and the third
444
10.0k
  // relocations used to modify result of the first one: extend it to
445
10.0k
  // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
446
10.0k
  // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
447
10.0k
  RelType Type2 = (Type >> 8) & 0xff;
448
10.0k
  RelType Type3 = (Type >> 16) & 0xff;
449
10.0k
  if (Type2 == R_MIPS_NONE && 
Type3 == R_MIPS_NONE10.0k
)
450
10.0k
    return std::make_pair(Type, Val);
451
12
  if (Type2 == R_MIPS_64 && 
Type3 == R_MIPS_NONE1
)
452
1
    return std::make_pair(Type2, Val);
453
11
  if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || 
Type3 == R_MIPS_LO164
))
454
11
    return std::make_pair(Type3, -Val);
455
0
  error(getErrorLocation(Loc) + "unsupported relocations combination " +
456
0
        Twine(Type));
457
0
  return std::make_pair(Type & 0xff, Val);
458
0
}
459
460
template <class ELFT>
461
10.4k
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
462
10.4k
  const endianness E = ELFT::TargetEndianness;
463
10.4k
464
10.4k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi374
)
465
10.0k
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
466
10.4k
467
10.4k
  // Thread pointer and DRP offsets from the start of TLS data area.
468
10.4k
  // https://www.linux-mips.org/wiki/NPTL
469
10.4k
  if (Type == R_MIPS_TLS_DTPREL_HI16 || 
Type == R_MIPS_TLS_DTPREL_LO1610.4k
||
470
10.4k
      
Type == R_MIPS_TLS_DTPREL3210.4k
||
Type == R_MIPS_TLS_DTPREL6410.4k
||
471
10.4k
      
Type == R_MICROMIPS_TLS_DTPREL_HI1610.4k
||
472
10.4k
      
Type == R_MICROMIPS_TLS_DTPREL_LO1610.4k
) {
473
6
    Val -= 0x8000;
474
10.4k
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || 
Type == R_MIPS_TLS_TPREL_LO1610.4k
||
475
10.4k
             
Type == R_MIPS_TLS_TPREL3210.4k
||
Type == R_MIPS_TLS_TPREL6410.4k
||
476
10.4k
             
Type == R_MICROMIPS_TLS_TPREL_HI1610.4k
||
477
10.4k
             
Type == R_MICROMIPS_TLS_TPREL_LO1610.4k
) {
478
6
    Val -= 0x7000;
479
6
  }
480
10.4k
481
10.4k
  switch (Type) {
482
10.4k
  case R_MIPS_32:
483
31
  case R_MIPS_GPREL32:
484
31
  case R_MIPS_TLS_DTPREL32:
485
31
  case R_MIPS_TLS_TPREL32:
486
31
    write32<E>(Loc, Val);
487
31
    break;
488
31
  case R_MIPS_64:
489
8
  case R_MIPS_TLS_DTPREL64:
490
8
  case R_MIPS_TLS_TPREL64:
491
8
    write64<E>(Loc, Val);
492
8
    break;
493
54
  case R_MIPS_26:
494
54
    writeValue<E>(Loc, Val, 26, 2);
495
54
    break;
496
42
  case R_MIPS_GOT16:
497
42
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
498
42
    // is updated addend (not a GOT index). In that case write high 16 bits
499
42
    // to store a correct addend value.
500
42
    if (Config->Relocatable) {
501
2
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
502
40
    } else {
503
40
      checkInt(Loc, Val, 16, Type);
504
40
      writeValue<E>(Loc, Val, 16, 0);
505
40
    }
506
42
    break;
507
8
  case R_MICROMIPS_GOT16:
508
4
    if (Config->Relocatable) {
509
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
510
4
    } else {
511
4
      checkInt(Loc, Val, 16, Type);
512
4
      writeShuffleValue<E>(Loc, Val, 16, 0);
513
4
    }
514
4
    break;
515
10.0k
  case R_MIPS_CALL16:
516
10.0k
  case R_MIPS_GOT_DISP:
517
10.0k
  case R_MIPS_GOT_PAGE:
518
10.0k
  case R_MIPS_GPREL16:
519
10.0k
  case R_MIPS_TLS_GD:
520
10.0k
  case R_MIPS_TLS_GOTTPREL:
521
10.0k
  case R_MIPS_TLS_LDM:
522
10.0k
    checkInt(Loc, Val, 16, Type);
523
10.0k
    LLVM_FALLTHROUGH;
524
10.1k
  case R_MIPS_CALL_LO16:
525
10.1k
  case R_MIPS_GOT_LO16:
526
10.1k
  case R_MIPS_GOT_OFST:
527
10.1k
  case R_MIPS_LO16:
528
10.1k
  case R_MIPS_PCLO16:
529
10.1k
  case R_MIPS_TLS_DTPREL_LO16:
530
10.1k
  case R_MIPS_TLS_TPREL_LO16:
531
10.1k
    writeValue<E>(Loc, Val, 16, 0);
532
10.1k
    break;
533
10.1k
  case R_MICROMIPS_GPREL16:
534
0
  case R_MICROMIPS_TLS_GD:
535
0
  case R_MICROMIPS_TLS_LDM:
536
0
    checkInt(Loc, Val, 16, Type);
537
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
538
0
    break;
539
12
  case R_MICROMIPS_CALL16:
540
12
  case R_MICROMIPS_CALL_LO16:
541
12
  case R_MICROMIPS_LO16:
542
12
  case R_MICROMIPS_TLS_DTPREL_LO16:
543
12
  case R_MICROMIPS_TLS_GOTTPREL:
544
12
  case R_MICROMIPS_TLS_TPREL_LO16:
545
12
    writeShuffleValue<E>(Loc, Val, 16, 0);
546
12
    break;
547
12
  case R_MICROMIPS_GPREL7_S2:
548
0
    checkInt(Loc, Val, 7, Type);
549
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
550
0
    break;
551
72
  case R_MIPS_CALL_HI16:
552
72
  case R_MIPS_GOT_HI16:
553
72
  case R_MIPS_HI16:
554
72
  case R_MIPS_PCHI16:
555
72
  case R_MIPS_TLS_DTPREL_HI16:
556
72
  case R_MIPS_TLS_TPREL_HI16:
557
72
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
558
72
    break;
559
72
  case R_MICROMIPS_CALL_HI16:
560
7
  case R_MICROMIPS_GOT_HI16:
561
7
  case R_MICROMIPS_HI16:
562
7
  case R_MICROMIPS_TLS_DTPREL_HI16:
563
7
  case R_MICROMIPS_TLS_TPREL_HI16:
564
7
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
565
7
    break;
566
7
  case R_MIPS_HIGHER:
567
2
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
568
2
    break;
569
7
  case R_MIPS_HIGHEST:
570
2
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
571
2
    break;
572
7
  case R_MIPS_JALR:
573
0
  case R_MICROMIPS_JALR:
574
0
    // Ignore this optimization relocation for now
575
0
    break;
576
2
  case R_MIPS_PC16:
577
2
    checkAlignment(Loc, Val, 4, Type);
578
2
    checkInt(Loc, Val, 18, Type);
579
2
    writeValue<E>(Loc, Val, 16, 2);
580
2
    break;
581
1
  case R_MIPS_PC19_S2:
582
1
    checkAlignment(Loc, Val, 4, Type);
583
1
    checkInt(Loc, Val, 21, Type);
584
1
    writeValue<E>(Loc, Val, 19, 2);
585
1
    break;
586
1
  case R_MIPS_PC21_S2:
587
1
    checkAlignment(Loc, Val, 4, Type);
588
1
    checkInt(Loc, Val, 23, Type);
589
1
    writeValue<E>(Loc, Val, 21, 2);
590
1
    break;
591
1
  case R_MIPS_PC26_S2:
592
1
    checkAlignment(Loc, Val, 4, Type);
593
1
    checkInt(Loc, Val, 28, Type);
594
1
    writeValue<E>(Loc, Val, 26, 2);
595
1
    break;
596
2
  case R_MIPS_PC32:
597
2
    writeValue<E>(Loc, Val, 32, 0);
598
2
    break;
599
16
  case R_MICROMIPS_26_S1:
600
16
  case R_MICROMIPS_PC26_S1:
601
16
    checkInt(Loc, Val, 27, Type);
602
16
    writeShuffleValue<E>(Loc, Val, 26, 1);
603
16
    break;
604
16
  case R_MICROMIPS_PC7_S1:
605
2
    checkInt(Loc, Val, 8, Type);
606
2
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
607
2
    break;
608
16
  case R_MICROMIPS_PC10_S1:
609
2
    checkInt(Loc, Val, 11, Type);
610
2
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
611
2
    break;
612
16
  case R_MICROMIPS_PC16_S1:
613
2
    checkInt(Loc, Val, 17, Type);
614
2
    writeShuffleValue<E>(Loc, Val, 16, 1);
615
2
    break;
616
16
  case R_MICROMIPS_PC18_S3:
617
0
    checkInt(Loc, Val, 21, Type);
618
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
619
0
    break;
620
16
  case R_MICROMIPS_PC19_S2:
621
6
    checkInt(Loc, Val, 21, Type);
622
6
    writeShuffleValue<E>(Loc, Val, 19, 2);
623
6
    break;
624
16
  case R_MICROMIPS_PC21_S1:
625
2
    checkInt(Loc, Val, 22, Type);
626
2
    writeShuffleValue<E>(Loc, Val, 21, 1);
627
2
    break;
628
16
  case R_MICROMIPS_PC23_S2:
629
8
    checkInt(Loc, Val, 25, Type);
630
8
    writeShuffleValue<E>(Loc, Val, 23, 2);
631
8
    break;
632
16
  default:
633
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
634
10.4k
  }
635
10.4k
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
461
30
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
462
30
  const endianness E = ELFT::TargetEndianness;
463
30
464
30
  if (ELFT::Is64Bits || Config->MipsN32Abi)
465
0
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
466
30
467
30
  // Thread pointer and DRP offsets from the start of TLS data area.
468
30
  // https://www.linux-mips.org/wiki/NPTL
469
30
  if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
470
30
      Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 ||
471
30
      Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
472
30
      Type == R_MICROMIPS_TLS_DTPREL_LO16) {
473
0
    Val -= 0x8000;
474
30
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
475
30
             Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 ||
476
30
             Type == R_MICROMIPS_TLS_TPREL_HI16 ||
477
30
             Type == R_MICROMIPS_TLS_TPREL_LO16) {
478
0
    Val -= 0x7000;
479
0
  }
480
30
481
30
  switch (Type) {
482
30
  case R_MIPS_32:
483
2
  case R_MIPS_GPREL32:
484
2
  case R_MIPS_TLS_DTPREL32:
485
2
  case R_MIPS_TLS_TPREL32:
486
2
    write32<E>(Loc, Val);
487
2
    break;
488
2
  case R_MIPS_64:
489
0
  case R_MIPS_TLS_DTPREL64:
490
0
  case R_MIPS_TLS_TPREL64:
491
0
    write64<E>(Loc, Val);
492
0
    break;
493
0
  case R_MIPS_26:
494
0
    writeValue<E>(Loc, Val, 26, 2);
495
0
    break;
496
4
  case R_MIPS_GOT16:
497
4
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
498
4
    // is updated addend (not a GOT index). In that case write high 16 bits
499
4
    // to store a correct addend value.
500
4
    if (Config->Relocatable) {
501
0
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
502
4
    } else {
503
4
      checkInt(Loc, Val, 16, Type);
504
4
      writeValue<E>(Loc, Val, 16, 0);
505
4
    }
506
4
    break;
507
1
  case R_MICROMIPS_GOT16:
508
1
    if (Config->Relocatable) {
509
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
510
1
    } else {
511
1
      checkInt(Loc, Val, 16, Type);
512
1
      writeShuffleValue<E>(Loc, Val, 16, 0);
513
1
    }
514
1
    break;
515
0
  case R_MIPS_CALL16:
516
0
  case R_MIPS_GOT_DISP:
517
0
  case R_MIPS_GOT_PAGE:
518
0
  case R_MIPS_GPREL16:
519
0
  case R_MIPS_TLS_GD:
520
0
  case R_MIPS_TLS_GOTTPREL:
521
0
  case R_MIPS_TLS_LDM:
522
0
    checkInt(Loc, Val, 16, Type);
523
0
    LLVM_FALLTHROUGH;
524
0
  case R_MIPS_CALL_LO16:
525
0
  case R_MIPS_GOT_LO16:
526
0
  case R_MIPS_GOT_OFST:
527
0
  case R_MIPS_LO16:
528
0
  case R_MIPS_PCLO16:
529
0
  case R_MIPS_TLS_DTPREL_LO16:
530
0
  case R_MIPS_TLS_TPREL_LO16:
531
0
    writeValue<E>(Loc, Val, 16, 0);
532
0
    break;
533
0
  case R_MICROMIPS_GPREL16:
534
0
  case R_MICROMIPS_TLS_GD:
535
0
  case R_MICROMIPS_TLS_LDM:
536
0
    checkInt(Loc, Val, 16, Type);
537
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
538
0
    break;
539
4
  case R_MICROMIPS_CALL16:
540
4
  case R_MICROMIPS_CALL_LO16:
541
4
  case R_MICROMIPS_LO16:
542
4
  case R_MICROMIPS_TLS_DTPREL_LO16:
543
4
  case R_MICROMIPS_TLS_GOTTPREL:
544
4
  case R_MICROMIPS_TLS_TPREL_LO16:
545
4
    writeShuffleValue<E>(Loc, Val, 16, 0);
546
4
    break;
547
4
  case R_MICROMIPS_GPREL7_S2:
548
0
    checkInt(Loc, Val, 7, Type);
549
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
550
0
    break;
551
4
  case R_MIPS_CALL_HI16:
552
0
  case R_MIPS_GOT_HI16:
553
0
  case R_MIPS_HI16:
554
0
  case R_MIPS_PCHI16:
555
0
  case R_MIPS_TLS_DTPREL_HI16:
556
0
  case R_MIPS_TLS_TPREL_HI16:
557
0
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
558
0
    break;
559
3
  case R_MICROMIPS_CALL_HI16:
560
3
  case R_MICROMIPS_GOT_HI16:
561
3
  case R_MICROMIPS_HI16:
562
3
  case R_MICROMIPS_TLS_DTPREL_HI16:
563
3
  case R_MICROMIPS_TLS_TPREL_HI16:
564
3
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
565
3
    break;
566
3
  case R_MIPS_HIGHER:
567
0
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
568
0
    break;
569
3
  case R_MIPS_HIGHEST:
570
0
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
571
0
    break;
572
3
  case R_MIPS_JALR:
573
0
  case R_MICROMIPS_JALR:
574
0
    // Ignore this optimization relocation for now
575
0
    break;
576
0
  case R_MIPS_PC16:
577
0
    checkAlignment(Loc, Val, 4, Type);
578
0
    checkInt(Loc, Val, 18, Type);
579
0
    writeValue<E>(Loc, Val, 16, 2);
580
0
    break;
581
0
  case R_MIPS_PC19_S2:
582
0
    checkAlignment(Loc, Val, 4, Type);
583
0
    checkInt(Loc, Val, 21, Type);
584
0
    writeValue<E>(Loc, Val, 19, 2);
585
0
    break;
586
0
  case R_MIPS_PC21_S2:
587
0
    checkAlignment(Loc, Val, 4, Type);
588
0
    checkInt(Loc, Val, 23, Type);
589
0
    writeValue<E>(Loc, Val, 21, 2);
590
0
    break;
591
0
  case R_MIPS_PC26_S2:
592
0
    checkAlignment(Loc, Val, 4, Type);
593
0
    checkInt(Loc, Val, 28, Type);
594
0
    writeValue<E>(Loc, Val, 26, 2);
595
0
    break;
596
0
  case R_MIPS_PC32:
597
0
    writeValue<E>(Loc, Val, 32, 0);
598
0
    break;
599
7
  case R_MICROMIPS_26_S1:
600
7
  case R_MICROMIPS_PC26_S1:
601
7
    checkInt(Loc, Val, 27, Type);
602
7
    writeShuffleValue<E>(Loc, Val, 26, 1);
603
7
    break;
604
7
  case R_MICROMIPS_PC7_S1:
605
1
    checkInt(Loc, Val, 8, Type);
606
1
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
607
1
    break;
608
7
  case R_MICROMIPS_PC10_S1:
609
1
    checkInt(Loc, Val, 11, Type);
610
1
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
611
1
    break;
612
7
  case R_MICROMIPS_PC16_S1:
613
1
    checkInt(Loc, Val, 17, Type);
614
1
    writeShuffleValue<E>(Loc, Val, 16, 1);
615
1
    break;
616
7
  case R_MICROMIPS_PC18_S3:
617
0
    checkInt(Loc, Val, 21, Type);
618
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
619
0
    break;
620
7
  case R_MICROMIPS_PC19_S2:
621
3
    checkInt(Loc, Val, 21, Type);
622
3
    writeShuffleValue<E>(Loc, Val, 19, 2);
623
3
    break;
624
7
  case R_MICROMIPS_PC21_S1:
625
1
    checkInt(Loc, Val, 22, Type);
626
1
    writeShuffleValue<E>(Loc, Val, 21, 1);
627
1
    break;
628
7
  case R_MICROMIPS_PC23_S2:
629
2
    checkInt(Loc, Val, 25, Type);
630
2
    writeShuffleValue<E>(Loc, Val, 23, 2);
631
2
    break;
632
7
  default:
633
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
634
30
  }
635
30
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
461
344
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
462
344
  const endianness E = ELFT::TargetEndianness;
463
344
464
344
  if (ELFT::Is64Bits || Config->MipsN32Abi)
465
5
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
466
344
467
344
  // Thread pointer and DRP offsets from the start of TLS data area.
468
344
  // https://www.linux-mips.org/wiki/NPTL
469
344
  if (Type == R_MIPS_TLS_DTPREL_HI16 || 
Type == R_MIPS_TLS_DTPREL_LO16342
||
470
344
      
Type == R_MIPS_TLS_DTPREL32340
||
Type == R_MIPS_TLS_DTPREL64339
||
471
344
      
Type == R_MICROMIPS_TLS_DTPREL_HI16339
||
472
344
      
Type == R_MICROMIPS_TLS_DTPREL_LO16339
) {
473
5
    Val -= 0x8000;
474
339
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || 
Type == R_MIPS_TLS_TPREL_LO16337
||
475
339
             
Type == R_MIPS_TLS_TPREL32335
||
Type == R_MIPS_TLS_TPREL64334
||
476
339
             
Type == R_MICROMIPS_TLS_TPREL_HI16334
||
477
339
             
Type == R_MICROMIPS_TLS_TPREL_LO16334
) {
478
5
    Val -= 0x7000;
479
5
  }
480
344
481
344
  switch (Type) {
482
344
  case R_MIPS_32:
483
26
  case R_MIPS_GPREL32:
484
26
  case R_MIPS_TLS_DTPREL32:
485
26
  case R_MIPS_TLS_TPREL32:
486
26
    write32<E>(Loc, Val);
487
26
    break;
488
26
  case R_MIPS_64:
489
0
  case R_MIPS_TLS_DTPREL64:
490
0
  case R_MIPS_TLS_TPREL64:
491
0
    write64<E>(Loc, Val);
492
0
    break;
493
52
  case R_MIPS_26:
494
52
    writeValue<E>(Loc, Val, 26, 2);
495
52
    break;
496
38
  case R_MIPS_GOT16:
497
38
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
498
38
    // is updated addend (not a GOT index). In that case write high 16 bits
499
38
    // to store a correct addend value.
500
38
    if (Config->Relocatable) {
501
2
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
502
36
    } else {
503
36
      checkInt(Loc, Val, 16, Type);
504
36
      writeValue<E>(Loc, Val, 16, 0);
505
36
    }
506
38
    break;
507
3
  case R_MICROMIPS_GOT16:
508
3
    if (Config->Relocatable) {
509
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
510
3
    } else {
511
3
      checkInt(Loc, Val, 16, Type);
512
3
      writeShuffleValue<E>(Loc, Val, 16, 0);
513
3
    }
514
3
    break;
515
34
  case R_MIPS_CALL16:
516
34
  case R_MIPS_GOT_DISP:
517
34
  case R_MIPS_GOT_PAGE:
518
34
  case R_MIPS_GPREL16:
519
34
  case R_MIPS_TLS_GD:
520
34
  case R_MIPS_TLS_GOTTPREL:
521
34
  case R_MIPS_TLS_LDM:
522
34
    checkInt(Loc, Val, 16, Type);
523
34
    LLVM_FALLTHROUGH;
524
119
  case R_MIPS_CALL_LO16:
525
119
  case R_MIPS_GOT_LO16:
526
119
  case R_MIPS_GOT_OFST:
527
119
  case R_MIPS_LO16:
528
119
  case R_MIPS_PCLO16:
529
119
  case R_MIPS_TLS_DTPREL_LO16:
530
119
  case R_MIPS_TLS_TPREL_LO16:
531
119
    writeValue<E>(Loc, Val, 16, 0);
532
119
    break;
533
119
  case R_MICROMIPS_GPREL16:
534
0
  case R_MICROMIPS_TLS_GD:
535
0
  case R_MICROMIPS_TLS_LDM:
536
0
    checkInt(Loc, Val, 16, Type);
537
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
538
0
    break;
539
8
  case R_MICROMIPS_CALL16:
540
8
  case R_MICROMIPS_CALL_LO16:
541
8
  case R_MICROMIPS_LO16:
542
8
  case R_MICROMIPS_TLS_DTPREL_LO16:
543
8
  case R_MICROMIPS_TLS_GOTTPREL:
544
8
  case R_MICROMIPS_TLS_TPREL_LO16:
545
8
    writeShuffleValue<E>(Loc, Val, 16, 0);
546
8
    break;
547
8
  case R_MICROMIPS_GPREL7_S2:
548
0
    checkInt(Loc, Val, 7, Type);
549
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
550
0
    break;
551
66
  case R_MIPS_CALL_HI16:
552
66
  case R_MIPS_GOT_HI16:
553
66
  case R_MIPS_HI16:
554
66
  case R_MIPS_PCHI16:
555
66
  case R_MIPS_TLS_DTPREL_HI16:
556
66
  case R_MIPS_TLS_TPREL_HI16:
557
66
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
558
66
    break;
559
66
  case R_MICROMIPS_CALL_HI16:
560
4
  case R_MICROMIPS_GOT_HI16:
561
4
  case R_MICROMIPS_HI16:
562
4
  case R_MICROMIPS_TLS_DTPREL_HI16:
563
4
  case R_MICROMIPS_TLS_TPREL_HI16:
564
4
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
565
4
    break;
566
4
  case R_MIPS_HIGHER:
567
0
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
568
0
    break;
569
4
  case R_MIPS_HIGHEST:
570
0
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
571
0
    break;
572
4
  case R_MIPS_JALR:
573
0
  case R_MICROMIPS_JALR:
574
0
    // Ignore this optimization relocation for now
575
0
    break;
576
2
  case R_MIPS_PC16:
577
2
    checkAlignment(Loc, Val, 4, Type);
578
2
    checkInt(Loc, Val, 18, Type);
579
2
    writeValue<E>(Loc, Val, 16, 2);
580
2
    break;
581
1
  case R_MIPS_PC19_S2:
582
1
    checkAlignment(Loc, Val, 4, Type);
583
1
    checkInt(Loc, Val, 21, Type);
584
1
    writeValue<E>(Loc, Val, 19, 2);
585
1
    break;
586
1
  case R_MIPS_PC21_S2:
587
1
    checkAlignment(Loc, Val, 4, Type);
588
1
    checkInt(Loc, Val, 23, Type);
589
1
    writeValue<E>(Loc, Val, 21, 2);
590
1
    break;
591
1
  case R_MIPS_PC26_S2:
592
1
    checkAlignment(Loc, Val, 4, Type);
593
1
    checkInt(Loc, Val, 28, Type);
594
1
    writeValue<E>(Loc, Val, 26, 2);
595
1
    break;
596
1
  case R_MIPS_PC32:
597
1
    writeValue<E>(Loc, Val, 32, 0);
598
1
    break;
599
9
  case R_MICROMIPS_26_S1:
600
9
  case R_MICROMIPS_PC26_S1:
601
9
    checkInt(Loc, Val, 27, Type);
602
9
    writeShuffleValue<E>(Loc, Val, 26, 1);
603
9
    break;
604
9
  case R_MICROMIPS_PC7_S1:
605
1
    checkInt(Loc, Val, 8, Type);
606
1
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
607
1
    break;
608
9
  case R_MICROMIPS_PC10_S1:
609
1
    checkInt(Loc, Val, 11, Type);
610
1
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
611
1
    break;
612
9
  case R_MICROMIPS_PC16_S1:
613
1
    checkInt(Loc, Val, 17, Type);
614
1
    writeShuffleValue<E>(Loc, Val, 16, 1);
615
1
    break;
616
9
  case R_MICROMIPS_PC18_S3:
617
0
    checkInt(Loc, Val, 21, Type);
618
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
619
0
    break;
620
9
  case R_MICROMIPS_PC19_S2:
621
3
    checkInt(Loc, Val, 21, Type);
622
3
    writeShuffleValue<E>(Loc, Val, 19, 2);
623
3
    break;
624
9
  case R_MICROMIPS_PC21_S1:
625
1
    checkInt(Loc, Val, 22, Type);
626
1
    writeShuffleValue<E>(Loc, Val, 21, 1);
627
1
    break;
628
9
  case R_MICROMIPS_PC23_S2:
629
6
    checkInt(Loc, Val, 25, Type);
630
6
    writeShuffleValue<E>(Loc, Val, 23, 2);
631
6
    break;
632
9
  default:
633
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
634
344
  }
635
344
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
461
10.0k
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
462
10.0k
  const endianness E = ELFT::TargetEndianness;
463
10.0k
464
10.0k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi0
)
465
10.0k
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
466
10.0k
467
10.0k
  // Thread pointer and DRP offsets from the start of TLS data area.
468
10.0k
  // https://www.linux-mips.org/wiki/NPTL
469
10.0k
  if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
470
10.0k
      Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 ||
471
10.0k
      
Type == R_MICROMIPS_TLS_DTPREL_HI1610.0k
||
472
10.0k
      
Type == R_MICROMIPS_TLS_DTPREL_LO1610.0k
) {
473
1
    Val -= 0x8000;
474
10.0k
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
475
10.0k
             Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 ||
476
10.0k
             
Type == R_MICROMIPS_TLS_TPREL_HI1610.0k
||
477
10.0k
             
Type == R_MICROMIPS_TLS_TPREL_LO1610.0k
) {
478
1
    Val -= 0x7000;
479
1
  }
480
10.0k
481
10.0k
  switch (Type) {
482
10.0k
  case R_MIPS_32:
483
3
  case R_MIPS_GPREL32:
484
3
  case R_MIPS_TLS_DTPREL32:
485
3
  case R_MIPS_TLS_TPREL32:
486
3
    write32<E>(Loc, Val);
487
3
    break;
488
8
  case R_MIPS_64:
489
8
  case R_MIPS_TLS_DTPREL64:
490
8
  case R_MIPS_TLS_TPREL64:
491
8
    write64<E>(Loc, Val);
492
8
    break;
493
8
  case R_MIPS_26:
494
2
    writeValue<E>(Loc, Val, 26, 2);
495
2
    break;
496
8
  case R_MIPS_GOT16:
497
0
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
498
0
    // is updated addend (not a GOT index). In that case write high 16 bits
499
0
    // to store a correct addend value.
500
0
    if (Config->Relocatable) {
501
0
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
502
0
    } else {
503
0
      checkInt(Loc, Val, 16, Type);
504
0
      writeValue<E>(Loc, Val, 16, 0);
505
0
    }
506
0
    break;
507
8
  case R_MICROMIPS_GOT16:
508
0
    if (Config->Relocatable) {
509
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
510
0
    } else {
511
0
      checkInt(Loc, Val, 16, Type);
512
0
      writeShuffleValue<E>(Loc, Val, 16, 0);
513
0
    }
514
0
    break;
515
10.0k
  case R_MIPS_CALL16:
516
10.0k
  case R_MIPS_GOT_DISP:
517
10.0k
  case R_MIPS_GOT_PAGE:
518
10.0k
  case R_MIPS_GPREL16:
519
10.0k
  case R_MIPS_TLS_GD:
520
10.0k
  case R_MIPS_TLS_GOTTPREL:
521
10.0k
  case R_MIPS_TLS_LDM:
522
10.0k
    checkInt(Loc, Val, 16, Type);
523
10.0k
    LLVM_FALLTHROUGH;
524
10.0k
  case R_MIPS_CALL_LO16:
525
10.0k
  case R_MIPS_GOT_LO16:
526
10.0k
  case R_MIPS_GOT_OFST:
527
10.0k
  case R_MIPS_LO16:
528
10.0k
  case R_MIPS_PCLO16:
529
10.0k
  case R_MIPS_TLS_DTPREL_LO16:
530
10.0k
  case R_MIPS_TLS_TPREL_LO16:
531
10.0k
    writeValue<E>(Loc, Val, 16, 0);
532
10.0k
    break;
533
10.0k
  case R_MICROMIPS_GPREL16:
534
0
  case R_MICROMIPS_TLS_GD:
535
0
  case R_MICROMIPS_TLS_LDM:
536
0
    checkInt(Loc, Val, 16, Type);
537
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
538
0
    break;
539
0
  case R_MICROMIPS_CALL16:
540
0
  case R_MICROMIPS_CALL_LO16:
541
0
  case R_MICROMIPS_LO16:
542
0
  case R_MICROMIPS_TLS_DTPREL_LO16:
543
0
  case R_MICROMIPS_TLS_GOTTPREL:
544
0
  case R_MICROMIPS_TLS_TPREL_LO16:
545
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
546
0
    break;
547
0
  case R_MICROMIPS_GPREL7_S2:
548
0
    checkInt(Loc, Val, 7, Type);
549
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
550
0
    break;
551
6
  case R_MIPS_CALL_HI16:
552
6
  case R_MIPS_GOT_HI16:
553
6
  case R_MIPS_HI16:
554
6
  case R_MIPS_PCHI16:
555
6
  case R_MIPS_TLS_DTPREL_HI16:
556
6
  case R_MIPS_TLS_TPREL_HI16:
557
6
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
558
6
    break;
559
6
  case R_MICROMIPS_CALL_HI16:
560
0
  case R_MICROMIPS_GOT_HI16:
561
0
  case R_MICROMIPS_HI16:
562
0
  case R_MICROMIPS_TLS_DTPREL_HI16:
563
0
  case R_MICROMIPS_TLS_TPREL_HI16:
564
0
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
565
0
    break;
566
2
  case R_MIPS_HIGHER:
567
2
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
568
2
    break;
569
2
  case R_MIPS_HIGHEST:
570
2
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
571
2
    break;
572
0
  case R_MIPS_JALR:
573
0
  case R_MICROMIPS_JALR:
574
0
    // Ignore this optimization relocation for now
575
0
    break;
576
0
  case R_MIPS_PC16:
577
0
    checkAlignment(Loc, Val, 4, Type);
578
0
    checkInt(Loc, Val, 18, Type);
579
0
    writeValue<E>(Loc, Val, 16, 2);
580
0
    break;
581
0
  case R_MIPS_PC19_S2:
582
0
    checkAlignment(Loc, Val, 4, Type);
583
0
    checkInt(Loc, Val, 21, Type);
584
0
    writeValue<E>(Loc, Val, 19, 2);
585
0
    break;
586
0
  case R_MIPS_PC21_S2:
587
0
    checkAlignment(Loc, Val, 4, Type);
588
0
    checkInt(Loc, Val, 23, Type);
589
0
    writeValue<E>(Loc, Val, 21, 2);
590
0
    break;
591
0
  case R_MIPS_PC26_S2:
592
0
    checkAlignment(Loc, Val, 4, Type);
593
0
    checkInt(Loc, Val, 28, Type);
594
0
    writeValue<E>(Loc, Val, 26, 2);
595
0
    break;
596
1
  case R_MIPS_PC32:
597
1
    writeValue<E>(Loc, Val, 32, 0);
598
1
    break;
599
0
  case R_MICROMIPS_26_S1:
600
0
  case R_MICROMIPS_PC26_S1:
601
0
    checkInt(Loc, Val, 27, Type);
602
0
    writeShuffleValue<E>(Loc, Val, 26, 1);
603
0
    break;
604
0
  case R_MICROMIPS_PC7_S1:
605
0
    checkInt(Loc, Val, 8, Type);
606
0
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
607
0
    break;
608
0
  case R_MICROMIPS_PC10_S1:
609
0
    checkInt(Loc, Val, 11, Type);
610
0
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
611
0
    break;
612
0
  case R_MICROMIPS_PC16_S1:
613
0
    checkInt(Loc, Val, 17, Type);
614
0
    writeShuffleValue<E>(Loc, Val, 16, 1);
615
0
    break;
616
0
  case R_MICROMIPS_PC18_S3:
617
0
    checkInt(Loc, Val, 21, Type);
618
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
619
0
    break;
620
0
  case R_MICROMIPS_PC19_S2:
621
0
    checkInt(Loc, Val, 21, Type);
622
0
    writeShuffleValue<E>(Loc, Val, 19, 2);
623
0
    break;
624
0
  case R_MICROMIPS_PC21_S1:
625
0
    checkInt(Loc, Val, 22, Type);
626
0
    writeShuffleValue<E>(Loc, Val, 21, 1);
627
0
    break;
628
0
  case R_MICROMIPS_PC23_S2:
629
0
    checkInt(Loc, Val, 25, Type);
630
0
    writeShuffleValue<E>(Loc, Val, 23, 2);
631
0
    break;
632
0
  default:
633
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
634
10.0k
  }
635
10.0k
}
636
637
34
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
638
34
  return Type == R_MIPS_LO16 || 
Type == R_MIPS_GOT_OFST18
||
639
34
         
Type == R_MICROMIPS_LO1617
;
640
34
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
637
2
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
638
2
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
639
2
         Type == R_MICROMIPS_LO16;
640
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
637
26
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
638
26
  return Type == R_MIPS_LO16 || 
Type == R_MIPS_GOT_OFST10
||
639
26
         
Type == R_MICROMIPS_LO1610
;
640
26
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::usesOnlyLowPageBits(unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
637
6
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
638
6
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
639
6
         
Type == R_MICROMIPS_LO165
;
640
6
}
641
642
// Return true if the symbol is a PIC function.
643
127
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
644
127
  if (!Sym->isFunc())
645
61
    return false;
646
66
647
66
  if (Sym->StOther & STO_MIPS_PIC)
648
7
    return true;
649
59
650
59
  if (!Sym->Section)
651
0
    return false;
652
59
653
59
  ObjFile<ELFT> *File =
654
59
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
655
59
  if (!File)
656
1
    return false;
657
58
658
58
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
659
58
}
bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)1, false> >(lld::elf::Defined const*)
Line
Count
Source
643
3
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
644
3
  if (!Sym->isFunc())
645
0
    return false;
646
3
647
3
  if (Sym->StOther & STO_MIPS_PIC)
648
0
    return true;
649
3
650
3
  if (!Sym->Section)
651
0
    return false;
652
3
653
3
  ObjFile<ELFT> *File =
654
3
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
655
3
  if (!File)
656
0
    return false;
657
3
658
3
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
659
3
}
bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)0, false> >(lld::elf::Defined const*)
Line
Count
Source
643
113
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
644
113
  if (!Sym->isFunc())
645
50
    return false;
646
63
647
63
  if (Sym->StOther & STO_MIPS_PIC)
648
7
    return true;
649
56
650
56
  if (!Sym->Section)
651
0
    return false;
652
56
653
56
  ObjFile<ELFT> *File =
654
56
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
655
56
  if (!File)
656
1
    return false;
657
55
658
55
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
659
55
}
Unexecuted instantiation: bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)1, true> >(lld::elf::Defined const*)
bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)0, true> >(lld::elf::Defined const*)
Line
Count
Source
643
11
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
644
11
  if (!Sym->isFunc())
645
11
    return false;
646
0
647
0
  if (Sym->StOther & STO_MIPS_PIC)
648
0
    return true;
649
0
650
0
  if (!Sym->Section)
651
0
    return false;
652
0
653
0
  ObjFile<ELFT> *File =
654
0
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
655
0
  if (!File)
656
0
    return false;
657
0
658
0
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
659
0
}
660
661
181
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
662
181
  static MIPS<ELFT> Target;
663
181
  return &Target;
664
181
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)1, false> >()
Line
Count
Source
661
17
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
662
17
  static MIPS<ELFT> Target;
663
17
  return &Target;
664
17
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)0, false> >()
Line
Count
Source
661
117
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
662
117
  static MIPS<ELFT> Target;
663
117
  return &Target;
664
117
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)1, true> >()
Line
Count
Source
661
2
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
662
2
  static MIPS<ELFT> Target;
663
2
  return &Target;
664
2
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)0, true> >()
Line
Count
Source
661
45
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
662
45
  static MIPS<ELFT> Target;
663
45
  return &Target;
664
45
}
665
666
template TargetInfo *elf::getMipsTargetInfo<ELF32LE>();
667
template TargetInfo *elf::getMipsTargetInfo<ELF32BE>();
668
template TargetInfo *elf::getMipsTargetInfo<ELF64LE>();
669
template TargetInfo *elf::getMipsTargetInfo<ELF64BE>();
670
671
template bool elf::isMipsPIC<ELF32LE>(const Defined *);
672
template bool elf::isMipsPIC<ELF32BE>(const Defined *);
673
template bool elf::isMipsPIC<ELF64LE>(const Defined *);
674
template bool elf::isMipsPIC<ELF64BE>(const Defined *);