Coverage Report

Created: 2018-08-19 21:11

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/Mips.cpp
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Source (jump to first uncovered line)
1
//===- MIPS.cpp -----------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
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// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
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//===----------------------------------------------------------------------===//
9
10
#include "InputFiles.h"
11
#include "OutputSections.h"
12
#include "Symbols.h"
13
#include "SyntheticSections.h"
14
#include "Target.h"
15
#include "Thunks.h"
16
#include "lld/Common/ErrorHandler.h"
17
#include "llvm/Object/ELF.h"
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#include "llvm/Support/Endian.h"
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20
using namespace llvm;
21
using namespace llvm::object;
22
using namespace llvm::support::endian;
23
using namespace llvm::ELF;
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using namespace lld;
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using namespace lld::elf;
26
27
namespace {
28
template <class ELFT> class MIPS final : public TargetInfo {
29
public:
30
  MIPS();
31
  uint32_t calcEFlags() const override;
32
  RelExpr getRelExpr(RelType Type, const Symbol &S,
33
                     const uint8_t *Loc) const override;
34
  int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
35
  RelType getDynRel(RelType Type) const override;
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  void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
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  void writePltHeader(uint8_t *Buf) const override;
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  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
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                int32_t Index, unsigned RelOff) const override;
40
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
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                  uint64_t BranchAddr, const Symbol &S) const override;
42
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
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  bool usesOnlyLowPageBits(RelType Type) const override;
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};
45
} // namespace
46
47
181
template <class ELFT> MIPS<ELFT>::MIPS() {
48
181
  GotPltHeaderEntriesNum = 2;
49
181
  DefaultMaxPageSize = 65536;
50
181
  GotEntrySize = sizeof(typename ELFT::uint);
51
181
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
181
  GotBaseSymInGotPlt = false;
53
181
  PltEntrySize = 16;
54
181
  PltHeaderSize = 32;
55
181
  CopyRel = R_MIPS_COPY;
56
181
  PltRel = R_MIPS_JUMP_SLOT;
57
181
  NeedsThunks = true;
58
181
  TrapInstr = 0xefefefef;
59
181
60
181
  if (ELFT::Is64Bits) {
61
47
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
62
47
    TlsGotRel = R_MIPS_TLS_TPREL64;
63
47
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
64
47
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
65
134
  } else {
66
134
    RelativeRel = R_MIPS_REL32;
67
134
    TlsGotRel = R_MIPS_TLS_TPREL32;
68
134
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
69
134
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
70
134
  }
71
181
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::MIPS()
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47
17
template <class ELFT> MIPS<ELFT>::MIPS() {
48
17
  GotPltHeaderEntriesNum = 2;
49
17
  DefaultMaxPageSize = 65536;
50
17
  GotEntrySize = sizeof(typename ELFT::uint);
51
17
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
17
  GotBaseSymInGotPlt = false;
53
17
  PltEntrySize = 16;
54
17
  PltHeaderSize = 32;
55
17
  CopyRel = R_MIPS_COPY;
56
17
  PltRel = R_MIPS_JUMP_SLOT;
57
17
  NeedsThunks = true;
58
17
  TrapInstr = 0xefefefef;
59
17
60
17
  if (ELFT::Is64Bits) {
61
0
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
62
0
    TlsGotRel = R_MIPS_TLS_TPREL64;
63
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
64
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
65
17
  } else {
66
17
    RelativeRel = R_MIPS_REL32;
67
17
    TlsGotRel = R_MIPS_TLS_TPREL32;
68
17
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
69
17
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
70
17
  }
71
17
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::MIPS()
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47
117
template <class ELFT> MIPS<ELFT>::MIPS() {
48
117
  GotPltHeaderEntriesNum = 2;
49
117
  DefaultMaxPageSize = 65536;
50
117
  GotEntrySize = sizeof(typename ELFT::uint);
51
117
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
117
  GotBaseSymInGotPlt = false;
53
117
  PltEntrySize = 16;
54
117
  PltHeaderSize = 32;
55
117
  CopyRel = R_MIPS_COPY;
56
117
  PltRel = R_MIPS_JUMP_SLOT;
57
117
  NeedsThunks = true;
58
117
  TrapInstr = 0xefefefef;
59
117
60
117
  if (ELFT::Is64Bits) {
61
0
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
62
0
    TlsGotRel = R_MIPS_TLS_TPREL64;
63
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
64
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
65
117
  } else {
66
117
    RelativeRel = R_MIPS_REL32;
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117
    TlsGotRel = R_MIPS_TLS_TPREL32;
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117
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
69
117
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
70
117
  }
71
117
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::MIPS()
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47
2
template <class ELFT> MIPS<ELFT>::MIPS() {
48
2
  GotPltHeaderEntriesNum = 2;
49
2
  DefaultMaxPageSize = 65536;
50
2
  GotEntrySize = sizeof(typename ELFT::uint);
51
2
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
2
  GotBaseSymInGotPlt = false;
53
2
  PltEntrySize = 16;
54
2
  PltHeaderSize = 32;
55
2
  CopyRel = R_MIPS_COPY;
56
2
  PltRel = R_MIPS_JUMP_SLOT;
57
2
  NeedsThunks = true;
58
2
  TrapInstr = 0xefefefef;
59
2
60
2
  if (ELFT::Is64Bits) {
61
2
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
62
2
    TlsGotRel = R_MIPS_TLS_TPREL64;
63
2
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
64
2
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
65
2
  } else {
66
0
    RelativeRel = R_MIPS_REL32;
67
0
    TlsGotRel = R_MIPS_TLS_TPREL32;
68
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
69
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
70
0
  }
71
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::MIPS()
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47
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template <class ELFT> MIPS<ELFT>::MIPS() {
48
45
  GotPltHeaderEntriesNum = 2;
49
45
  DefaultMaxPageSize = 65536;
50
45
  GotEntrySize = sizeof(typename ELFT::uint);
51
45
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
45
  GotBaseSymInGotPlt = false;
53
45
  PltEntrySize = 16;
54
45
  PltHeaderSize = 32;
55
45
  CopyRel = R_MIPS_COPY;
56
45
  PltRel = R_MIPS_JUMP_SLOT;
57
45
  NeedsThunks = true;
58
45
  TrapInstr = 0xefefefef;
59
45
60
45
  if (ELFT::Is64Bits) {
61
45
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
62
45
    TlsGotRel = R_MIPS_TLS_TPREL64;
63
45
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
64
45
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
65
45
  } else {
66
0
    RelativeRel = R_MIPS_REL32;
67
0
    TlsGotRel = R_MIPS_TLS_TPREL32;
68
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
69
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
70
0
  }
71
45
}
72
73
179
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
74
179
  return calcMipsEFlags<ELFT>();
75
179
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::calcEFlags() const
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73
17
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
74
17
  return calcMipsEFlags<ELFT>();
75
17
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::calcEFlags() const
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73
116
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
74
116
  return calcMipsEFlags<ELFT>();
75
116
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::calcEFlags() const
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73
2
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
74
2
  return calcMipsEFlags<ELFT>();
75
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::calcEFlags() const
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73
44
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
74
44
  return calcMipsEFlags<ELFT>();
75
44
}
76
77
template <class ELFT>
78
RelExpr MIPS<ELFT>::getRelExpr(RelType Type, const Symbol &S,
79
10.3k
                               const uint8_t *Loc) const {
80
10.3k
  // See comment in the calculateMipsRelChain.
81
10.3k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi293
)
82
10.0k
    Type &= 0xff;
83
10.3k
84
10.3k
  switch (Type) {
85
10.3k
  case R_MIPS_JALR:
86
1
  case R_MICROMIPS_JALR:
87
1
    return R_HINT;
88
26
  case R_MIPS_GPREL16:
89
26
  case R_MIPS_GPREL32:
90
26
  case R_MICROMIPS_GPREL16:
91
26
  case R_MICROMIPS_GPREL7_S2:
92
26
    return R_MIPS_GOTREL;
93
60
  case R_MIPS_26:
94
60
  case R_MICROMIPS_26_S1:
95
60
    return R_PLT;
96
60
  case R_MICROMIPS_PC26_S1:
97
6
    return R_PLT_PC;
98
77
  case R_MIPS_HI16:
99
77
  case R_MIPS_LO16:
100
77
  case R_MIPS_HIGHER:
101
77
  case R_MIPS_HIGHEST:
102
77
  case R_MICROMIPS_HI16:
103
77
  case R_MICROMIPS_LO16:
104
77
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
105
77
    // offset between start of function and 'gp' value which by default
106
77
    // equal to the start of .got section. In that case we consider these
107
77
    // relocations as relative.
108
77
    if (&S == ElfSym::MipsGpDisp)
109
20
      return R_MIPS_GOT_GP_PC;
110
57
    if (&S == ElfSym::MipsLocalGp)
111
2
      return R_MIPS_GOT_GP;
112
55
    LLVM_FALLTHROUGH;
113
90
  case R_MIPS_32:
114
90
  case R_MIPS_64:
115
90
  case R_MIPS_GOT_OFST:
116
90
  case R_MIPS_SUB:
117
90
  case R_MIPS_TLS_DTPREL_HI16:
118
90
  case R_MIPS_TLS_DTPREL_LO16:
119
90
  case R_MIPS_TLS_DTPREL32:
120
90
  case R_MIPS_TLS_DTPREL64:
121
90
  case R_MIPS_TLS_TPREL_HI16:
122
90
  case R_MIPS_TLS_TPREL_LO16:
123
90
  case R_MIPS_TLS_TPREL32:
124
90
  case R_MIPS_TLS_TPREL64:
125
90
  case R_MICROMIPS_TLS_DTPREL_HI16:
126
90
  case R_MICROMIPS_TLS_DTPREL_LO16:
127
90
  case R_MICROMIPS_TLS_TPREL_HI16:
128
90
  case R_MICROMIPS_TLS_TPREL_LO16:
129
90
    return R_ABS;
130
90
  case R_MIPS_PC32:
131
19
  case R_MIPS_PC16:
132
19
  case R_MIPS_PC19_S2:
133
19
  case R_MIPS_PC21_S2:
134
19
  case R_MIPS_PC26_S2:
135
19
  case R_MIPS_PCHI16:
136
19
  case R_MIPS_PCLO16:
137
19
  case R_MICROMIPS_PC7_S1:
138
19
  case R_MICROMIPS_PC10_S1:
139
19
  case R_MICROMIPS_PC16_S1:
140
19
  case R_MICROMIPS_PC18_S3:
141
19
  case R_MICROMIPS_PC19_S2:
142
19
  case R_MICROMIPS_PC23_S2:
143
19
  case R_MICROMIPS_PC21_S1:
144
19
    return R_PC;
145
46
  case R_MIPS_GOT16:
146
46
  case R_MICROMIPS_GOT16:
147
46
    if (S.isLocal())
148
19
      return R_MIPS_GOT_LOCAL_PAGE;
149
27
    LLVM_FALLTHROUGH;
150
10.0k
  case R_MIPS_CALL16:
151
10.0k
  case R_MIPS_GOT_DISP:
152
10.0k
  case R_MIPS_TLS_GOTTPREL:
153
10.0k
  case R_MICROMIPS_CALL16:
154
10.0k
  case R_MICROMIPS_TLS_GOTTPREL:
155
10.0k
    return R_MIPS_GOT_OFF;
156
10.0k
  case R_MIPS_CALL_HI16:
157
16
  case R_MIPS_CALL_LO16:
158
16
  case R_MIPS_GOT_HI16:
159
16
  case R_MIPS_GOT_LO16:
160
16
  case R_MICROMIPS_CALL_HI16:
161
16
  case R_MICROMIPS_CALL_LO16:
162
16
  case R_MICROMIPS_GOT_HI16:
163
16
  case R_MICROMIPS_GOT_LO16:
164
16
    return R_MIPS_GOT_OFF32;
165
16
  case R_MIPS_GOT_PAGE:
166
12
    return R_MIPS_GOT_LOCAL_PAGE;
167
16
  case R_MIPS_TLS_GD:
168
12
  case R_MICROMIPS_TLS_GD:
169
12
    return R_MIPS_TLSGD;
170
12
  case R_MIPS_TLS_LDM:
171
6
  case R_MICROMIPS_TLS_LDM:
172
6
    return R_MIPS_TLSLD;
173
6
  case R_MIPS_NONE:
174
0
    return R_NONE;
175
6
  default:
176
0
    return R_INVALID;
177
10.3k
  }
178
10.3k
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
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Source
79
21
                               const uint8_t *Loc) const {
80
21
  // See comment in the calculateMipsRelChain.
81
21
  if (ELFT::Is64Bits || Config->MipsN32Abi)
82
0
    Type &= 0xff;
83
21
84
21
  switch (Type) {
85
21
  case R_MIPS_JALR:
86
1
  case R_MICROMIPS_JALR:
87
1
    return R_HINT;
88
1
  case R_MIPS_GPREL16:
89
0
  case R_MIPS_GPREL32:
90
0
  case R_MICROMIPS_GPREL16:
91
0
  case R_MICROMIPS_GPREL7_S2:
92
0
    return R_MIPS_GOTREL;
93
2
  case R_MIPS_26:
94
2
  case R_MICROMIPS_26_S1:
95
2
    return R_PLT;
96
3
  case R_MICROMIPS_PC26_S1:
97
3
    return R_PLT_PC;
98
2
  case R_MIPS_HI16:
99
2
  case R_MIPS_LO16:
100
2
  case R_MIPS_HIGHER:
101
2
  case R_MIPS_HIGHEST:
102
2
  case R_MICROMIPS_HI16:
103
2
  case R_MICROMIPS_LO16:
104
2
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
105
2
    // offset between start of function and 'gp' value which by default
106
2
    // equal to the start of .got section. In that case we consider these
107
2
    // relocations as relative.
108
2
    if (&S == ElfSym::MipsGpDisp)
109
2
      return R_MIPS_GOT_GP_PC;
110
0
    if (&S == ElfSym::MipsLocalGp)
111
0
      return R_MIPS_GOT_GP;
112
0
    LLVM_FALLTHROUGH;
113
2
  case R_MIPS_32:
114
2
  case R_MIPS_64:
115
2
  case R_MIPS_GOT_OFST:
116
2
  case R_MIPS_SUB:
117
2
  case R_MIPS_TLS_DTPREL_HI16:
118
2
  case R_MIPS_TLS_DTPREL_LO16:
119
2
  case R_MIPS_TLS_DTPREL32:
120
2
  case R_MIPS_TLS_DTPREL64:
121
2
  case R_MIPS_TLS_TPREL_HI16:
122
2
  case R_MIPS_TLS_TPREL_LO16:
123
2
  case R_MIPS_TLS_TPREL32:
124
2
  case R_MIPS_TLS_TPREL64:
125
2
  case R_MICROMIPS_TLS_DTPREL_HI16:
126
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
127
2
  case R_MICROMIPS_TLS_TPREL_HI16:
128
2
  case R_MICROMIPS_TLS_TPREL_LO16:
129
2
    return R_ABS;
130
5
  case R_MIPS_PC32:
131
5
  case R_MIPS_PC16:
132
5
  case R_MIPS_PC19_S2:
133
5
  case R_MIPS_PC21_S2:
134
5
  case R_MIPS_PC26_S2:
135
5
  case R_MIPS_PCHI16:
136
5
  case R_MIPS_PCLO16:
137
5
  case R_MICROMIPS_PC7_S1:
138
5
  case R_MICROMIPS_PC10_S1:
139
5
  case R_MICROMIPS_PC16_S1:
140
5
  case R_MICROMIPS_PC18_S3:
141
5
  case R_MICROMIPS_PC19_S2:
142
5
  case R_MICROMIPS_PC23_S2:
143
5
  case R_MICROMIPS_PC21_S1:
144
5
    return R_PC;
145
5
  case R_MIPS_GOT16:
146
5
  case R_MICROMIPS_GOT16:
147
5
    if (S.isLocal())
148
0
      return R_MIPS_GOT_LOCAL_PAGE;
149
5
    LLVM_FALLTHROUGH;
150
6
  case R_MIPS_CALL16:
151
6
  case R_MIPS_GOT_DISP:
152
6
  case R_MIPS_TLS_GOTTPREL:
153
6
  case R_MICROMIPS_CALL16:
154
6
  case R_MICROMIPS_TLS_GOTTPREL:
155
6
    return R_MIPS_GOT_OFF;
156
6
  case R_MIPS_CALL_HI16:
157
0
  case R_MIPS_CALL_LO16:
158
0
  case R_MIPS_GOT_HI16:
159
0
  case R_MIPS_GOT_LO16:
160
0
  case R_MICROMIPS_CALL_HI16:
161
0
  case R_MICROMIPS_CALL_LO16:
162
0
  case R_MICROMIPS_GOT_HI16:
163
0
  case R_MICROMIPS_GOT_LO16:
164
0
    return R_MIPS_GOT_OFF32;
165
0
  case R_MIPS_GOT_PAGE:
166
0
    return R_MIPS_GOT_LOCAL_PAGE;
167
0
  case R_MIPS_TLS_GD:
168
0
  case R_MICROMIPS_TLS_GD:
169
0
    return R_MIPS_TLSGD;
170
0
  case R_MIPS_TLS_LDM:
171
0
  case R_MICROMIPS_TLS_LDM:
172
0
    return R_MIPS_TLSLD;
173
0
  case R_MIPS_NONE:
174
0
    return R_NONE;
175
0
  default:
176
0
    return R_INVALID;
177
21
  }
178
21
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Line
Count
Source
79
272
                               const uint8_t *Loc) const {
80
272
  // See comment in the calculateMipsRelChain.
81
272
  if (ELFT::Is64Bits || Config->MipsN32Abi)
82
5
    Type &= 0xff;
83
272
84
272
  switch (Type) {
85
272
  case R_MIPS_JALR:
86
0
  case R_MICROMIPS_JALR:
87
0
    return R_HINT;
88
15
  case R_MIPS_GPREL16:
89
15
  case R_MIPS_GPREL32:
90
15
  case R_MICROMIPS_GPREL16:
91
15
  case R_MICROMIPS_GPREL7_S2:
92
15
    return R_MIPS_GOTREL;
93
56
  case R_MIPS_26:
94
56
  case R_MICROMIPS_26_S1:
95
56
    return R_PLT;
96
56
  case R_MICROMIPS_PC26_S1:
97
3
    return R_PLT_PC;
98
71
  case R_MIPS_HI16:
99
71
  case R_MIPS_LO16:
100
71
  case R_MIPS_HIGHER:
101
71
  case R_MIPS_HIGHEST:
102
71
  case R_MICROMIPS_HI16:
103
71
  case R_MICROMIPS_LO16:
104
71
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
105
71
    // offset between start of function and 'gp' value which by default
106
71
    // equal to the start of .got section. In that case we consider these
107
71
    // relocations as relative.
108
71
    if (&S == ElfSym::MipsGpDisp)
109
18
      return R_MIPS_GOT_GP_PC;
110
53
    if (&S == ElfSym::MipsLocalGp)
111
2
      return R_MIPS_GOT_GP;
112
51
    LLVM_FALLTHROUGH;
113
72
  case R_MIPS_32:
114
72
  case R_MIPS_64:
115
72
  case R_MIPS_GOT_OFST:
116
72
  case R_MIPS_SUB:
117
72
  case R_MIPS_TLS_DTPREL_HI16:
118
72
  case R_MIPS_TLS_DTPREL_LO16:
119
72
  case R_MIPS_TLS_DTPREL32:
120
72
  case R_MIPS_TLS_DTPREL64:
121
72
  case R_MIPS_TLS_TPREL_HI16:
122
72
  case R_MIPS_TLS_TPREL_LO16:
123
72
  case R_MIPS_TLS_TPREL32:
124
72
  case R_MIPS_TLS_TPREL64:
125
72
  case R_MICROMIPS_TLS_DTPREL_HI16:
126
72
  case R_MICROMIPS_TLS_DTPREL_LO16:
127
72
  case R_MICROMIPS_TLS_TPREL_HI16:
128
72
  case R_MICROMIPS_TLS_TPREL_LO16:
129
72
    return R_ABS;
130
72
  case R_MIPS_PC32:
131
13
  case R_MIPS_PC16:
132
13
  case R_MIPS_PC19_S2:
133
13
  case R_MIPS_PC21_S2:
134
13
  case R_MIPS_PC26_S2:
135
13
  case R_MIPS_PCHI16:
136
13
  case R_MIPS_PCLO16:
137
13
  case R_MICROMIPS_PC7_S1:
138
13
  case R_MICROMIPS_PC10_S1:
139
13
  case R_MICROMIPS_PC16_S1:
140
13
  case R_MICROMIPS_PC18_S3:
141
13
  case R_MICROMIPS_PC19_S2:
142
13
  case R_MICROMIPS_PC23_S2:
143
13
  case R_MICROMIPS_PC21_S1:
144
13
    return R_PC;
145
41
  case R_MIPS_GOT16:
146
41
  case R_MICROMIPS_GOT16:
147
41
    if (S.isLocal())
148
19
      return R_MIPS_GOT_LOCAL_PAGE;
149
22
    LLVM_FALLTHROUGH;
150
47
  case R_MIPS_CALL16:
151
47
  case R_MIPS_GOT_DISP:
152
47
  case R_MIPS_TLS_GOTTPREL:
153
47
  case R_MICROMIPS_CALL16:
154
47
  case R_MICROMIPS_TLS_GOTTPREL:
155
47
    return R_MIPS_GOT_OFF;
156
47
  case R_MIPS_CALL_HI16:
157
16
  case R_MIPS_CALL_LO16:
158
16
  case R_MIPS_GOT_HI16:
159
16
  case R_MIPS_GOT_LO16:
160
16
  case R_MICROMIPS_CALL_HI16:
161
16
  case R_MICROMIPS_CALL_LO16:
162
16
  case R_MICROMIPS_GOT_HI16:
163
16
  case R_MICROMIPS_GOT_LO16:
164
16
    return R_MIPS_GOT_OFF32;
165
16
  case R_MIPS_GOT_PAGE:
166
0
    return R_MIPS_GOT_LOCAL_PAGE;
167
16
  case R_MIPS_TLS_GD:
168
7
  case R_MICROMIPS_TLS_GD:
169
7
    return R_MIPS_TLSGD;
170
7
  case R_MIPS_TLS_LDM:
171
4
  case R_MICROMIPS_TLS_LDM:
172
4
    return R_MIPS_TLSLD;
173
4
  case R_MIPS_NONE:
174
0
    return R_NONE;
175
4
  default:
176
0
    return R_INVALID;
177
272
  }
178
272
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Line
Count
Source
79
10.0k
                               const uint8_t *Loc) const {
80
10.0k
  // See comment in the calculateMipsRelChain.
81
10.0k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi0
)
82
10.0k
    Type &= 0xff;
83
10.0k
84
10.0k
  switch (Type) {
85
10.0k
  case R_MIPS_JALR:
86
0
  case R_MICROMIPS_JALR:
87
0
    return R_HINT;
88
11
  case R_MIPS_GPREL16:
89
11
  case R_MIPS_GPREL32:
90
11
  case R_MICROMIPS_GPREL16:
91
11
  case R_MICROMIPS_GPREL7_S2:
92
11
    return R_MIPS_GOTREL;
93
11
  case R_MIPS_26:
94
2
  case R_MICROMIPS_26_S1:
95
2
    return R_PLT;
96
2
  case R_MICROMIPS_PC26_S1:
97
0
    return R_PLT_PC;
98
4
  case R_MIPS_HI16:
99
4
  case R_MIPS_LO16:
100
4
  case R_MIPS_HIGHER:
101
4
  case R_MIPS_HIGHEST:
102
4
  case R_MICROMIPS_HI16:
103
4
  case R_MICROMIPS_LO16:
104
4
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
105
4
    // offset between start of function and 'gp' value which by default
106
4
    // equal to the start of .got section. In that case we consider these
107
4
    // relocations as relative.
108
4
    if (&S == ElfSym::MipsGpDisp)
109
0
      return R_MIPS_GOT_GP_PC;
110
4
    if (&S == ElfSym::MipsLocalGp)
111
0
      return R_MIPS_GOT_GP;
112
4
    LLVM_FALLTHROUGH;
113
16
  case R_MIPS_32:
114
16
  case R_MIPS_64:
115
16
  case R_MIPS_GOT_OFST:
116
16
  case R_MIPS_SUB:
117
16
  case R_MIPS_TLS_DTPREL_HI16:
118
16
  case R_MIPS_TLS_DTPREL_LO16:
119
16
  case R_MIPS_TLS_DTPREL32:
120
16
  case R_MIPS_TLS_DTPREL64:
121
16
  case R_MIPS_TLS_TPREL_HI16:
122
16
  case R_MIPS_TLS_TPREL_LO16:
123
16
  case R_MIPS_TLS_TPREL32:
124
16
  case R_MIPS_TLS_TPREL64:
125
16
  case R_MICROMIPS_TLS_DTPREL_HI16:
126
16
  case R_MICROMIPS_TLS_DTPREL_LO16:
127
16
  case R_MICROMIPS_TLS_TPREL_HI16:
128
16
  case R_MICROMIPS_TLS_TPREL_LO16:
129
16
    return R_ABS;
130
16
  case R_MIPS_PC32:
131
1
  case R_MIPS_PC16:
132
1
  case R_MIPS_PC19_S2:
133
1
  case R_MIPS_PC21_S2:
134
1
  case R_MIPS_PC26_S2:
135
1
  case R_MIPS_PCHI16:
136
1
  case R_MIPS_PCLO16:
137
1
  case R_MICROMIPS_PC7_S1:
138
1
  case R_MICROMIPS_PC10_S1:
139
1
  case R_MICROMIPS_PC16_S1:
140
1
  case R_MICROMIPS_PC18_S3:
141
1
  case R_MICROMIPS_PC19_S2:
142
1
  case R_MICROMIPS_PC23_S2:
143
1
  case R_MICROMIPS_PC21_S1:
144
1
    return R_PC;
145
1
  case R_MIPS_GOT16:
146
0
  case R_MICROMIPS_GOT16:
147
0
    if (S.isLocal())
148
0
      return R_MIPS_GOT_LOCAL_PAGE;
149
0
    LLVM_FALLTHROUGH;
150
10.0k
  case R_MIPS_CALL16:
151
10.0k
  case R_MIPS_GOT_DISP:
152
10.0k
  case R_MIPS_TLS_GOTTPREL:
153
10.0k
  case R_MICROMIPS_CALL16:
154
10.0k
  case R_MICROMIPS_TLS_GOTTPREL:
155
10.0k
    return R_MIPS_GOT_OFF;
156
10.0k
  case R_MIPS_CALL_HI16:
157
0
  case R_MIPS_CALL_LO16:
158
0
  case R_MIPS_GOT_HI16:
159
0
  case R_MIPS_GOT_LO16:
160
0
  case R_MICROMIPS_CALL_HI16:
161
0
  case R_MICROMIPS_CALL_LO16:
162
0
  case R_MICROMIPS_GOT_HI16:
163
0
  case R_MICROMIPS_GOT_LO16:
164
0
    return R_MIPS_GOT_OFF32;
165
12
  case R_MIPS_GOT_PAGE:
166
12
    return R_MIPS_GOT_LOCAL_PAGE;
167
5
  case R_MIPS_TLS_GD:
168
5
  case R_MICROMIPS_TLS_GD:
169
5
    return R_MIPS_TLSGD;
170
5
  case R_MIPS_TLS_LDM:
171
2
  case R_MICROMIPS_TLS_LDM:
172
2
    return R_MIPS_TLSLD;
173
2
  case R_MIPS_NONE:
174
0
    return R_NONE;
175
2
  default:
176
0
    return R_INVALID;
177
10.0k
  }
178
10.0k
}
179
180
4
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
181
4
  if (Type == R_MIPS_32 || 
Type == R_MIPS_642
)
182
4
    return RelativeRel;
183
0
  return R_MIPS_NONE;
184
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getDynRel(unsigned int) const
Line
Count
Source
180
1
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
181
1
  if (Type == R_MIPS_32 || 
Type == R_MIPS_640
)
182
1
    return RelativeRel;
183
0
  return R_MIPS_NONE;
184
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getDynRel(unsigned int) const
Line
Count
Source
180
1
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
181
1
  if (Type == R_MIPS_32 || 
Type == R_MIPS_640
)
182
1
    return RelativeRel;
183
0
  return R_MIPS_NONE;
184
0
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getDynRel(unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getDynRel(unsigned int) const
Line
Count
Source
180
2
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
181
2
  if (Type == R_MIPS_32 || Type == R_MIPS_64)
182
2
    return RelativeRel;
183
0
  return R_MIPS_NONE;
184
0
}
185
186
template <class ELFT>
187
17
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
188
17
  uint64_t VA = InX::Plt->getVA();
189
17
  if (isMicroMips())
190
6
    VA |= 1;
191
17
  write32<ELFT::TargetEndianness>(Buf, VA);
192
17
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Line
Count
Source
187
2
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
188
2
  uint64_t VA = InX::Plt->getVA();
189
2
  if (isMicroMips())
190
2
    VA |= 1;
191
2
  write32<ELFT::TargetEndianness>(Buf, VA);
192
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Line
Count
Source
187
13
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
188
13
  uint64_t VA = InX::Plt->getVA();
189
13
  if (isMicroMips())
190
4
    VA |= 1;
191
13
  write32<ELFT::TargetEndianness>(Buf, VA);
192
13
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Line
Count
Source
187
2
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
188
2
  uint64_t VA = InX::Plt->getVA();
189
2
  if (isMicroMips())
190
0
    VA |= 1;
191
2
  write32<ELFT::TargetEndianness>(Buf, VA);
192
2
}
193
194
34
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
195
34
  // The major opcode of a microMIPS instruction needs to appear
196
34
  // in the first 16-bit word (lowest address) for efficient hardware
197
34
  // decode so that it knows if the instruction is 16-bit or 32-bit
198
34
  // as early as possible. To do so, little-endian binaries keep 16-bit
199
34
  // words in a big-endian order. That is why we have to swap these
200
34
  // words to get a correct value.
201
34
  uint32_t V = read32<E>(Loc);
202
34
  if (E == support::little)
203
12
    return (V << 16) | (V >> 16);
204
22
  return V;
205
22
}
Mips.cpp:unsigned int readShuffle<(llvm::support::endianness)1>(unsigned char const*)
Line
Count
Source
194
12
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
195
12
  // The major opcode of a microMIPS instruction needs to appear
196
12
  // in the first 16-bit word (lowest address) for efficient hardware
197
12
  // decode so that it knows if the instruction is 16-bit or 32-bit
198
12
  // as early as possible. To do so, little-endian binaries keep 16-bit
199
12
  // words in a big-endian order. That is why we have to swap these
200
12
  // words to get a correct value.
201
12
  uint32_t V = read32<E>(Loc);
202
12
  if (E == support::little)
203
12
    return (V << 16) | (V >> 16);
204
0
  return V;
205
0
}
Mips.cpp:unsigned int readShuffle<(llvm::support::endianness)0>(unsigned char const*)
Line
Count
Source
194
22
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
195
22
  // The major opcode of a microMIPS instruction needs to appear
196
22
  // in the first 16-bit word (lowest address) for efficient hardware
197
22
  // decode so that it knows if the instruction is 16-bit or 32-bit
198
22
  // as early as possible. To do so, little-endian binaries keep 16-bit
199
22
  // words in a big-endian order. That is why we have to swap these
200
22
  // words to get a correct value.
201
22
  uint32_t V = read32<E>(Loc);
202
22
  if (E == support::little)
203
0
    return (V << 16) | (V >> 16);
204
22
  return V;
205
22
}
206
207
template <endianness E>
208
static void writeValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
209
10.4k
                       uint8_t Shift) {
210
10.4k
  uint32_t Instr = read32<E>(Loc);
211
10.4k
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
212
10.4k
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
213
10.4k
  write32<E>(Loc, Data);
214
10.4k
}
Mips.cpp:void writeValue<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
209
26
                       uint8_t Shift) {
210
26
  uint32_t Instr = read32<E>(Loc);
211
26
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
212
26
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
213
26
  write32<E>(Loc, Data);
214
26
}
Mips.cpp:void writeValue<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
209
10.4k
                       uint8_t Shift) {
210
10.4k
  uint32_t Instr = read32<E>(Loc);
211
10.4k
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
212
10.4k
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
213
10.4k
  write32<E>(Loc, Data);
214
10.4k
}
215
216
template <endianness E>
217
static void writeShuffleValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
218
57
                              uint8_t Shift) {
219
57
  // See comments in readShuffle for purpose of this code.
220
57
  uint16_t *Words = (uint16_t *)Loc;
221
57
  if (E == support::little)
222
22
    std::swap(Words[0], Words[1]);
223
57
224
57
  writeValue<E>(Loc, V, BitsSize, Shift);
225
57
226
57
  if (E == support::little)
227
22
    std::swap(Words[0], Words[1]);
228
57
}
Mips.cpp:void writeShuffleValue<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
218
22
                              uint8_t Shift) {
219
22
  // See comments in readShuffle for purpose of this code.
220
22
  uint16_t *Words = (uint16_t *)Loc;
221
22
  if (E == support::little)
222
22
    std::swap(Words[0], Words[1]);
223
22
224
22
  writeValue<E>(Loc, V, BitsSize, Shift);
225
22
226
22
  if (E == support::little)
227
22
    std::swap(Words[0], Words[1]);
228
22
}
Mips.cpp:void writeShuffleValue<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
218
35
                              uint8_t Shift) {
219
35
  // See comments in readShuffle for purpose of this code.
220
35
  uint16_t *Words = (uint16_t *)Loc;
221
35
  if (E == support::little)
222
0
    std::swap(Words[0], Words[1]);
223
35
224
35
  writeValue<E>(Loc, V, BitsSize, Shift);
225
35
226
35
  if (E == support::little)
227
0
    std::swap(Words[0], Words[1]);
228
35
}
229
230
template <endianness E>
231
static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
232
4
                                   uint8_t Shift) {
233
4
  uint16_t Instr = read16<E>(Loc);
234
4
  uint16_t Mask = 0xffff >> (16 - BitsSize);
235
4
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
236
4
  write16<E>(Loc, Data);
237
4
}
Mips.cpp:void writeMicroRelocation16<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
232
2
                                   uint8_t Shift) {
233
2
  uint16_t Instr = read16<E>(Loc);
234
2
  uint16_t Mask = 0xffff >> (16 - BitsSize);
235
2
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
236
2
  write16<E>(Loc, Data);
237
2
}
Mips.cpp:void writeMicroRelocation16<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
232
2
                                   uint8_t Shift) {
233
2
  uint16_t Instr = read16<E>(Loc);
234
2
  uint16_t Mask = 0xffff >> (16 - BitsSize);
235
2
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
236
2
  write16<E>(Loc, Data);
237
2
}
238
239
15
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
240
15
  const endianness E = ELFT::TargetEndianness;
241
15
  if (isMicroMips()) {
242
6
    uint64_t GotPlt = InX::GotPlt->getVA();
243
6
    uint64_t Plt = InX::Plt->getVA();
244
6
    // Overwrite trap instructions written by Writer::writeTrapInstr.
245
6
    memset(Buf, 0, PltHeaderSize);
246
6
247
6
    write16<E>(Buf, isMipsR6() ? 
0x78602
:
0x79804
); // addiupc v1, (GOTPLT) - .
248
6
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
249
6
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
250
6
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
251
6
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
252
6
    write16<E>(Buf + 14, 0xfffe);
253
6
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
254
6
    if (isMipsR6()) {
255
2
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
256
2
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
257
2
      write16<E>(Buf + 22, 0x0c00); // nop
258
2
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
259
4
    } else {
260
4
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
261
4
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
262
4
      write16<E>(Buf + 22, 0x0c00); // nop
263
4
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
264
4
    }
265
6
    return;
266
6
  }
267
9
268
9
  if (Config->MipsN32Abi) {
269
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
270
2
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
271
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
272
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
273
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
274
2
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
275
7
  } else if (ELFT::Is64Bits) {
276
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
277
2
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
278
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
279
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
280
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
281
2
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
282
5
  } else {
283
5
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
284
5
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
285
5
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
286
5
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
287
5
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
288
5
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
289
5
  }
290
9
291
9
  uint32_t JalrInst = Config->ZHazardplt ? 
0x0320fc093
:
0x0320f8096
;
292
9
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
293
9
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
294
9
295
9
  uint64_t GotPlt = InX::GotPlt->getVA();
296
9
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
297
9
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
298
9
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
299
9
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writePltHeader(unsigned char*) const
Line
Count
Source
239
2
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
240
2
  const endianness E = ELFT::TargetEndianness;
241
2
  if (isMicroMips()) {
242
2
    uint64_t GotPlt = InX::GotPlt->getVA();
243
2
    uint64_t Plt = InX::Plt->getVA();
244
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
245
2
    memset(Buf, 0, PltHeaderSize);
246
2
247
2
    write16<E>(Buf, isMipsR6() ? 
0x78601
:
0x79801
); // addiupc v1, (GOTPLT) - .
248
2
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
249
2
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
250
2
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
251
2
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
252
2
    write16<E>(Buf + 14, 0xfffe);
253
2
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
254
2
    if (isMipsR6()) {
255
1
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
256
1
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
257
1
      write16<E>(Buf + 22, 0x0c00); // nop
258
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
259
1
    } else {
260
1
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
261
1
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
262
1
      write16<E>(Buf + 22, 0x0c00); // nop
263
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
264
1
    }
265
2
    return;
266
2
  }
267
0
268
0
  if (Config->MipsN32Abi) {
269
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
270
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
271
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
272
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
273
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
274
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
275
0
  } else if (ELFT::Is64Bits) {
276
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
277
0
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
278
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
279
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
280
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
281
0
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
282
0
  } else {
283
0
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
284
0
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
285
0
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
286
0
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
287
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
288
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
289
0
  }
290
0
291
0
  uint32_t JalrInst = Config->ZHazardplt ? 0x0320fc09 : 0x0320f809;
292
0
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
293
0
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
294
0
295
0
  uint64_t GotPlt = InX::GotPlt->getVA();
296
0
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
297
0
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
298
0
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
299
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writePltHeader(unsigned char*) const
Line
Count
Source
239
11
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
240
11
  const endianness E = ELFT::TargetEndianness;
241
11
  if (isMicroMips()) {
242
4
    uint64_t GotPlt = InX::GotPlt->getVA();
243
4
    uint64_t Plt = InX::Plt->getVA();
244
4
    // Overwrite trap instructions written by Writer::writeTrapInstr.
245
4
    memset(Buf, 0, PltHeaderSize);
246
4
247
4
    write16<E>(Buf, isMipsR6() ? 
0x78601
:
0x79803
); // addiupc v1, (GOTPLT) - .
248
4
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
249
4
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
250
4
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
251
4
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
252
4
    write16<E>(Buf + 14, 0xfffe);
253
4
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
254
4
    if (isMipsR6()) {
255
1
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
256
1
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
257
1
      write16<E>(Buf + 22, 0x0c00); // nop
258
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
259
3
    } else {
260
3
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
261
3
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
262
3
      write16<E>(Buf + 22, 0x0c00); // nop
263
3
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
264
3
    }
265
4
    return;
266
4
  }
267
7
268
7
  if (Config->MipsN32Abi) {
269
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
270
2
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
271
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
272
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
273
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
274
2
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
275
5
  } else if (ELFT::Is64Bits) {
276
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
277
0
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
278
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
279
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
280
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
281
0
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
282
5
  } else {
283
5
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
284
5
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
285
5
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
286
5
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
287
5
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
288
5
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
289
5
  }
290
7
291
7
  uint32_t JalrInst = Config->ZHazardplt ? 
0x0320fc092
:
0x0320f8095
;
292
7
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
293
7
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
294
7
295
7
  uint64_t GotPlt = InX::GotPlt->getVA();
296
7
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
297
7
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
298
7
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
299
7
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writePltHeader(unsigned char*) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writePltHeader(unsigned char*) const
Line
Count
Source
239
2
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
240
2
  const endianness E = ELFT::TargetEndianness;
241
2
  if (isMicroMips()) {
242
0
    uint64_t GotPlt = InX::GotPlt->getVA();
243
0
    uint64_t Plt = InX::Plt->getVA();
244
0
    // Overwrite trap instructions written by Writer::writeTrapInstr.
245
0
    memset(Buf, 0, PltHeaderSize);
246
0
247
0
    write16<E>(Buf, isMipsR6() ? 0x7860 : 0x7980);  // addiupc v1, (GOTPLT) - .
248
0
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
249
0
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
250
0
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
251
0
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
252
0
    write16<E>(Buf + 14, 0xfffe);
253
0
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
254
0
    if (isMipsR6()) {
255
0
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
256
0
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
257
0
      write16<E>(Buf + 22, 0x0c00); // nop
258
0
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
259
0
    } else {
260
0
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
261
0
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
262
0
      write16<E>(Buf + 22, 0x0c00); // nop
263
0
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
264
0
    }
265
0
    return;
266
0
  }
267
2
268
2
  if (Config->MipsN32Abi) {
269
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
270
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
271
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
272
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
273
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
274
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
275
2
  } else if (ELFT::Is64Bits) {
276
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
277
2
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
278
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
279
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
280
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
281
2
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
282
2
  } else {
283
0
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
284
0
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
285
0
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
286
0
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
287
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
288
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
289
0
  }
290
2
291
2
  uint32_t JalrInst = Config->ZHazardplt ? 
0x0320fc091
:
0x0320f8091
;
292
2
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
293
2
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
294
2
295
2
  uint64_t GotPlt = InX::GotPlt->getVA();
296
2
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
297
2
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
298
2
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
299
2
}
300
301
template <class ELFT>
302
void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
303
                          uint64_t PltEntryAddr, int32_t Index,
304
17
                          unsigned RelOff) const {
305
17
  const endianness E = ELFT::TargetEndianness;
306
17
  if (isMicroMips()) {
307
6
    // Overwrite trap instructions written by Writer::writeTrapInstr.
308
6
    memset(Buf, 0, PltEntrySize);
309
6
310
6
    if (isMipsR6()) {
311
2
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
312
2
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
313
2
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
314
2
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
315
2
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
316
4
    } else {
317
4
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
318
4
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
319
4
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
320
4
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
321
4
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
322
4
    }
323
6
    return;
324
6
  }
325
11
326
11
  uint32_t JrInst = isMipsR6() ? 
(Config->ZHazardplt 2
?
0x032004091
:
0x032000091
)
327
11
                               : 
(Config->ZHazardplt 9
?
0x032004082
:
0x032000087
);
328
11
329
11
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
330
11
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
331
11
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
332
11
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
333
11
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
334
11
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
335
11
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
336
11
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
304
2
                          unsigned RelOff) const {
305
2
  const endianness E = ELFT::TargetEndianness;
306
2
  if (isMicroMips()) {
307
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
308
2
    memset(Buf, 0, PltEntrySize);
309
2
310
2
    if (isMipsR6()) {
311
1
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
312
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
313
1
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
314
1
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
315
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
316
1
    } else {
317
1
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
318
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
319
1
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
320
1
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
321
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
322
1
    }
323
2
    return;
324
2
  }
325
0
326
0
  uint32_t JrInst = isMipsR6() ? (Config->ZHazardplt ? 0x03200409 : 0x03200009)
327
0
                               : (Config->ZHazardplt ? 0x03200408 : 0x03200008);
328
0
329
0
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
330
0
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
331
0
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
332
0
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
333
0
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
334
0
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
335
0
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
336
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
304
13
                          unsigned RelOff) const {
305
13
  const endianness E = ELFT::TargetEndianness;
306
13
  if (isMicroMips()) {
307
4
    // Overwrite trap instructions written by Writer::writeTrapInstr.
308
4
    memset(Buf, 0, PltEntrySize);
309
4
310
4
    if (isMipsR6()) {
311
1
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
312
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
313
1
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
314
1
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
315
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
316
3
    } else {
317
3
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
318
3
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
319
3
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
320
3
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
321
3
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
322
3
    }
323
4
    return;
324
4
  }
325
9
326
9
  uint32_t JrInst = isMipsR6() ? 
(Config->ZHazardplt 2
?
0x032004091
:
0x032000091
)
327
9
                               : 
(Config->ZHazardplt 7
?
0x032004081
:
0x032000086
);
328
9
329
9
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
330
9
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
331
9
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
332
9
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
333
9
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
334
9
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
335
9
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
336
9
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
304
2
                          unsigned RelOff) const {
305
2
  const endianness E = ELFT::TargetEndianness;
306
2
  if (isMicroMips()) {
307
0
    // Overwrite trap instructions written by Writer::writeTrapInstr.
308
0
    memset(Buf, 0, PltEntrySize);
309
0
310
0
    if (isMipsR6()) {
311
0
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
312
0
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
313
0
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
314
0
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
315
0
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
316
0
    } else {
317
0
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
318
0
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
319
0
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
320
0
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
321
0
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
322
0
    }
323
0
    return;
324
0
  }
325
2
326
2
  uint32_t JrInst = isMipsR6() ? 
(Config->ZHazardplt 0
?
0x032004090
:
0x032000090
)
327
2
                               : (Config->ZHazardplt ? 
0x032004081
:
0x032000081
);
328
2
329
2
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
330
2
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
331
2
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
332
2
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
333
2
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
334
2
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
335
2
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
336
2
}
337
338
template <class ELFT>
339
bool MIPS<ELFT>::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
340
10.3k
                            uint64_t BranchAddr, const Symbol &S) const {
341
10.3k
  // Any MIPS PIC code function is invoked with its address in register $t9.
342
10.3k
  // So if we have a branch instruction from non-PIC code to the PIC one
343
10.3k
  // we cannot make the jump directly and need to create a small stubs
344
10.3k
  // to save the target function address.
345
10.3k
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
346
10.3k
  if (Type != R_MIPS_26 && 
Type != R_MICROMIPS_26_S110.2k
&&
347
10.3k
      
Type != R_MICROMIPS_PC26_S110.2k
)
348
10.2k
    return false;
349
73
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
350
73
  if (!F)
351
0
    return false;
352
73
  // If current file has PIC code, LA25 stub is not required.
353
73
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
354
0
    return false;
355
73
  auto *D = dyn_cast<Defined>(&S);
356
73
  // LA25 is required if target file has PIC code
357
73
  // or target symbol is a PIC symbol.
358
73
  return D && 
isMipsPIC<ELFT>(D)60
;
359
73
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Line
Count
Source
340
18
                            uint64_t BranchAddr, const Symbol &S) const {
341
18
  // Any MIPS PIC code function is invoked with its address in register $t9.
342
18
  // So if we have a branch instruction from non-PIC code to the PIC one
343
18
  // we cannot make the jump directly and need to create a small stubs
344
18
  // to save the target function address.
345
18
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
346
18
  if (Type != R_MIPS_26 && Type != R_MICROMIPS_26_S1 &&
347
18
      
Type != R_MICROMIPS_PC26_S116
)
348
13
    return false;
349
5
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
350
5
  if (!F)
351
0
    return false;
352
5
  // If current file has PIC code, LA25 stub is not required.
353
5
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
354
0
    return false;
355
5
  auto *D = dyn_cast<Defined>(&S);
356
5
  // LA25 is required if target file has PIC code
357
5
  // or target symbol is a PIC symbol.
358
5
  return D && 
isMipsPIC<ELFT>(D)3
;
359
5
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Line
Count
Source
340
248
                            uint64_t BranchAddr, const Symbol &S) const {
341
248
  // Any MIPS PIC code function is invoked with its address in register $t9.
342
248
  // So if we have a branch instruction from non-PIC code to the PIC one
343
248
  // we cannot make the jump directly and need to create a small stubs
344
248
  // to save the target function address.
345
248
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
346
248
  if (Type != R_MIPS_26 && 
Type != R_MICROMIPS_26_S1189
&&
347
248
      
Type != R_MICROMIPS_PC26_S1185
)
348
182
    return false;
349
66
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
350
66
  if (!F)
351
0
    return false;
352
66
  // If current file has PIC code, LA25 stub is not required.
353
66
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
354
0
    return false;
355
66
  auto *D = dyn_cast<Defined>(&S);
356
66
  // LA25 is required if target file has PIC code
357
66
  // or target symbol is a PIC symbol.
358
66
  return D && 
isMipsPIC<ELFT>(D)57
;
359
66
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Line
Count
Source
340
10.0k
                            uint64_t BranchAddr, const Symbol &S) const {
341
10.0k
  // Any MIPS PIC code function is invoked with its address in register $t9.
342
10.0k
  // So if we have a branch instruction from non-PIC code to the PIC one
343
10.0k
  // we cannot make the jump directly and need to create a small stubs
344
10.0k
  // to save the target function address.
345
10.0k
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
346
10.0k
  if (Type != R_MIPS_26 && 
Type != R_MICROMIPS_26_S110.0k
&&
347
10.0k
      
Type != R_MICROMIPS_PC26_S110.0k
)
348
10.0k
    return false;
349
2
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
350
2
  if (!F)
351
0
    return false;
352
2
  // If current file has PIC code, LA25 stub is not required.
353
2
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
354
0
    return false;
355
2
  auto *D = dyn_cast<Defined>(&S);
356
2
  // LA25 is required if target file has PIC code
357
2
  // or target symbol is a PIC symbol.
358
2
  return D && 
isMipsPIC<ELFT>(D)0
;
359
2
}
360
361
template <class ELFT>
362
330
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
363
330
  const endianness E = ELFT::TargetEndianness;
364
330
  switch (Type) {
365
330
  case R_MIPS_32:
366
27
  case R_MIPS_GPREL32:
367
27
  case R_MIPS_TLS_DTPREL32:
368
27
  case R_MIPS_TLS_TPREL32:
369
27
    return SignExtend64<32>(read32<E>(Buf));
370
50
  case R_MIPS_26:
371
50
    // FIXME (simon): If the relocation target symbol is not a PLT entry
372
50
    // we should use another expression for calculation:
373
50
    // ((A << 2) | (P & 0xf0000000)) >> 2
374
50
    return SignExtend64<28>(read32<E>(Buf) << 2);
375
66
  case R_MIPS_GOT16:
376
66
  case R_MIPS_HI16:
377
66
  case R_MIPS_PCHI16:
378
66
    return SignExtend64<16>(read32<E>(Buf)) << 16;
379
90
  case R_MIPS_GPREL16:
380
90
  case R_MIPS_LO16:
381
90
  case R_MIPS_PCLO16:
382
90
  case R_MIPS_TLS_DTPREL_HI16:
383
90
  case R_MIPS_TLS_DTPREL_LO16:
384
90
  case R_MIPS_TLS_TPREL_HI16:
385
90
  case R_MIPS_TLS_TPREL_LO16:
386
90
    return SignExtend64<16>(read32<E>(Buf));
387
90
  case R_MICROMIPS_GOT16:
388
7
  case R_MICROMIPS_HI16:
389
7
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
390
9
  case R_MICROMIPS_GPREL16:
391
9
  case R_MICROMIPS_LO16:
392
9
  case R_MICROMIPS_TLS_DTPREL_HI16:
393
9
  case R_MICROMIPS_TLS_DTPREL_LO16:
394
9
  case R_MICROMIPS_TLS_TPREL_HI16:
395
9
  case R_MICROMIPS_TLS_TPREL_LO16:
396
9
    return SignExtend64<16>(readShuffle<E>(Buf));
397
9
  case R_MICROMIPS_GPREL7_S2:
398
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
399
9
  case R_MIPS_PC16:
400
2
    return SignExtend64<18>(read32<E>(Buf) << 2);
401
9
  case R_MIPS_PC19_S2:
402
1
    return SignExtend64<21>(read32<E>(Buf) << 2);
403
9
  case R_MIPS_PC21_S2:
404
1
    return SignExtend64<23>(read32<E>(Buf) << 2);
405
9
  case R_MIPS_PC26_S2:
406
1
    return SignExtend64<28>(read32<E>(Buf) << 2);
407
9
  case R_MIPS_PC32:
408
1
    return SignExtend64<32>(read32<E>(Buf));
409
9
  case R_MICROMIPS_26_S1:
410
6
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
411
9
  case R_MICROMIPS_PC7_S1:
412
2
    return SignExtend64<8>(read16<E>(Buf) << 1);
413
9
  case R_MICROMIPS_PC10_S1:
414
2
    return SignExtend64<11>(read16<E>(Buf) << 1);
415
9
  case R_MICROMIPS_PC16_S1:
416
2
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
417
9
  case R_MICROMIPS_PC18_S3:
418
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
419
9
  case R_MICROMIPS_PC19_S2:
420
2
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
421
9
  case R_MICROMIPS_PC21_S1:
422
2
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
423
9
  case R_MICROMIPS_PC23_S2:
424
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
425
9
  case R_MICROMIPS_PC26_S1:
426
6
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
427
53
  default:
428
53
    return 0;
429
330
  }
430
330
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getImplicitAddend(unsigned char const*, unsigned int) const
Line
Count
Source
362
21
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
363
21
  const endianness E = ELFT::TargetEndianness;
364
21
  switch (Type) {
365
21
  case R_MIPS_32:
366
2
  case R_MIPS_GPREL32:
367
2
  case R_MIPS_TLS_DTPREL32:
368
2
  case R_MIPS_TLS_TPREL32:
369
2
    return SignExtend64<32>(read32<E>(Buf));
370
2
  case R_MIPS_26:
371
0
    // FIXME (simon): If the relocation target symbol is not a PLT entry
372
0
    // we should use another expression for calculation:
373
0
    // ((A << 2) | (P & 0xf0000000)) >> 2
374
0
    return SignExtend64<28>(read32<E>(Buf) << 2);
375
4
  case R_MIPS_GOT16:
376
4
  case R_MIPS_HI16:
377
4
  case R_MIPS_PCHI16:
378
4
    return SignExtend64<16>(read32<E>(Buf)) << 16;
379
4
  case R_MIPS_GPREL16:
380
0
  case R_MIPS_LO16:
381
0
  case R_MIPS_PCLO16:
382
0
  case R_MIPS_TLS_DTPREL_HI16:
383
0
  case R_MIPS_TLS_DTPREL_LO16:
384
0
  case R_MIPS_TLS_TPREL_HI16:
385
0
  case R_MIPS_TLS_TPREL_LO16:
386
0
    return SignExtend64<16>(read32<E>(Buf));
387
2
  case R_MICROMIPS_GOT16:
388
2
  case R_MICROMIPS_HI16:
389
2
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
390
2
  case R_MICROMIPS_GPREL16:
391
2
  case R_MICROMIPS_LO16:
392
2
  case R_MICROMIPS_TLS_DTPREL_HI16:
393
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
394
2
  case R_MICROMIPS_TLS_TPREL_HI16:
395
2
  case R_MICROMIPS_TLS_TPREL_LO16:
396
2
    return SignExtend64<16>(readShuffle<E>(Buf));
397
2
  case R_MICROMIPS_GPREL7_S2:
398
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
399
2
  case R_MIPS_PC16:
400
0
    return SignExtend64<18>(read32<E>(Buf) << 2);
401
2
  case R_MIPS_PC19_S2:
402
0
    return SignExtend64<21>(read32<E>(Buf) << 2);
403
2
  case R_MIPS_PC21_S2:
404
0
    return SignExtend64<23>(read32<E>(Buf) << 2);
405
2
  case R_MIPS_PC26_S2:
406
0
    return SignExtend64<28>(read32<E>(Buf) << 2);
407
2
  case R_MIPS_PC32:
408
0
    return SignExtend64<32>(read32<E>(Buf));
409
2
  case R_MICROMIPS_26_S1:
410
2
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
411
2
  case R_MICROMIPS_PC7_S1:
412
1
    return SignExtend64<8>(read16<E>(Buf) << 1);
413
2
  case R_MICROMIPS_PC10_S1:
414
1
    return SignExtend64<11>(read16<E>(Buf) << 1);
415
2
  case R_MICROMIPS_PC16_S1:
416
1
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
417
2
  case R_MICROMIPS_PC18_S3:
418
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
419
2
  case R_MICROMIPS_PC19_S2:
420
1
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
421
2
  case R_MICROMIPS_PC21_S1:
422
1
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
423
2
  case R_MICROMIPS_PC23_S2:
424
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
425
3
  case R_MICROMIPS_PC26_S1:
426
3
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
427
2
  default:
428
1
    return 0;
429
21
  }
430
21
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getImplicitAddend(unsigned char const*, unsigned int) const
Line
Count
Source
362
309
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
363
309
  const endianness E = ELFT::TargetEndianness;
364
309
  switch (Type) {
365
309
  case R_MIPS_32:
366
25
  case R_MIPS_GPREL32:
367
25
  case R_MIPS_TLS_DTPREL32:
368
25
  case R_MIPS_TLS_TPREL32:
369
25
    return SignExtend64<32>(read32<E>(Buf));
370
50
  case R_MIPS_26:
371
50
    // FIXME (simon): If the relocation target symbol is not a PLT entry
372
50
    // we should use another expression for calculation:
373
50
    // ((A << 2) | (P & 0xf0000000)) >> 2
374
50
    return SignExtend64<28>(read32<E>(Buf) << 2);
375
62
  case R_MIPS_GOT16:
376
62
  case R_MIPS_HI16:
377
62
  case R_MIPS_PCHI16:
378
62
    return SignExtend64<16>(read32<E>(Buf)) << 16;
379
90
  case R_MIPS_GPREL16:
380
90
  case R_MIPS_LO16:
381
90
  case R_MIPS_PCLO16:
382
90
  case R_MIPS_TLS_DTPREL_HI16:
383
90
  case R_MIPS_TLS_DTPREL_LO16:
384
90
  case R_MIPS_TLS_TPREL_HI16:
385
90
  case R_MIPS_TLS_TPREL_LO16:
386
90
    return SignExtend64<16>(read32<E>(Buf));
387
90
  case R_MICROMIPS_GOT16:
388
5
  case R_MICROMIPS_HI16:
389
5
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
390
7
  case R_MICROMIPS_GPREL16:
391
7
  case R_MICROMIPS_LO16:
392
7
  case R_MICROMIPS_TLS_DTPREL_HI16:
393
7
  case R_MICROMIPS_TLS_DTPREL_LO16:
394
7
  case R_MICROMIPS_TLS_TPREL_HI16:
395
7
  case R_MICROMIPS_TLS_TPREL_LO16:
396
7
    return SignExtend64<16>(readShuffle<E>(Buf));
397
7
  case R_MICROMIPS_GPREL7_S2:
398
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
399
7
  case R_MIPS_PC16:
400
2
    return SignExtend64<18>(read32<E>(Buf) << 2);
401
7
  case R_MIPS_PC19_S2:
402
1
    return SignExtend64<21>(read32<E>(Buf) << 2);
403
7
  case R_MIPS_PC21_S2:
404
1
    return SignExtend64<23>(read32<E>(Buf) << 2);
405
7
  case R_MIPS_PC26_S2:
406
1
    return SignExtend64<28>(read32<E>(Buf) << 2);
407
7
  case R_MIPS_PC32:
408
1
    return SignExtend64<32>(read32<E>(Buf));
409
7
  case R_MICROMIPS_26_S1:
410
4
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
411
7
  case R_MICROMIPS_PC7_S1:
412
1
    return SignExtend64<8>(read16<E>(Buf) << 1);
413
7
  case R_MICROMIPS_PC10_S1:
414
1
    return SignExtend64<11>(read16<E>(Buf) << 1);
415
7
  case R_MICROMIPS_PC16_S1:
416
1
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
417
7
  case R_MICROMIPS_PC18_S3:
418
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
419
7
  case R_MICROMIPS_PC19_S2:
420
1
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
421
7
  case R_MICROMIPS_PC21_S1:
422
1
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
423
7
  case R_MICROMIPS_PC23_S2:
424
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
425
7
  case R_MICROMIPS_PC26_S1:
426
3
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
427
52
  default:
428
52
    return 0;
429
309
  }
430
309
}
431
432
static std::pair<uint32_t, uint64_t>
433
10.0k
calculateMipsRelChain(uint8_t *Loc, RelType Type, uint64_t Val) {
434
10.0k
  // MIPS N64 ABI packs multiple relocations into the single relocation
435
10.0k
  // record. In general, all up to three relocations can have arbitrary
436
10.0k
  // types. In fact, Clang and GCC uses only a few combinations. For now,
437
10.0k
  // we support two of them. That is allow to pass at least all LLVM
438
10.0k
  // test suite cases.
439
10.0k
  // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
440
10.0k
  // <any relocation> / R_MIPS_64 / R_MIPS_NONE
441
10.0k
  // The first relocation is a 'real' relocation which is calculated
442
10.0k
  // using the corresponding symbol's value. The second and the third
443
10.0k
  // relocations used to modify result of the first one: extend it to
444
10.0k
  // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
445
10.0k
  // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
446
10.0k
  RelType Type2 = (Type >> 8) & 0xff;
447
10.0k
  RelType Type3 = (Type >> 16) & 0xff;
448
10.0k
  if (Type2 == R_MIPS_NONE && 
Type3 == R_MIPS_NONE10.0k
)
449
10.0k
    return std::make_pair(Type, Val);
450
12
  if (Type2 == R_MIPS_64 && 
Type3 == R_MIPS_NONE1
)
451
1
    return std::make_pair(Type2, Val);
452
11
  if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || 
Type3 == R_MIPS_LO164
))
453
11
    return std::make_pair(Type3, -Val);
454
0
  error(getErrorLocation(Loc) + "unsupported relocations combination " +
455
0
        Twine(Type));
456
0
  return std::make_pair(Type & 0xff, Val);
457
0
}
458
459
template <class ELFT>
460
10.4k
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
461
10.4k
  const endianness E = ELFT::TargetEndianness;
462
10.4k
463
10.4k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi374
)
464
10.0k
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
465
10.4k
466
10.4k
  // Thread pointer and DRP offsets from the start of TLS data area.
467
10.4k
  // https://www.linux-mips.org/wiki/NPTL
468
10.4k
  if (Type == R_MIPS_TLS_DTPREL_HI16 || 
Type == R_MIPS_TLS_DTPREL_LO1610.4k
||
469
10.4k
      
Type == R_MIPS_TLS_DTPREL3210.4k
||
Type == R_MIPS_TLS_DTPREL6410.4k
||
470
10.4k
      
Type == R_MICROMIPS_TLS_DTPREL_HI1610.4k
||
471
10.4k
      
Type == R_MICROMIPS_TLS_DTPREL_LO1610.4k
) {
472
6
    Val -= 0x8000;
473
10.4k
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || 
Type == R_MIPS_TLS_TPREL_LO1610.4k
||
474
10.4k
             
Type == R_MIPS_TLS_TPREL3210.4k
||
Type == R_MIPS_TLS_TPREL6410.4k
||
475
10.4k
             
Type == R_MICROMIPS_TLS_TPREL_HI1610.4k
||
476
10.4k
             
Type == R_MICROMIPS_TLS_TPREL_LO1610.4k
) {
477
6
    Val -= 0x7000;
478
6
  }
479
10.4k
480
10.4k
  switch (Type) {
481
10.4k
  case R_MIPS_32:
482
31
  case R_MIPS_GPREL32:
483
31
  case R_MIPS_TLS_DTPREL32:
484
31
  case R_MIPS_TLS_TPREL32:
485
31
    write32<E>(Loc, Val);
486
31
    break;
487
31
  case R_MIPS_64:
488
8
  case R_MIPS_TLS_DTPREL64:
489
8
  case R_MIPS_TLS_TPREL64:
490
8
    write64<E>(Loc, Val);
491
8
    break;
492
54
  case R_MIPS_26:
493
54
    writeValue<E>(Loc, Val, 26, 2);
494
54
    break;
495
42
  case R_MIPS_GOT16:
496
42
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
497
42
    // is updated addend (not a GOT index). In that case write high 16 bits
498
42
    // to store a correct addend value.
499
42
    if (Config->Relocatable) {
500
2
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
501
40
    } else {
502
40
      checkInt(Loc, Val, 16, Type);
503
40
      writeValue<E>(Loc, Val, 16, 0);
504
40
    }
505
42
    break;
506
8
  case R_MICROMIPS_GOT16:
507
4
    if (Config->Relocatable) {
508
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
509
4
    } else {
510
4
      checkInt(Loc, Val, 16, Type);
511
4
      writeShuffleValue<E>(Loc, Val, 16, 0);
512
4
    }
513
4
    break;
514
10.0k
  case R_MIPS_CALL16:
515
10.0k
  case R_MIPS_GOT_DISP:
516
10.0k
  case R_MIPS_GOT_PAGE:
517
10.0k
  case R_MIPS_GPREL16:
518
10.0k
  case R_MIPS_TLS_GD:
519
10.0k
  case R_MIPS_TLS_GOTTPREL:
520
10.0k
  case R_MIPS_TLS_LDM:
521
10.0k
    checkInt(Loc, Val, 16, Type);
522
10.0k
    LLVM_FALLTHROUGH;
523
10.1k
  case R_MIPS_CALL_LO16:
524
10.1k
  case R_MIPS_GOT_LO16:
525
10.1k
  case R_MIPS_GOT_OFST:
526
10.1k
  case R_MIPS_LO16:
527
10.1k
  case R_MIPS_PCLO16:
528
10.1k
  case R_MIPS_TLS_DTPREL_LO16:
529
10.1k
  case R_MIPS_TLS_TPREL_LO16:
530
10.1k
    writeValue<E>(Loc, Val, 16, 0);
531
10.1k
    break;
532
10.1k
  case R_MICROMIPS_GPREL16:
533
0
  case R_MICROMIPS_TLS_GD:
534
0
  case R_MICROMIPS_TLS_LDM:
535
0
    checkInt(Loc, Val, 16, Type);
536
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
537
0
    break;
538
12
  case R_MICROMIPS_CALL16:
539
12
  case R_MICROMIPS_CALL_LO16:
540
12
  case R_MICROMIPS_LO16:
541
12
  case R_MICROMIPS_TLS_DTPREL_LO16:
542
12
  case R_MICROMIPS_TLS_GOTTPREL:
543
12
  case R_MICROMIPS_TLS_TPREL_LO16:
544
12
    writeShuffleValue<E>(Loc, Val, 16, 0);
545
12
    break;
546
12
  case R_MICROMIPS_GPREL7_S2:
547
0
    checkInt(Loc, Val, 7, Type);
548
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
549
0
    break;
550
72
  case R_MIPS_CALL_HI16:
551
72
  case R_MIPS_GOT_HI16:
552
72
  case R_MIPS_HI16:
553
72
  case R_MIPS_PCHI16:
554
72
  case R_MIPS_TLS_DTPREL_HI16:
555
72
  case R_MIPS_TLS_TPREL_HI16:
556
72
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
557
72
    break;
558
72
  case R_MICROMIPS_CALL_HI16:
559
7
  case R_MICROMIPS_GOT_HI16:
560
7
  case R_MICROMIPS_HI16:
561
7
  case R_MICROMIPS_TLS_DTPREL_HI16:
562
7
  case R_MICROMIPS_TLS_TPREL_HI16:
563
7
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
564
7
    break;
565
7
  case R_MIPS_HIGHER:
566
2
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
567
2
    break;
568
7
  case R_MIPS_HIGHEST:
569
2
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
570
2
    break;
571
7
  case R_MIPS_JALR:
572
0
  case R_MICROMIPS_JALR:
573
0
    // Ignore this optimization relocation for now
574
0
    break;
575
2
  case R_MIPS_PC16:
576
2
    checkAlignment(Loc, Val, 4, Type);
577
2
    checkInt(Loc, Val, 18, Type);
578
2
    writeValue<E>(Loc, Val, 16, 2);
579
2
    break;
580
1
  case R_MIPS_PC19_S2:
581
1
    checkAlignment(Loc, Val, 4, Type);
582
1
    checkInt(Loc, Val, 21, Type);
583
1
    writeValue<E>(Loc, Val, 19, 2);
584
1
    break;
585
1
  case R_MIPS_PC21_S2:
586
1
    checkAlignment(Loc, Val, 4, Type);
587
1
    checkInt(Loc, Val, 23, Type);
588
1
    writeValue<E>(Loc, Val, 21, 2);
589
1
    break;
590
1
  case R_MIPS_PC26_S2:
591
1
    checkAlignment(Loc, Val, 4, Type);
592
1
    checkInt(Loc, Val, 28, Type);
593
1
    writeValue<E>(Loc, Val, 26, 2);
594
1
    break;
595
2
  case R_MIPS_PC32:
596
2
    writeValue<E>(Loc, Val, 32, 0);
597
2
    break;
598
16
  case R_MICROMIPS_26_S1:
599
16
  case R_MICROMIPS_PC26_S1:
600
16
    checkInt(Loc, Val, 27, Type);
601
16
    writeShuffleValue<E>(Loc, Val, 26, 1);
602
16
    break;
603
16
  case R_MICROMIPS_PC7_S1:
604
2
    checkInt(Loc, Val, 8, Type);
605
2
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
606
2
    break;
607
16
  case R_MICROMIPS_PC10_S1:
608
2
    checkInt(Loc, Val, 11, Type);
609
2
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
610
2
    break;
611
16
  case R_MICROMIPS_PC16_S1:
612
2
    checkInt(Loc, Val, 17, Type);
613
2
    writeShuffleValue<E>(Loc, Val, 16, 1);
614
2
    break;
615
16
  case R_MICROMIPS_PC18_S3:
616
0
    checkInt(Loc, Val, 21, Type);
617
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
618
0
    break;
619
16
  case R_MICROMIPS_PC19_S2:
620
6
    checkInt(Loc, Val, 21, Type);
621
6
    writeShuffleValue<E>(Loc, Val, 19, 2);
622
6
    break;
623
16
  case R_MICROMIPS_PC21_S1:
624
2
    checkInt(Loc, Val, 22, Type);
625
2
    writeShuffleValue<E>(Loc, Val, 21, 1);
626
2
    break;
627
16
  case R_MICROMIPS_PC23_S2:
628
8
    checkInt(Loc, Val, 25, Type);
629
8
    writeShuffleValue<E>(Loc, Val, 23, 2);
630
8
    break;
631
16
  default:
632
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
633
10.4k
  }
634
10.4k
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
460
30
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
461
30
  const endianness E = ELFT::TargetEndianness;
462
30
463
30
  if (ELFT::Is64Bits || Config->MipsN32Abi)
464
0
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
465
30
466
30
  // Thread pointer and DRP offsets from the start of TLS data area.
467
30
  // https://www.linux-mips.org/wiki/NPTL
468
30
  if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
469
30
      Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 ||
470
30
      Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
471
30
      Type == R_MICROMIPS_TLS_DTPREL_LO16) {
472
0
    Val -= 0x8000;
473
30
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
474
30
             Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 ||
475
30
             Type == R_MICROMIPS_TLS_TPREL_HI16 ||
476
30
             Type == R_MICROMIPS_TLS_TPREL_LO16) {
477
0
    Val -= 0x7000;
478
0
  }
479
30
480
30
  switch (Type) {
481
30
  case R_MIPS_32:
482
2
  case R_MIPS_GPREL32:
483
2
  case R_MIPS_TLS_DTPREL32:
484
2
  case R_MIPS_TLS_TPREL32:
485
2
    write32<E>(Loc, Val);
486
2
    break;
487
2
  case R_MIPS_64:
488
0
  case R_MIPS_TLS_DTPREL64:
489
0
  case R_MIPS_TLS_TPREL64:
490
0
    write64<E>(Loc, Val);
491
0
    break;
492
0
  case R_MIPS_26:
493
0
    writeValue<E>(Loc, Val, 26, 2);
494
0
    break;
495
4
  case R_MIPS_GOT16:
496
4
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
497
4
    // is updated addend (not a GOT index). In that case write high 16 bits
498
4
    // to store a correct addend value.
499
4
    if (Config->Relocatable) {
500
0
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
501
4
    } else {
502
4
      checkInt(Loc, Val, 16, Type);
503
4
      writeValue<E>(Loc, Val, 16, 0);
504
4
    }
505
4
    break;
506
1
  case R_MICROMIPS_GOT16:
507
1
    if (Config->Relocatable) {
508
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
509
1
    } else {
510
1
      checkInt(Loc, Val, 16, Type);
511
1
      writeShuffleValue<E>(Loc, Val, 16, 0);
512
1
    }
513
1
    break;
514
0
  case R_MIPS_CALL16:
515
0
  case R_MIPS_GOT_DISP:
516
0
  case R_MIPS_GOT_PAGE:
517
0
  case R_MIPS_GPREL16:
518
0
  case R_MIPS_TLS_GD:
519
0
  case R_MIPS_TLS_GOTTPREL:
520
0
  case R_MIPS_TLS_LDM:
521
0
    checkInt(Loc, Val, 16, Type);
522
0
    LLVM_FALLTHROUGH;
523
0
  case R_MIPS_CALL_LO16:
524
0
  case R_MIPS_GOT_LO16:
525
0
  case R_MIPS_GOT_OFST:
526
0
  case R_MIPS_LO16:
527
0
  case R_MIPS_PCLO16:
528
0
  case R_MIPS_TLS_DTPREL_LO16:
529
0
  case R_MIPS_TLS_TPREL_LO16:
530
0
    writeValue<E>(Loc, Val, 16, 0);
531
0
    break;
532
0
  case R_MICROMIPS_GPREL16:
533
0
  case R_MICROMIPS_TLS_GD:
534
0
  case R_MICROMIPS_TLS_LDM:
535
0
    checkInt(Loc, Val, 16, Type);
536
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
537
0
    break;
538
4
  case R_MICROMIPS_CALL16:
539
4
  case R_MICROMIPS_CALL_LO16:
540
4
  case R_MICROMIPS_LO16:
541
4
  case R_MICROMIPS_TLS_DTPREL_LO16:
542
4
  case R_MICROMIPS_TLS_GOTTPREL:
543
4
  case R_MICROMIPS_TLS_TPREL_LO16:
544
4
    writeShuffleValue<E>(Loc, Val, 16, 0);
545
4
    break;
546
4
  case R_MICROMIPS_GPREL7_S2:
547
0
    checkInt(Loc, Val, 7, Type);
548
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
549
0
    break;
550
4
  case R_MIPS_CALL_HI16:
551
0
  case R_MIPS_GOT_HI16:
552
0
  case R_MIPS_HI16:
553
0
  case R_MIPS_PCHI16:
554
0
  case R_MIPS_TLS_DTPREL_HI16:
555
0
  case R_MIPS_TLS_TPREL_HI16:
556
0
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
557
0
    break;
558
3
  case R_MICROMIPS_CALL_HI16:
559
3
  case R_MICROMIPS_GOT_HI16:
560
3
  case R_MICROMIPS_HI16:
561
3
  case R_MICROMIPS_TLS_DTPREL_HI16:
562
3
  case R_MICROMIPS_TLS_TPREL_HI16:
563
3
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
564
3
    break;
565
3
  case R_MIPS_HIGHER:
566
0
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
567
0
    break;
568
3
  case R_MIPS_HIGHEST:
569
0
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
570
0
    break;
571
3
  case R_MIPS_JALR:
572
0
  case R_MICROMIPS_JALR:
573
0
    // Ignore this optimization relocation for now
574
0
    break;
575
0
  case R_MIPS_PC16:
576
0
    checkAlignment(Loc, Val, 4, Type);
577
0
    checkInt(Loc, Val, 18, Type);
578
0
    writeValue<E>(Loc, Val, 16, 2);
579
0
    break;
580
0
  case R_MIPS_PC19_S2:
581
0
    checkAlignment(Loc, Val, 4, Type);
582
0
    checkInt(Loc, Val, 21, Type);
583
0
    writeValue<E>(Loc, Val, 19, 2);
584
0
    break;
585
0
  case R_MIPS_PC21_S2:
586
0
    checkAlignment(Loc, Val, 4, Type);
587
0
    checkInt(Loc, Val, 23, Type);
588
0
    writeValue<E>(Loc, Val, 21, 2);
589
0
    break;
590
0
  case R_MIPS_PC26_S2:
591
0
    checkAlignment(Loc, Val, 4, Type);
592
0
    checkInt(Loc, Val, 28, Type);
593
0
    writeValue<E>(Loc, Val, 26, 2);
594
0
    break;
595
0
  case R_MIPS_PC32:
596
0
    writeValue<E>(Loc, Val, 32, 0);
597
0
    break;
598
7
  case R_MICROMIPS_26_S1:
599
7
  case R_MICROMIPS_PC26_S1:
600
7
    checkInt(Loc, Val, 27, Type);
601
7
    writeShuffleValue<E>(Loc, Val, 26, 1);
602
7
    break;
603
7
  case R_MICROMIPS_PC7_S1:
604
1
    checkInt(Loc, Val, 8, Type);
605
1
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
606
1
    break;
607
7
  case R_MICROMIPS_PC10_S1:
608
1
    checkInt(Loc, Val, 11, Type);
609
1
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
610
1
    break;
611
7
  case R_MICROMIPS_PC16_S1:
612
1
    checkInt(Loc, Val, 17, Type);
613
1
    writeShuffleValue<E>(Loc, Val, 16, 1);
614
1
    break;
615
7
  case R_MICROMIPS_PC18_S3:
616
0
    checkInt(Loc, Val, 21, Type);
617
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
618
0
    break;
619
7
  case R_MICROMIPS_PC19_S2:
620
3
    checkInt(Loc, Val, 21, Type);
621
3
    writeShuffleValue<E>(Loc, Val, 19, 2);
622
3
    break;
623
7
  case R_MICROMIPS_PC21_S1:
624
1
    checkInt(Loc, Val, 22, Type);
625
1
    writeShuffleValue<E>(Loc, Val, 21, 1);
626
1
    break;
627
7
  case R_MICROMIPS_PC23_S2:
628
2
    checkInt(Loc, Val, 25, Type);
629
2
    writeShuffleValue<E>(Loc, Val, 23, 2);
630
2
    break;
631
7
  default:
632
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
633
30
  }
634
30
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
460
344
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
461
344
  const endianness E = ELFT::TargetEndianness;
462
344
463
344
  if (ELFT::Is64Bits || Config->MipsN32Abi)
464
5
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
465
344
466
344
  // Thread pointer and DRP offsets from the start of TLS data area.
467
344
  // https://www.linux-mips.org/wiki/NPTL
468
344
  if (Type == R_MIPS_TLS_DTPREL_HI16 || 
Type == R_MIPS_TLS_DTPREL_LO16342
||
469
344
      
Type == R_MIPS_TLS_DTPREL32340
||
Type == R_MIPS_TLS_DTPREL64339
||
470
344
      
Type == R_MICROMIPS_TLS_DTPREL_HI16339
||
471
344
      
Type == R_MICROMIPS_TLS_DTPREL_LO16339
) {
472
5
    Val -= 0x8000;
473
339
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || 
Type == R_MIPS_TLS_TPREL_LO16337
||
474
339
             
Type == R_MIPS_TLS_TPREL32335
||
Type == R_MIPS_TLS_TPREL64334
||
475
339
             
Type == R_MICROMIPS_TLS_TPREL_HI16334
||
476
339
             
Type == R_MICROMIPS_TLS_TPREL_LO16334
) {
477
5
    Val -= 0x7000;
478
5
  }
479
344
480
344
  switch (Type) {
481
344
  case R_MIPS_32:
482
26
  case R_MIPS_GPREL32:
483
26
  case R_MIPS_TLS_DTPREL32:
484
26
  case R_MIPS_TLS_TPREL32:
485
26
    write32<E>(Loc, Val);
486
26
    break;
487
26
  case R_MIPS_64:
488
0
  case R_MIPS_TLS_DTPREL64:
489
0
  case R_MIPS_TLS_TPREL64:
490
0
    write64<E>(Loc, Val);
491
0
    break;
492
52
  case R_MIPS_26:
493
52
    writeValue<E>(Loc, Val, 26, 2);
494
52
    break;
495
38
  case R_MIPS_GOT16:
496
38
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
497
38
    // is updated addend (not a GOT index). In that case write high 16 bits
498
38
    // to store a correct addend value.
499
38
    if (Config->Relocatable) {
500
2
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
501
36
    } else {
502
36
      checkInt(Loc, Val, 16, Type);
503
36
      writeValue<E>(Loc, Val, 16, 0);
504
36
    }
505
38
    break;
506
3
  case R_MICROMIPS_GOT16:
507
3
    if (Config->Relocatable) {
508
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
509
3
    } else {
510
3
      checkInt(Loc, Val, 16, Type);
511
3
      writeShuffleValue<E>(Loc, Val, 16, 0);
512
3
    }
513
3
    break;
514
34
  case R_MIPS_CALL16:
515
34
  case R_MIPS_GOT_DISP:
516
34
  case R_MIPS_GOT_PAGE:
517
34
  case R_MIPS_GPREL16:
518
34
  case R_MIPS_TLS_GD:
519
34
  case R_MIPS_TLS_GOTTPREL:
520
34
  case R_MIPS_TLS_LDM:
521
34
    checkInt(Loc, Val, 16, Type);
522
34
    LLVM_FALLTHROUGH;
523
119
  case R_MIPS_CALL_LO16:
524
119
  case R_MIPS_GOT_LO16:
525
119
  case R_MIPS_GOT_OFST:
526
119
  case R_MIPS_LO16:
527
119
  case R_MIPS_PCLO16:
528
119
  case R_MIPS_TLS_DTPREL_LO16:
529
119
  case R_MIPS_TLS_TPREL_LO16:
530
119
    writeValue<E>(Loc, Val, 16, 0);
531
119
    break;
532
119
  case R_MICROMIPS_GPREL16:
533
0
  case R_MICROMIPS_TLS_GD:
534
0
  case R_MICROMIPS_TLS_LDM:
535
0
    checkInt(Loc, Val, 16, Type);
536
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
537
0
    break;
538
8
  case R_MICROMIPS_CALL16:
539
8
  case R_MICROMIPS_CALL_LO16:
540
8
  case R_MICROMIPS_LO16:
541
8
  case R_MICROMIPS_TLS_DTPREL_LO16:
542
8
  case R_MICROMIPS_TLS_GOTTPREL:
543
8
  case R_MICROMIPS_TLS_TPREL_LO16:
544
8
    writeShuffleValue<E>(Loc, Val, 16, 0);
545
8
    break;
546
8
  case R_MICROMIPS_GPREL7_S2:
547
0
    checkInt(Loc, Val, 7, Type);
548
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
549
0
    break;
550
66
  case R_MIPS_CALL_HI16:
551
66
  case R_MIPS_GOT_HI16:
552
66
  case R_MIPS_HI16:
553
66
  case R_MIPS_PCHI16:
554
66
  case R_MIPS_TLS_DTPREL_HI16:
555
66
  case R_MIPS_TLS_TPREL_HI16:
556
66
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
557
66
    break;
558
66
  case R_MICROMIPS_CALL_HI16:
559
4
  case R_MICROMIPS_GOT_HI16:
560
4
  case R_MICROMIPS_HI16:
561
4
  case R_MICROMIPS_TLS_DTPREL_HI16:
562
4
  case R_MICROMIPS_TLS_TPREL_HI16:
563
4
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
564
4
    break;
565
4
  case R_MIPS_HIGHER:
566
0
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
567
0
    break;
568
4
  case R_MIPS_HIGHEST:
569
0
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
570
0
    break;
571
4
  case R_MIPS_JALR:
572
0
  case R_MICROMIPS_JALR:
573
0
    // Ignore this optimization relocation for now
574
0
    break;
575
2
  case R_MIPS_PC16:
576
2
    checkAlignment(Loc, Val, 4, Type);
577
2
    checkInt(Loc, Val, 18, Type);
578
2
    writeValue<E>(Loc, Val, 16, 2);
579
2
    break;
580
1
  case R_MIPS_PC19_S2:
581
1
    checkAlignment(Loc, Val, 4, Type);
582
1
    checkInt(Loc, Val, 21, Type);
583
1
    writeValue<E>(Loc, Val, 19, 2);
584
1
    break;
585
1
  case R_MIPS_PC21_S2:
586
1
    checkAlignment(Loc, Val, 4, Type);
587
1
    checkInt(Loc, Val, 23, Type);
588
1
    writeValue<E>(Loc, Val, 21, 2);
589
1
    break;
590
1
  case R_MIPS_PC26_S2:
591
1
    checkAlignment(Loc, Val, 4, Type);
592
1
    checkInt(Loc, Val, 28, Type);
593
1
    writeValue<E>(Loc, Val, 26, 2);
594
1
    break;
595
1
  case R_MIPS_PC32:
596
1
    writeValue<E>(Loc, Val, 32, 0);
597
1
    break;
598
9
  case R_MICROMIPS_26_S1:
599
9
  case R_MICROMIPS_PC26_S1:
600
9
    checkInt(Loc, Val, 27, Type);
601
9
    writeShuffleValue<E>(Loc, Val, 26, 1);
602
9
    break;
603
9
  case R_MICROMIPS_PC7_S1:
604
1
    checkInt(Loc, Val, 8, Type);
605
1
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
606
1
    break;
607
9
  case R_MICROMIPS_PC10_S1:
608
1
    checkInt(Loc, Val, 11, Type);
609
1
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
610
1
    break;
611
9
  case R_MICROMIPS_PC16_S1:
612
1
    checkInt(Loc, Val, 17, Type);
613
1
    writeShuffleValue<E>(Loc, Val, 16, 1);
614
1
    break;
615
9
  case R_MICROMIPS_PC18_S3:
616
0
    checkInt(Loc, Val, 21, Type);
617
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
618
0
    break;
619
9
  case R_MICROMIPS_PC19_S2:
620
3
    checkInt(Loc, Val, 21, Type);
621
3
    writeShuffleValue<E>(Loc, Val, 19, 2);
622
3
    break;
623
9
  case R_MICROMIPS_PC21_S1:
624
1
    checkInt(Loc, Val, 22, Type);
625
1
    writeShuffleValue<E>(Loc, Val, 21, 1);
626
1
    break;
627
9
  case R_MICROMIPS_PC23_S2:
628
6
    checkInt(Loc, Val, 25, Type);
629
6
    writeShuffleValue<E>(Loc, Val, 23, 2);
630
6
    break;
631
9
  default:
632
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
633
344
  }
634
344
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
460
10.0k
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
461
10.0k
  const endianness E = ELFT::TargetEndianness;
462
10.0k
463
10.0k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi0
)
464
10.0k
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
465
10.0k
466
10.0k
  // Thread pointer and DRP offsets from the start of TLS data area.
467
10.0k
  // https://www.linux-mips.org/wiki/NPTL
468
10.0k
  if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
469
10.0k
      Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 ||
470
10.0k
      
Type == R_MICROMIPS_TLS_DTPREL_HI1610.0k
||
471
10.0k
      
Type == R_MICROMIPS_TLS_DTPREL_LO1610.0k
) {
472
1
    Val -= 0x8000;
473
10.0k
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
474
10.0k
             Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 ||
475
10.0k
             
Type == R_MICROMIPS_TLS_TPREL_HI1610.0k
||
476
10.0k
             
Type == R_MICROMIPS_TLS_TPREL_LO1610.0k
) {
477
1
    Val -= 0x7000;
478
1
  }
479
10.0k
480
10.0k
  switch (Type) {
481
10.0k
  case R_MIPS_32:
482
3
  case R_MIPS_GPREL32:
483
3
  case R_MIPS_TLS_DTPREL32:
484
3
  case R_MIPS_TLS_TPREL32:
485
3
    write32<E>(Loc, Val);
486
3
    break;
487
8
  case R_MIPS_64:
488
8
  case R_MIPS_TLS_DTPREL64:
489
8
  case R_MIPS_TLS_TPREL64:
490
8
    write64<E>(Loc, Val);
491
8
    break;
492
8
  case R_MIPS_26:
493
2
    writeValue<E>(Loc, Val, 26, 2);
494
2
    break;
495
8
  case R_MIPS_GOT16:
496
0
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
497
0
    // is updated addend (not a GOT index). In that case write high 16 bits
498
0
    // to store a correct addend value.
499
0
    if (Config->Relocatable) {
500
0
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
501
0
    } else {
502
0
      checkInt(Loc, Val, 16, Type);
503
0
      writeValue<E>(Loc, Val, 16, 0);
504
0
    }
505
0
    break;
506
8
  case R_MICROMIPS_GOT16:
507
0
    if (Config->Relocatable) {
508
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
509
0
    } else {
510
0
      checkInt(Loc, Val, 16, Type);
511
0
      writeShuffleValue<E>(Loc, Val, 16, 0);
512
0
    }
513
0
    break;
514
10.0k
  case R_MIPS_CALL16:
515
10.0k
  case R_MIPS_GOT_DISP:
516
10.0k
  case R_MIPS_GOT_PAGE:
517
10.0k
  case R_MIPS_GPREL16:
518
10.0k
  case R_MIPS_TLS_GD:
519
10.0k
  case R_MIPS_TLS_GOTTPREL:
520
10.0k
  case R_MIPS_TLS_LDM:
521
10.0k
    checkInt(Loc, Val, 16, Type);
522
10.0k
    LLVM_FALLTHROUGH;
523
10.0k
  case R_MIPS_CALL_LO16:
524
10.0k
  case R_MIPS_GOT_LO16:
525
10.0k
  case R_MIPS_GOT_OFST:
526
10.0k
  case R_MIPS_LO16:
527
10.0k
  case R_MIPS_PCLO16:
528
10.0k
  case R_MIPS_TLS_DTPREL_LO16:
529
10.0k
  case R_MIPS_TLS_TPREL_LO16:
530
10.0k
    writeValue<E>(Loc, Val, 16, 0);
531
10.0k
    break;
532
10.0k
  case R_MICROMIPS_GPREL16:
533
0
  case R_MICROMIPS_TLS_GD:
534
0
  case R_MICROMIPS_TLS_LDM:
535
0
    checkInt(Loc, Val, 16, Type);
536
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
537
0
    break;
538
0
  case R_MICROMIPS_CALL16:
539
0
  case R_MICROMIPS_CALL_LO16:
540
0
  case R_MICROMIPS_LO16:
541
0
  case R_MICROMIPS_TLS_DTPREL_LO16:
542
0
  case R_MICROMIPS_TLS_GOTTPREL:
543
0
  case R_MICROMIPS_TLS_TPREL_LO16:
544
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
545
0
    break;
546
0
  case R_MICROMIPS_GPREL7_S2:
547
0
    checkInt(Loc, Val, 7, Type);
548
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
549
0
    break;
550
6
  case R_MIPS_CALL_HI16:
551
6
  case R_MIPS_GOT_HI16:
552
6
  case R_MIPS_HI16:
553
6
  case R_MIPS_PCHI16:
554
6
  case R_MIPS_TLS_DTPREL_HI16:
555
6
  case R_MIPS_TLS_TPREL_HI16:
556
6
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
557
6
    break;
558
6
  case R_MICROMIPS_CALL_HI16:
559
0
  case R_MICROMIPS_GOT_HI16:
560
0
  case R_MICROMIPS_HI16:
561
0
  case R_MICROMIPS_TLS_DTPREL_HI16:
562
0
  case R_MICROMIPS_TLS_TPREL_HI16:
563
0
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
564
0
    break;
565
2
  case R_MIPS_HIGHER:
566
2
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
567
2
    break;
568
2
  case R_MIPS_HIGHEST:
569
2
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
570
2
    break;
571
0
  case R_MIPS_JALR:
572
0
  case R_MICROMIPS_JALR:
573
0
    // Ignore this optimization relocation for now
574
0
    break;
575
0
  case R_MIPS_PC16:
576
0
    checkAlignment(Loc, Val, 4, Type);
577
0
    checkInt(Loc, Val, 18, Type);
578
0
    writeValue<E>(Loc, Val, 16, 2);
579
0
    break;
580
0
  case R_MIPS_PC19_S2:
581
0
    checkAlignment(Loc, Val, 4, Type);
582
0
    checkInt(Loc, Val, 21, Type);
583
0
    writeValue<E>(Loc, Val, 19, 2);
584
0
    break;
585
0
  case R_MIPS_PC21_S2:
586
0
    checkAlignment(Loc, Val, 4, Type);
587
0
    checkInt(Loc, Val, 23, Type);
588
0
    writeValue<E>(Loc, Val, 21, 2);
589
0
    break;
590
0
  case R_MIPS_PC26_S2:
591
0
    checkAlignment(Loc, Val, 4, Type);
592
0
    checkInt(Loc, Val, 28, Type);
593
0
    writeValue<E>(Loc, Val, 26, 2);
594
0
    break;
595
1
  case R_MIPS_PC32:
596
1
    writeValue<E>(Loc, Val, 32, 0);
597
1
    break;
598
0
  case R_MICROMIPS_26_S1:
599
0
  case R_MICROMIPS_PC26_S1:
600
0
    checkInt(Loc, Val, 27, Type);
601
0
    writeShuffleValue<E>(Loc, Val, 26, 1);
602
0
    break;
603
0
  case R_MICROMIPS_PC7_S1:
604
0
    checkInt(Loc, Val, 8, Type);
605
0
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
606
0
    break;
607
0
  case R_MICROMIPS_PC10_S1:
608
0
    checkInt(Loc, Val, 11, Type);
609
0
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
610
0
    break;
611
0
  case R_MICROMIPS_PC16_S1:
612
0
    checkInt(Loc, Val, 17, Type);
613
0
    writeShuffleValue<E>(Loc, Val, 16, 1);
614
0
    break;
615
0
  case R_MICROMIPS_PC18_S3:
616
0
    checkInt(Loc, Val, 21, Type);
617
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
618
0
    break;
619
0
  case R_MICROMIPS_PC19_S2:
620
0
    checkInt(Loc, Val, 21, Type);
621
0
    writeShuffleValue<E>(Loc, Val, 19, 2);
622
0
    break;
623
0
  case R_MICROMIPS_PC21_S1:
624
0
    checkInt(Loc, Val, 22, Type);
625
0
    writeShuffleValue<E>(Loc, Val, 21, 1);
626
0
    break;
627
0
  case R_MICROMIPS_PC23_S2:
628
0
    checkInt(Loc, Val, 25, Type);
629
0
    writeShuffleValue<E>(Loc, Val, 23, 2);
630
0
    break;
631
0
  default:
632
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
633
10.0k
  }
634
10.0k
}
635
636
34
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
637
34
  return Type == R_MIPS_LO16 || 
Type == R_MIPS_GOT_OFST18
||
638
34
         
Type == R_MICROMIPS_LO1617
;
639
34
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
636
2
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
637
2
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
638
2
         Type == R_MICROMIPS_LO16;
639
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
636
26
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
637
26
  return Type == R_MIPS_LO16 || 
Type == R_MIPS_GOT_OFST10
||
638
26
         
Type == R_MICROMIPS_LO1610
;
639
26
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::usesOnlyLowPageBits(unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
636
6
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
637
6
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
638
6
         
Type == R_MICROMIPS_LO165
;
639
6
}
640
641
// Return true if the symbol is a PIC function.
642
127
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
643
127
  if (!Sym->isFunc())
644
61
    return false;
645
66
646
66
  if (Sym->StOther & STO_MIPS_PIC)
647
7
    return true;
648
59
649
59
  if (!Sym->Section)
650
0
    return false;
651
59
652
59
  ObjFile<ELFT> *File =
653
59
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
654
59
  if (!File)
655
1
    return false;
656
58
657
58
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
658
58
}
bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)1, false> >(lld::elf::Defined const*)
Line
Count
Source
642
3
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
643
3
  if (!Sym->isFunc())
644
0
    return false;
645
3
646
3
  if (Sym->StOther & STO_MIPS_PIC)
647
0
    return true;
648
3
649
3
  if (!Sym->Section)
650
0
    return false;
651
3
652
3
  ObjFile<ELFT> *File =
653
3
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
654
3
  if (!File)
655
0
    return false;
656
3
657
3
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
658
3
}
bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)0, false> >(lld::elf::Defined const*)
Line
Count
Source
642
113
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
643
113
  if (!Sym->isFunc())
644
50
    return false;
645
63
646
63
  if (Sym->StOther & STO_MIPS_PIC)
647
7
    return true;
648
56
649
56
  if (!Sym->Section)
650
0
    return false;
651
56
652
56
  ObjFile<ELFT> *File =
653
56
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
654
56
  if (!File)
655
1
    return false;
656
55
657
55
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
658
55
}
Unexecuted instantiation: bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)1, true> >(lld::elf::Defined const*)
bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)0, true> >(lld::elf::Defined const*)
Line
Count
Source
642
11
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
643
11
  if (!Sym->isFunc())
644
11
    return false;
645
0
646
0
  if (Sym->StOther & STO_MIPS_PIC)
647
0
    return true;
648
0
649
0
  if (!Sym->Section)
650
0
    return false;
651
0
652
0
  ObjFile<ELFT> *File =
653
0
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
654
0
  if (!File)
655
0
    return false;
656
0
657
0
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
658
0
}
659
660
181
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
661
181
  static MIPS<ELFT> Target;
662
181
  return &Target;
663
181
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)1, false> >()
Line
Count
Source
660
17
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
661
17
  static MIPS<ELFT> Target;
662
17
  return &Target;
663
17
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)0, false> >()
Line
Count
Source
660
117
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
661
117
  static MIPS<ELFT> Target;
662
117
  return &Target;
663
117
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)1, true> >()
Line
Count
Source
660
2
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
661
2
  static MIPS<ELFT> Target;
662
2
  return &Target;
663
2
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)0, true> >()
Line
Count
Source
660
45
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
661
45
  static MIPS<ELFT> Target;
662
45
  return &Target;
663
45
}
664
665
template TargetInfo *elf::getMipsTargetInfo<ELF32LE>();
666
template TargetInfo *elf::getMipsTargetInfo<ELF32BE>();
667
template TargetInfo *elf::getMipsTargetInfo<ELF64LE>();
668
template TargetInfo *elf::getMipsTargetInfo<ELF64BE>();
669
670
template bool elf::isMipsPIC<ELF32LE>(const Defined *);
671
template bool elf::isMipsPIC<ELF32BE>(const Defined *);
672
template bool elf::isMipsPIC<ELF64LE>(const Defined *);
673
template bool elf::isMipsPIC<ELF64BE>(const Defined *);