Coverage Report

Created: 2019-01-18 03:29

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/Mips.cpp
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1
//===- MIPS.cpp -----------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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10
#include "InputFiles.h"
11
#include "OutputSections.h"
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#include "Symbols.h"
13
#include "SyntheticSections.h"
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#include "Target.h"
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#include "Thunks.h"
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#include "lld/Common/ErrorHandler.h"
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#include "llvm/Object/ELF.h"
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#include "llvm/Support/Endian.h"
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using namespace llvm;
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using namespace llvm::object;
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using namespace llvm::support::endian;
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using namespace llvm::ELF;
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using namespace lld;
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using namespace lld::elf;
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27
namespace {
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template <class ELFT> class MIPS final : public TargetInfo {
29
public:
30
  MIPS();
31
  uint32_t calcEFlags() const override;
32
  RelExpr getRelExpr(RelType Type, const Symbol &S,
33
                     const uint8_t *Loc) const override;
34
  int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
35
  RelType getDynRel(RelType Type) const override;
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  void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
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  void writePltHeader(uint8_t *Buf) const override;
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  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
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                int32_t Index, unsigned RelOff) const override;
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  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
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                  uint64_t BranchAddr, const Symbol &S) const override;
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  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
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  bool usesOnlyLowPageBits(RelType Type) const override;
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};
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} // namespace
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47
194
template <class ELFT> MIPS<ELFT>::MIPS() {
48
194
  GotPltHeaderEntriesNum = 2;
49
194
  DefaultMaxPageSize = 65536;
50
194
  GotEntrySize = sizeof(typename ELFT::uint);
51
194
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
194
  GotBaseSymInGotPlt = false;
53
194
  PltEntrySize = 16;
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194
  PltHeaderSize = 32;
55
194
  CopyRel = R_MIPS_COPY;
56
194
  NoneRel = R_MIPS_NONE;
57
194
  PltRel = R_MIPS_JUMP_SLOT;
58
194
  NeedsThunks = true;
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194
60
194
  // Set `sigrie 1` as a trap instruction.
61
194
  write32(TrapInstr.data(), 0x04170001);
62
194
63
194
  if (ELFT::Is64Bits) {
64
49
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
65
49
    TlsGotRel = R_MIPS_TLS_TPREL64;
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49
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
67
49
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
68
145
  } else {
69
145
    RelativeRel = R_MIPS_REL32;
70
145
    TlsGotRel = R_MIPS_TLS_TPREL32;
71
145
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
72
145
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
73
145
  }
74
194
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::MIPS()
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47
23
template <class ELFT> MIPS<ELFT>::MIPS() {
48
23
  GotPltHeaderEntriesNum = 2;
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23
  DefaultMaxPageSize = 65536;
50
23
  GotEntrySize = sizeof(typename ELFT::uint);
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23
  GotPltEntrySize = sizeof(typename ELFT::uint);
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23
  GotBaseSymInGotPlt = false;
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23
  PltEntrySize = 16;
54
23
  PltHeaderSize = 32;
55
23
  CopyRel = R_MIPS_COPY;
56
23
  NoneRel = R_MIPS_NONE;
57
23
  PltRel = R_MIPS_JUMP_SLOT;
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23
  NeedsThunks = true;
59
23
60
23
  // Set `sigrie 1` as a trap instruction.
61
23
  write32(TrapInstr.data(), 0x04170001);
62
23
63
23
  if (ELFT::Is64Bits) {
64
0
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
65
0
    TlsGotRel = R_MIPS_TLS_TPREL64;
66
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
67
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
68
23
  } else {
69
23
    RelativeRel = R_MIPS_REL32;
70
23
    TlsGotRel = R_MIPS_TLS_TPREL32;
71
23
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
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23
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
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23
  }
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23
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::MIPS()
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47
122
template <class ELFT> MIPS<ELFT>::MIPS() {
48
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  GotPltHeaderEntriesNum = 2;
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  DefaultMaxPageSize = 65536;
50
122
  GotEntrySize = sizeof(typename ELFT::uint);
51
122
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
122
  GotBaseSymInGotPlt = false;
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122
  PltEntrySize = 16;
54
122
  PltHeaderSize = 32;
55
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  CopyRel = R_MIPS_COPY;
56
122
  NoneRel = R_MIPS_NONE;
57
122
  PltRel = R_MIPS_JUMP_SLOT;
58
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  NeedsThunks = true;
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122
60
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  // Set `sigrie 1` as a trap instruction.
61
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  write32(TrapInstr.data(), 0x04170001);
62
122
63
122
  if (ELFT::Is64Bits) {
64
0
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
65
0
    TlsGotRel = R_MIPS_TLS_TPREL64;
66
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
67
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
68
122
  } else {
69
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    RelativeRel = R_MIPS_REL32;
70
122
    TlsGotRel = R_MIPS_TLS_TPREL32;
71
122
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
72
122
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
73
122
  }
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122
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::MIPS()
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47
3
template <class ELFT> MIPS<ELFT>::MIPS() {
48
3
  GotPltHeaderEntriesNum = 2;
49
3
  DefaultMaxPageSize = 65536;
50
3
  GotEntrySize = sizeof(typename ELFT::uint);
51
3
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
3
  GotBaseSymInGotPlt = false;
53
3
  PltEntrySize = 16;
54
3
  PltHeaderSize = 32;
55
3
  CopyRel = R_MIPS_COPY;
56
3
  NoneRel = R_MIPS_NONE;
57
3
  PltRel = R_MIPS_JUMP_SLOT;
58
3
  NeedsThunks = true;
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3
60
3
  // Set `sigrie 1` as a trap instruction.
61
3
  write32(TrapInstr.data(), 0x04170001);
62
3
63
3
  if (ELFT::Is64Bits) {
64
3
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
65
3
    TlsGotRel = R_MIPS_TLS_TPREL64;
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3
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
67
3
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
68
3
  } else {
69
0
    RelativeRel = R_MIPS_REL32;
70
0
    TlsGotRel = R_MIPS_TLS_TPREL32;
71
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
72
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
73
0
  }
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3
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::MIPS()
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47
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template <class ELFT> MIPS<ELFT>::MIPS() {
48
46
  GotPltHeaderEntriesNum = 2;
49
46
  DefaultMaxPageSize = 65536;
50
46
  GotEntrySize = sizeof(typename ELFT::uint);
51
46
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
46
  GotBaseSymInGotPlt = false;
53
46
  PltEntrySize = 16;
54
46
  PltHeaderSize = 32;
55
46
  CopyRel = R_MIPS_COPY;
56
46
  NoneRel = R_MIPS_NONE;
57
46
  PltRel = R_MIPS_JUMP_SLOT;
58
46
  NeedsThunks = true;
59
46
60
46
  // Set `sigrie 1` as a trap instruction.
61
46
  write32(TrapInstr.data(), 0x04170001);
62
46
63
46
  if (ELFT::Is64Bits) {
64
46
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
65
46
    TlsGotRel = R_MIPS_TLS_TPREL64;
66
46
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
67
46
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
68
46
  } else {
69
0
    RelativeRel = R_MIPS_REL32;
70
0
    TlsGotRel = R_MIPS_TLS_TPREL32;
71
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
72
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
73
0
  }
74
46
}
75
76
192
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
77
192
  return calcMipsEFlags<ELFT>();
78
192
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::calcEFlags() const
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76
23
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
77
23
  return calcMipsEFlags<ELFT>();
78
23
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::calcEFlags() const
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76
121
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
77
121
  return calcMipsEFlags<ELFT>();
78
121
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::calcEFlags() const
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76
3
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
77
3
  return calcMipsEFlags<ELFT>();
78
3
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::calcEFlags() const
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76
45
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
77
45
  return calcMipsEFlags<ELFT>();
78
45
}
79
80
template <class ELFT>
81
RelExpr MIPS<ELFT>::getRelExpr(RelType Type, const Symbol &S,
82
10.3k
                               const uint8_t *Loc) const {
83
10.3k
  // See comment in the calculateMipsRelChain.
84
10.3k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi301
)
85
10.0k
    Type &= 0xff;
86
10.3k
87
10.3k
  switch (Type) {
88
10.3k
  case R_MIPS_JALR:
89
1
  case R_MICROMIPS_JALR:
90
1
    return R_HINT;
91
26
  case R_MIPS_GPREL16:
92
26
  case R_MIPS_GPREL32:
93
26
  case R_MICROMIPS_GPREL16:
94
26
  case R_MICROMIPS_GPREL7_S2:
95
26
    return R_MIPS_GOTREL;
96
60
  case R_MIPS_26:
97
60
  case R_MICROMIPS_26_S1:
98
60
    return R_PLT;
99
60
  case R_MICROMIPS_PC26_S1:
100
6
    return R_PLT_PC;
101
81
  case R_MIPS_HI16:
102
81
  case R_MIPS_LO16:
103
81
  case R_MIPS_HIGHER:
104
81
  case R_MIPS_HIGHEST:
105
81
  case R_MICROMIPS_HI16:
106
81
  case R_MICROMIPS_LO16:
107
81
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
108
81
    // offset between start of function and 'gp' value which by default
109
81
    // equal to the start of .got section. In that case we consider these
110
81
    // relocations as relative.
111
81
    if (&S == ElfSym::MipsGpDisp)
112
20
      return R_MIPS_GOT_GP_PC;
113
61
    if (&S == ElfSym::MipsLocalGp)
114
2
      return R_MIPS_GOT_GP;
115
59
    LLVM_FALLTHROUGH;
116
94
  case R_MIPS_32:
117
94
  case R_MIPS_64:
118
94
  case R_MIPS_GOT_OFST:
119
94
  case R_MIPS_SUB:
120
94
  case R_MIPS_TLS_DTPREL_HI16:
121
94
  case R_MIPS_TLS_DTPREL_LO16:
122
94
  case R_MIPS_TLS_DTPREL32:
123
94
  case R_MIPS_TLS_DTPREL64:
124
94
  case R_MIPS_TLS_TPREL_HI16:
125
94
  case R_MIPS_TLS_TPREL_LO16:
126
94
  case R_MIPS_TLS_TPREL32:
127
94
  case R_MIPS_TLS_TPREL64:
128
94
  case R_MICROMIPS_TLS_DTPREL_HI16:
129
94
  case R_MICROMIPS_TLS_DTPREL_LO16:
130
94
  case R_MICROMIPS_TLS_TPREL_HI16:
131
94
  case R_MICROMIPS_TLS_TPREL_LO16:
132
94
    return R_ABS;
133
94
  case R_MIPS_PC32:
134
19
  case R_MIPS_PC16:
135
19
  case R_MIPS_PC19_S2:
136
19
  case R_MIPS_PC21_S2:
137
19
  case R_MIPS_PC26_S2:
138
19
  case R_MIPS_PCHI16:
139
19
  case R_MIPS_PCLO16:
140
19
  case R_MICROMIPS_PC7_S1:
141
19
  case R_MICROMIPS_PC10_S1:
142
19
  case R_MICROMIPS_PC16_S1:
143
19
  case R_MICROMIPS_PC18_S3:
144
19
  case R_MICROMIPS_PC19_S2:
145
19
  case R_MICROMIPS_PC23_S2:
146
19
  case R_MICROMIPS_PC21_S1:
147
19
    return R_PC;
148
50
  case R_MIPS_GOT16:
149
50
  case R_MICROMIPS_GOT16:
150
50
    if (S.isLocal())
151
23
      return R_MIPS_GOT_LOCAL_PAGE;
152
27
    LLVM_FALLTHROUGH;
153
10.0k
  case R_MIPS_CALL16:
154
10.0k
  case R_MIPS_GOT_DISP:
155
10.0k
  case R_MIPS_TLS_GOTTPREL:
156
10.0k
  case R_MICROMIPS_CALL16:
157
10.0k
  case R_MICROMIPS_TLS_GOTTPREL:
158
10.0k
    return R_MIPS_GOT_OFF;
159
10.0k
  case R_MIPS_CALL_HI16:
160
16
  case R_MIPS_CALL_LO16:
161
16
  case R_MIPS_GOT_HI16:
162
16
  case R_MIPS_GOT_LO16:
163
16
  case R_MICROMIPS_CALL_HI16:
164
16
  case R_MICROMIPS_CALL_LO16:
165
16
  case R_MICROMIPS_GOT_HI16:
166
16
  case R_MICROMIPS_GOT_LO16:
167
16
    return R_MIPS_GOT_OFF32;
168
16
  case R_MIPS_GOT_PAGE:
169
12
    return R_MIPS_GOT_LOCAL_PAGE;
170
16
  case R_MIPS_TLS_GD:
171
12
  case R_MICROMIPS_TLS_GD:
172
12
    return R_MIPS_TLSGD;
173
12
  case R_MIPS_TLS_LDM:
174
6
  case R_MICROMIPS_TLS_LDM:
175
6
    return R_MIPS_TLSLD;
176
6
  case R_MIPS_NONE:
177
0
    return R_NONE;
178
6
  default:
179
0
    return R_INVALID;
180
10.3k
  }
181
10.3k
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
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Source
82
25
                               const uint8_t *Loc) const {
83
25
  // See comment in the calculateMipsRelChain.
84
25
  if (ELFT::Is64Bits || Config->MipsN32Abi)
85
0
    Type &= 0xff;
86
25
87
25
  switch (Type) {
88
25
  case R_MIPS_JALR:
89
1
  case R_MICROMIPS_JALR:
90
1
    return R_HINT;
91
1
  case R_MIPS_GPREL16:
92
0
  case R_MIPS_GPREL32:
93
0
  case R_MICROMIPS_GPREL16:
94
0
  case R_MICROMIPS_GPREL7_S2:
95
0
    return R_MIPS_GOTREL;
96
2
  case R_MIPS_26:
97
2
  case R_MICROMIPS_26_S1:
98
2
    return R_PLT;
99
3
  case R_MICROMIPS_PC26_S1:
100
3
    return R_PLT_PC;
101
4
  case R_MIPS_HI16:
102
4
  case R_MIPS_LO16:
103
4
  case R_MIPS_HIGHER:
104
4
  case R_MIPS_HIGHEST:
105
4
  case R_MICROMIPS_HI16:
106
4
  case R_MICROMIPS_LO16:
107
4
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
108
4
    // offset between start of function and 'gp' value which by default
109
4
    // equal to the start of .got section. In that case we consider these
110
4
    // relocations as relative.
111
4
    if (&S == ElfSym::MipsGpDisp)
112
2
      return R_MIPS_GOT_GP_PC;
113
2
    if (&S == ElfSym::MipsLocalGp)
114
0
      return R_MIPS_GOT_GP;
115
2
    LLVM_FALLTHROUGH;
116
4
  case R_MIPS_32:
117
4
  case R_MIPS_64:
118
4
  case R_MIPS_GOT_OFST:
119
4
  case R_MIPS_SUB:
120
4
  case R_MIPS_TLS_DTPREL_HI16:
121
4
  case R_MIPS_TLS_DTPREL_LO16:
122
4
  case R_MIPS_TLS_DTPREL32:
123
4
  case R_MIPS_TLS_DTPREL64:
124
4
  case R_MIPS_TLS_TPREL_HI16:
125
4
  case R_MIPS_TLS_TPREL_LO16:
126
4
  case R_MIPS_TLS_TPREL32:
127
4
  case R_MIPS_TLS_TPREL64:
128
4
  case R_MICROMIPS_TLS_DTPREL_HI16:
129
4
  case R_MICROMIPS_TLS_DTPREL_LO16:
130
4
  case R_MICROMIPS_TLS_TPREL_HI16:
131
4
  case R_MICROMIPS_TLS_TPREL_LO16:
132
4
    return R_ABS;
133
5
  case R_MIPS_PC32:
134
5
  case R_MIPS_PC16:
135
5
  case R_MIPS_PC19_S2:
136
5
  case R_MIPS_PC21_S2:
137
5
  case R_MIPS_PC26_S2:
138
5
  case R_MIPS_PCHI16:
139
5
  case R_MIPS_PCLO16:
140
5
  case R_MICROMIPS_PC7_S1:
141
5
  case R_MICROMIPS_PC10_S1:
142
5
  case R_MICROMIPS_PC16_S1:
143
5
  case R_MICROMIPS_PC18_S3:
144
5
  case R_MICROMIPS_PC19_S2:
145
5
  case R_MICROMIPS_PC23_S2:
146
5
  case R_MICROMIPS_PC21_S1:
147
5
    return R_PC;
148
7
  case R_MIPS_GOT16:
149
7
  case R_MICROMIPS_GOT16:
150
7
    if (S.isLocal())
151
2
      return R_MIPS_GOT_LOCAL_PAGE;
152
5
    LLVM_FALLTHROUGH;
153
6
  case R_MIPS_CALL16:
154
6
  case R_MIPS_GOT_DISP:
155
6
  case R_MIPS_TLS_GOTTPREL:
156
6
  case R_MICROMIPS_CALL16:
157
6
  case R_MICROMIPS_TLS_GOTTPREL:
158
6
    return R_MIPS_GOT_OFF;
159
6
  case R_MIPS_CALL_HI16:
160
0
  case R_MIPS_CALL_LO16:
161
0
  case R_MIPS_GOT_HI16:
162
0
  case R_MIPS_GOT_LO16:
163
0
  case R_MICROMIPS_CALL_HI16:
164
0
  case R_MICROMIPS_CALL_LO16:
165
0
  case R_MICROMIPS_GOT_HI16:
166
0
  case R_MICROMIPS_GOT_LO16:
167
0
    return R_MIPS_GOT_OFF32;
168
0
  case R_MIPS_GOT_PAGE:
169
0
    return R_MIPS_GOT_LOCAL_PAGE;
170
0
  case R_MIPS_TLS_GD:
171
0
  case R_MICROMIPS_TLS_GD:
172
0
    return R_MIPS_TLSGD;
173
0
  case R_MIPS_TLS_LDM:
174
0
  case R_MICROMIPS_TLS_LDM:
175
0
    return R_MIPS_TLSLD;
176
0
  case R_MIPS_NONE:
177
0
    return R_NONE;
178
0
  default:
179
0
    return R_INVALID;
180
25
  }
181
25
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Line
Count
Source
82
276
                               const uint8_t *Loc) const {
83
276
  // See comment in the calculateMipsRelChain.
84
276
  if (ELFT::Is64Bits || Config->MipsN32Abi)
85
5
    Type &= 0xff;
86
276
87
276
  switch (Type) {
88
276
  case R_MIPS_JALR:
89
0
  case R_MICROMIPS_JALR:
90
0
    return R_HINT;
91
15
  case R_MIPS_GPREL16:
92
15
  case R_MIPS_GPREL32:
93
15
  case R_MICROMIPS_GPREL16:
94
15
  case R_MICROMIPS_GPREL7_S2:
95
15
    return R_MIPS_GOTREL;
96
56
  case R_MIPS_26:
97
56
  case R_MICROMIPS_26_S1:
98
56
    return R_PLT;
99
56
  case R_MICROMIPS_PC26_S1:
100
3
    return R_PLT_PC;
101
73
  case R_MIPS_HI16:
102
73
  case R_MIPS_LO16:
103
73
  case R_MIPS_HIGHER:
104
73
  case R_MIPS_HIGHEST:
105
73
  case R_MICROMIPS_HI16:
106
73
  case R_MICROMIPS_LO16:
107
73
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
108
73
    // offset between start of function and 'gp' value which by default
109
73
    // equal to the start of .got section. In that case we consider these
110
73
    // relocations as relative.
111
73
    if (&S == ElfSym::MipsGpDisp)
112
18
      return R_MIPS_GOT_GP_PC;
113
55
    if (&S == ElfSym::MipsLocalGp)
114
2
      return R_MIPS_GOT_GP;
115
53
    LLVM_FALLTHROUGH;
116
74
  case R_MIPS_32:
117
74
  case R_MIPS_64:
118
74
  case R_MIPS_GOT_OFST:
119
74
  case R_MIPS_SUB:
120
74
  case R_MIPS_TLS_DTPREL_HI16:
121
74
  case R_MIPS_TLS_DTPREL_LO16:
122
74
  case R_MIPS_TLS_DTPREL32:
123
74
  case R_MIPS_TLS_DTPREL64:
124
74
  case R_MIPS_TLS_TPREL_HI16:
125
74
  case R_MIPS_TLS_TPREL_LO16:
126
74
  case R_MIPS_TLS_TPREL32:
127
74
  case R_MIPS_TLS_TPREL64:
128
74
  case R_MICROMIPS_TLS_DTPREL_HI16:
129
74
  case R_MICROMIPS_TLS_DTPREL_LO16:
130
74
  case R_MICROMIPS_TLS_TPREL_HI16:
131
74
  case R_MICROMIPS_TLS_TPREL_LO16:
132
74
    return R_ABS;
133
74
  case R_MIPS_PC32:
134
13
  case R_MIPS_PC16:
135
13
  case R_MIPS_PC19_S2:
136
13
  case R_MIPS_PC21_S2:
137
13
  case R_MIPS_PC26_S2:
138
13
  case R_MIPS_PCHI16:
139
13
  case R_MIPS_PCLO16:
140
13
  case R_MICROMIPS_PC7_S1:
141
13
  case R_MICROMIPS_PC10_S1:
142
13
  case R_MICROMIPS_PC16_S1:
143
13
  case R_MICROMIPS_PC18_S3:
144
13
  case R_MICROMIPS_PC19_S2:
145
13
  case R_MICROMIPS_PC23_S2:
146
13
  case R_MICROMIPS_PC21_S1:
147
13
    return R_PC;
148
43
  case R_MIPS_GOT16:
149
43
  case R_MICROMIPS_GOT16:
150
43
    if (S.isLocal())
151
21
      return R_MIPS_GOT_LOCAL_PAGE;
152
22
    LLVM_FALLTHROUGH;
153
47
  case R_MIPS_CALL16:
154
47
  case R_MIPS_GOT_DISP:
155
47
  case R_MIPS_TLS_GOTTPREL:
156
47
  case R_MICROMIPS_CALL16:
157
47
  case R_MICROMIPS_TLS_GOTTPREL:
158
47
    return R_MIPS_GOT_OFF;
159
47
  case R_MIPS_CALL_HI16:
160
16
  case R_MIPS_CALL_LO16:
161
16
  case R_MIPS_GOT_HI16:
162
16
  case R_MIPS_GOT_LO16:
163
16
  case R_MICROMIPS_CALL_HI16:
164
16
  case R_MICROMIPS_CALL_LO16:
165
16
  case R_MICROMIPS_GOT_HI16:
166
16
  case R_MICROMIPS_GOT_LO16:
167
16
    return R_MIPS_GOT_OFF32;
168
16
  case R_MIPS_GOT_PAGE:
169
0
    return R_MIPS_GOT_LOCAL_PAGE;
170
16
  case R_MIPS_TLS_GD:
171
7
  case R_MICROMIPS_TLS_GD:
172
7
    return R_MIPS_TLSGD;
173
7
  case R_MIPS_TLS_LDM:
174
4
  case R_MICROMIPS_TLS_LDM:
175
4
    return R_MIPS_TLSLD;
176
4
  case R_MIPS_NONE:
177
0
    return R_NONE;
178
4
  default:
179
0
    return R_INVALID;
180
276
  }
181
276
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Line
Count
Source
82
10.0k
                               const uint8_t *Loc) const {
83
10.0k
  // See comment in the calculateMipsRelChain.
84
10.0k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi0
)
85
10.0k
    Type &= 0xff;
86
10.0k
87
10.0k
  switch (Type) {
88
10.0k
  case R_MIPS_JALR:
89
0
  case R_MICROMIPS_JALR:
90
0
    return R_HINT;
91
11
  case R_MIPS_GPREL16:
92
11
  case R_MIPS_GPREL32:
93
11
  case R_MICROMIPS_GPREL16:
94
11
  case R_MICROMIPS_GPREL7_S2:
95
11
    return R_MIPS_GOTREL;
96
11
  case R_MIPS_26:
97
2
  case R_MICROMIPS_26_S1:
98
2
    return R_PLT;
99
2
  case R_MICROMIPS_PC26_S1:
100
0
    return R_PLT_PC;
101
4
  case R_MIPS_HI16:
102
4
  case R_MIPS_LO16:
103
4
  case R_MIPS_HIGHER:
104
4
  case R_MIPS_HIGHEST:
105
4
  case R_MICROMIPS_HI16:
106
4
  case R_MICROMIPS_LO16:
107
4
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
108
4
    // offset between start of function and 'gp' value which by default
109
4
    // equal to the start of .got section. In that case we consider these
110
4
    // relocations as relative.
111
4
    if (&S == ElfSym::MipsGpDisp)
112
0
      return R_MIPS_GOT_GP_PC;
113
4
    if (&S == ElfSym::MipsLocalGp)
114
0
      return R_MIPS_GOT_GP;
115
4
    LLVM_FALLTHROUGH;
116
16
  case R_MIPS_32:
117
16
  case R_MIPS_64:
118
16
  case R_MIPS_GOT_OFST:
119
16
  case R_MIPS_SUB:
120
16
  case R_MIPS_TLS_DTPREL_HI16:
121
16
  case R_MIPS_TLS_DTPREL_LO16:
122
16
  case R_MIPS_TLS_DTPREL32:
123
16
  case R_MIPS_TLS_DTPREL64:
124
16
  case R_MIPS_TLS_TPREL_HI16:
125
16
  case R_MIPS_TLS_TPREL_LO16:
126
16
  case R_MIPS_TLS_TPREL32:
127
16
  case R_MIPS_TLS_TPREL64:
128
16
  case R_MICROMIPS_TLS_DTPREL_HI16:
129
16
  case R_MICROMIPS_TLS_DTPREL_LO16:
130
16
  case R_MICROMIPS_TLS_TPREL_HI16:
131
16
  case R_MICROMIPS_TLS_TPREL_LO16:
132
16
    return R_ABS;
133
16
  case R_MIPS_PC32:
134
1
  case R_MIPS_PC16:
135
1
  case R_MIPS_PC19_S2:
136
1
  case R_MIPS_PC21_S2:
137
1
  case R_MIPS_PC26_S2:
138
1
  case R_MIPS_PCHI16:
139
1
  case R_MIPS_PCLO16:
140
1
  case R_MICROMIPS_PC7_S1:
141
1
  case R_MICROMIPS_PC10_S1:
142
1
  case R_MICROMIPS_PC16_S1:
143
1
  case R_MICROMIPS_PC18_S3:
144
1
  case R_MICROMIPS_PC19_S2:
145
1
  case R_MICROMIPS_PC23_S2:
146
1
  case R_MICROMIPS_PC21_S1:
147
1
    return R_PC;
148
1
  case R_MIPS_GOT16:
149
0
  case R_MICROMIPS_GOT16:
150
0
    if (S.isLocal())
151
0
      return R_MIPS_GOT_LOCAL_PAGE;
152
0
    LLVM_FALLTHROUGH;
153
10.0k
  case R_MIPS_CALL16:
154
10.0k
  case R_MIPS_GOT_DISP:
155
10.0k
  case R_MIPS_TLS_GOTTPREL:
156
10.0k
  case R_MICROMIPS_CALL16:
157
10.0k
  case R_MICROMIPS_TLS_GOTTPREL:
158
10.0k
    return R_MIPS_GOT_OFF;
159
10.0k
  case R_MIPS_CALL_HI16:
160
0
  case R_MIPS_CALL_LO16:
161
0
  case R_MIPS_GOT_HI16:
162
0
  case R_MIPS_GOT_LO16:
163
0
  case R_MICROMIPS_CALL_HI16:
164
0
  case R_MICROMIPS_CALL_LO16:
165
0
  case R_MICROMIPS_GOT_HI16:
166
0
  case R_MICROMIPS_GOT_LO16:
167
0
    return R_MIPS_GOT_OFF32;
168
12
  case R_MIPS_GOT_PAGE:
169
12
    return R_MIPS_GOT_LOCAL_PAGE;
170
5
  case R_MIPS_TLS_GD:
171
5
  case R_MICROMIPS_TLS_GD:
172
5
    return R_MIPS_TLSGD;
173
5
  case R_MIPS_TLS_LDM:
174
2
  case R_MICROMIPS_TLS_LDM:
175
2
    return R_MIPS_TLSLD;
176
2
  case R_MIPS_NONE:
177
0
    return R_NONE;
178
2
  default:
179
0
    return R_INVALID;
180
10.0k
  }
181
10.0k
}
182
183
4
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
184
4
  if (Type == R_MIPS_32 || 
Type == R_MIPS_642
)
185
4
    return RelativeRel;
186
0
  return R_MIPS_NONE;
187
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getDynRel(unsigned int) const
Line
Count
Source
183
1
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
184
1
  if (Type == R_MIPS_32 || 
Type == R_MIPS_640
)
185
1
    return RelativeRel;
186
0
  return R_MIPS_NONE;
187
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getDynRel(unsigned int) const
Line
Count
Source
183
1
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
184
1
  if (Type == R_MIPS_32 || 
Type == R_MIPS_640
)
185
1
    return RelativeRel;
186
0
  return R_MIPS_NONE;
187
0
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getDynRel(unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getDynRel(unsigned int) const
Line
Count
Source
183
2
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
184
2
  if (Type == R_MIPS_32 || Type == R_MIPS_64)
185
2
    return RelativeRel;
186
0
  return R_MIPS_NONE;
187
0
}
188
189
template <class ELFT>
190
17
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
191
17
  uint64_t VA = In.Plt->getVA();
192
17
  if (isMicroMips())
193
6
    VA |= 1;
194
17
  write32<ELFT::TargetEndianness>(Buf, VA);
195
17
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Line
Count
Source
190
2
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
191
2
  uint64_t VA = In.Plt->getVA();
192
2
  if (isMicroMips())
193
2
    VA |= 1;
194
2
  write32<ELFT::TargetEndianness>(Buf, VA);
195
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Line
Count
Source
190
13
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
191
13
  uint64_t VA = In.Plt->getVA();
192
13
  if (isMicroMips())
193
4
    VA |= 1;
194
13
  write32<ELFT::TargetEndianness>(Buf, VA);
195
13
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Line
Count
Source
190
2
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
191
2
  uint64_t VA = In.Plt->getVA();
192
2
  if (isMicroMips())
193
0
    VA |= 1;
194
2
  write32<ELFT::TargetEndianness>(Buf, VA);
195
2
}
196
197
34
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
198
34
  // The major opcode of a microMIPS instruction needs to appear
199
34
  // in the first 16-bit word (lowest address) for efficient hardware
200
34
  // decode so that it knows if the instruction is 16-bit or 32-bit
201
34
  // as early as possible. To do so, little-endian binaries keep 16-bit
202
34
  // words in a big-endian order. That is why we have to swap these
203
34
  // words to get a correct value.
204
34
  uint32_t V = read32<E>(Loc);
205
34
  if (E == support::little)
206
12
    return (V << 16) | (V >> 16);
207
22
  return V;
208
22
}
Mips.cpp:unsigned int readShuffle<(llvm::support::endianness)1>(unsigned char const*)
Line
Count
Source
197
12
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
198
12
  // The major opcode of a microMIPS instruction needs to appear
199
12
  // in the first 16-bit word (lowest address) for efficient hardware
200
12
  // decode so that it knows if the instruction is 16-bit or 32-bit
201
12
  // as early as possible. To do so, little-endian binaries keep 16-bit
202
12
  // words in a big-endian order. That is why we have to swap these
203
12
  // words to get a correct value.
204
12
  uint32_t V = read32<E>(Loc);
205
12
  if (E == support::little)
206
12
    return (V << 16) | (V >> 16);
207
0
  return V;
208
0
}
Mips.cpp:unsigned int readShuffle<(llvm::support::endianness)0>(unsigned char const*)
Line
Count
Source
197
22
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
198
22
  // The major opcode of a microMIPS instruction needs to appear
199
22
  // in the first 16-bit word (lowest address) for efficient hardware
200
22
  // decode so that it knows if the instruction is 16-bit or 32-bit
201
22
  // as early as possible. To do so, little-endian binaries keep 16-bit
202
22
  // words in a big-endian order. That is why we have to swap these
203
22
  // words to get a correct value.
204
22
  uint32_t V = read32<E>(Loc);
205
22
  if (E == support::little)
206
0
    return (V << 16) | (V >> 16);
207
22
  return V;
208
22
}
209
210
template <endianness E>
211
static void writeValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
212
10.4k
                       uint8_t Shift) {
213
10.4k
  uint32_t Instr = read32<E>(Loc);
214
10.4k
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
215
10.4k
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
216
10.4k
  write32<E>(Loc, Data);
217
10.4k
}
Mips.cpp:void writeValue<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
212
30
                       uint8_t Shift) {
213
30
  uint32_t Instr = read32<E>(Loc);
214
30
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
215
30
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
216
30
  write32<E>(Loc, Data);
217
30
}
Mips.cpp:void writeValue<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
212
10.4k
                       uint8_t Shift) {
213
10.4k
  uint32_t Instr = read32<E>(Loc);
214
10.4k
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
215
10.4k
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
216
10.4k
  write32<E>(Loc, Data);
217
10.4k
}
218
219
template <endianness E>
220
static void writeShuffleValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
221
57
                              uint8_t Shift) {
222
57
  // See comments in readShuffle for purpose of this code.
223
57
  uint16_t *Words = (uint16_t *)Loc;
224
57
  if (E == support::little)
225
22
    std::swap(Words[0], Words[1]);
226
57
227
57
  writeValue<E>(Loc, V, BitsSize, Shift);
228
57
229
57
  if (E == support::little)
230
22
    std::swap(Words[0], Words[1]);
231
57
}
Mips.cpp:void writeShuffleValue<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
221
22
                              uint8_t Shift) {
222
22
  // See comments in readShuffle for purpose of this code.
223
22
  uint16_t *Words = (uint16_t *)Loc;
224
22
  if (E == support::little)
225
22
    std::swap(Words[0], Words[1]);
226
22
227
22
  writeValue<E>(Loc, V, BitsSize, Shift);
228
22
229
22
  if (E == support::little)
230
22
    std::swap(Words[0], Words[1]);
231
22
}
Mips.cpp:void writeShuffleValue<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
221
35
                              uint8_t Shift) {
222
35
  // See comments in readShuffle for purpose of this code.
223
35
  uint16_t *Words = (uint16_t *)Loc;
224
35
  if (E == support::little)
225
0
    std::swap(Words[0], Words[1]);
226
35
227
35
  writeValue<E>(Loc, V, BitsSize, Shift);
228
35
229
35
  if (E == support::little)
230
0
    std::swap(Words[0], Words[1]);
231
35
}
232
233
template <endianness E>
234
static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
235
4
                                   uint8_t Shift) {
236
4
  uint16_t Instr = read16<E>(Loc);
237
4
  uint16_t Mask = 0xffff >> (16 - BitsSize);
238
4
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
239
4
  write16<E>(Loc, Data);
240
4
}
Mips.cpp:void writeMicroRelocation16<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
235
2
                                   uint8_t Shift) {
236
2
  uint16_t Instr = read16<E>(Loc);
237
2
  uint16_t Mask = 0xffff >> (16 - BitsSize);
238
2
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
239
2
  write16<E>(Loc, Data);
240
2
}
Mips.cpp:void writeMicroRelocation16<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
235
2
                                   uint8_t Shift) {
236
2
  uint16_t Instr = read16<E>(Loc);
237
2
  uint16_t Mask = 0xffff >> (16 - BitsSize);
238
2
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
239
2
  write16<E>(Loc, Data);
240
2
}
241
242
15
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
243
15
  const endianness E = ELFT::TargetEndianness;
244
15
  if (isMicroMips()) {
245
6
    uint64_t GotPlt = In.GotPlt->getVA();
246
6
    uint64_t Plt = In.Plt->getVA();
247
6
    // Overwrite trap instructions written by Writer::writeTrapInstr.
248
6
    memset(Buf, 0, PltHeaderSize);
249
6
250
6
    write16<E>(Buf, isMipsR6() ? 
0x78602
:
0x79804
); // addiupc v1, (GOTPLT) - .
251
6
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
252
6
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
253
6
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
254
6
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
255
6
    write16<E>(Buf + 14, 0xfffe);
256
6
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
257
6
    if (isMipsR6()) {
258
2
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
259
2
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
260
2
      write16<E>(Buf + 22, 0x0c00); // nop
261
2
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
262
4
    } else {
263
4
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
264
4
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
265
4
      write16<E>(Buf + 22, 0x0c00); // nop
266
4
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
267
4
    }
268
6
    return;
269
6
  }
270
9
271
9
  if (Config->MipsN32Abi) {
272
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
273
2
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
274
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
275
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
276
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
277
2
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
278
7
  } else if (ELFT::Is64Bits) {
279
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
280
2
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
281
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
282
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
283
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
284
2
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
285
5
  } else {
286
5
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
287
5
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
288
5
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
289
5
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
290
5
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
291
5
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
292
5
  }
293
9
294
9
  uint32_t JalrInst = Config->ZHazardplt ? 
0x0320fc093
:
0x0320f8096
;
295
9
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
296
9
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
297
9
298
9
  uint64_t GotPlt = In.GotPlt->getVA();
299
9
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
300
9
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
301
9
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
302
9
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writePltHeader(unsigned char*) const
Line
Count
Source
242
2
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
243
2
  const endianness E = ELFT::TargetEndianness;
244
2
  if (isMicroMips()) {
245
2
    uint64_t GotPlt = In.GotPlt->getVA();
246
2
    uint64_t Plt = In.Plt->getVA();
247
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
248
2
    memset(Buf, 0, PltHeaderSize);
249
2
250
2
    write16<E>(Buf, isMipsR6() ? 
0x78601
:
0x79801
); // addiupc v1, (GOTPLT) - .
251
2
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
252
2
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
253
2
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
254
2
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
255
2
    write16<E>(Buf + 14, 0xfffe);
256
2
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
257
2
    if (isMipsR6()) {
258
1
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
259
1
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
260
1
      write16<E>(Buf + 22, 0x0c00); // nop
261
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
262
1
    } else {
263
1
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
264
1
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
265
1
      write16<E>(Buf + 22, 0x0c00); // nop
266
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
267
1
    }
268
2
    return;
269
2
  }
270
0
271
0
  if (Config->MipsN32Abi) {
272
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
273
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
274
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
275
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
276
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
277
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
278
0
  } else if (ELFT::Is64Bits) {
279
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
280
0
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
281
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
282
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
283
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
284
0
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
285
0
  } else {
286
0
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
287
0
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
288
0
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
289
0
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
290
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
291
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
292
0
  }
293
0
294
0
  uint32_t JalrInst = Config->ZHazardplt ? 0x0320fc09 : 0x0320f809;
295
0
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
296
0
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
297
0
298
0
  uint64_t GotPlt = In.GotPlt->getVA();
299
0
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
300
0
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
301
0
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
302
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writePltHeader(unsigned char*) const
Line
Count
Source
242
11
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
243
11
  const endianness E = ELFT::TargetEndianness;
244
11
  if (isMicroMips()) {
245
4
    uint64_t GotPlt = In.GotPlt->getVA();
246
4
    uint64_t Plt = In.Plt->getVA();
247
4
    // Overwrite trap instructions written by Writer::writeTrapInstr.
248
4
    memset(Buf, 0, PltHeaderSize);
249
4
250
4
    write16<E>(Buf, isMipsR6() ? 
0x78601
:
0x79803
); // addiupc v1, (GOTPLT) - .
251
4
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
252
4
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
253
4
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
254
4
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
255
4
    write16<E>(Buf + 14, 0xfffe);
256
4
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
257
4
    if (isMipsR6()) {
258
1
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
259
1
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
260
1
      write16<E>(Buf + 22, 0x0c00); // nop
261
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
262
3
    } else {
263
3
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
264
3
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
265
3
      write16<E>(Buf + 22, 0x0c00); // nop
266
3
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
267
3
    }
268
4
    return;
269
4
  }
270
7
271
7
  if (Config->MipsN32Abi) {
272
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
273
2
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
274
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
275
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
276
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
277
2
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
278
5
  } else if (ELFT::Is64Bits) {
279
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
280
0
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
281
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
282
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
283
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
284
0
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
285
5
  } else {
286
5
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
287
5
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
288
5
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
289
5
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
290
5
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
291
5
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
292
5
  }
293
7
294
7
  uint32_t JalrInst = Config->ZHazardplt ? 
0x0320fc092
:
0x0320f8095
;
295
7
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
296
7
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
297
7
298
7
  uint64_t GotPlt = In.GotPlt->getVA();
299
7
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
300
7
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
301
7
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
302
7
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writePltHeader(unsigned char*) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writePltHeader(unsigned char*) const
Line
Count
Source
242
2
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
243
2
  const endianness E = ELFT::TargetEndianness;
244
2
  if (isMicroMips()) {
245
0
    uint64_t GotPlt = In.GotPlt->getVA();
246
0
    uint64_t Plt = In.Plt->getVA();
247
0
    // Overwrite trap instructions written by Writer::writeTrapInstr.
248
0
    memset(Buf, 0, PltHeaderSize);
249
0
250
0
    write16<E>(Buf, isMipsR6() ? 0x7860 : 0x7980);  // addiupc v1, (GOTPLT) - .
251
0
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
252
0
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
253
0
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
254
0
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
255
0
    write16<E>(Buf + 14, 0xfffe);
256
0
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
257
0
    if (isMipsR6()) {
258
0
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
259
0
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
260
0
      write16<E>(Buf + 22, 0x0c00); // nop
261
0
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
262
0
    } else {
263
0
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
264
0
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
265
0
      write16<E>(Buf + 22, 0x0c00); // nop
266
0
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
267
0
    }
268
0
    return;
269
0
  }
270
2
271
2
  if (Config->MipsN32Abi) {
272
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
273
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
274
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
275
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
276
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
277
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
278
2
  } else if (ELFT::Is64Bits) {
279
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
280
2
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
281
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
282
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
283
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
284
2
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
285
2
  } else {
286
0
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
287
0
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
288
0
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
289
0
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
290
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
291
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
292
0
  }
293
2
294
2
  uint32_t JalrInst = Config->ZHazardplt ? 
0x0320fc091
:
0x0320f8091
;
295
2
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
296
2
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
297
2
298
2
  uint64_t GotPlt = In.GotPlt->getVA();
299
2
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
300
2
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
301
2
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
302
2
}
303
304
template <class ELFT>
305
void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
306
                          uint64_t PltEntryAddr, int32_t Index,
307
17
                          unsigned RelOff) const {
308
17
  const endianness E = ELFT::TargetEndianness;
309
17
  if (isMicroMips()) {
310
6
    // Overwrite trap instructions written by Writer::writeTrapInstr.
311
6
    memset(Buf, 0, PltEntrySize);
312
6
313
6
    if (isMipsR6()) {
314
2
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
315
2
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
316
2
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
317
2
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
318
2
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
319
4
    } else {
320
4
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
321
4
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
322
4
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
323
4
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
324
4
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
325
4
    }
326
6
    return;
327
6
  }
328
11
329
11
  uint32_t JrInst = isMipsR6() ? 
(Config->ZHazardplt 2
?
0x032004091
:
0x032000091
)
330
11
                               : 
(Config->ZHazardplt 9
?
0x032004082
:
0x032000087
);
331
11
332
11
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
333
11
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
334
11
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
335
11
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
336
11
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
337
11
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
338
11
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
339
11
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
307
2
                          unsigned RelOff) const {
308
2
  const endianness E = ELFT::TargetEndianness;
309
2
  if (isMicroMips()) {
310
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
311
2
    memset(Buf, 0, PltEntrySize);
312
2
313
2
    if (isMipsR6()) {
314
1
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
315
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
316
1
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
317
1
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
318
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
319
1
    } else {
320
1
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
321
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
322
1
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
323
1
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
324
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
325
1
    }
326
2
    return;
327
2
  }
328
0
329
0
  uint32_t JrInst = isMipsR6() ? (Config->ZHazardplt ? 0x03200409 : 0x03200009)
330
0
                               : (Config->ZHazardplt ? 0x03200408 : 0x03200008);
331
0
332
0
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
333
0
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
334
0
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
335
0
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
336
0
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
337
0
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
338
0
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
339
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
307
13
                          unsigned RelOff) const {
308
13
  const endianness E = ELFT::TargetEndianness;
309
13
  if (isMicroMips()) {
310
4
    // Overwrite trap instructions written by Writer::writeTrapInstr.
311
4
    memset(Buf, 0, PltEntrySize);
312
4
313
4
    if (isMipsR6()) {
314
1
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
315
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
316
1
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
317
1
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
318
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
319
3
    } else {
320
3
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
321
3
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
322
3
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
323
3
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
324
3
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
325
3
    }
326
4
    return;
327
4
  }
328
9
329
9
  uint32_t JrInst = isMipsR6() ? 
(Config->ZHazardplt 2
?
0x032004091
:
0x032000091
)
330
9
                               : 
(Config->ZHazardplt 7
?
0x032004081
:
0x032000086
);
331
9
332
9
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
333
9
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
334
9
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
335
9
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
336
9
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
337
9
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
338
9
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
339
9
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
307
2
                          unsigned RelOff) const {
308
2
  const endianness E = ELFT::TargetEndianness;
309
2
  if (isMicroMips()) {
310
0
    // Overwrite trap instructions written by Writer::writeTrapInstr.
311
0
    memset(Buf, 0, PltEntrySize);
312
0
313
0
    if (isMipsR6()) {
314
0
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
315
0
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
316
0
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
317
0
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
318
0
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
319
0
    } else {
320
0
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
321
0
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
322
0
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
323
0
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
324
0
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
325
0
    }
326
0
    return;
327
0
  }
328
2
329
2
  uint32_t JrInst = isMipsR6() ? 
(Config->ZHazardplt 0
?
0x032004090
:
0x032000090
)
330
2
                               : (Config->ZHazardplt ? 
0x032004081
:
0x032000081
);
331
2
332
2
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
333
2
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
334
2
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
335
2
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
336
2
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
337
2
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
338
2
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
339
2
}
340
341
template <class ELFT>
342
bool MIPS<ELFT>::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
343
10.3k
                            uint64_t BranchAddr, const Symbol &S) const {
344
10.3k
  // Any MIPS PIC code function is invoked with its address in register $t9.
345
10.3k
  // So if we have a branch instruction from non-PIC code to the PIC one
346
10.3k
  // we cannot make the jump directly and need to create a small stubs
347
10.3k
  // to save the target function address.
348
10.3k
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
349
10.3k
  if (Type != R_MIPS_26 && 
Type != R_MICROMIPS_26_S110.2k
&&
350
10.3k
      
Type != R_MICROMIPS_PC26_S110.2k
)
351
10.2k
    return false;
352
73
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
353
73
  if (!F)
354
0
    return false;
355
73
  // If current file has PIC code, LA25 stub is not required.
356
73
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
357
0
    return false;
358
73
  auto *D = dyn_cast<Defined>(&S);
359
73
  // LA25 is required if target file has PIC code
360
73
  // or target symbol is a PIC symbol.
361
73
  return D && 
isMipsPIC<ELFT>(D)60
;
362
73
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Line
Count
Source
343
18
                            uint64_t BranchAddr, const Symbol &S) const {
344
18
  // Any MIPS PIC code function is invoked with its address in register $t9.
345
18
  // So if we have a branch instruction from non-PIC code to the PIC one
346
18
  // we cannot make the jump directly and need to create a small stubs
347
18
  // to save the target function address.
348
18
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
349
18
  if (Type != R_MIPS_26 && Type != R_MICROMIPS_26_S1 &&
350
18
      
Type != R_MICROMIPS_PC26_S116
)
351
13
    return false;
352
5
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
353
5
  if (!F)
354
0
    return false;
355
5
  // If current file has PIC code, LA25 stub is not required.
356
5
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
357
0
    return false;
358
5
  auto *D = dyn_cast<Defined>(&S);
359
5
  // LA25 is required if target file has PIC code
360
5
  // or target symbol is a PIC symbol.
361
5
  return D && 
isMipsPIC<ELFT>(D)3
;
362
5
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Line
Count
Source
343
248
                            uint64_t BranchAddr, const Symbol &S) const {
344
248
  // Any MIPS PIC code function is invoked with its address in register $t9.
345
248
  // So if we have a branch instruction from non-PIC code to the PIC one
346
248
  // we cannot make the jump directly and need to create a small stubs
347
248
  // to save the target function address.
348
248
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
349
248
  if (Type != R_MIPS_26 && 
Type != R_MICROMIPS_26_S1189
&&
350
248
      
Type != R_MICROMIPS_PC26_S1185
)
351
182
    return false;
352
66
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
353
66
  if (!F)
354
0
    return false;
355
66
  // If current file has PIC code, LA25 stub is not required.
356
66
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
357
0
    return false;
358
66
  auto *D = dyn_cast<Defined>(&S);
359
66
  // LA25 is required if target file has PIC code
360
66
  // or target symbol is a PIC symbol.
361
66
  return D && 
isMipsPIC<ELFT>(D)57
;
362
66
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Line
Count
Source
343
10.0k
                            uint64_t BranchAddr, const Symbol &S) const {
344
10.0k
  // Any MIPS PIC code function is invoked with its address in register $t9.
345
10.0k
  // So if we have a branch instruction from non-PIC code to the PIC one
346
10.0k
  // we cannot make the jump directly and need to create a small stubs
347
10.0k
  // to save the target function address.
348
10.0k
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
349
10.0k
  if (Type != R_MIPS_26 && 
Type != R_MICROMIPS_26_S110.0k
&&
350
10.0k
      
Type != R_MICROMIPS_PC26_S110.0k
)
351
10.0k
    return false;
352
2
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
353
2
  if (!F)
354
0
    return false;
355
2
  // If current file has PIC code, LA25 stub is not required.
356
2
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
357
0
    return false;
358
2
  auto *D = dyn_cast<Defined>(&S);
359
2
  // LA25 is required if target file has PIC code
360
2
  // or target symbol is a PIC symbol.
361
2
  return D && 
isMipsPIC<ELFT>(D)0
;
362
2
}
363
364
template <class ELFT>
365
338
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
366
338
  const endianness E = ELFT::TargetEndianness;
367
338
  switch (Type) {
368
338
  case R_MIPS_32:
369
27
  case R_MIPS_GPREL32:
370
27
  case R_MIPS_TLS_DTPREL32:
371
27
  case R_MIPS_TLS_TPREL32:
372
27
    return SignExtend64<32>(read32<E>(Buf));
373
50
  case R_MIPS_26:
374
50
    // FIXME (simon): If the relocation target symbol is not a PLT entry
375
50
    // we should use another expression for calculation:
376
50
    // ((A << 2) | (P & 0xf0000000)) >> 2
377
50
    return SignExtend64<28>(read32<E>(Buf) << 2);
378
70
  case R_MIPS_GOT16:
379
70
  case R_MIPS_HI16:
380
70
  case R_MIPS_PCHI16:
381
70
    return SignExtend64<16>(read32<E>(Buf)) << 16;
382
94
  case R_MIPS_GPREL16:
383
94
  case R_MIPS_LO16:
384
94
  case R_MIPS_PCLO16:
385
94
  case R_MIPS_TLS_DTPREL_HI16:
386
94
  case R_MIPS_TLS_DTPREL_LO16:
387
94
  case R_MIPS_TLS_TPREL_HI16:
388
94
  case R_MIPS_TLS_TPREL_LO16:
389
94
    return SignExtend64<16>(read32<E>(Buf));
390
94
  case R_MICROMIPS_GOT16:
391
7
  case R_MICROMIPS_HI16:
392
7
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
393
9
  case R_MICROMIPS_GPREL16:
394
9
  case R_MICROMIPS_LO16:
395
9
  case R_MICROMIPS_TLS_DTPREL_HI16:
396
9
  case R_MICROMIPS_TLS_DTPREL_LO16:
397
9
  case R_MICROMIPS_TLS_TPREL_HI16:
398
9
  case R_MICROMIPS_TLS_TPREL_LO16:
399
9
    return SignExtend64<16>(readShuffle<E>(Buf));
400
9
  case R_MICROMIPS_GPREL7_S2:
401
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
402
9
  case R_MIPS_PC16:
403
2
    return SignExtend64<18>(read32<E>(Buf) << 2);
404
9
  case R_MIPS_PC19_S2:
405
1
    return SignExtend64<21>(read32<E>(Buf) << 2);
406
9
  case R_MIPS_PC21_S2:
407
1
    return SignExtend64<23>(read32<E>(Buf) << 2);
408
9
  case R_MIPS_PC26_S2:
409
1
    return SignExtend64<28>(read32<E>(Buf) << 2);
410
9
  case R_MIPS_PC32:
411
1
    return SignExtend64<32>(read32<E>(Buf));
412
9
  case R_MICROMIPS_26_S1:
413
6
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
414
9
  case R_MICROMIPS_PC7_S1:
415
2
    return SignExtend64<8>(read16<E>(Buf) << 1);
416
9
  case R_MICROMIPS_PC10_S1:
417
2
    return SignExtend64<11>(read16<E>(Buf) << 1);
418
9
  case R_MICROMIPS_PC16_S1:
419
2
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
420
9
  case R_MICROMIPS_PC18_S3:
421
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
422
9
  case R_MICROMIPS_PC19_S2:
423
2
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
424
9
  case R_MICROMIPS_PC21_S1:
425
2
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
426
9
  case R_MICROMIPS_PC23_S2:
427
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
428
9
  case R_MICROMIPS_PC26_S1:
429
6
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
430
53
  default:
431
53
    return 0;
432
338
  }
433
338
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getImplicitAddend(unsigned char const*, unsigned int) const
Line
Count
Source
365
25
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
366
25
  const endianness E = ELFT::TargetEndianness;
367
25
  switch (Type) {
368
25
  case R_MIPS_32:
369
2
  case R_MIPS_GPREL32:
370
2
  case R_MIPS_TLS_DTPREL32:
371
2
  case R_MIPS_TLS_TPREL32:
372
2
    return SignExtend64<32>(read32<E>(Buf));
373
2
  case R_MIPS_26:
374
0
    // FIXME (simon): If the relocation target symbol is not a PLT entry
375
0
    // we should use another expression for calculation:
376
0
    // ((A << 2) | (P & 0xf0000000)) >> 2
377
0
    return SignExtend64<28>(read32<E>(Buf) << 2);
378
6
  case R_MIPS_GOT16:
379
6
  case R_MIPS_HI16:
380
6
  case R_MIPS_PCHI16:
381
6
    return SignExtend64<16>(read32<E>(Buf)) << 16;
382
6
  case R_MIPS_GPREL16:
383
2
  case R_MIPS_LO16:
384
2
  case R_MIPS_PCLO16:
385
2
  case R_MIPS_TLS_DTPREL_HI16:
386
2
  case R_MIPS_TLS_DTPREL_LO16:
387
2
  case R_MIPS_TLS_TPREL_HI16:
388
2
  case R_MIPS_TLS_TPREL_LO16:
389
2
    return SignExtend64<16>(read32<E>(Buf));
390
2
  case R_MICROMIPS_GOT16:
391
2
  case R_MICROMIPS_HI16:
392
2
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
393
2
  case R_MICROMIPS_GPREL16:
394
2
  case R_MICROMIPS_LO16:
395
2
  case R_MICROMIPS_TLS_DTPREL_HI16:
396
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
397
2
  case R_MICROMIPS_TLS_TPREL_HI16:
398
2
  case R_MICROMIPS_TLS_TPREL_LO16:
399
2
    return SignExtend64<16>(readShuffle<E>(Buf));
400
2
  case R_MICROMIPS_GPREL7_S2:
401
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
402
2
  case R_MIPS_PC16:
403
0
    return SignExtend64<18>(read32<E>(Buf) << 2);
404
2
  case R_MIPS_PC19_S2:
405
0
    return SignExtend64<21>(read32<E>(Buf) << 2);
406
2
  case R_MIPS_PC21_S2:
407
0
    return SignExtend64<23>(read32<E>(Buf) << 2);
408
2
  case R_MIPS_PC26_S2:
409
0
    return SignExtend64<28>(read32<E>(Buf) << 2);
410
2
  case R_MIPS_PC32:
411
0
    return SignExtend64<32>(read32<E>(Buf));
412
2
  case R_MICROMIPS_26_S1:
413
2
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
414
2
  case R_MICROMIPS_PC7_S1:
415
1
    return SignExtend64<8>(read16<E>(Buf) << 1);
416
2
  case R_MICROMIPS_PC10_S1:
417
1
    return SignExtend64<11>(read16<E>(Buf) << 1);
418
2
  case R_MICROMIPS_PC16_S1:
419
1
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
420
2
  case R_MICROMIPS_PC18_S3:
421
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
422
2
  case R_MICROMIPS_PC19_S2:
423
1
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
424
2
  case R_MICROMIPS_PC21_S1:
425
1
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
426
2
  case R_MICROMIPS_PC23_S2:
427
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
428
3
  case R_MICROMIPS_PC26_S1:
429
3
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
430
2
  default:
431
1
    return 0;
432
25
  }
433
25
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getImplicitAddend(unsigned char const*, unsigned int) const
Line
Count
Source
365
313
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
366
313
  const endianness E = ELFT::TargetEndianness;
367
313
  switch (Type) {
368
313
  case R_MIPS_32:
369
25
  case R_MIPS_GPREL32:
370
25
  case R_MIPS_TLS_DTPREL32:
371
25
  case R_MIPS_TLS_TPREL32:
372
25
    return SignExtend64<32>(read32<E>(Buf));
373
50
  case R_MIPS_26:
374
50
    // FIXME (simon): If the relocation target symbol is not a PLT entry
375
50
    // we should use another expression for calculation:
376
50
    // ((A << 2) | (P & 0xf0000000)) >> 2
377
50
    return SignExtend64<28>(read32<E>(Buf) << 2);
378
64
  case R_MIPS_GOT16:
379
64
  case R_MIPS_HI16:
380
64
  case R_MIPS_PCHI16:
381
64
    return SignExtend64<16>(read32<E>(Buf)) << 16;
382
92
  case R_MIPS_GPREL16:
383
92
  case R_MIPS_LO16:
384
92
  case R_MIPS_PCLO16:
385
92
  case R_MIPS_TLS_DTPREL_HI16:
386
92
  case R_MIPS_TLS_DTPREL_LO16:
387
92
  case R_MIPS_TLS_TPREL_HI16:
388
92
  case R_MIPS_TLS_TPREL_LO16:
389
92
    return SignExtend64<16>(read32<E>(Buf));
390
92
  case R_MICROMIPS_GOT16:
391
5
  case R_MICROMIPS_HI16:
392
5
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
393
7
  case R_MICROMIPS_GPREL16:
394
7
  case R_MICROMIPS_LO16:
395
7
  case R_MICROMIPS_TLS_DTPREL_HI16:
396
7
  case R_MICROMIPS_TLS_DTPREL_LO16:
397
7
  case R_MICROMIPS_TLS_TPREL_HI16:
398
7
  case R_MICROMIPS_TLS_TPREL_LO16:
399
7
    return SignExtend64<16>(readShuffle<E>(Buf));
400
7
  case R_MICROMIPS_GPREL7_S2:
401
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
402
7
  case R_MIPS_PC16:
403
2
    return SignExtend64<18>(read32<E>(Buf) << 2);
404
7
  case R_MIPS_PC19_S2:
405
1
    return SignExtend64<21>(read32<E>(Buf) << 2);
406
7
  case R_MIPS_PC21_S2:
407
1
    return SignExtend64<23>(read32<E>(Buf) << 2);
408
7
  case R_MIPS_PC26_S2:
409
1
    return SignExtend64<28>(read32<E>(Buf) << 2);
410
7
  case R_MIPS_PC32:
411
1
    return SignExtend64<32>(read32<E>(Buf));
412
7
  case R_MICROMIPS_26_S1:
413
4
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
414
7
  case R_MICROMIPS_PC7_S1:
415
1
    return SignExtend64<8>(read16<E>(Buf) << 1);
416
7
  case R_MICROMIPS_PC10_S1:
417
1
    return SignExtend64<11>(read16<E>(Buf) << 1);
418
7
  case R_MICROMIPS_PC16_S1:
419
1
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
420
7
  case R_MICROMIPS_PC18_S3:
421
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
422
7
  case R_MICROMIPS_PC19_S2:
423
1
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
424
7
  case R_MICROMIPS_PC21_S1:
425
1
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
426
7
  case R_MICROMIPS_PC23_S2:
427
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
428
7
  case R_MICROMIPS_PC26_S1:
429
3
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
430
52
  default:
431
52
    return 0;
432
313
  }
433
313
}
434
435
static std::pair<uint32_t, uint64_t>
436
10.0k
calculateMipsRelChain(uint8_t *Loc, RelType Type, uint64_t Val) {
437
10.0k
  // MIPS N64 ABI packs multiple relocations into the single relocation
438
10.0k
  // record. In general, all up to three relocations can have arbitrary
439
10.0k
  // types. In fact, Clang and GCC uses only a few combinations. For now,
440
10.0k
  // we support two of them. That is allow to pass at least all LLVM
441
10.0k
  // test suite cases.
442
10.0k
  // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
443
10.0k
  // <any relocation> / R_MIPS_64 / R_MIPS_NONE
444
10.0k
  // The first relocation is a 'real' relocation which is calculated
445
10.0k
  // using the corresponding symbol's value. The second and the third
446
10.0k
  // relocations used to modify result of the first one: extend it to
447
10.0k
  // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
448
10.0k
  // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
449
10.0k
  RelType Type2 = (Type >> 8) & 0xff;
450
10.0k
  RelType Type3 = (Type >> 16) & 0xff;
451
10.0k
  if (Type2 == R_MIPS_NONE && 
Type3 == R_MIPS_NONE10.0k
)
452
10.0k
    return std::make_pair(Type, Val);
453
12
  if (Type2 == R_MIPS_64 && 
Type3 == R_MIPS_NONE1
)
454
1
    return std::make_pair(Type2, Val);
455
11
  if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || 
Type3 == R_MIPS_LO164
))
456
11
    return std::make_pair(Type3, -Val);
457
0
  error(getErrorLocation(Loc) + "unsupported relocations combination " +
458
0
        Twine(Type));
459
0
  return std::make_pair(Type & 0xff, Val);
460
0
}
461
462
template <class ELFT>
463
10.4k
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
464
10.4k
  const endianness E = ELFT::TargetEndianness;
465
10.4k
466
10.4k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi382
)
467
10.0k
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
468
10.4k
469
10.4k
  // Thread pointer and DRP offsets from the start of TLS data area.
470
10.4k
  // https://www.linux-mips.org/wiki/NPTL
471
10.4k
  if (Type == R_MIPS_TLS_DTPREL_HI16 || 
Type == R_MIPS_TLS_DTPREL_LO1610.4k
||
472
10.4k
      
Type == R_MIPS_TLS_DTPREL3210.4k
||
Type == R_MIPS_TLS_DTPREL6410.4k
||
473
10.4k
      
Type == R_MICROMIPS_TLS_DTPREL_HI1610.4k
||
474
10.4k
      
Type == R_MICROMIPS_TLS_DTPREL_LO1610.4k
) {
475
6
    Val -= 0x8000;
476
10.4k
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || 
Type == R_MIPS_TLS_TPREL_LO1610.4k
||
477
10.4k
             
Type == R_MIPS_TLS_TPREL3210.4k
||
Type == R_MIPS_TLS_TPREL6410.4k
||
478
10.4k
             
Type == R_MICROMIPS_TLS_TPREL_HI1610.4k
||
479
10.4k
             
Type == R_MICROMIPS_TLS_TPREL_LO1610.4k
) {
480
6
    Val -= 0x7000;
481
6
  }
482
10.4k
483
10.4k
  switch (Type) {
484
10.4k
  case R_MIPS_32:
485
31
  case R_MIPS_GPREL32:
486
31
  case R_MIPS_TLS_DTPREL32:
487
31
  case R_MIPS_TLS_TPREL32:
488
31
    write32<E>(Loc, Val);
489
31
    break;
490
31
  case R_MIPS_64:
491
8
  case R_MIPS_TLS_DTPREL64:
492
8
  case R_MIPS_TLS_TPREL64:
493
8
    write64<E>(Loc, Val);
494
8
    break;
495
54
  case R_MIPS_26:
496
54
    writeValue<E>(Loc, Val, 26, 2);
497
54
    break;
498
46
  case R_MIPS_GOT16:
499
46
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
500
46
    // is updated addend (not a GOT index). In that case write high 16 bits
501
46
    // to store a correct addend value.
502
46
    if (Config->Relocatable) {
503
6
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
504
40
    } else {
505
40
      checkInt(Loc, Val, 16, Type);
506
40
      writeValue<E>(Loc, Val, 16, 0);
507
40
    }
508
46
    break;
509
8
  case R_MICROMIPS_GOT16:
510
4
    if (Config->Relocatable) {
511
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
512
4
    } else {
513
4
      checkInt(Loc, Val, 16, Type);
514
4
      writeShuffleValue<E>(Loc, Val, 16, 0);
515
4
    }
516
4
    break;
517
10.0k
  case R_MIPS_CALL16:
518
10.0k
  case R_MIPS_GOT_DISP:
519
10.0k
  case R_MIPS_GOT_PAGE:
520
10.0k
  case R_MIPS_GPREL16:
521
10.0k
  case R_MIPS_TLS_GD:
522
10.0k
  case R_MIPS_TLS_GOTTPREL:
523
10.0k
  case R_MIPS_TLS_LDM:
524
10.0k
    checkInt(Loc, Val, 16, Type);
525
10.0k
    LLVM_FALLTHROUGH;
526
10.1k
  case R_MIPS_CALL_LO16:
527
10.1k
  case R_MIPS_GOT_LO16:
528
10.1k
  case R_MIPS_GOT_OFST:
529
10.1k
  case R_MIPS_LO16:
530
10.1k
  case R_MIPS_PCLO16:
531
10.1k
  case R_MIPS_TLS_DTPREL_LO16:
532
10.1k
  case R_MIPS_TLS_TPREL_LO16:
533
10.1k
    writeValue<E>(Loc, Val, 16, 0);
534
10.1k
    break;
535
10.1k
  case R_MICROMIPS_GPREL16:
536
0
  case R_MICROMIPS_TLS_GD:
537
0
  case R_MICROMIPS_TLS_LDM:
538
0
    checkInt(Loc, Val, 16, Type);
539
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
540
0
    break;
541
12
  case R_MICROMIPS_CALL16:
542
12
  case R_MICROMIPS_CALL_LO16:
543
12
  case R_MICROMIPS_LO16:
544
12
  case R_MICROMIPS_TLS_DTPREL_LO16:
545
12
  case R_MICROMIPS_TLS_GOTTPREL:
546
12
  case R_MICROMIPS_TLS_TPREL_LO16:
547
12
    writeShuffleValue<E>(Loc, Val, 16, 0);
548
12
    break;
549
12
  case R_MICROMIPS_GPREL7_S2:
550
0
    checkInt(Loc, Val, 7, Type);
551
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
552
0
    break;
553
72
  case R_MIPS_CALL_HI16:
554
72
  case R_MIPS_GOT_HI16:
555
72
  case R_MIPS_HI16:
556
72
  case R_MIPS_PCHI16:
557
72
  case R_MIPS_TLS_DTPREL_HI16:
558
72
  case R_MIPS_TLS_TPREL_HI16:
559
72
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
560
72
    break;
561
72
  case R_MICROMIPS_CALL_HI16:
562
7
  case R_MICROMIPS_GOT_HI16:
563
7
  case R_MICROMIPS_HI16:
564
7
  case R_MICROMIPS_TLS_DTPREL_HI16:
565
7
  case R_MICROMIPS_TLS_TPREL_HI16:
566
7
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
567
7
    break;
568
7
  case R_MIPS_HIGHER:
569
2
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
570
2
    break;
571
7
  case R_MIPS_HIGHEST:
572
2
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
573
2
    break;
574
7
  case R_MIPS_JALR:
575
0
  case R_MICROMIPS_JALR:
576
0
    // Ignore this optimization relocation for now
577
0
    break;
578
2
  case R_MIPS_PC16:
579
2
    checkAlignment(Loc, Val, 4, Type);
580
2
    checkInt(Loc, Val, 18, Type);
581
2
    writeValue<E>(Loc, Val, 16, 2);
582
2
    break;
583
1
  case R_MIPS_PC19_S2:
584
1
    checkAlignment(Loc, Val, 4, Type);
585
1
    checkInt(Loc, Val, 21, Type);
586
1
    writeValue<E>(Loc, Val, 19, 2);
587
1
    break;
588
1
  case R_MIPS_PC21_S2:
589
1
    checkAlignment(Loc, Val, 4, Type);
590
1
    checkInt(Loc, Val, 23, Type);
591
1
    writeValue<E>(Loc, Val, 21, 2);
592
1
    break;
593
1
  case R_MIPS_PC26_S2:
594
1
    checkAlignment(Loc, Val, 4, Type);
595
1
    checkInt(Loc, Val, 28, Type);
596
1
    writeValue<E>(Loc, Val, 26, 2);
597
1
    break;
598
2
  case R_MIPS_PC32:
599
2
    writeValue<E>(Loc, Val, 32, 0);
600
2
    break;
601
16
  case R_MICROMIPS_26_S1:
602
16
  case R_MICROMIPS_PC26_S1:
603
16
    checkInt(Loc, Val, 27, Type);
604
16
    writeShuffleValue<E>(Loc, Val, 26, 1);
605
16
    break;
606
16
  case R_MICROMIPS_PC7_S1:
607
2
    checkInt(Loc, Val, 8, Type);
608
2
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
609
2
    break;
610
16
  case R_MICROMIPS_PC10_S1:
611
2
    checkInt(Loc, Val, 11, Type);
612
2
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
613
2
    break;
614
16
  case R_MICROMIPS_PC16_S1:
615
2
    checkInt(Loc, Val, 17, Type);
616
2
    writeShuffleValue<E>(Loc, Val, 16, 1);
617
2
    break;
618
16
  case R_MICROMIPS_PC18_S3:
619
0
    checkInt(Loc, Val, 21, Type);
620
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
621
0
    break;
622
16
  case R_MICROMIPS_PC19_S2:
623
6
    checkInt(Loc, Val, 21, Type);
624
6
    writeShuffleValue<E>(Loc, Val, 19, 2);
625
6
    break;
626
16
  case R_MICROMIPS_PC21_S1:
627
2
    checkInt(Loc, Val, 22, Type);
628
2
    writeShuffleValue<E>(Loc, Val, 21, 1);
629
2
    break;
630
16
  case R_MICROMIPS_PC23_S2:
631
8
    checkInt(Loc, Val, 25, Type);
632
8
    writeShuffleValue<E>(Loc, Val, 23, 2);
633
8
    break;
634
16
  default:
635
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
636
10.4k
  }
637
10.4k
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
463
34
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
464
34
  const endianness E = ELFT::TargetEndianness;
465
34
466
34
  if (ELFT::Is64Bits || Config->MipsN32Abi)
467
0
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
468
34
469
34
  // Thread pointer and DRP offsets from the start of TLS data area.
470
34
  // https://www.linux-mips.org/wiki/NPTL
471
34
  if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
472
34
      Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 ||
473
34
      Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
474
34
      Type == R_MICROMIPS_TLS_DTPREL_LO16) {
475
0
    Val -= 0x8000;
476
34
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
477
34
             Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 ||
478
34
             Type == R_MICROMIPS_TLS_TPREL_HI16 ||
479
34
             Type == R_MICROMIPS_TLS_TPREL_LO16) {
480
0
    Val -= 0x7000;
481
0
  }
482
34
483
34
  switch (Type) {
484
34
  case R_MIPS_32:
485
2
  case R_MIPS_GPREL32:
486
2
  case R_MIPS_TLS_DTPREL32:
487
2
  case R_MIPS_TLS_TPREL32:
488
2
    write32<E>(Loc, Val);
489
2
    break;
490
2
  case R_MIPS_64:
491
0
  case R_MIPS_TLS_DTPREL64:
492
0
  case R_MIPS_TLS_TPREL64:
493
0
    write64<E>(Loc, Val);
494
0
    break;
495
0
  case R_MIPS_26:
496
0
    writeValue<E>(Loc, Val, 26, 2);
497
0
    break;
498
6
  case R_MIPS_GOT16:
499
6
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
500
6
    // is updated addend (not a GOT index). In that case write high 16 bits
501
6
    // to store a correct addend value.
502
6
    if (Config->Relocatable) {
503
2
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
504
4
    } else {
505
4
      checkInt(Loc, Val, 16, Type);
506
4
      writeValue<E>(Loc, Val, 16, 0);
507
4
    }
508
6
    break;
509
1
  case R_MICROMIPS_GOT16:
510
1
    if (Config->Relocatable) {
511
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
512
1
    } else {
513
1
      checkInt(Loc, Val, 16, Type);
514
1
      writeShuffleValue<E>(Loc, Val, 16, 0);
515
1
    }
516
1
    break;
517
0
  case R_MIPS_CALL16:
518
0
  case R_MIPS_GOT_DISP:
519
0
  case R_MIPS_GOT_PAGE:
520
0
  case R_MIPS_GPREL16:
521
0
  case R_MIPS_TLS_GD:
522
0
  case R_MIPS_TLS_GOTTPREL:
523
0
  case R_MIPS_TLS_LDM:
524
0
    checkInt(Loc, Val, 16, Type);
525
0
    LLVM_FALLTHROUGH;
526
2
  case R_MIPS_CALL_LO16:
527
2
  case R_MIPS_GOT_LO16:
528
2
  case R_MIPS_GOT_OFST:
529
2
  case R_MIPS_LO16:
530
2
  case R_MIPS_PCLO16:
531
2
  case R_MIPS_TLS_DTPREL_LO16:
532
2
  case R_MIPS_TLS_TPREL_LO16:
533
2
    writeValue<E>(Loc, Val, 16, 0);
534
2
    break;
535
2
  case R_MICROMIPS_GPREL16:
536
0
  case R_MICROMIPS_TLS_GD:
537
0
  case R_MICROMIPS_TLS_LDM:
538
0
    checkInt(Loc, Val, 16, Type);
539
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
540
0
    break;
541
4
  case R_MICROMIPS_CALL16:
542
4
  case R_MICROMIPS_CALL_LO16:
543
4
  case R_MICROMIPS_LO16:
544
4
  case R_MICROMIPS_TLS_DTPREL_LO16:
545
4
  case R_MICROMIPS_TLS_GOTTPREL:
546
4
  case R_MICROMIPS_TLS_TPREL_LO16:
547
4
    writeShuffleValue<E>(Loc, Val, 16, 0);
548
4
    break;
549
4
  case R_MICROMIPS_GPREL7_S2:
550
0
    checkInt(Loc, Val, 7, Type);
551
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
552
0
    break;
553
4
  case R_MIPS_CALL_HI16:
554
0
  case R_MIPS_GOT_HI16:
555
0
  case R_MIPS_HI16:
556
0
  case R_MIPS_PCHI16:
557
0
  case R_MIPS_TLS_DTPREL_HI16:
558
0
  case R_MIPS_TLS_TPREL_HI16:
559
0
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
560
0
    break;
561
3
  case R_MICROMIPS_CALL_HI16:
562
3
  case R_MICROMIPS_GOT_HI16:
563
3
  case R_MICROMIPS_HI16:
564
3
  case R_MICROMIPS_TLS_DTPREL_HI16:
565
3
  case R_MICROMIPS_TLS_TPREL_HI16:
566
3
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
567
3
    break;
568
3
  case R_MIPS_HIGHER:
569
0
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
570
0
    break;
571
3
  case R_MIPS_HIGHEST:
572
0
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
573
0
    break;
574
3
  case R_MIPS_JALR:
575
0
  case R_MICROMIPS_JALR:
576
0
    // Ignore this optimization relocation for now
577
0
    break;
578
0
  case R_MIPS_PC16:
579
0
    checkAlignment(Loc, Val, 4, Type);
580
0
    checkInt(Loc, Val, 18, Type);
581
0
    writeValue<E>(Loc, Val, 16, 2);
582
0
    break;
583
0
  case R_MIPS_PC19_S2:
584
0
    checkAlignment(Loc, Val, 4, Type);
585
0
    checkInt(Loc, Val, 21, Type);
586
0
    writeValue<E>(Loc, Val, 19, 2);
587
0
    break;
588
0
  case R_MIPS_PC21_S2:
589
0
    checkAlignment(Loc, Val, 4, Type);
590
0
    checkInt(Loc, Val, 23, Type);
591
0
    writeValue<E>(Loc, Val, 21, 2);
592
0
    break;
593
0
  case R_MIPS_PC26_S2:
594
0
    checkAlignment(Loc, Val, 4, Type);
595
0
    checkInt(Loc, Val, 28, Type);
596
0
    writeValue<E>(Loc, Val, 26, 2);
597
0
    break;
598
0
  case R_MIPS_PC32:
599
0
    writeValue<E>(Loc, Val, 32, 0);
600
0
    break;
601
7
  case R_MICROMIPS_26_S1:
602
7
  case R_MICROMIPS_PC26_S1:
603
7
    checkInt(Loc, Val, 27, Type);
604
7
    writeShuffleValue<E>(Loc, Val, 26, 1);
605
7
    break;
606
7
  case R_MICROMIPS_PC7_S1:
607
1
    checkInt(Loc, Val, 8, Type);
608
1
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
609
1
    break;
610
7
  case R_MICROMIPS_PC10_S1:
611
1
    checkInt(Loc, Val, 11, Type);
612
1
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
613
1
    break;
614
7
  case R_MICROMIPS_PC16_S1:
615
1
    checkInt(Loc, Val, 17, Type);
616
1
    writeShuffleValue<E>(Loc, Val, 16, 1);
617
1
    break;
618
7
  case R_MICROMIPS_PC18_S3:
619
0
    checkInt(Loc, Val, 21, Type);
620
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
621
0
    break;
622
7
  case R_MICROMIPS_PC19_S2:
623
3
    checkInt(Loc, Val, 21, Type);
624
3
    writeShuffleValue<E>(Loc, Val, 19, 2);
625
3
    break;
626
7
  case R_MICROMIPS_PC21_S1:
627
1
    checkInt(Loc, Val, 22, Type);
628
1
    writeShuffleValue<E>(Loc, Val, 21, 1);
629
1
    break;
630
7
  case R_MICROMIPS_PC23_S2:
631
2
    checkInt(Loc, Val, 25, Type);
632
2
    writeShuffleValue<E>(Loc, Val, 23, 2);
633
2
    break;
634
7
  default:
635
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
636
34
  }
637
34
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
463
348
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
464
348
  const endianness E = ELFT::TargetEndianness;
465
348
466
348
  if (ELFT::Is64Bits || Config->MipsN32Abi)
467
5
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
468
348
469
348
  // Thread pointer and DRP offsets from the start of TLS data area.
470
348
  // https://www.linux-mips.org/wiki/NPTL
471
348
  if (Type == R_MIPS_TLS_DTPREL_HI16 || 
Type == R_MIPS_TLS_DTPREL_LO16346
||
472
348
      
Type == R_MIPS_TLS_DTPREL32344
||
Type == R_MIPS_TLS_DTPREL64343
||
473
348
      
Type == R_MICROMIPS_TLS_DTPREL_HI16343
||
474
348
      
Type == R_MICROMIPS_TLS_DTPREL_LO16343
) {
475
5
    Val -= 0x8000;
476
343
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || 
Type == R_MIPS_TLS_TPREL_LO16341
||
477
343
             
Type == R_MIPS_TLS_TPREL32339
||
Type == R_MIPS_TLS_TPREL64338
||
478
343
             
Type == R_MICROMIPS_TLS_TPREL_HI16338
||
479
343
             
Type == R_MICROMIPS_TLS_TPREL_LO16338
) {
480
5
    Val -= 0x7000;
481
5
  }
482
348
483
348
  switch (Type) {
484
348
  case R_MIPS_32:
485
26
  case R_MIPS_GPREL32:
486
26
  case R_MIPS_TLS_DTPREL32:
487
26
  case R_MIPS_TLS_TPREL32:
488
26
    write32<E>(Loc, Val);
489
26
    break;
490
26
  case R_MIPS_64:
491
0
  case R_MIPS_TLS_DTPREL64:
492
0
  case R_MIPS_TLS_TPREL64:
493
0
    write64<E>(Loc, Val);
494
0
    break;
495
52
  case R_MIPS_26:
496
52
    writeValue<E>(Loc, Val, 26, 2);
497
52
    break;
498
40
  case R_MIPS_GOT16:
499
40
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
500
40
    // is updated addend (not a GOT index). In that case write high 16 bits
501
40
    // to store a correct addend value.
502
40
    if (Config->Relocatable) {
503
4
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
504
36
    } else {
505
36
      checkInt(Loc, Val, 16, Type);
506
36
      writeValue<E>(Loc, Val, 16, 0);
507
36
    }
508
40
    break;
509
3
  case R_MICROMIPS_GOT16:
510
3
    if (Config->Relocatable) {
511
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
512
3
    } else {
513
3
      checkInt(Loc, Val, 16, Type);
514
3
      writeShuffleValue<E>(Loc, Val, 16, 0);
515
3
    }
516
3
    break;
517
34
  case R_MIPS_CALL16:
518
34
  case R_MIPS_GOT_DISP:
519
34
  case R_MIPS_GOT_PAGE:
520
34
  case R_MIPS_GPREL16:
521
34
  case R_MIPS_TLS_GD:
522
34
  case R_MIPS_TLS_GOTTPREL:
523
34
  case R_MIPS_TLS_LDM:
524
34
    checkInt(Loc, Val, 16, Type);
525
34
    LLVM_FALLTHROUGH;
526
121
  case R_MIPS_CALL_LO16:
527
121
  case R_MIPS_GOT_LO16:
528
121
  case R_MIPS_GOT_OFST:
529
121
  case R_MIPS_LO16:
530
121
  case R_MIPS_PCLO16:
531
121
  case R_MIPS_TLS_DTPREL_LO16:
532
121
  case R_MIPS_TLS_TPREL_LO16:
533
121
    writeValue<E>(Loc, Val, 16, 0);
534
121
    break;
535
121
  case R_MICROMIPS_GPREL16:
536
0
  case R_MICROMIPS_TLS_GD:
537
0
  case R_MICROMIPS_TLS_LDM:
538
0
    checkInt(Loc, Val, 16, Type);
539
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
540
0
    break;
541
8
  case R_MICROMIPS_CALL16:
542
8
  case R_MICROMIPS_CALL_LO16:
543
8
  case R_MICROMIPS_LO16:
544
8
  case R_MICROMIPS_TLS_DTPREL_LO16:
545
8
  case R_MICROMIPS_TLS_GOTTPREL:
546
8
  case R_MICROMIPS_TLS_TPREL_LO16:
547
8
    writeShuffleValue<E>(Loc, Val, 16, 0);
548
8
    break;
549
8
  case R_MICROMIPS_GPREL7_S2:
550
0
    checkInt(Loc, Val, 7, Type);
551
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
552
0
    break;
553
66
  case R_MIPS_CALL_HI16:
554
66
  case R_MIPS_GOT_HI16:
555
66
  case R_MIPS_HI16:
556
66
  case R_MIPS_PCHI16:
557
66
  case R_MIPS_TLS_DTPREL_HI16:
558
66
  case R_MIPS_TLS_TPREL_HI16:
559
66
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
560
66
    break;
561
66
  case R_MICROMIPS_CALL_HI16:
562
4
  case R_MICROMIPS_GOT_HI16:
563
4
  case R_MICROMIPS_HI16:
564
4
  case R_MICROMIPS_TLS_DTPREL_HI16:
565
4
  case R_MICROMIPS_TLS_TPREL_HI16:
566
4
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
567
4
    break;
568
4
  case R_MIPS_HIGHER:
569
0
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
570
0
    break;
571
4
  case R_MIPS_HIGHEST:
572
0
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
573
0
    break;
574
4
  case R_MIPS_JALR:
575
0
  case R_MICROMIPS_JALR:
576
0
    // Ignore this optimization relocation for now
577
0
    break;
578
2
  case R_MIPS_PC16:
579
2
    checkAlignment(Loc, Val, 4, Type);
580
2
    checkInt(Loc, Val, 18, Type);
581
2
    writeValue<E>(Loc, Val, 16, 2);
582
2
    break;
583
1
  case R_MIPS_PC19_S2:
584
1
    checkAlignment(Loc, Val, 4, Type);
585
1
    checkInt(Loc, Val, 21, Type);
586
1
    writeValue<E>(Loc, Val, 19, 2);
587
1
    break;
588
1
  case R_MIPS_PC21_S2:
589
1
    checkAlignment(Loc, Val, 4, Type);
590
1
    checkInt(Loc, Val, 23, Type);
591
1
    writeValue<E>(Loc, Val, 21, 2);
592
1
    break;
593
1
  case R_MIPS_PC26_S2:
594
1
    checkAlignment(Loc, Val, 4, Type);
595
1
    checkInt(Loc, Val, 28, Type);
596
1
    writeValue<E>(Loc, Val, 26, 2);
597
1
    break;
598
1
  case R_MIPS_PC32:
599
1
    writeValue<E>(Loc, Val, 32, 0);
600
1
    break;
601
9
  case R_MICROMIPS_26_S1:
602
9
  case R_MICROMIPS_PC26_S1:
603
9
    checkInt(Loc, Val, 27, Type);
604
9
    writeShuffleValue<E>(Loc, Val, 26, 1);
605
9
    break;
606
9
  case R_MICROMIPS_PC7_S1:
607
1
    checkInt(Loc, Val, 8, Type);
608
1
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
609
1
    break;
610
9
  case R_MICROMIPS_PC10_S1:
611
1
    checkInt(Loc, Val, 11, Type);
612
1
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
613
1
    break;
614
9
  case R_MICROMIPS_PC16_S1:
615
1
    checkInt(Loc, Val, 17, Type);
616
1
    writeShuffleValue<E>(Loc, Val, 16, 1);
617
1
    break;
618
9
  case R_MICROMIPS_PC18_S3:
619
0
    checkInt(Loc, Val, 21, Type);
620
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
621
0
    break;
622
9
  case R_MICROMIPS_PC19_S2:
623
3
    checkInt(Loc, Val, 21, Type);
624
3
    writeShuffleValue<E>(Loc, Val, 19, 2);
625
3
    break;
626
9
  case R_MICROMIPS_PC21_S1:
627
1
    checkInt(Loc, Val, 22, Type);
628
1
    writeShuffleValue<E>(Loc, Val, 21, 1);
629
1
    break;
630
9
  case R_MICROMIPS_PC23_S2:
631
6
    checkInt(Loc, Val, 25, Type);
632
6
    writeShuffleValue<E>(Loc, Val, 23, 2);
633
6
    break;
634
9
  default:
635
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
636
348
  }
637
348
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
463
10.0k
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
464
10.0k
  const endianness E = ELFT::TargetEndianness;
465
10.0k
466
10.0k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi0
)
467
10.0k
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
468
10.0k
469
10.0k
  // Thread pointer and DRP offsets from the start of TLS data area.
470
10.0k
  // https://www.linux-mips.org/wiki/NPTL
471
10.0k
  if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
472
10.0k
      Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 ||
473
10.0k
      
Type == R_MICROMIPS_TLS_DTPREL_HI1610.0k
||
474
10.0k
      
Type == R_MICROMIPS_TLS_DTPREL_LO1610.0k
) {
475
1
    Val -= 0x8000;
476
10.0k
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
477
10.0k
             Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 ||
478
10.0k
             
Type == R_MICROMIPS_TLS_TPREL_HI1610.0k
||
479
10.0k
             
Type == R_MICROMIPS_TLS_TPREL_LO1610.0k
) {
480
1
    Val -= 0x7000;
481
1
  }
482
10.0k
483
10.0k
  switch (Type) {
484
10.0k
  case R_MIPS_32:
485
3
  case R_MIPS_GPREL32:
486
3
  case R_MIPS_TLS_DTPREL32:
487
3
  case R_MIPS_TLS_TPREL32:
488
3
    write32<E>(Loc, Val);
489
3
    break;
490
8
  case R_MIPS_64:
491
8
  case R_MIPS_TLS_DTPREL64:
492
8
  case R_MIPS_TLS_TPREL64:
493
8
    write64<E>(Loc, Val);
494
8
    break;
495
8
  case R_MIPS_26:
496
2
    writeValue<E>(Loc, Val, 26, 2);
497
2
    break;
498
8
  case R_MIPS_GOT16:
499
0
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
500
0
    // is updated addend (not a GOT index). In that case write high 16 bits
501
0
    // to store a correct addend value.
502
0
    if (Config->Relocatable) {
503
0
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
504
0
    } else {
505
0
      checkInt(Loc, Val, 16, Type);
506
0
      writeValue<E>(Loc, Val, 16, 0);
507
0
    }
508
0
    break;
509
8
  case R_MICROMIPS_GOT16:
510
0
    if (Config->Relocatable) {
511
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
512
0
    } else {
513
0
      checkInt(Loc, Val, 16, Type);
514
0
      writeShuffleValue<E>(Loc, Val, 16, 0);
515
0
    }
516
0
    break;
517
10.0k
  case R_MIPS_CALL16:
518
10.0k
  case R_MIPS_GOT_DISP:
519
10.0k
  case R_MIPS_GOT_PAGE:
520
10.0k
  case R_MIPS_GPREL16:
521
10.0k
  case R_MIPS_TLS_GD:
522
10.0k
  case R_MIPS_TLS_GOTTPREL:
523
10.0k
  case R_MIPS_TLS_LDM:
524
10.0k
    checkInt(Loc, Val, 16, Type);
525
10.0k
    LLVM_FALLTHROUGH;
526
10.0k
  case R_MIPS_CALL_LO16:
527
10.0k
  case R_MIPS_GOT_LO16:
528
10.0k
  case R_MIPS_GOT_OFST:
529
10.0k
  case R_MIPS_LO16:
530
10.0k
  case R_MIPS_PCLO16:
531
10.0k
  case R_MIPS_TLS_DTPREL_LO16:
532
10.0k
  case R_MIPS_TLS_TPREL_LO16:
533
10.0k
    writeValue<E>(Loc, Val, 16, 0);
534
10.0k
    break;
535
10.0k
  case R_MICROMIPS_GPREL16:
536
0
  case R_MICROMIPS_TLS_GD:
537
0
  case R_MICROMIPS_TLS_LDM:
538
0
    checkInt(Loc, Val, 16, Type);
539
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
540
0
    break;
541
0
  case R_MICROMIPS_CALL16:
542
0
  case R_MICROMIPS_CALL_LO16:
543
0
  case R_MICROMIPS_LO16:
544
0
  case R_MICROMIPS_TLS_DTPREL_LO16:
545
0
  case R_MICROMIPS_TLS_GOTTPREL:
546
0
  case R_MICROMIPS_TLS_TPREL_LO16:
547
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
548
0
    break;
549
0
  case R_MICROMIPS_GPREL7_S2:
550
0
    checkInt(Loc, Val, 7, Type);
551
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
552
0
    break;
553
6
  case R_MIPS_CALL_HI16:
554
6
  case R_MIPS_GOT_HI16:
555
6
  case R_MIPS_HI16:
556
6
  case R_MIPS_PCHI16:
557
6
  case R_MIPS_TLS_DTPREL_HI16:
558
6
  case R_MIPS_TLS_TPREL_HI16:
559
6
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
560
6
    break;
561
6
  case R_MICROMIPS_CALL_HI16:
562
0
  case R_MICROMIPS_GOT_HI16:
563
0
  case R_MICROMIPS_HI16:
564
0
  case R_MICROMIPS_TLS_DTPREL_HI16:
565
0
  case R_MICROMIPS_TLS_TPREL_HI16:
566
0
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
567
0
    break;
568
2
  case R_MIPS_HIGHER:
569
2
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
570
2
    break;
571
2
  case R_MIPS_HIGHEST:
572
2
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
573
2
    break;
574
0
  case R_MIPS_JALR:
575
0
  case R_MICROMIPS_JALR:
576
0
    // Ignore this optimization relocation for now
577
0
    break;
578
0
  case R_MIPS_PC16:
579
0
    checkAlignment(Loc, Val, 4, Type);
580
0
    checkInt(Loc, Val, 18, Type);
581
0
    writeValue<E>(Loc, Val, 16, 2);
582
0
    break;
583
0
  case R_MIPS_PC19_S2:
584
0
    checkAlignment(Loc, Val, 4, Type);
585
0
    checkInt(Loc, Val, 21, Type);
586
0
    writeValue<E>(Loc, Val, 19, 2);
587
0
    break;
588
0
  case R_MIPS_PC21_S2:
589
0
    checkAlignment(Loc, Val, 4, Type);
590
0
    checkInt(Loc, Val, 23, Type);
591
0
    writeValue<E>(Loc, Val, 21, 2);
592
0
    break;
593
0
  case R_MIPS_PC26_S2:
594
0
    checkAlignment(Loc, Val, 4, Type);
595
0
    checkInt(Loc, Val, 28, Type);
596
0
    writeValue<E>(Loc, Val, 26, 2);
597
0
    break;
598
1
  case R_MIPS_PC32:
599
1
    writeValue<E>(Loc, Val, 32, 0);
600
1
    break;
601
0
  case R_MICROMIPS_26_S1:
602
0
  case R_MICROMIPS_PC26_S1:
603
0
    checkInt(Loc, Val, 27, Type);
604
0
    writeShuffleValue<E>(Loc, Val, 26, 1);
605
0
    break;
606
0
  case R_MICROMIPS_PC7_S1:
607
0
    checkInt(Loc, Val, 8, Type);
608
0
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
609
0
    break;
610
0
  case R_MICROMIPS_PC10_S1:
611
0
    checkInt(Loc, Val, 11, Type);
612
0
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
613
0
    break;
614
0
  case R_MICROMIPS_PC16_S1:
615
0
    checkInt(Loc, Val, 17, Type);
616
0
    writeShuffleValue<E>(Loc, Val, 16, 1);
617
0
    break;
618
0
  case R_MICROMIPS_PC18_S3:
619
0
    checkInt(Loc, Val, 21, Type);
620
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
621
0
    break;
622
0
  case R_MICROMIPS_PC19_S2:
623
0
    checkInt(Loc, Val, 21, Type);
624
0
    writeShuffleValue<E>(Loc, Val, 19, 2);
625
0
    break;
626
0
  case R_MICROMIPS_PC21_S1:
627
0
    checkInt(Loc, Val, 22, Type);
628
0
    writeShuffleValue<E>(Loc, Val, 21, 1);
629
0
    break;
630
0
  case R_MICROMIPS_PC23_S2:
631
0
    checkInt(Loc, Val, 25, Type);
632
0
    writeShuffleValue<E>(Loc, Val, 23, 2);
633
0
    break;
634
0
  default:
635
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
636
10.0k
  }
637
10.0k
}
638
639
34
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
640
34
  return Type == R_MIPS_LO16 || 
Type == R_MIPS_GOT_OFST18
||
641
34
         
Type == R_MICROMIPS_LO1617
;
642
34
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
639
2
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
640
2
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
641
2
         Type == R_MICROMIPS_LO16;
642
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
639
26
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
640
26
  return Type == R_MIPS_LO16 || 
Type == R_MIPS_GOT_OFST10
||
641
26
         
Type == R_MICROMIPS_LO1610
;
642
26
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::usesOnlyLowPageBits(unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
639
6
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
640
6
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
641
6
         
Type == R_MICROMIPS_LO165
;
642
6
}
643
644
// Return true if the symbol is a PIC function.
645
137
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
646
137
  if (!Sym->isFunc())
647
71
    return false;
648
66
649
66
  if (Sym->StOther & STO_MIPS_PIC)
650
7
    return true;
651
59
652
59
  if (!Sym->Section)
653
0
    return false;
654
59
655
59
  ObjFile<ELFT> *File =
656
59
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
657
59
  if (!File)
658
1
    return false;
659
58
660
58
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
661
58
}
bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)1, false> >(lld::elf::Defined const*)
Line
Count
Source
645
8
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
646
8
  if (!Sym->isFunc())
647
5
    return false;
648
3
649
3
  if (Sym->StOther & STO_MIPS_PIC)
650
0
    return true;
651
3
652
3
  if (!Sym->Section)
653
0
    return false;
654
3
655
3
  ObjFile<ELFT> *File =
656
3
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
657
3
  if (!File)
658
0
    return false;
659
3
660
3
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
661
3
}
bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)0, false> >(lld::elf::Defined const*)
Line
Count
Source
645
118
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
646
118
  if (!Sym->isFunc())
647
55
    return false;
648
63
649
63
  if (Sym->StOther & STO_MIPS_PIC)
650
7
    return true;
651
56
652
56
  if (!Sym->Section)
653
0
    return false;
654
56
655
56
  ObjFile<ELFT> *File =
656
56
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
657
56
  if (!File)
658
1
    return false;
659
55
660
55
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
661
55
}
Unexecuted instantiation: bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)1, true> >(lld::elf::Defined const*)
bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)0, true> >(lld::elf::Defined const*)
Line
Count
Source
645
11
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
646
11
  if (!Sym->isFunc())
647
11
    return false;
648
0
649
0
  if (Sym->StOther & STO_MIPS_PIC)
650
0
    return true;
651
0
652
0
  if (!Sym->Section)
653
0
    return false;
654
0
655
0
  ObjFile<ELFT> *File =
656
0
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
657
0
  if (!File)
658
0
    return false;
659
0
660
0
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
661
0
}
662
663
194
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
664
194
  static MIPS<ELFT> Target;
665
194
  return &Target;
666
194
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)1, false> >()
Line
Count
Source
663
23
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
664
23
  static MIPS<ELFT> Target;
665
23
  return &Target;
666
23
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)0, false> >()
Line
Count
Source
663
122
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
664
122
  static MIPS<ELFT> Target;
665
122
  return &Target;
666
122
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)1, true> >()
Line
Count
Source
663
3
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
664
3
  static MIPS<ELFT> Target;
665
3
  return &Target;
666
3
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)0, true> >()
Line
Count
Source
663
46
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
664
46
  static MIPS<ELFT> Target;
665
46
  return &Target;
666
46
}
667
668
template TargetInfo *elf::getMipsTargetInfo<ELF32LE>();
669
template TargetInfo *elf::getMipsTargetInfo<ELF32BE>();
670
template TargetInfo *elf::getMipsTargetInfo<ELF64LE>();
671
template TargetInfo *elf::getMipsTargetInfo<ELF64BE>();
672
673
template bool elf::isMipsPIC<ELF32LE>(const Defined *);
674
template bool elf::isMipsPIC<ELF32BE>(const Defined *);
675
template bool elf::isMipsPIC<ELF64LE>(const Defined *);
676
template bool elf::isMipsPIC<ELF64BE>(const Defined *);