Coverage Report

Created: 2018-06-25 02:00

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/Mips.cpp
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Source (jump to first uncovered line)
1
//===- MIPS.cpp -----------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
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//===----------------------------------------------------------------------===//
9
10
#include "InputFiles.h"
11
#include "OutputSections.h"
12
#include "Symbols.h"
13
#include "SyntheticSections.h"
14
#include "Target.h"
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#include "Thunks.h"
16
#include "lld/Common/ErrorHandler.h"
17
#include "llvm/Object/ELF.h"
18
#include "llvm/Support/Endian.h"
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20
using namespace llvm;
21
using namespace llvm::object;
22
using namespace llvm::support::endian;
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using namespace llvm::ELF;
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using namespace lld;
25
using namespace lld::elf;
26
27
namespace {
28
template <class ELFT> class MIPS final : public TargetInfo {
29
public:
30
  MIPS();
31
  uint32_t calcEFlags() const override;
32
  RelExpr getRelExpr(RelType Type, const Symbol &S,
33
                     const uint8_t *Loc) const override;
34
  int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override;
35
  RelType getDynRel(RelType Type) const override;
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  void writeGotPlt(uint8_t *Buf, const Symbol &S) const override;
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  void writePltHeader(uint8_t *Buf) const override;
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  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
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                int32_t Index, unsigned RelOff) const override;
40
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
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                  uint64_t BranchAddr, const Symbol &S) const override;
42
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
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  bool usesOnlyLowPageBits(RelType Type) const override;
44
};
45
} // namespace
46
47
175
template <class ELFT> MIPS<ELFT>::MIPS() {
48
175
  GotPltHeaderEntriesNum = 2;
49
175
  DefaultMaxPageSize = 65536;
50
175
  GotEntrySize = sizeof(typename ELFT::uint);
51
175
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
175
  GotBaseSymInGotPlt = false;
53
175
  PltEntrySize = 16;
54
175
  PltHeaderSize = 32;
55
175
  CopyRel = R_MIPS_COPY;
56
175
  PltRel = R_MIPS_JUMP_SLOT;
57
175
  NeedsThunks = true;
58
175
  TrapInstr = 0xefefefef;
59
175
60
175
  if (ELFT::Is64Bits) {
61
40
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
62
40
    TlsGotRel = R_MIPS_TLS_TPREL64;
63
40
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
64
40
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
65
135
  } else {
66
135
    RelativeRel = R_MIPS_REL32;
67
135
    TlsGotRel = R_MIPS_TLS_TPREL32;
68
135
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
69
135
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
70
135
  }
71
175
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::MIPS()
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47
17
template <class ELFT> MIPS<ELFT>::MIPS() {
48
17
  GotPltHeaderEntriesNum = 2;
49
17
  DefaultMaxPageSize = 65536;
50
17
  GotEntrySize = sizeof(typename ELFT::uint);
51
17
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
17
  GotBaseSymInGotPlt = false;
53
17
  PltEntrySize = 16;
54
17
  PltHeaderSize = 32;
55
17
  CopyRel = R_MIPS_COPY;
56
17
  PltRel = R_MIPS_JUMP_SLOT;
57
17
  NeedsThunks = true;
58
17
  TrapInstr = 0xefefefef;
59
17
60
17
  if (ELFT::Is64Bits) {
61
0
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
62
0
    TlsGotRel = R_MIPS_TLS_TPREL64;
63
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
64
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
65
17
  } else {
66
17
    RelativeRel = R_MIPS_REL32;
67
17
    TlsGotRel = R_MIPS_TLS_TPREL32;
68
17
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
69
17
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
70
17
  }
71
17
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::MIPS()
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47
118
template <class ELFT> MIPS<ELFT>::MIPS() {
48
118
  GotPltHeaderEntriesNum = 2;
49
118
  DefaultMaxPageSize = 65536;
50
118
  GotEntrySize = sizeof(typename ELFT::uint);
51
118
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
118
  GotBaseSymInGotPlt = false;
53
118
  PltEntrySize = 16;
54
118
  PltHeaderSize = 32;
55
118
  CopyRel = R_MIPS_COPY;
56
118
  PltRel = R_MIPS_JUMP_SLOT;
57
118
  NeedsThunks = true;
58
118
  TrapInstr = 0xefefefef;
59
118
60
118
  if (ELFT::Is64Bits) {
61
0
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
62
0
    TlsGotRel = R_MIPS_TLS_TPREL64;
63
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
64
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
65
118
  } else {
66
118
    RelativeRel = R_MIPS_REL32;
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118
    TlsGotRel = R_MIPS_TLS_TPREL32;
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118
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
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118
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
70
118
  }
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118
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::MIPS()
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47
2
template <class ELFT> MIPS<ELFT>::MIPS() {
48
2
  GotPltHeaderEntriesNum = 2;
49
2
  DefaultMaxPageSize = 65536;
50
2
  GotEntrySize = sizeof(typename ELFT::uint);
51
2
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
2
  GotBaseSymInGotPlt = false;
53
2
  PltEntrySize = 16;
54
2
  PltHeaderSize = 32;
55
2
  CopyRel = R_MIPS_COPY;
56
2
  PltRel = R_MIPS_JUMP_SLOT;
57
2
  NeedsThunks = true;
58
2
  TrapInstr = 0xefefefef;
59
2
60
2
  if (ELFT::Is64Bits) {
61
2
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
62
2
    TlsGotRel = R_MIPS_TLS_TPREL64;
63
2
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
64
2
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
65
2
  } else {
66
0
    RelativeRel = R_MIPS_REL32;
67
0
    TlsGotRel = R_MIPS_TLS_TPREL32;
68
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
69
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
70
0
  }
71
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::MIPS()
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47
38
template <class ELFT> MIPS<ELFT>::MIPS() {
48
38
  GotPltHeaderEntriesNum = 2;
49
38
  DefaultMaxPageSize = 65536;
50
38
  GotEntrySize = sizeof(typename ELFT::uint);
51
38
  GotPltEntrySize = sizeof(typename ELFT::uint);
52
38
  GotBaseSymInGotPlt = false;
53
38
  PltEntrySize = 16;
54
38
  PltHeaderSize = 32;
55
38
  CopyRel = R_MIPS_COPY;
56
38
  PltRel = R_MIPS_JUMP_SLOT;
57
38
  NeedsThunks = true;
58
38
  TrapInstr = 0xefefefef;
59
38
60
38
  if (ELFT::Is64Bits) {
61
38
    RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
62
38
    TlsGotRel = R_MIPS_TLS_TPREL64;
63
38
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
64
38
    TlsOffsetRel = R_MIPS_TLS_DTPREL64;
65
38
  } else {
66
0
    RelativeRel = R_MIPS_REL32;
67
0
    TlsGotRel = R_MIPS_TLS_TPREL32;
68
0
    TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
69
0
    TlsOffsetRel = R_MIPS_TLS_DTPREL32;
70
0
  }
71
38
}
72
73
172
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
74
172
  return calcMipsEFlags<ELFT>();
75
172
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::calcEFlags() const
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73
17
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
74
17
  return calcMipsEFlags<ELFT>();
75
17
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::calcEFlags() const
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73
116
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
74
116
  return calcMipsEFlags<ELFT>();
75
116
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::calcEFlags() const
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73
2
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
74
2
  return calcMipsEFlags<ELFT>();
75
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::calcEFlags() const
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73
37
template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const {
74
37
  return calcMipsEFlags<ELFT>();
75
37
}
76
77
template <class ELFT>
78
RelExpr MIPS<ELFT>::getRelExpr(RelType Type, const Symbol &S,
79
10.3k
                               const uint8_t *Loc) const {
80
10.3k
  // See comment in the calculateMipsRelChain.
81
10.3k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi293
)
82
10.0k
    Type &= 0xff;
83
10.3k
84
10.3k
  switch (Type) {
85
10.3k
  case R_MIPS_JALR:
86
1
  case R_MICROMIPS_JALR:
87
1
    return R_HINT;
88
26
  case R_MIPS_GPREL16:
89
26
  case R_MIPS_GPREL32:
90
26
  case R_MICROMIPS_GPREL16:
91
26
  case R_MICROMIPS_GPREL7_S2:
92
26
    return R_MIPS_GOTREL;
93
60
  case R_MIPS_26:
94
60
  case R_MICROMIPS_26_S1:
95
60
    return R_PLT;
96
60
  case R_MICROMIPS_PC26_S1:
97
6
    return R_PLT_PC;
98
77
  case R_MIPS_HI16:
99
77
  case R_MIPS_LO16:
100
77
  case R_MIPS_HIGHER:
101
77
  case R_MIPS_HIGHEST:
102
77
  case R_MICROMIPS_HI16:
103
77
  case R_MICROMIPS_LO16:
104
77
  case R_MICROMIPS_HIGHER:
105
77
  case R_MICROMIPS_HIGHEST:
106
77
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
107
77
    // offset between start of function and 'gp' value which by default
108
77
    // equal to the start of .got section. In that case we consider these
109
77
    // relocations as relative.
110
77
    if (&S == ElfSym::MipsGpDisp)
111
20
      return R_MIPS_GOT_GP_PC;
112
57
    if (&S == ElfSym::MipsLocalGp)
113
2
      return R_MIPS_GOT_GP;
114
55
    LLVM_FALLTHROUGH;
115
91
  case R_MIPS_32:
116
91
  case R_MIPS_64:
117
91
  case R_MIPS_GOT_OFST:
118
91
  case R_MIPS_SUB:
119
91
  case R_MIPS_TLS_DTPREL_HI16:
120
91
  case R_MIPS_TLS_DTPREL_LO16:
121
91
  case R_MIPS_TLS_DTPREL32:
122
91
  case R_MIPS_TLS_DTPREL64:
123
91
  case R_MIPS_TLS_TPREL_HI16:
124
91
  case R_MIPS_TLS_TPREL_LO16:
125
91
  case R_MIPS_TLS_TPREL32:
126
91
  case R_MIPS_TLS_TPREL64:
127
91
  case R_MICROMIPS_GOT_OFST:
128
91
  case R_MICROMIPS_SUB:
129
91
  case R_MICROMIPS_TLS_DTPREL_HI16:
130
91
  case R_MICROMIPS_TLS_DTPREL_LO16:
131
91
  case R_MICROMIPS_TLS_TPREL_HI16:
132
91
  case R_MICROMIPS_TLS_TPREL_LO16:
133
91
    return R_ABS;
134
91
  case R_MIPS_PC32:
135
19
  case R_MIPS_PC16:
136
19
  case R_MIPS_PC19_S2:
137
19
  case R_MIPS_PC21_S2:
138
19
  case R_MIPS_PC26_S2:
139
19
  case R_MIPS_PCHI16:
140
19
  case R_MIPS_PCLO16:
141
19
  case R_MICROMIPS_PC7_S1:
142
19
  case R_MICROMIPS_PC10_S1:
143
19
  case R_MICROMIPS_PC16_S1:
144
19
  case R_MICROMIPS_PC18_S3:
145
19
  case R_MICROMIPS_PC19_S2:
146
19
  case R_MICROMIPS_PC23_S2:
147
19
  case R_MICROMIPS_PC21_S1:
148
19
    return R_PC;
149
46
  case R_MIPS_GOT16:
150
46
  case R_MICROMIPS_GOT16:
151
46
    if (S.isLocal())
152
19
      return R_MIPS_GOT_LOCAL_PAGE;
153
27
    LLVM_FALLTHROUGH;
154
10.0k
  case R_MIPS_CALL16:
155
10.0k
  case R_MIPS_GOT_DISP:
156
10.0k
  case R_MIPS_TLS_GOTTPREL:
157
10.0k
  case R_MICROMIPS_CALL16:
158
10.0k
  case R_MICROMIPS_GOT_DISP:
159
10.0k
  case R_MICROMIPS_TLS_GOTTPREL:
160
10.0k
    return R_MIPS_GOT_OFF;
161
10.0k
  case R_MIPS_CALL_HI16:
162
16
  case R_MIPS_CALL_LO16:
163
16
  case R_MIPS_GOT_HI16:
164
16
  case R_MIPS_GOT_LO16:
165
16
  case R_MICROMIPS_CALL_HI16:
166
16
  case R_MICROMIPS_CALL_LO16:
167
16
  case R_MICROMIPS_GOT_HI16:
168
16
  case R_MICROMIPS_GOT_LO16:
169
16
    return R_MIPS_GOT_OFF32;
170
16
  case R_MIPS_GOT_PAGE:
171
12
  case R_MICROMIPS_GOT_PAGE:
172
12
    return R_MIPS_GOT_LOCAL_PAGE;
173
12
  case R_MIPS_TLS_GD:
174
12
  case R_MICROMIPS_TLS_GD:
175
12
    return R_MIPS_TLSGD;
176
12
  case R_MIPS_TLS_LDM:
177
6
  case R_MICROMIPS_TLS_LDM:
178
6
    return R_MIPS_TLSLD;
179
6
  case R_MIPS_NONE:
180
0
    return R_NONE;
181
6
  default:
182
0
    return R_INVALID;
183
10.3k
  }
184
10.3k
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Line
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Source
79
21
                               const uint8_t *Loc) const {
80
21
  // See comment in the calculateMipsRelChain.
81
21
  if (ELFT::Is64Bits || Config->MipsN32Abi)
82
0
    Type &= 0xff;
83
21
84
21
  switch (Type) {
85
21
  case R_MIPS_JALR:
86
1
  case R_MICROMIPS_JALR:
87
1
    return R_HINT;
88
1
  case R_MIPS_GPREL16:
89
0
  case R_MIPS_GPREL32:
90
0
  case R_MICROMIPS_GPREL16:
91
0
  case R_MICROMIPS_GPREL7_S2:
92
0
    return R_MIPS_GOTREL;
93
2
  case R_MIPS_26:
94
2
  case R_MICROMIPS_26_S1:
95
2
    return R_PLT;
96
3
  case R_MICROMIPS_PC26_S1:
97
3
    return R_PLT_PC;
98
2
  case R_MIPS_HI16:
99
2
  case R_MIPS_LO16:
100
2
  case R_MIPS_HIGHER:
101
2
  case R_MIPS_HIGHEST:
102
2
  case R_MICROMIPS_HI16:
103
2
  case R_MICROMIPS_LO16:
104
2
  case R_MICROMIPS_HIGHER:
105
2
  case R_MICROMIPS_HIGHEST:
106
2
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
107
2
    // offset between start of function and 'gp' value which by default
108
2
    // equal to the start of .got section. In that case we consider these
109
2
    // relocations as relative.
110
2
    if (&S == ElfSym::MipsGpDisp)
111
2
      return R_MIPS_GOT_GP_PC;
112
0
    if (&S == ElfSym::MipsLocalGp)
113
0
      return R_MIPS_GOT_GP;
114
0
    LLVM_FALLTHROUGH;
115
2
  case R_MIPS_32:
116
2
  case R_MIPS_64:
117
2
  case R_MIPS_GOT_OFST:
118
2
  case R_MIPS_SUB:
119
2
  case R_MIPS_TLS_DTPREL_HI16:
120
2
  case R_MIPS_TLS_DTPREL_LO16:
121
2
  case R_MIPS_TLS_DTPREL32:
122
2
  case R_MIPS_TLS_DTPREL64:
123
2
  case R_MIPS_TLS_TPREL_HI16:
124
2
  case R_MIPS_TLS_TPREL_LO16:
125
2
  case R_MIPS_TLS_TPREL32:
126
2
  case R_MIPS_TLS_TPREL64:
127
2
  case R_MICROMIPS_GOT_OFST:
128
2
  case R_MICROMIPS_SUB:
129
2
  case R_MICROMIPS_TLS_DTPREL_HI16:
130
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
131
2
  case R_MICROMIPS_TLS_TPREL_HI16:
132
2
  case R_MICROMIPS_TLS_TPREL_LO16:
133
2
    return R_ABS;
134
5
  case R_MIPS_PC32:
135
5
  case R_MIPS_PC16:
136
5
  case R_MIPS_PC19_S2:
137
5
  case R_MIPS_PC21_S2:
138
5
  case R_MIPS_PC26_S2:
139
5
  case R_MIPS_PCHI16:
140
5
  case R_MIPS_PCLO16:
141
5
  case R_MICROMIPS_PC7_S1:
142
5
  case R_MICROMIPS_PC10_S1:
143
5
  case R_MICROMIPS_PC16_S1:
144
5
  case R_MICROMIPS_PC18_S3:
145
5
  case R_MICROMIPS_PC19_S2:
146
5
  case R_MICROMIPS_PC23_S2:
147
5
  case R_MICROMIPS_PC21_S1:
148
5
    return R_PC;
149
5
  case R_MIPS_GOT16:
150
5
  case R_MICROMIPS_GOT16:
151
5
    if (S.isLocal())
152
0
      return R_MIPS_GOT_LOCAL_PAGE;
153
5
    LLVM_FALLTHROUGH;
154
6
  case R_MIPS_CALL16:
155
6
  case R_MIPS_GOT_DISP:
156
6
  case R_MIPS_TLS_GOTTPREL:
157
6
  case R_MICROMIPS_CALL16:
158
6
  case R_MICROMIPS_GOT_DISP:
159
6
  case R_MICROMIPS_TLS_GOTTPREL:
160
6
    return R_MIPS_GOT_OFF;
161
6
  case R_MIPS_CALL_HI16:
162
0
  case R_MIPS_CALL_LO16:
163
0
  case R_MIPS_GOT_HI16:
164
0
  case R_MIPS_GOT_LO16:
165
0
  case R_MICROMIPS_CALL_HI16:
166
0
  case R_MICROMIPS_CALL_LO16:
167
0
  case R_MICROMIPS_GOT_HI16:
168
0
  case R_MICROMIPS_GOT_LO16:
169
0
    return R_MIPS_GOT_OFF32;
170
0
  case R_MIPS_GOT_PAGE:
171
0
  case R_MICROMIPS_GOT_PAGE:
172
0
    return R_MIPS_GOT_LOCAL_PAGE;
173
0
  case R_MIPS_TLS_GD:
174
0
  case R_MICROMIPS_TLS_GD:
175
0
    return R_MIPS_TLSGD;
176
0
  case R_MIPS_TLS_LDM:
177
0
  case R_MICROMIPS_TLS_LDM:
178
0
    return R_MIPS_TLSLD;
179
0
  case R_MIPS_NONE:
180
0
    return R_NONE;
181
0
  default:
182
0
    return R_INVALID;
183
21
  }
184
21
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Line
Count
Source
79
272
                               const uint8_t *Loc) const {
80
272
  // See comment in the calculateMipsRelChain.
81
272
  if (ELFT::Is64Bits || Config->MipsN32Abi)
82
5
    Type &= 0xff;
83
272
84
272
  switch (Type) {
85
272
  case R_MIPS_JALR:
86
0
  case R_MICROMIPS_JALR:
87
0
    return R_HINT;
88
14
  case R_MIPS_GPREL16:
89
14
  case R_MIPS_GPREL32:
90
14
  case R_MICROMIPS_GPREL16:
91
14
  case R_MICROMIPS_GPREL7_S2:
92
14
    return R_MIPS_GOTREL;
93
56
  case R_MIPS_26:
94
56
  case R_MICROMIPS_26_S1:
95
56
    return R_PLT;
96
56
  case R_MICROMIPS_PC26_S1:
97
3
    return R_PLT_PC;
98
71
  case R_MIPS_HI16:
99
71
  case R_MIPS_LO16:
100
71
  case R_MIPS_HIGHER:
101
71
  case R_MIPS_HIGHEST:
102
71
  case R_MICROMIPS_HI16:
103
71
  case R_MICROMIPS_LO16:
104
71
  case R_MICROMIPS_HIGHER:
105
71
  case R_MICROMIPS_HIGHEST:
106
71
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
107
71
    // offset between start of function and 'gp' value which by default
108
71
    // equal to the start of .got section. In that case we consider these
109
71
    // relocations as relative.
110
71
    if (&S == ElfSym::MipsGpDisp)
111
18
      return R_MIPS_GOT_GP_PC;
112
53
    if (&S == ElfSym::MipsLocalGp)
113
2
      return R_MIPS_GOT_GP;
114
51
    LLVM_FALLTHROUGH;
115
73
  case R_MIPS_32:
116
73
  case R_MIPS_64:
117
73
  case R_MIPS_GOT_OFST:
118
73
  case R_MIPS_SUB:
119
73
  case R_MIPS_TLS_DTPREL_HI16:
120
73
  case R_MIPS_TLS_DTPREL_LO16:
121
73
  case R_MIPS_TLS_DTPREL32:
122
73
  case R_MIPS_TLS_DTPREL64:
123
73
  case R_MIPS_TLS_TPREL_HI16:
124
73
  case R_MIPS_TLS_TPREL_LO16:
125
73
  case R_MIPS_TLS_TPREL32:
126
73
  case R_MIPS_TLS_TPREL64:
127
73
  case R_MICROMIPS_GOT_OFST:
128
73
  case R_MICROMIPS_SUB:
129
73
  case R_MICROMIPS_TLS_DTPREL_HI16:
130
73
  case R_MICROMIPS_TLS_DTPREL_LO16:
131
73
  case R_MICROMIPS_TLS_TPREL_HI16:
132
73
  case R_MICROMIPS_TLS_TPREL_LO16:
133
73
    return R_ABS;
134
73
  case R_MIPS_PC32:
135
13
  case R_MIPS_PC16:
136
13
  case R_MIPS_PC19_S2:
137
13
  case R_MIPS_PC21_S2:
138
13
  case R_MIPS_PC26_S2:
139
13
  case R_MIPS_PCHI16:
140
13
  case R_MIPS_PCLO16:
141
13
  case R_MICROMIPS_PC7_S1:
142
13
  case R_MICROMIPS_PC10_S1:
143
13
  case R_MICROMIPS_PC16_S1:
144
13
  case R_MICROMIPS_PC18_S3:
145
13
  case R_MICROMIPS_PC19_S2:
146
13
  case R_MICROMIPS_PC23_S2:
147
13
  case R_MICROMIPS_PC21_S1:
148
13
    return R_PC;
149
41
  case R_MIPS_GOT16:
150
41
  case R_MICROMIPS_GOT16:
151
41
    if (S.isLocal())
152
19
      return R_MIPS_GOT_LOCAL_PAGE;
153
22
    LLVM_FALLTHROUGH;
154
47
  case R_MIPS_CALL16:
155
47
  case R_MIPS_GOT_DISP:
156
47
  case R_MIPS_TLS_GOTTPREL:
157
47
  case R_MICROMIPS_CALL16:
158
47
  case R_MICROMIPS_GOT_DISP:
159
47
  case R_MICROMIPS_TLS_GOTTPREL:
160
47
    return R_MIPS_GOT_OFF;
161
47
  case R_MIPS_CALL_HI16:
162
16
  case R_MIPS_CALL_LO16:
163
16
  case R_MIPS_GOT_HI16:
164
16
  case R_MIPS_GOT_LO16:
165
16
  case R_MICROMIPS_CALL_HI16:
166
16
  case R_MICROMIPS_CALL_LO16:
167
16
  case R_MICROMIPS_GOT_HI16:
168
16
  case R_MICROMIPS_GOT_LO16:
169
16
    return R_MIPS_GOT_OFF32;
170
16
  case R_MIPS_GOT_PAGE:
171
0
  case R_MICROMIPS_GOT_PAGE:
172
0
    return R_MIPS_GOT_LOCAL_PAGE;
173
7
  case R_MIPS_TLS_GD:
174
7
  case R_MICROMIPS_TLS_GD:
175
7
    return R_MIPS_TLSGD;
176
7
  case R_MIPS_TLS_LDM:
177
4
  case R_MICROMIPS_TLS_LDM:
178
4
    return R_MIPS_TLSLD;
179
4
  case R_MIPS_NONE:
180
0
    return R_NONE;
181
4
  default:
182
0
    return R_INVALID;
183
272
  }
184
272
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getRelExpr(unsigned int, lld::elf::Symbol const&, unsigned char const*) const
Line
Count
Source
79
10.0k
                               const uint8_t *Loc) const {
80
10.0k
  // See comment in the calculateMipsRelChain.
81
10.0k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi0
)
82
10.0k
    Type &= 0xff;
83
10.0k
84
10.0k
  switch (Type) {
85
10.0k
  case R_MIPS_JALR:
86
0
  case R_MICROMIPS_JALR:
87
0
    return R_HINT;
88
12
  case R_MIPS_GPREL16:
89
12
  case R_MIPS_GPREL32:
90
12
  case R_MICROMIPS_GPREL16:
91
12
  case R_MICROMIPS_GPREL7_S2:
92
12
    return R_MIPS_GOTREL;
93
12
  case R_MIPS_26:
94
2
  case R_MICROMIPS_26_S1:
95
2
    return R_PLT;
96
2
  case R_MICROMIPS_PC26_S1:
97
0
    return R_PLT_PC;
98
4
  case R_MIPS_HI16:
99
4
  case R_MIPS_LO16:
100
4
  case R_MIPS_HIGHER:
101
4
  case R_MIPS_HIGHEST:
102
4
  case R_MICROMIPS_HI16:
103
4
  case R_MICROMIPS_LO16:
104
4
  case R_MICROMIPS_HIGHER:
105
4
  case R_MICROMIPS_HIGHEST:
106
4
    // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
107
4
    // offset between start of function and 'gp' value which by default
108
4
    // equal to the start of .got section. In that case we consider these
109
4
    // relocations as relative.
110
4
    if (&S == ElfSym::MipsGpDisp)
111
0
      return R_MIPS_GOT_GP_PC;
112
4
    if (&S == ElfSym::MipsLocalGp)
113
0
      return R_MIPS_GOT_GP;
114
4
    LLVM_FALLTHROUGH;
115
16
  case R_MIPS_32:
116
16
  case R_MIPS_64:
117
16
  case R_MIPS_GOT_OFST:
118
16
  case R_MIPS_SUB:
119
16
  case R_MIPS_TLS_DTPREL_HI16:
120
16
  case R_MIPS_TLS_DTPREL_LO16:
121
16
  case R_MIPS_TLS_DTPREL32:
122
16
  case R_MIPS_TLS_DTPREL64:
123
16
  case R_MIPS_TLS_TPREL_HI16:
124
16
  case R_MIPS_TLS_TPREL_LO16:
125
16
  case R_MIPS_TLS_TPREL32:
126
16
  case R_MIPS_TLS_TPREL64:
127
16
  case R_MICROMIPS_GOT_OFST:
128
16
  case R_MICROMIPS_SUB:
129
16
  case R_MICROMIPS_TLS_DTPREL_HI16:
130
16
  case R_MICROMIPS_TLS_DTPREL_LO16:
131
16
  case R_MICROMIPS_TLS_TPREL_HI16:
132
16
  case R_MICROMIPS_TLS_TPREL_LO16:
133
16
    return R_ABS;
134
16
  case R_MIPS_PC32:
135
1
  case R_MIPS_PC16:
136
1
  case R_MIPS_PC19_S2:
137
1
  case R_MIPS_PC21_S2:
138
1
  case R_MIPS_PC26_S2:
139
1
  case R_MIPS_PCHI16:
140
1
  case R_MIPS_PCLO16:
141
1
  case R_MICROMIPS_PC7_S1:
142
1
  case R_MICROMIPS_PC10_S1:
143
1
  case R_MICROMIPS_PC16_S1:
144
1
  case R_MICROMIPS_PC18_S3:
145
1
  case R_MICROMIPS_PC19_S2:
146
1
  case R_MICROMIPS_PC23_S2:
147
1
  case R_MICROMIPS_PC21_S1:
148
1
    return R_PC;
149
1
  case R_MIPS_GOT16:
150
0
  case R_MICROMIPS_GOT16:
151
0
    if (S.isLocal())
152
0
      return R_MIPS_GOT_LOCAL_PAGE;
153
0
    LLVM_FALLTHROUGH;
154
10.0k
  case R_MIPS_CALL16:
155
10.0k
  case R_MIPS_GOT_DISP:
156
10.0k
  case R_MIPS_TLS_GOTTPREL:
157
10.0k
  case R_MICROMIPS_CALL16:
158
10.0k
  case R_MICROMIPS_GOT_DISP:
159
10.0k
  case R_MICROMIPS_TLS_GOTTPREL:
160
10.0k
    return R_MIPS_GOT_OFF;
161
10.0k
  case R_MIPS_CALL_HI16:
162
0
  case R_MIPS_CALL_LO16:
163
0
  case R_MIPS_GOT_HI16:
164
0
  case R_MIPS_GOT_LO16:
165
0
  case R_MICROMIPS_CALL_HI16:
166
0
  case R_MICROMIPS_CALL_LO16:
167
0
  case R_MICROMIPS_GOT_HI16:
168
0
  case R_MICROMIPS_GOT_LO16:
169
0
    return R_MIPS_GOT_OFF32;
170
12
  case R_MIPS_GOT_PAGE:
171
12
  case R_MICROMIPS_GOT_PAGE:
172
12
    return R_MIPS_GOT_LOCAL_PAGE;
173
12
  case R_MIPS_TLS_GD:
174
5
  case R_MICROMIPS_TLS_GD:
175
5
    return R_MIPS_TLSGD;
176
5
  case R_MIPS_TLS_LDM:
177
2
  case R_MICROMIPS_TLS_LDM:
178
2
    return R_MIPS_TLSLD;
179
2
  case R_MIPS_NONE:
180
0
    return R_NONE;
181
2
  default:
182
0
    return R_INVALID;
183
10.0k
  }
184
10.0k
}
185
186
4
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
187
4
  if (Type == R_MIPS_32 || 
Type == R_MIPS_642
)
188
4
    return RelativeRel;
189
0
  return R_MIPS_NONE;
190
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getDynRel(unsigned int) const
Line
Count
Source
186
1
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
187
1
  if (Type == R_MIPS_32 || 
Type == R_MIPS_640
)
188
1
    return RelativeRel;
189
0
  return R_MIPS_NONE;
190
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getDynRel(unsigned int) const
Line
Count
Source
186
1
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
187
1
  if (Type == R_MIPS_32 || 
Type == R_MIPS_640
)
188
1
    return RelativeRel;
189
0
  return R_MIPS_NONE;
190
0
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::getDynRel(unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::getDynRel(unsigned int) const
Line
Count
Source
186
2
template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
187
2
  if (Type == R_MIPS_32 || Type == R_MIPS_64)
188
2
    return RelativeRel;
189
0
  return R_MIPS_NONE;
190
0
}
191
192
template <class ELFT>
193
17
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
194
17
  uint64_t VA = InX::Plt->getVA();
195
17
  if (isMicroMips())
196
6
    VA |= 1;
197
17
  write32<ELFT::TargetEndianness>(Buf, VA);
198
17
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Line
Count
Source
193
2
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
194
2
  uint64_t VA = InX::Plt->getVA();
195
2
  if (isMicroMips())
196
2
    VA |= 1;
197
2
  write32<ELFT::TargetEndianness>(Buf, VA);
198
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Line
Count
Source
193
13
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
194
13
  uint64_t VA = InX::Plt->getVA();
195
13
  if (isMicroMips())
196
4
    VA |= 1;
197
13
  write32<ELFT::TargetEndianness>(Buf, VA);
198
13
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writeGotPlt(unsigned char*, lld::elf::Symbol const&) const
Line
Count
Source
193
2
void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
194
2
  uint64_t VA = InX::Plt->getVA();
195
2
  if (isMicroMips())
196
0
    VA |= 1;
197
2
  write32<ELFT::TargetEndianness>(Buf, VA);
198
2
}
199
200
34
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
201
34
  // The major opcode of a microMIPS instruction needs to appear
202
34
  // in the first 16-bit word (lowest address) for efficient hardware
203
34
  // decode so that it knows if the instruction is 16-bit or 32-bit
204
34
  // as early as possible. To do so, little-endian binaries keep 16-bit
205
34
  // words in a big-endian order. That is why we have to swap these
206
34
  // words to get a correct value.
207
34
  uint32_t V = read32<E>(Loc);
208
34
  if (E == support::little)
209
12
    return (V << 16) | (V >> 16);
210
22
  return V;
211
22
}
Mips.cpp:unsigned int readShuffle<(llvm::support::endianness)1>(unsigned char const*)
Line
Count
Source
200
12
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
201
12
  // The major opcode of a microMIPS instruction needs to appear
202
12
  // in the first 16-bit word (lowest address) for efficient hardware
203
12
  // decode so that it knows if the instruction is 16-bit or 32-bit
204
12
  // as early as possible. To do so, little-endian binaries keep 16-bit
205
12
  // words in a big-endian order. That is why we have to swap these
206
12
  // words to get a correct value.
207
12
  uint32_t V = read32<E>(Loc);
208
12
  if (E == support::little)
209
12
    return (V << 16) | (V >> 16);
210
0
  return V;
211
0
}
Mips.cpp:unsigned int readShuffle<(llvm::support::endianness)0>(unsigned char const*)
Line
Count
Source
200
22
template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) {
201
22
  // The major opcode of a microMIPS instruction needs to appear
202
22
  // in the first 16-bit word (lowest address) for efficient hardware
203
22
  // decode so that it knows if the instruction is 16-bit or 32-bit
204
22
  // as early as possible. To do so, little-endian binaries keep 16-bit
205
22
  // words in a big-endian order. That is why we have to swap these
206
22
  // words to get a correct value.
207
22
  uint32_t V = read32<E>(Loc);
208
22
  if (E == support::little)
209
0
    return (V << 16) | (V >> 16);
210
22
  return V;
211
22
}
212
213
template <endianness E>
214
static void writeValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
215
10.4k
                       uint8_t Shift) {
216
10.4k
  uint32_t Instr = read32<E>(Loc);
217
10.4k
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
218
10.4k
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
219
10.4k
  write32<E>(Loc, Data);
220
10.4k
}
Mips.cpp:void writeValue<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
215
26
                       uint8_t Shift) {
216
26
  uint32_t Instr = read32<E>(Loc);
217
26
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
218
26
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
219
26
  write32<E>(Loc, Data);
220
26
}
Mips.cpp:void writeValue<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
215
10.4k
                       uint8_t Shift) {
216
10.4k
  uint32_t Instr = read32<E>(Loc);
217
10.4k
  uint32_t Mask = 0xffffffff >> (32 - BitsSize);
218
10.4k
  uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
219
10.4k
  write32<E>(Loc, Data);
220
10.4k
}
221
222
template <endianness E>
223
static void writeShuffleValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
224
57
                              uint8_t Shift) {
225
57
  // See comments in readShuffle for purpose of this code.
226
57
  uint16_t *Words = (uint16_t *)Loc;
227
57
  if (E == support::little)
228
22
    std::swap(Words[0], Words[1]);
229
57
230
57
  writeValue<E>(Loc, V, BitsSize, Shift);
231
57
232
57
  if (E == support::little)
233
22
    std::swap(Words[0], Words[1]);
234
57
}
Mips.cpp:void writeShuffleValue<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
224
22
                              uint8_t Shift) {
225
22
  // See comments in readShuffle for purpose of this code.
226
22
  uint16_t *Words = (uint16_t *)Loc;
227
22
  if (E == support::little)
228
22
    std::swap(Words[0], Words[1]);
229
22
230
22
  writeValue<E>(Loc, V, BitsSize, Shift);
231
22
232
22
  if (E == support::little)
233
22
    std::swap(Words[0], Words[1]);
234
22
}
Mips.cpp:void writeShuffleValue<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
224
35
                              uint8_t Shift) {
225
35
  // See comments in readShuffle for purpose of this code.
226
35
  uint16_t *Words = (uint16_t *)Loc;
227
35
  if (E == support::little)
228
0
    std::swap(Words[0], Words[1]);
229
35
230
35
  writeValue<E>(Loc, V, BitsSize, Shift);
231
35
232
35
  if (E == support::little)
233
0
    std::swap(Words[0], Words[1]);
234
35
}
235
236
template <endianness E>
237
static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
238
4
                                   uint8_t Shift) {
239
4
  uint16_t Instr = read16<E>(Loc);
240
4
  uint16_t Mask = 0xffff >> (16 - BitsSize);
241
4
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
242
4
  write16<E>(Loc, Data);
243
4
}
Mips.cpp:void writeMicroRelocation16<(llvm::support::endianness)1>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
238
2
                                   uint8_t Shift) {
239
2
  uint16_t Instr = read16<E>(Loc);
240
2
  uint16_t Mask = 0xffff >> (16 - BitsSize);
241
2
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
242
2
  write16<E>(Loc, Data);
243
2
}
Mips.cpp:void writeMicroRelocation16<(llvm::support::endianness)0>(unsigned char*, unsigned long long, unsigned char, unsigned char)
Line
Count
Source
238
2
                                   uint8_t Shift) {
239
2
  uint16_t Instr = read16<E>(Loc);
240
2
  uint16_t Mask = 0xffff >> (16 - BitsSize);
241
2
  uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask);
242
2
  write16<E>(Loc, Data);
243
2
}
244
245
15
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
246
15
  const endianness E = ELFT::TargetEndianness;
247
15
  if (isMicroMips()) {
248
6
    uint64_t GotPlt = InX::GotPlt->getVA();
249
6
    uint64_t Plt = InX::Plt->getVA();
250
6
    // Overwrite trap instructions written by Writer::writeTrapInstr.
251
6
    memset(Buf, 0, PltHeaderSize);
252
6
253
6
    write16<E>(Buf, isMipsR6() ? 
0x78602
:
0x79804
); // addiupc v1, (GOTPLT) - .
254
6
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
255
6
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
256
6
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
257
6
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
258
6
    write16<E>(Buf + 14, 0xfffe);
259
6
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
260
6
    if (isMipsR6()) {
261
2
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
262
2
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
263
2
      write16<E>(Buf + 22, 0x0c00); // nop
264
2
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
265
4
    } else {
266
4
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
267
4
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
268
4
      write16<E>(Buf + 22, 0x0c00); // nop
269
4
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
270
4
    }
271
6
    return;
272
6
  }
273
9
274
9
  if (Config->MipsN32Abi) {
275
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
276
2
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
277
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
278
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
279
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
280
2
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
281
7
  } else if (ELFT::Is64Bits) {
282
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
283
2
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
284
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
285
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
286
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
287
2
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
288
5
  } else {
289
5
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
290
5
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
291
5
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
292
5
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
293
5
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
294
5
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
295
5
  }
296
9
297
9
  uint32_t JalrInst = Config->ZHazardplt ? 
0x0320fc093
:
0x0320f8096
;
298
9
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
299
9
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
300
9
301
9
  uint64_t GotPlt = InX::GotPlt->getVA();
302
9
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
303
9
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
304
9
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
305
9
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writePltHeader(unsigned char*) const
Line
Count
Source
245
2
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
246
2
  const endianness E = ELFT::TargetEndianness;
247
2
  if (isMicroMips()) {
248
2
    uint64_t GotPlt = InX::GotPlt->getVA();
249
2
    uint64_t Plt = InX::Plt->getVA();
250
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
251
2
    memset(Buf, 0, PltHeaderSize);
252
2
253
2
    write16<E>(Buf, isMipsR6() ? 
0x78601
:
0x79801
); // addiupc v1, (GOTPLT) - .
254
2
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
255
2
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
256
2
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
257
2
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
258
2
    write16<E>(Buf + 14, 0xfffe);
259
2
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
260
2
    if (isMipsR6()) {
261
1
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
262
1
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
263
1
      write16<E>(Buf + 22, 0x0c00); // nop
264
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
265
1
    } else {
266
1
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
267
1
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
268
1
      write16<E>(Buf + 22, 0x0c00); // nop
269
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
270
1
    }
271
2
    return;
272
2
  }
273
0
274
0
  if (Config->MipsN32Abi) {
275
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
276
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
277
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
278
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
279
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
280
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
281
0
  } else if (ELFT::Is64Bits) {
282
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
283
0
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
284
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
285
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
286
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
287
0
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
288
0
  } else {
289
0
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
290
0
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
291
0
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
292
0
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
293
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
294
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
295
0
  }
296
0
297
0
  uint32_t JalrInst = Config->ZHazardplt ? 0x0320fc09 : 0x0320f809;
298
0
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
299
0
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
300
0
301
0
  uint64_t GotPlt = InX::GotPlt->getVA();
302
0
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
303
0
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
304
0
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
305
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writePltHeader(unsigned char*) const
Line
Count
Source
245
11
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
246
11
  const endianness E = ELFT::TargetEndianness;
247
11
  if (isMicroMips()) {
248
4
    uint64_t GotPlt = InX::GotPlt->getVA();
249
4
    uint64_t Plt = InX::Plt->getVA();
250
4
    // Overwrite trap instructions written by Writer::writeTrapInstr.
251
4
    memset(Buf, 0, PltHeaderSize);
252
4
253
4
    write16<E>(Buf, isMipsR6() ? 
0x78601
:
0x79803
); // addiupc v1, (GOTPLT) - .
254
4
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
255
4
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
256
4
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
257
4
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
258
4
    write16<E>(Buf + 14, 0xfffe);
259
4
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
260
4
    if (isMipsR6()) {
261
1
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
262
1
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
263
1
      write16<E>(Buf + 22, 0x0c00); // nop
264
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
265
3
    } else {
266
3
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
267
3
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
268
3
      write16<E>(Buf + 22, 0x0c00); // nop
269
3
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
270
3
    }
271
4
    return;
272
4
  }
273
7
274
7
  if (Config->MipsN32Abi) {
275
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
276
2
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
277
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
278
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
279
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
280
2
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
281
5
  } else if (ELFT::Is64Bits) {
282
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
283
0
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
284
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
285
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
286
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
287
0
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
288
5
  } else {
289
5
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
290
5
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
291
5
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
292
5
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
293
5
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
294
5
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
295
5
  }
296
7
297
7
  uint32_t JalrInst = Config->ZHazardplt ? 
0x0320fc092
:
0x0320f8095
;
298
7
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
299
7
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
300
7
301
7
  uint64_t GotPlt = InX::GotPlt->getVA();
302
7
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
303
7
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
304
7
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
305
7
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writePltHeader(unsigned char*) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writePltHeader(unsigned char*) const
Line
Count
Source
245
2
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
246
2
  const endianness E = ELFT::TargetEndianness;
247
2
  if (isMicroMips()) {
248
0
    uint64_t GotPlt = InX::GotPlt->getVA();
249
0
    uint64_t Plt = InX::Plt->getVA();
250
0
    // Overwrite trap instructions written by Writer::writeTrapInstr.
251
0
    memset(Buf, 0, PltHeaderSize);
252
0
253
0
    write16<E>(Buf, isMipsR6() ? 0x7860 : 0x7980);  // addiupc v1, (GOTPLT) - .
254
0
    write16<E>(Buf + 4, 0xff23);    // lw      $25, 0($3)
255
0
    write16<E>(Buf + 8, 0x0535);    // subu16  $2,  $2, $3
256
0
    write16<E>(Buf + 10, 0x2525);   // srl16   $2,  $2, 2
257
0
    write16<E>(Buf + 12, 0x3302);   // addiu   $24, $2, -2
258
0
    write16<E>(Buf + 14, 0xfffe);
259
0
    write16<E>(Buf + 16, 0x0dff);   // move    $15, $31
260
0
    if (isMipsR6()) {
261
0
      write16<E>(Buf + 18, 0x0f83); // move    $28, $3
262
0
      write16<E>(Buf + 20, 0x472b); // jalrc   $25
263
0
      write16<E>(Buf + 22, 0x0c00); // nop
264
0
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt);
265
0
    } else {
266
0
      write16<E>(Buf + 18, 0x45f9); // jalrc   $25
267
0
      write16<E>(Buf + 20, 0x0f83); // move    $28, $3
268
0
      write16<E>(Buf + 22, 0x0c00); // nop
269
0
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt);
270
0
    }
271
0
    return;
272
0
  }
273
2
274
2
  if (Config->MipsN32Abi) {
275
0
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
276
0
    write32<E>(Buf + 4, 0x8dd90000);  // lw    $25, %lo(&GOTPLT[0])($14)
277
0
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
278
0
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
279
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
280
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
281
2
  } else if (ELFT::Is64Bits) {
282
2
    write32<E>(Buf, 0x3c0e0000);      // lui   $14, %hi(&GOTPLT[0])
283
2
    write32<E>(Buf + 4, 0xddd90000);  // ld    $25, %lo(&GOTPLT[0])($14)
284
2
    write32<E>(Buf + 8, 0x25ce0000);  // addiu $14, $14, %lo(&GOTPLT[0])
285
2
    write32<E>(Buf + 12, 0x030ec023); // subu  $24, $24, $14
286
2
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
287
2
    write32<E>(Buf + 20, 0x0018c0c2); // srl   $24, $24, 3
288
2
  } else {
289
0
    write32<E>(Buf, 0x3c1c0000);      // lui   $28, %hi(&GOTPLT[0])
290
0
    write32<E>(Buf + 4, 0x8f990000);  // lw    $25, %lo(&GOTPLT[0])($28)
291
0
    write32<E>(Buf + 8, 0x279c0000);  // addiu $28, $28, %lo(&GOTPLT[0])
292
0
    write32<E>(Buf + 12, 0x031cc023); // subu  $24, $24, $28
293
0
    write32<E>(Buf + 16, 0x03e07825); // move  $15, $31
294
0
    write32<E>(Buf + 20, 0x0018c082); // srl   $24, $24, 2
295
0
  }
296
2
297
2
  uint32_t JalrInst = Config->ZHazardplt ? 
0x0320fc091
:
0x0320f8091
;
298
2
  write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
299
2
  write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
300
2
301
2
  uint64_t GotPlt = InX::GotPlt->getVA();
302
2
  writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
303
2
  writeValue<E>(Buf + 4, GotPlt, 16, 0);
304
2
  writeValue<E>(Buf + 8, GotPlt, 16, 0);
305
2
}
306
307
template <class ELFT>
308
void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
309
                          uint64_t PltEntryAddr, int32_t Index,
310
17
                          unsigned RelOff) const {
311
17
  const endianness E = ELFT::TargetEndianness;
312
17
  if (isMicroMips()) {
313
6
    // Overwrite trap instructions written by Writer::writeTrapInstr.
314
6
    memset(Buf, 0, PltEntrySize);
315
6
316
6
    if (isMipsR6()) {
317
2
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
318
2
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
319
2
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
320
2
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
321
2
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
322
4
    } else {
323
4
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
324
4
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
325
4
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
326
4
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
327
4
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
328
4
    }
329
6
    return;
330
6
  }
331
11
332
11
  uint32_t JrInst = isMipsR6() ? 
(Config->ZHazardplt 2
?
0x032004091
:
0x032000091
)
333
11
                               : 
(Config->ZHazardplt 9
?
0x032004082
:
0x032000087
);
334
11
335
11
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
336
11
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
337
11
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
338
11
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
339
11
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
340
11
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
341
11
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
342
11
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
310
2
                          unsigned RelOff) const {
311
2
  const endianness E = ELFT::TargetEndianness;
312
2
  if (isMicroMips()) {
313
2
    // Overwrite trap instructions written by Writer::writeTrapInstr.
314
2
    memset(Buf, 0, PltEntrySize);
315
2
316
2
    if (isMipsR6()) {
317
1
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
318
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
319
1
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
320
1
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
321
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
322
1
    } else {
323
1
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
324
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
325
1
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
326
1
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
327
1
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
328
1
    }
329
2
    return;
330
2
  }
331
0
332
0
  uint32_t JrInst = isMipsR6() ? (Config->ZHazardplt ? 0x03200409 : 0x03200009)
333
0
                               : (Config->ZHazardplt ? 0x03200408 : 0x03200008);
334
0
335
0
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
336
0
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
337
0
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
338
0
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
339
0
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
340
0
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
341
0
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
342
0
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
310
13
                          unsigned RelOff) const {
311
13
  const endianness E = ELFT::TargetEndianness;
312
13
  if (isMicroMips()) {
313
4
    // Overwrite trap instructions written by Writer::writeTrapInstr.
314
4
    memset(Buf, 0, PltEntrySize);
315
4
316
4
    if (isMipsR6()) {
317
1
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
318
1
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
319
1
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
320
1
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
321
1
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
322
3
    } else {
323
3
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
324
3
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
325
3
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
326
3
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
327
3
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
328
3
    }
329
4
    return;
330
4
  }
331
9
332
9
  uint32_t JrInst = isMipsR6() ? 
(Config->ZHazardplt 2
?
0x032004091
:
0x032000091
)
333
9
                               : 
(Config->ZHazardplt 7
?
0x032004081
:
0x032000086
);
334
9
335
9
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
336
9
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
337
9
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
338
9
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
339
9
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
340
9
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
341
9
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
342
9
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::writePlt(unsigned char*, unsigned long long, unsigned long long, int, unsigned int) const
Line
Count
Source
310
2
                          unsigned RelOff) const {
311
2
  const endianness E = ELFT::TargetEndianness;
312
2
  if (isMicroMips()) {
313
0
    // Overwrite trap instructions written by Writer::writeTrapInstr.
314
0
    memset(Buf, 0, PltEntrySize);
315
0
316
0
    if (isMipsR6()) {
317
0
      write16<E>(Buf, 0x7840);      // addiupc $2, (GOTPLT) - .
318
0
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
319
0
      write16<E>(Buf + 8, 0x0f02);  // move $24, $2
320
0
      write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25
321
0
      relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr);
322
0
    } else {
323
0
      write16<E>(Buf, 0x7900);      // addiupc $2, (GOTPLT) - .
324
0
      write16<E>(Buf + 4, 0xff22);  // lw $25, 0($2)
325
0
      write16<E>(Buf + 8, 0x4599);  // jrc $25 / jr16 $25
326
0
      write16<E>(Buf + 10, 0x0f02); // move $24, $2
327
0
      relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr);
328
0
    }
329
0
    return;
330
0
  }
331
2
332
2
  uint32_t JrInst = isMipsR6() ? 
(Config->ZHazardplt 0
?
0x032004090
:
0x032000090
)
333
2
                               : (Config->ZHazardplt ? 
0x032004081
:
0x032000081
);
334
2
335
2
  write32<E>(Buf, 0x3c0f0000);     // lui   $15, %hi(.got.plt entry)
336
2
  write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
337
2
  write32<E>(Buf + 8, JrInst);     // jr  $25 / jr.hb $25
338
2
  write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
339
2
  writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16);
340
2
  writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0);
341
2
  writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0);
342
2
}
343
344
template <class ELFT>
345
bool MIPS<ELFT>::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
346
10.3k
                            uint64_t BranchAddr, const Symbol &S) const {
347
10.3k
  // Any MIPS PIC code function is invoked with its address in register $t9.
348
10.3k
  // So if we have a branch instruction from non-PIC code to the PIC one
349
10.3k
  // we cannot make the jump directly and need to create a small stubs
350
10.3k
  // to save the target function address.
351
10.3k
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
352
10.3k
  if (Type != R_MIPS_26 && 
Type != R_MICROMIPS_26_S110.2k
&&
353
10.3k
      
Type != R_MICROMIPS_PC26_S110.2k
)
354
10.2k
    return false;
355
73
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
356
73
  if (!F)
357
0
    return false;
358
73
  // If current file has PIC code, LA25 stub is not required.
359
73
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
360
0
    return false;
361
73
  auto *D = dyn_cast<Defined>(&S);
362
73
  // LA25 is required if target file has PIC code
363
73
  // or target symbol is a PIC symbol.
364
73
  return D && 
isMipsPIC<ELFT>(D)60
;
365
73
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Line
Count
Source
346
18
                            uint64_t BranchAddr, const Symbol &S) const {
347
18
  // Any MIPS PIC code function is invoked with its address in register $t9.
348
18
  // So if we have a branch instruction from non-PIC code to the PIC one
349
18
  // we cannot make the jump directly and need to create a small stubs
350
18
  // to save the target function address.
351
18
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
352
18
  if (Type != R_MIPS_26 && Type != R_MICROMIPS_26_S1 &&
353
18
      
Type != R_MICROMIPS_PC26_S116
)
354
13
    return false;
355
5
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
356
5
  if (!F)
357
0
    return false;
358
5
  // If current file has PIC code, LA25 stub is not required.
359
5
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
360
0
    return false;
361
5
  auto *D = dyn_cast<Defined>(&S);
362
5
  // LA25 is required if target file has PIC code
363
5
  // or target symbol is a PIC symbol.
364
5
  return D && 
isMipsPIC<ELFT>(D)3
;
365
5
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Line
Count
Source
346
248
                            uint64_t BranchAddr, const Symbol &S) const {
347
248
  // Any MIPS PIC code function is invoked with its address in register $t9.
348
248
  // So if we have a branch instruction from non-PIC code to the PIC one
349
248
  // we cannot make the jump directly and need to create a small stubs
350
248
  // to save the target function address.
351
248
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
352
248
  if (Type != R_MIPS_26 && 
Type != R_MICROMIPS_26_S1189
&&
353
248
      
Type != R_MICROMIPS_PC26_S1185
)
354
182
    return false;
355
66
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
356
66
  if (!F)
357
0
    return false;
358
66
  // If current file has PIC code, LA25 stub is not required.
359
66
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
360
0
    return false;
361
66
  auto *D = dyn_cast<Defined>(&S);
362
66
  // LA25 is required if target file has PIC code
363
66
  // or target symbol is a PIC symbol.
364
66
  return D && 
isMipsPIC<ELFT>(D)57
;
365
66
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::needsThunk(lld::elf::RelExpr, unsigned int, lld::elf::InputFile const*, unsigned long long, lld::elf::Symbol const&) const
Line
Count
Source
346
10.0k
                            uint64_t BranchAddr, const Symbol &S) const {
347
10.0k
  // Any MIPS PIC code function is invoked with its address in register $t9.
348
10.0k
  // So if we have a branch instruction from non-PIC code to the PIC one
349
10.0k
  // we cannot make the jump directly and need to create a small stubs
350
10.0k
  // to save the target function address.
351
10.0k
  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
352
10.0k
  if (Type != R_MIPS_26 && 
Type != R_MICROMIPS_26_S110.0k
&&
353
10.0k
      
Type != R_MICROMIPS_PC26_S110.0k
)
354
10.0k
    return false;
355
2
  auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
356
2
  if (!F)
357
0
    return false;
358
2
  // If current file has PIC code, LA25 stub is not required.
359
2
  if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
360
0
    return false;
361
2
  auto *D = dyn_cast<Defined>(&S);
362
2
  // LA25 is required if target file has PIC code
363
2
  // or target symbol is a PIC symbol.
364
2
  return D && 
isMipsPIC<ELFT>(D)0
;
365
2
}
366
367
template <class ELFT>
368
330
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
369
330
  const endianness E = ELFT::TargetEndianness;
370
330
  switch (Type) {
371
330
  case R_MIPS_32:
372
27
  case R_MIPS_GPREL32:
373
27
  case R_MIPS_TLS_DTPREL32:
374
27
  case R_MIPS_TLS_TPREL32:
375
27
    return SignExtend64<32>(read32<E>(Buf));
376
50
  case R_MIPS_26:
377
50
    // FIXME (simon): If the relocation target symbol is not a PLT entry
378
50
    // we should use another expression for calculation:
379
50
    // ((A << 2) | (P & 0xf0000000)) >> 2
380
50
    return SignExtend64<28>(read32<E>(Buf) << 2);
381
66
  case R_MIPS_GOT16:
382
66
  case R_MIPS_HI16:
383
66
  case R_MIPS_PCHI16:
384
66
    return SignExtend64<16>(read32<E>(Buf)) << 16;
385
90
  case R_MIPS_GPREL16:
386
90
  case R_MIPS_LO16:
387
90
  case R_MIPS_PCLO16:
388
90
  case R_MIPS_TLS_DTPREL_HI16:
389
90
  case R_MIPS_TLS_DTPREL_LO16:
390
90
  case R_MIPS_TLS_TPREL_HI16:
391
90
  case R_MIPS_TLS_TPREL_LO16:
392
90
    return SignExtend64<16>(read32<E>(Buf));
393
90
  case R_MICROMIPS_GOT16:
394
7
  case R_MICROMIPS_HI16:
395
7
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
396
9
  case R_MICROMIPS_GPREL16:
397
9
  case R_MICROMIPS_LO16:
398
9
  case R_MICROMIPS_TLS_DTPREL_HI16:
399
9
  case R_MICROMIPS_TLS_DTPREL_LO16:
400
9
  case R_MICROMIPS_TLS_TPREL_HI16:
401
9
  case R_MICROMIPS_TLS_TPREL_LO16:
402
9
    return SignExtend64<16>(readShuffle<E>(Buf));
403
9
  case R_MICROMIPS_GPREL7_S2:
404
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
405
9
  case R_MIPS_PC16:
406
2
    return SignExtend64<18>(read32<E>(Buf) << 2);
407
9
  case R_MIPS_PC19_S2:
408
1
    return SignExtend64<21>(read32<E>(Buf) << 2);
409
9
  case R_MIPS_PC21_S2:
410
1
    return SignExtend64<23>(read32<E>(Buf) << 2);
411
9
  case R_MIPS_PC26_S2:
412
1
    return SignExtend64<28>(read32<E>(Buf) << 2);
413
9
  case R_MIPS_PC32:
414
1
    return SignExtend64<32>(read32<E>(Buf));
415
9
  case R_MICROMIPS_26_S1:
416
6
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
417
9
  case R_MICROMIPS_PC7_S1:
418
2
    return SignExtend64<8>(read16<E>(Buf) << 1);
419
9
  case R_MICROMIPS_PC10_S1:
420
2
    return SignExtend64<11>(read16<E>(Buf) << 1);
421
9
  case R_MICROMIPS_PC16_S1:
422
2
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
423
9
  case R_MICROMIPS_PC18_S3:
424
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
425
9
  case R_MICROMIPS_PC19_S2:
426
2
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
427
9
  case R_MICROMIPS_PC21_S1:
428
2
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
429
9
  case R_MICROMIPS_PC23_S2:
430
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
431
9
  case R_MICROMIPS_PC26_S1:
432
6
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
433
53
  default:
434
53
    return 0;
435
330
  }
436
330
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::getImplicitAddend(unsigned char const*, unsigned int) const
Line
Count
Source
368
21
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
369
21
  const endianness E = ELFT::TargetEndianness;
370
21
  switch (Type) {
371
21
  case R_MIPS_32:
372
2
  case R_MIPS_GPREL32:
373
2
  case R_MIPS_TLS_DTPREL32:
374
2
  case R_MIPS_TLS_TPREL32:
375
2
    return SignExtend64<32>(read32<E>(Buf));
376
2
  case R_MIPS_26:
377
0
    // FIXME (simon): If the relocation target symbol is not a PLT entry
378
0
    // we should use another expression for calculation:
379
0
    // ((A << 2) | (P & 0xf0000000)) >> 2
380
0
    return SignExtend64<28>(read32<E>(Buf) << 2);
381
4
  case R_MIPS_GOT16:
382
4
  case R_MIPS_HI16:
383
4
  case R_MIPS_PCHI16:
384
4
    return SignExtend64<16>(read32<E>(Buf)) << 16;
385
4
  case R_MIPS_GPREL16:
386
0
  case R_MIPS_LO16:
387
0
  case R_MIPS_PCLO16:
388
0
  case R_MIPS_TLS_DTPREL_HI16:
389
0
  case R_MIPS_TLS_DTPREL_LO16:
390
0
  case R_MIPS_TLS_TPREL_HI16:
391
0
  case R_MIPS_TLS_TPREL_LO16:
392
0
    return SignExtend64<16>(read32<E>(Buf));
393
2
  case R_MICROMIPS_GOT16:
394
2
  case R_MICROMIPS_HI16:
395
2
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
396
2
  case R_MICROMIPS_GPREL16:
397
2
  case R_MICROMIPS_LO16:
398
2
  case R_MICROMIPS_TLS_DTPREL_HI16:
399
2
  case R_MICROMIPS_TLS_DTPREL_LO16:
400
2
  case R_MICROMIPS_TLS_TPREL_HI16:
401
2
  case R_MICROMIPS_TLS_TPREL_LO16:
402
2
    return SignExtend64<16>(readShuffle<E>(Buf));
403
2
  case R_MICROMIPS_GPREL7_S2:
404
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
405
2
  case R_MIPS_PC16:
406
0
    return SignExtend64<18>(read32<E>(Buf) << 2);
407
2
  case R_MIPS_PC19_S2:
408
0
    return SignExtend64<21>(read32<E>(Buf) << 2);
409
2
  case R_MIPS_PC21_S2:
410
0
    return SignExtend64<23>(read32<E>(Buf) << 2);
411
2
  case R_MIPS_PC26_S2:
412
0
    return SignExtend64<28>(read32<E>(Buf) << 2);
413
2
  case R_MIPS_PC32:
414
0
    return SignExtend64<32>(read32<E>(Buf));
415
2
  case R_MICROMIPS_26_S1:
416
2
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
417
2
  case R_MICROMIPS_PC7_S1:
418
1
    return SignExtend64<8>(read16<E>(Buf) << 1);
419
2
  case R_MICROMIPS_PC10_S1:
420
1
    return SignExtend64<11>(read16<E>(Buf) << 1);
421
2
  case R_MICROMIPS_PC16_S1:
422
1
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
423
2
  case R_MICROMIPS_PC18_S3:
424
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
425
2
  case R_MICROMIPS_PC19_S2:
426
1
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
427
2
  case R_MICROMIPS_PC21_S1:
428
1
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
429
2
  case R_MICROMIPS_PC23_S2:
430
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
431
3
  case R_MICROMIPS_PC26_S1:
432
3
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
433
2
  default:
434
1
    return 0;
435
21
  }
436
21
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::getImplicitAddend(unsigned char const*, unsigned int) const
Line
Count
Source
368
309
int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
369
309
  const endianness E = ELFT::TargetEndianness;
370
309
  switch (Type) {
371
309
  case R_MIPS_32:
372
25
  case R_MIPS_GPREL32:
373
25
  case R_MIPS_TLS_DTPREL32:
374
25
  case R_MIPS_TLS_TPREL32:
375
25
    return SignExtend64<32>(read32<E>(Buf));
376
50
  case R_MIPS_26:
377
50
    // FIXME (simon): If the relocation target symbol is not a PLT entry
378
50
    // we should use another expression for calculation:
379
50
    // ((A << 2) | (P & 0xf0000000)) >> 2
380
50
    return SignExtend64<28>(read32<E>(Buf) << 2);
381
62
  case R_MIPS_GOT16:
382
62
  case R_MIPS_HI16:
383
62
  case R_MIPS_PCHI16:
384
62
    return SignExtend64<16>(read32<E>(Buf)) << 16;
385
90
  case R_MIPS_GPREL16:
386
90
  case R_MIPS_LO16:
387
90
  case R_MIPS_PCLO16:
388
90
  case R_MIPS_TLS_DTPREL_HI16:
389
90
  case R_MIPS_TLS_DTPREL_LO16:
390
90
  case R_MIPS_TLS_TPREL_HI16:
391
90
  case R_MIPS_TLS_TPREL_LO16:
392
90
    return SignExtend64<16>(read32<E>(Buf));
393
90
  case R_MICROMIPS_GOT16:
394
5
  case R_MICROMIPS_HI16:
395
5
    return SignExtend64<16>(readShuffle<E>(Buf)) << 16;
396
7
  case R_MICROMIPS_GPREL16:
397
7
  case R_MICROMIPS_LO16:
398
7
  case R_MICROMIPS_TLS_DTPREL_HI16:
399
7
  case R_MICROMIPS_TLS_DTPREL_LO16:
400
7
  case R_MICROMIPS_TLS_TPREL_HI16:
401
7
  case R_MICROMIPS_TLS_TPREL_LO16:
402
7
    return SignExtend64<16>(readShuffle<E>(Buf));
403
7
  case R_MICROMIPS_GPREL7_S2:
404
0
    return SignExtend64<9>(readShuffle<E>(Buf) << 2);
405
7
  case R_MIPS_PC16:
406
2
    return SignExtend64<18>(read32<E>(Buf) << 2);
407
7
  case R_MIPS_PC19_S2:
408
1
    return SignExtend64<21>(read32<E>(Buf) << 2);
409
7
  case R_MIPS_PC21_S2:
410
1
    return SignExtend64<23>(read32<E>(Buf) << 2);
411
7
  case R_MIPS_PC26_S2:
412
1
    return SignExtend64<28>(read32<E>(Buf) << 2);
413
7
  case R_MIPS_PC32:
414
1
    return SignExtend64<32>(read32<E>(Buf));
415
7
  case R_MICROMIPS_26_S1:
416
4
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
417
7
  case R_MICROMIPS_PC7_S1:
418
1
    return SignExtend64<8>(read16<E>(Buf) << 1);
419
7
  case R_MICROMIPS_PC10_S1:
420
1
    return SignExtend64<11>(read16<E>(Buf) << 1);
421
7
  case R_MICROMIPS_PC16_S1:
422
1
    return SignExtend64<17>(readShuffle<E>(Buf) << 1);
423
7
  case R_MICROMIPS_PC18_S3:
424
0
    return SignExtend64<21>(readShuffle<E>(Buf) << 3);
425
7
  case R_MICROMIPS_PC19_S2:
426
1
    return SignExtend64<21>(readShuffle<E>(Buf) << 2);
427
7
  case R_MICROMIPS_PC21_S1:
428
1
    return SignExtend64<22>(readShuffle<E>(Buf) << 1);
429
7
  case R_MICROMIPS_PC23_S2:
430
0
    return SignExtend64<25>(readShuffle<E>(Buf) << 2);
431
7
  case R_MICROMIPS_PC26_S1:
432
3
    return SignExtend64<27>(readShuffle<E>(Buf) << 1);
433
52
  default:
434
52
    return 0;
435
309
  }
436
309
}
437
438
static std::pair<uint32_t, uint64_t>
439
10.0k
calculateMipsRelChain(uint8_t *Loc, RelType Type, uint64_t Val) {
440
10.0k
  // MIPS N64 ABI packs multiple relocations into the single relocation
441
10.0k
  // record. In general, all up to three relocations can have arbitrary
442
10.0k
  // types. In fact, Clang and GCC uses only a few combinations. For now,
443
10.0k
  // we support two of them. That is allow to pass at least all LLVM
444
10.0k
  // test suite cases.
445
10.0k
  // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
446
10.0k
  // <any relocation> / R_MIPS_64 / R_MIPS_NONE
447
10.0k
  // The first relocation is a 'real' relocation which is calculated
448
10.0k
  // using the corresponding symbol's value. The second and the third
449
10.0k
  // relocations used to modify result of the first one: extend it to
450
10.0k
  // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
451
10.0k
  // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
452
10.0k
  RelType Type2 = (Type >> 8) & 0xff;
453
10.0k
  RelType Type3 = (Type >> 16) & 0xff;
454
10.0k
  if (Type2 == R_MIPS_NONE && 
Type3 == R_MIPS_NONE10.0k
)
455
10.0k
    return std::make_pair(Type, Val);
456
12
  if (Type2 == R_MIPS_64 && 
Type3 == R_MIPS_NONE1
)
457
1
    return std::make_pair(Type2, Val);
458
11
  if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || 
Type3 == R_MIPS_LO164
))
459
11
    return std::make_pair(Type3, -Val);
460
0
  if (Type2 == R_MICROMIPS_SUB &&
461
0
      (Type3 == R_MICROMIPS_HI16 || Type3 == R_MICROMIPS_LO16))
462
0
    return std::make_pair(Type3, -Val);
463
0
  error(getErrorLocation(Loc) + "unsupported relocations combination " +
464
0
        Twine(Type));
465
0
  return std::make_pair(Type & 0xff, Val);
466
0
}
467
468
template <class ELFT>
469
10.4k
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
470
10.4k
  const endianness E = ELFT::TargetEndianness;
471
10.4k
472
10.4k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi374
)
473
10.0k
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
474
10.4k
475
10.4k
  // Thread pointer and DRP offsets from the start of TLS data area.
476
10.4k
  // https://www.linux-mips.org/wiki/NPTL
477
10.4k
  if (Type == R_MIPS_TLS_DTPREL_HI16 || 
Type == R_MIPS_TLS_DTPREL_LO1610.4k
||
478
10.4k
      
Type == R_MIPS_TLS_DTPREL3210.4k
||
Type == R_MIPS_TLS_DTPREL6410.4k
||
479
10.4k
      
Type == R_MICROMIPS_TLS_DTPREL_HI1610.4k
||
480
10.4k
      
Type == R_MICROMIPS_TLS_DTPREL_LO1610.4k
) {
481
6
    Val -= 0x8000;
482
10.4k
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || 
Type == R_MIPS_TLS_TPREL_LO1610.4k
||
483
10.4k
             
Type == R_MIPS_TLS_TPREL3210.4k
||
Type == R_MIPS_TLS_TPREL6410.4k
||
484
10.4k
             
Type == R_MICROMIPS_TLS_TPREL_HI1610.4k
||
485
10.4k
             
Type == R_MICROMIPS_TLS_TPREL_LO1610.4k
) {
486
6
    Val -= 0x7000;
487
6
  }
488
10.4k
489
10.4k
  switch (Type) {
490
10.4k
  case R_MIPS_32:
491
31
  case R_MIPS_GPREL32:
492
31
  case R_MIPS_TLS_DTPREL32:
493
31
  case R_MIPS_TLS_TPREL32:
494
31
    write32<E>(Loc, Val);
495
31
    break;
496
31
  case R_MIPS_64:
497
8
  case R_MIPS_TLS_DTPREL64:
498
8
  case R_MIPS_TLS_TPREL64:
499
8
    write64<E>(Loc, Val);
500
8
    break;
501
54
  case R_MIPS_26:
502
54
    writeValue<E>(Loc, Val, 26, 2);
503
54
    break;
504
42
  case R_MIPS_GOT16:
505
42
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
506
42
    // is updated addend (not a GOT index). In that case write high 16 bits
507
42
    // to store a correct addend value.
508
42
    if (Config->Relocatable) {
509
1
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
510
41
    } else {
511
41
      checkInt(Loc, Val, 16, Type);
512
41
      writeValue<E>(Loc, Val, 16, 0);
513
41
    }
514
42
    break;
515
8
  case R_MICROMIPS_GOT16:
516
4
    if (Config->Relocatable) {
517
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
518
4
    } else {
519
4
      checkInt(Loc, Val, 16, Type);
520
4
      writeShuffleValue<E>(Loc, Val, 16, 0);
521
4
    }
522
4
    break;
523
10.0k
  case R_MIPS_CALL16:
524
10.0k
  case R_MIPS_GOT_DISP:
525
10.0k
  case R_MIPS_GOT_PAGE:
526
10.0k
  case R_MIPS_GPREL16:
527
10.0k
  case R_MIPS_TLS_GD:
528
10.0k
  case R_MIPS_TLS_GOTTPREL:
529
10.0k
  case R_MIPS_TLS_LDM:
530
10.0k
    checkInt(Loc, Val, 16, Type);
531
10.0k
    LLVM_FALLTHROUGH;
532
10.1k
  case R_MIPS_CALL_LO16:
533
10.1k
  case R_MIPS_GOT_LO16:
534
10.1k
  case R_MIPS_GOT_OFST:
535
10.1k
  case R_MIPS_LO16:
536
10.1k
  case R_MIPS_PCLO16:
537
10.1k
  case R_MIPS_TLS_DTPREL_LO16:
538
10.1k
  case R_MIPS_TLS_TPREL_LO16:
539
10.1k
    writeValue<E>(Loc, Val, 16, 0);
540
10.1k
    break;
541
10.1k
  case R_MICROMIPS_GOT_DISP:
542
0
  case R_MICROMIPS_GOT_PAGE:
543
0
  case R_MICROMIPS_GPREL16:
544
0
  case R_MICROMIPS_TLS_GD:
545
0
  case R_MICROMIPS_TLS_LDM:
546
0
    checkInt(Loc, Val, 16, Type);
547
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
548
0
    break;
549
12
  case R_MICROMIPS_CALL16:
550
12
  case R_MICROMIPS_CALL_LO16:
551
12
  case R_MICROMIPS_GOT_OFST:
552
12
  case R_MICROMIPS_LO16:
553
12
  case R_MICROMIPS_TLS_DTPREL_LO16:
554
12
  case R_MICROMIPS_TLS_GOTTPREL:
555
12
  case R_MICROMIPS_TLS_TPREL_LO16:
556
12
    writeShuffleValue<E>(Loc, Val, 16, 0);
557
12
    break;
558
12
  case R_MICROMIPS_GPREL7_S2:
559
0
    checkInt(Loc, Val, 7, Type);
560
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
561
0
    break;
562
72
  case R_MIPS_CALL_HI16:
563
72
  case R_MIPS_GOT_HI16:
564
72
  case R_MIPS_HI16:
565
72
  case R_MIPS_PCHI16:
566
72
  case R_MIPS_TLS_DTPREL_HI16:
567
72
  case R_MIPS_TLS_TPREL_HI16:
568
72
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
569
72
    break;
570
72
  case R_MICROMIPS_CALL_HI16:
571
7
  case R_MICROMIPS_GOT_HI16:
572
7
  case R_MICROMIPS_HI16:
573
7
  case R_MICROMIPS_TLS_DTPREL_HI16:
574
7
  case R_MICROMIPS_TLS_TPREL_HI16:
575
7
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
576
7
    break;
577
7
  case R_MIPS_HIGHER:
578
2
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
579
2
    break;
580
7
  case R_MIPS_HIGHEST:
581
2
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
582
2
    break;
583
7
  case R_MICROMIPS_HIGHER:
584
0
    writeShuffleValue<E>(Loc, Val + 0x80008000, 16, 32);
585
0
    break;
586
7
  case R_MICROMIPS_HIGHEST:
587
0
    writeShuffleValue<E>(Loc, Val + 0x800080008000, 16, 48);
588
0
    break;
589
7
  case R_MIPS_JALR:
590
0
  case R_MICROMIPS_JALR:
591
0
    // Ignore this optimization relocation for now
592
0
    break;
593
2
  case R_MIPS_PC16:
594
2
    checkAlignment(Loc, Val, 4, Type);
595
2
    checkInt(Loc, Val, 18, Type);
596
2
    writeValue<E>(Loc, Val, 16, 2);
597
2
    break;
598
1
  case R_MIPS_PC19_S2:
599
1
    checkAlignment(Loc, Val, 4, Type);
600
1
    checkInt(Loc, Val, 21, Type);
601
1
    writeValue<E>(Loc, Val, 19, 2);
602
1
    break;
603
1
  case R_MIPS_PC21_S2:
604
1
    checkAlignment(Loc, Val, 4, Type);
605
1
    checkInt(Loc, Val, 23, Type);
606
1
    writeValue<E>(Loc, Val, 21, 2);
607
1
    break;
608
1
  case R_MIPS_PC26_S2:
609
1
    checkAlignment(Loc, Val, 4, Type);
610
1
    checkInt(Loc, Val, 28, Type);
611
1
    writeValue<E>(Loc, Val, 26, 2);
612
1
    break;
613
2
  case R_MIPS_PC32:
614
2
    writeValue<E>(Loc, Val, 32, 0);
615
2
    break;
616
16
  case R_MICROMIPS_26_S1:
617
16
  case R_MICROMIPS_PC26_S1:
618
16
    checkInt(Loc, Val, 27, Type);
619
16
    writeShuffleValue<E>(Loc, Val, 26, 1);
620
16
    break;
621
16
  case R_MICROMIPS_PC7_S1:
622
2
    checkInt(Loc, Val, 8, Type);
623
2
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
624
2
    break;
625
16
  case R_MICROMIPS_PC10_S1:
626
2
    checkInt(Loc, Val, 11, Type);
627
2
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
628
2
    break;
629
16
  case R_MICROMIPS_PC16_S1:
630
2
    checkInt(Loc, Val, 17, Type);
631
2
    writeShuffleValue<E>(Loc, Val, 16, 1);
632
2
    break;
633
16
  case R_MICROMIPS_PC18_S3:
634
0
    checkInt(Loc, Val, 21, Type);
635
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
636
0
    break;
637
16
  case R_MICROMIPS_PC19_S2:
638
6
    checkInt(Loc, Val, 21, Type);
639
6
    writeShuffleValue<E>(Loc, Val, 19, 2);
640
6
    break;
641
16
  case R_MICROMIPS_PC21_S1:
642
2
    checkInt(Loc, Val, 22, Type);
643
2
    writeShuffleValue<E>(Loc, Val, 21, 1);
644
2
    break;
645
16
  case R_MICROMIPS_PC23_S2:
646
8
    checkInt(Loc, Val, 25, Type);
647
8
    writeShuffleValue<E>(Loc, Val, 23, 2);
648
8
    break;
649
16
  default:
650
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
651
10.4k
  }
652
10.4k
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
469
30
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
470
30
  const endianness E = ELFT::TargetEndianness;
471
30
472
30
  if (ELFT::Is64Bits || Config->MipsN32Abi)
473
0
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
474
30
475
30
  // Thread pointer and DRP offsets from the start of TLS data area.
476
30
  // https://www.linux-mips.org/wiki/NPTL
477
30
  if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
478
30
      Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 ||
479
30
      Type == R_MICROMIPS_TLS_DTPREL_HI16 ||
480
30
      Type == R_MICROMIPS_TLS_DTPREL_LO16) {
481
0
    Val -= 0x8000;
482
30
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
483
30
             Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 ||
484
30
             Type == R_MICROMIPS_TLS_TPREL_HI16 ||
485
30
             Type == R_MICROMIPS_TLS_TPREL_LO16) {
486
0
    Val -= 0x7000;
487
0
  }
488
30
489
30
  switch (Type) {
490
30
  case R_MIPS_32:
491
2
  case R_MIPS_GPREL32:
492
2
  case R_MIPS_TLS_DTPREL32:
493
2
  case R_MIPS_TLS_TPREL32:
494
2
    write32<E>(Loc, Val);
495
2
    break;
496
2
  case R_MIPS_64:
497
0
  case R_MIPS_TLS_DTPREL64:
498
0
  case R_MIPS_TLS_TPREL64:
499
0
    write64<E>(Loc, Val);
500
0
    break;
501
0
  case R_MIPS_26:
502
0
    writeValue<E>(Loc, Val, 26, 2);
503
0
    break;
504
4
  case R_MIPS_GOT16:
505
4
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
506
4
    // is updated addend (not a GOT index). In that case write high 16 bits
507
4
    // to store a correct addend value.
508
4
    if (Config->Relocatable) {
509
0
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
510
4
    } else {
511
4
      checkInt(Loc, Val, 16, Type);
512
4
      writeValue<E>(Loc, Val, 16, 0);
513
4
    }
514
4
    break;
515
1
  case R_MICROMIPS_GOT16:
516
1
    if (Config->Relocatable) {
517
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
518
1
    } else {
519
1
      checkInt(Loc, Val, 16, Type);
520
1
      writeShuffleValue<E>(Loc, Val, 16, 0);
521
1
    }
522
1
    break;
523
0
  case R_MIPS_CALL16:
524
0
  case R_MIPS_GOT_DISP:
525
0
  case R_MIPS_GOT_PAGE:
526
0
  case R_MIPS_GPREL16:
527
0
  case R_MIPS_TLS_GD:
528
0
  case R_MIPS_TLS_GOTTPREL:
529
0
  case R_MIPS_TLS_LDM:
530
0
    checkInt(Loc, Val, 16, Type);
531
0
    LLVM_FALLTHROUGH;
532
0
  case R_MIPS_CALL_LO16:
533
0
  case R_MIPS_GOT_LO16:
534
0
  case R_MIPS_GOT_OFST:
535
0
  case R_MIPS_LO16:
536
0
  case R_MIPS_PCLO16:
537
0
  case R_MIPS_TLS_DTPREL_LO16:
538
0
  case R_MIPS_TLS_TPREL_LO16:
539
0
    writeValue<E>(Loc, Val, 16, 0);
540
0
    break;
541
0
  case R_MICROMIPS_GOT_DISP:
542
0
  case R_MICROMIPS_GOT_PAGE:
543
0
  case R_MICROMIPS_GPREL16:
544
0
  case R_MICROMIPS_TLS_GD:
545
0
  case R_MICROMIPS_TLS_LDM:
546
0
    checkInt(Loc, Val, 16, Type);
547
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
548
0
    break;
549
4
  case R_MICROMIPS_CALL16:
550
4
  case R_MICROMIPS_CALL_LO16:
551
4
  case R_MICROMIPS_GOT_OFST:
552
4
  case R_MICROMIPS_LO16:
553
4
  case R_MICROMIPS_TLS_DTPREL_LO16:
554
4
  case R_MICROMIPS_TLS_GOTTPREL:
555
4
  case R_MICROMIPS_TLS_TPREL_LO16:
556
4
    writeShuffleValue<E>(Loc, Val, 16, 0);
557
4
    break;
558
4
  case R_MICROMIPS_GPREL7_S2:
559
0
    checkInt(Loc, Val, 7, Type);
560
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
561
0
    break;
562
4
  case R_MIPS_CALL_HI16:
563
0
  case R_MIPS_GOT_HI16:
564
0
  case R_MIPS_HI16:
565
0
  case R_MIPS_PCHI16:
566
0
  case R_MIPS_TLS_DTPREL_HI16:
567
0
  case R_MIPS_TLS_TPREL_HI16:
568
0
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
569
0
    break;
570
3
  case R_MICROMIPS_CALL_HI16:
571
3
  case R_MICROMIPS_GOT_HI16:
572
3
  case R_MICROMIPS_HI16:
573
3
  case R_MICROMIPS_TLS_DTPREL_HI16:
574
3
  case R_MICROMIPS_TLS_TPREL_HI16:
575
3
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
576
3
    break;
577
3
  case R_MIPS_HIGHER:
578
0
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
579
0
    break;
580
3
  case R_MIPS_HIGHEST:
581
0
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
582
0
    break;
583
3
  case R_MICROMIPS_HIGHER:
584
0
    writeShuffleValue<E>(Loc, Val + 0x80008000, 16, 32);
585
0
    break;
586
3
  case R_MICROMIPS_HIGHEST:
587
0
    writeShuffleValue<E>(Loc, Val + 0x800080008000, 16, 48);
588
0
    break;
589
3
  case R_MIPS_JALR:
590
0
  case R_MICROMIPS_JALR:
591
0
    // Ignore this optimization relocation for now
592
0
    break;
593
0
  case R_MIPS_PC16:
594
0
    checkAlignment(Loc, Val, 4, Type);
595
0
    checkInt(Loc, Val, 18, Type);
596
0
    writeValue<E>(Loc, Val, 16, 2);
597
0
    break;
598
0
  case R_MIPS_PC19_S2:
599
0
    checkAlignment(Loc, Val, 4, Type);
600
0
    checkInt(Loc, Val, 21, Type);
601
0
    writeValue<E>(Loc, Val, 19, 2);
602
0
    break;
603
0
  case R_MIPS_PC21_S2:
604
0
    checkAlignment(Loc, Val, 4, Type);
605
0
    checkInt(Loc, Val, 23, Type);
606
0
    writeValue<E>(Loc, Val, 21, 2);
607
0
    break;
608
0
  case R_MIPS_PC26_S2:
609
0
    checkAlignment(Loc, Val, 4, Type);
610
0
    checkInt(Loc, Val, 28, Type);
611
0
    writeValue<E>(Loc, Val, 26, 2);
612
0
    break;
613
0
  case R_MIPS_PC32:
614
0
    writeValue<E>(Loc, Val, 32, 0);
615
0
    break;
616
7
  case R_MICROMIPS_26_S1:
617
7
  case R_MICROMIPS_PC26_S1:
618
7
    checkInt(Loc, Val, 27, Type);
619
7
    writeShuffleValue<E>(Loc, Val, 26, 1);
620
7
    break;
621
7
  case R_MICROMIPS_PC7_S1:
622
1
    checkInt(Loc, Val, 8, Type);
623
1
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
624
1
    break;
625
7
  case R_MICROMIPS_PC10_S1:
626
1
    checkInt(Loc, Val, 11, Type);
627
1
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
628
1
    break;
629
7
  case R_MICROMIPS_PC16_S1:
630
1
    checkInt(Loc, Val, 17, Type);
631
1
    writeShuffleValue<E>(Loc, Val, 16, 1);
632
1
    break;
633
7
  case R_MICROMIPS_PC18_S3:
634
0
    checkInt(Loc, Val, 21, Type);
635
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
636
0
    break;
637
7
  case R_MICROMIPS_PC19_S2:
638
3
    checkInt(Loc, Val, 21, Type);
639
3
    writeShuffleValue<E>(Loc, Val, 19, 2);
640
3
    break;
641
7
  case R_MICROMIPS_PC21_S1:
642
1
    checkInt(Loc, Val, 22, Type);
643
1
    writeShuffleValue<E>(Loc, Val, 21, 1);
644
1
    break;
645
7
  case R_MICROMIPS_PC23_S2:
646
2
    checkInt(Loc, Val, 25, Type);
647
2
    writeShuffleValue<E>(Loc, Val, 23, 2);
648
2
    break;
649
7
  default:
650
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
651
30
  }
652
30
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
469
344
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
470
344
  const endianness E = ELFT::TargetEndianness;
471
344
472
344
  if (ELFT::Is64Bits || Config->MipsN32Abi)
473
5
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
474
344
475
344
  // Thread pointer and DRP offsets from the start of TLS data area.
476
344
  // https://www.linux-mips.org/wiki/NPTL
477
344
  if (Type == R_MIPS_TLS_DTPREL_HI16 || 
Type == R_MIPS_TLS_DTPREL_LO16342
||
478
344
      
Type == R_MIPS_TLS_DTPREL32340
||
Type == R_MIPS_TLS_DTPREL64339
||
479
344
      
Type == R_MICROMIPS_TLS_DTPREL_HI16339
||
480
344
      
Type == R_MICROMIPS_TLS_DTPREL_LO16339
) {
481
5
    Val -= 0x8000;
482
339
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || 
Type == R_MIPS_TLS_TPREL_LO16337
||
483
339
             
Type == R_MIPS_TLS_TPREL32335
||
Type == R_MIPS_TLS_TPREL64334
||
484
339
             
Type == R_MICROMIPS_TLS_TPREL_HI16334
||
485
339
             
Type == R_MICROMIPS_TLS_TPREL_LO16334
) {
486
5
    Val -= 0x7000;
487
5
  }
488
344
489
344
  switch (Type) {
490
344
  case R_MIPS_32:
491
26
  case R_MIPS_GPREL32:
492
26
  case R_MIPS_TLS_DTPREL32:
493
26
  case R_MIPS_TLS_TPREL32:
494
26
    write32<E>(Loc, Val);
495
26
    break;
496
26
  case R_MIPS_64:
497
0
  case R_MIPS_TLS_DTPREL64:
498
0
  case R_MIPS_TLS_TPREL64:
499
0
    write64<E>(Loc, Val);
500
0
    break;
501
52
  case R_MIPS_26:
502
52
    writeValue<E>(Loc, Val, 26, 2);
503
52
    break;
504
38
  case R_MIPS_GOT16:
505
38
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
506
38
    // is updated addend (not a GOT index). In that case write high 16 bits
507
38
    // to store a correct addend value.
508
38
    if (Config->Relocatable) {
509
1
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
510
37
    } else {
511
37
      checkInt(Loc, Val, 16, Type);
512
37
      writeValue<E>(Loc, Val, 16, 0);
513
37
    }
514
38
    break;
515
3
  case R_MICROMIPS_GOT16:
516
3
    if (Config->Relocatable) {
517
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
518
3
    } else {
519
3
      checkInt(Loc, Val, 16, Type);
520
3
      writeShuffleValue<E>(Loc, Val, 16, 0);
521
3
    }
522
3
    break;
523
34
  case R_MIPS_CALL16:
524
34
  case R_MIPS_GOT_DISP:
525
34
  case R_MIPS_GOT_PAGE:
526
34
  case R_MIPS_GPREL16:
527
34
  case R_MIPS_TLS_GD:
528
34
  case R_MIPS_TLS_GOTTPREL:
529
34
  case R_MIPS_TLS_LDM:
530
34
    checkInt(Loc, Val, 16, Type);
531
34
    LLVM_FALLTHROUGH;
532
119
  case R_MIPS_CALL_LO16:
533
119
  case R_MIPS_GOT_LO16:
534
119
  case R_MIPS_GOT_OFST:
535
119
  case R_MIPS_LO16:
536
119
  case R_MIPS_PCLO16:
537
119
  case R_MIPS_TLS_DTPREL_LO16:
538
119
  case R_MIPS_TLS_TPREL_LO16:
539
119
    writeValue<E>(Loc, Val, 16, 0);
540
119
    break;
541
119
  case R_MICROMIPS_GOT_DISP:
542
0
  case R_MICROMIPS_GOT_PAGE:
543
0
  case R_MICROMIPS_GPREL16:
544
0
  case R_MICROMIPS_TLS_GD:
545
0
  case R_MICROMIPS_TLS_LDM:
546
0
    checkInt(Loc, Val, 16, Type);
547
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
548
0
    break;
549
8
  case R_MICROMIPS_CALL16:
550
8
  case R_MICROMIPS_CALL_LO16:
551
8
  case R_MICROMIPS_GOT_OFST:
552
8
  case R_MICROMIPS_LO16:
553
8
  case R_MICROMIPS_TLS_DTPREL_LO16:
554
8
  case R_MICROMIPS_TLS_GOTTPREL:
555
8
  case R_MICROMIPS_TLS_TPREL_LO16:
556
8
    writeShuffleValue<E>(Loc, Val, 16, 0);
557
8
    break;
558
8
  case R_MICROMIPS_GPREL7_S2:
559
0
    checkInt(Loc, Val, 7, Type);
560
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
561
0
    break;
562
66
  case R_MIPS_CALL_HI16:
563
66
  case R_MIPS_GOT_HI16:
564
66
  case R_MIPS_HI16:
565
66
  case R_MIPS_PCHI16:
566
66
  case R_MIPS_TLS_DTPREL_HI16:
567
66
  case R_MIPS_TLS_TPREL_HI16:
568
66
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
569
66
    break;
570
66
  case R_MICROMIPS_CALL_HI16:
571
4
  case R_MICROMIPS_GOT_HI16:
572
4
  case R_MICROMIPS_HI16:
573
4
  case R_MICROMIPS_TLS_DTPREL_HI16:
574
4
  case R_MICROMIPS_TLS_TPREL_HI16:
575
4
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
576
4
    break;
577
4
  case R_MIPS_HIGHER:
578
0
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
579
0
    break;
580
4
  case R_MIPS_HIGHEST:
581
0
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
582
0
    break;
583
4
  case R_MICROMIPS_HIGHER:
584
0
    writeShuffleValue<E>(Loc, Val + 0x80008000, 16, 32);
585
0
    break;
586
4
  case R_MICROMIPS_HIGHEST:
587
0
    writeShuffleValue<E>(Loc, Val + 0x800080008000, 16, 48);
588
0
    break;
589
4
  case R_MIPS_JALR:
590
0
  case R_MICROMIPS_JALR:
591
0
    // Ignore this optimization relocation for now
592
0
    break;
593
2
  case R_MIPS_PC16:
594
2
    checkAlignment(Loc, Val, 4, Type);
595
2
    checkInt(Loc, Val, 18, Type);
596
2
    writeValue<E>(Loc, Val, 16, 2);
597
2
    break;
598
1
  case R_MIPS_PC19_S2:
599
1
    checkAlignment(Loc, Val, 4, Type);
600
1
    checkInt(Loc, Val, 21, Type);
601
1
    writeValue<E>(Loc, Val, 19, 2);
602
1
    break;
603
1
  case R_MIPS_PC21_S2:
604
1
    checkAlignment(Loc, Val, 4, Type);
605
1
    checkInt(Loc, Val, 23, Type);
606
1
    writeValue<E>(Loc, Val, 21, 2);
607
1
    break;
608
1
  case R_MIPS_PC26_S2:
609
1
    checkAlignment(Loc, Val, 4, Type);
610
1
    checkInt(Loc, Val, 28, Type);
611
1
    writeValue<E>(Loc, Val, 26, 2);
612
1
    break;
613
1
  case R_MIPS_PC32:
614
1
    writeValue<E>(Loc, Val, 32, 0);
615
1
    break;
616
9
  case R_MICROMIPS_26_S1:
617
9
  case R_MICROMIPS_PC26_S1:
618
9
    checkInt(Loc, Val, 27, Type);
619
9
    writeShuffleValue<E>(Loc, Val, 26, 1);
620
9
    break;
621
9
  case R_MICROMIPS_PC7_S1:
622
1
    checkInt(Loc, Val, 8, Type);
623
1
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
624
1
    break;
625
9
  case R_MICROMIPS_PC10_S1:
626
1
    checkInt(Loc, Val, 11, Type);
627
1
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
628
1
    break;
629
9
  case R_MICROMIPS_PC16_S1:
630
1
    checkInt(Loc, Val, 17, Type);
631
1
    writeShuffleValue<E>(Loc, Val, 16, 1);
632
1
    break;
633
9
  case R_MICROMIPS_PC18_S3:
634
0
    checkInt(Loc, Val, 21, Type);
635
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
636
0
    break;
637
9
  case R_MICROMIPS_PC19_S2:
638
3
    checkInt(Loc, Val, 21, Type);
639
3
    writeShuffleValue<E>(Loc, Val, 19, 2);
640
3
    break;
641
9
  case R_MICROMIPS_PC21_S1:
642
1
    checkInt(Loc, Val, 22, Type);
643
1
    writeShuffleValue<E>(Loc, Val, 21, 1);
644
1
    break;
645
9
  case R_MICROMIPS_PC23_S2:
646
6
    checkInt(Loc, Val, 25, Type);
647
6
    writeShuffleValue<E>(Loc, Val, 23, 2);
648
6
    break;
649
9
  default:
650
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
651
344
  }
652
344
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::relocateOne(unsigned char*, unsigned int, unsigned long long) const
Line
Count
Source
469
10.0k
void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
470
10.0k
  const endianness E = ELFT::TargetEndianness;
471
10.0k
472
10.0k
  if (ELFT::Is64Bits || 
Config->MipsN32Abi0
)
473
10.0k
    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
474
10.0k
475
10.0k
  // Thread pointer and DRP offsets from the start of TLS data area.
476
10.0k
  // https://www.linux-mips.org/wiki/NPTL
477
10.0k
  if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
478
10.0k
      Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 ||
479
10.0k
      
Type == R_MICROMIPS_TLS_DTPREL_HI1610.0k
||
480
10.0k
      
Type == R_MICROMIPS_TLS_DTPREL_LO1610.0k
) {
481
1
    Val -= 0x8000;
482
10.0k
  } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
483
10.0k
             Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 ||
484
10.0k
             
Type == R_MICROMIPS_TLS_TPREL_HI1610.0k
||
485
10.0k
             
Type == R_MICROMIPS_TLS_TPREL_LO1610.0k
) {
486
1
    Val -= 0x7000;
487
1
  }
488
10.0k
489
10.0k
  switch (Type) {
490
10.0k
  case R_MIPS_32:
491
3
  case R_MIPS_GPREL32:
492
3
  case R_MIPS_TLS_DTPREL32:
493
3
  case R_MIPS_TLS_TPREL32:
494
3
    write32<E>(Loc, Val);
495
3
    break;
496
8
  case R_MIPS_64:
497
8
  case R_MIPS_TLS_DTPREL64:
498
8
  case R_MIPS_TLS_TPREL64:
499
8
    write64<E>(Loc, Val);
500
8
    break;
501
8
  case R_MIPS_26:
502
2
    writeValue<E>(Loc, Val, 26, 2);
503
2
    break;
504
8
  case R_MIPS_GOT16:
505
0
    // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
506
0
    // is updated addend (not a GOT index). In that case write high 16 bits
507
0
    // to store a correct addend value.
508
0
    if (Config->Relocatable) {
509
0
      writeValue<E>(Loc, Val + 0x8000, 16, 16);
510
0
    } else {
511
0
      checkInt(Loc, Val, 16, Type);
512
0
      writeValue<E>(Loc, Val, 16, 0);
513
0
    }
514
0
    break;
515
8
  case R_MICROMIPS_GOT16:
516
0
    if (Config->Relocatable) {
517
0
      writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
518
0
    } else {
519
0
      checkInt(Loc, Val, 16, Type);
520
0
      writeShuffleValue<E>(Loc, Val, 16, 0);
521
0
    }
522
0
    break;
523
10.0k
  case R_MIPS_CALL16:
524
10.0k
  case R_MIPS_GOT_DISP:
525
10.0k
  case R_MIPS_GOT_PAGE:
526
10.0k
  case R_MIPS_GPREL16:
527
10.0k
  case R_MIPS_TLS_GD:
528
10.0k
  case R_MIPS_TLS_GOTTPREL:
529
10.0k
  case R_MIPS_TLS_LDM:
530
10.0k
    checkInt(Loc, Val, 16, Type);
531
10.0k
    LLVM_FALLTHROUGH;
532
10.0k
  case R_MIPS_CALL_LO16:
533
10.0k
  case R_MIPS_GOT_LO16:
534
10.0k
  case R_MIPS_GOT_OFST:
535
10.0k
  case R_MIPS_LO16:
536
10.0k
  case R_MIPS_PCLO16:
537
10.0k
  case R_MIPS_TLS_DTPREL_LO16:
538
10.0k
  case R_MIPS_TLS_TPREL_LO16:
539
10.0k
    writeValue<E>(Loc, Val, 16, 0);
540
10.0k
    break;
541
10.0k
  case R_MICROMIPS_GOT_DISP:
542
0
  case R_MICROMIPS_GOT_PAGE:
543
0
  case R_MICROMIPS_GPREL16:
544
0
  case R_MICROMIPS_TLS_GD:
545
0
  case R_MICROMIPS_TLS_LDM:
546
0
    checkInt(Loc, Val, 16, Type);
547
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
548
0
    break;
549
0
  case R_MICROMIPS_CALL16:
550
0
  case R_MICROMIPS_CALL_LO16:
551
0
  case R_MICROMIPS_GOT_OFST:
552
0
  case R_MICROMIPS_LO16:
553
0
  case R_MICROMIPS_TLS_DTPREL_LO16:
554
0
  case R_MICROMIPS_TLS_GOTTPREL:
555
0
  case R_MICROMIPS_TLS_TPREL_LO16:
556
0
    writeShuffleValue<E>(Loc, Val, 16, 0);
557
0
    break;
558
0
  case R_MICROMIPS_GPREL7_S2:
559
0
    checkInt(Loc, Val, 7, Type);
560
0
    writeShuffleValue<E>(Loc, Val, 7, 2);
561
0
    break;
562
6
  case R_MIPS_CALL_HI16:
563
6
  case R_MIPS_GOT_HI16:
564
6
  case R_MIPS_HI16:
565
6
  case R_MIPS_PCHI16:
566
6
  case R_MIPS_TLS_DTPREL_HI16:
567
6
  case R_MIPS_TLS_TPREL_HI16:
568
6
    writeValue<E>(Loc, Val + 0x8000, 16, 16);
569
6
    break;
570
6
  case R_MICROMIPS_CALL_HI16:
571
0
  case R_MICROMIPS_GOT_HI16:
572
0
  case R_MICROMIPS_HI16:
573
0
  case R_MICROMIPS_TLS_DTPREL_HI16:
574
0
  case R_MICROMIPS_TLS_TPREL_HI16:
575
0
    writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16);
576
0
    break;
577
2
  case R_MIPS_HIGHER:
578
2
    writeValue<E>(Loc, Val + 0x80008000, 16, 32);
579
2
    break;
580
2
  case R_MIPS_HIGHEST:
581
2
    writeValue<E>(Loc, Val + 0x800080008000, 16, 48);
582
2
    break;
583
0
  case R_MICROMIPS_HIGHER:
584
0
    writeShuffleValue<E>(Loc, Val + 0x80008000, 16, 32);
585
0
    break;
586
0
  case R_MICROMIPS_HIGHEST:
587
0
    writeShuffleValue<E>(Loc, Val + 0x800080008000, 16, 48);
588
0
    break;
589
0
  case R_MIPS_JALR:
590
0
  case R_MICROMIPS_JALR:
591
0
    // Ignore this optimization relocation for now
592
0
    break;
593
0
  case R_MIPS_PC16:
594
0
    checkAlignment(Loc, Val, 4, Type);
595
0
    checkInt(Loc, Val, 18, Type);
596
0
    writeValue<E>(Loc, Val, 16, 2);
597
0
    break;
598
0
  case R_MIPS_PC19_S2:
599
0
    checkAlignment(Loc, Val, 4, Type);
600
0
    checkInt(Loc, Val, 21, Type);
601
0
    writeValue<E>(Loc, Val, 19, 2);
602
0
    break;
603
0
  case R_MIPS_PC21_S2:
604
0
    checkAlignment(Loc, Val, 4, Type);
605
0
    checkInt(Loc, Val, 23, Type);
606
0
    writeValue<E>(Loc, Val, 21, 2);
607
0
    break;
608
0
  case R_MIPS_PC26_S2:
609
0
    checkAlignment(Loc, Val, 4, Type);
610
0
    checkInt(Loc, Val, 28, Type);
611
0
    writeValue<E>(Loc, Val, 26, 2);
612
0
    break;
613
1
  case R_MIPS_PC32:
614
1
    writeValue<E>(Loc, Val, 32, 0);
615
1
    break;
616
0
  case R_MICROMIPS_26_S1:
617
0
  case R_MICROMIPS_PC26_S1:
618
0
    checkInt(Loc, Val, 27, Type);
619
0
    writeShuffleValue<E>(Loc, Val, 26, 1);
620
0
    break;
621
0
  case R_MICROMIPS_PC7_S1:
622
0
    checkInt(Loc, Val, 8, Type);
623
0
    writeMicroRelocation16<E>(Loc, Val, 7, 1);
624
0
    break;
625
0
  case R_MICROMIPS_PC10_S1:
626
0
    checkInt(Loc, Val, 11, Type);
627
0
    writeMicroRelocation16<E>(Loc, Val, 10, 1);
628
0
    break;
629
0
  case R_MICROMIPS_PC16_S1:
630
0
    checkInt(Loc, Val, 17, Type);
631
0
    writeShuffleValue<E>(Loc, Val, 16, 1);
632
0
    break;
633
0
  case R_MICROMIPS_PC18_S3:
634
0
    checkInt(Loc, Val, 21, Type);
635
0
    writeShuffleValue<E>(Loc, Val, 18, 3);
636
0
    break;
637
0
  case R_MICROMIPS_PC19_S2:
638
0
    checkInt(Loc, Val, 21, Type);
639
0
    writeShuffleValue<E>(Loc, Val, 19, 2);
640
0
    break;
641
0
  case R_MICROMIPS_PC21_S1:
642
0
    checkInt(Loc, Val, 22, Type);
643
0
    writeShuffleValue<E>(Loc, Val, 21, 1);
644
0
    break;
645
0
  case R_MICROMIPS_PC23_S2:
646
0
    checkInt(Loc, Val, 25, Type);
647
0
    writeShuffleValue<E>(Loc, Val, 23, 2);
648
0
    break;
649
0
  default:
650
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
651
10.0k
  }
652
10.0k
}
653
654
34
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
655
34
  return Type == R_MIPS_LO16 || 
Type == R_MIPS_GOT_OFST18
||
656
34
         
Type == R_MICROMIPS_LO1617
||
Type == R_MICROMIPS_GOT_OFST17
;
657
34
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, false> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
654
2
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
655
2
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
656
2
         Type == R_MICROMIPS_LO16 || Type == R_MICROMIPS_GOT_OFST;
657
2
}
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, false> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
654
26
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
655
26
  return Type == R_MIPS_LO16 || 
Type == R_MIPS_GOT_OFST10
||
656
26
         
Type == R_MICROMIPS_LO1610
||
Type == R_MICROMIPS_GOT_OFST10
;
657
26
}
Unexecuted instantiation: Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)1, true> >::usesOnlyLowPageBits(unsigned int) const
Mips.cpp:(anonymous namespace)::MIPS<llvm::object::ELFType<(llvm::support::endianness)0, true> >::usesOnlyLowPageBits(unsigned int) const
Line
Count
Source
654
6
template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const {
655
6
  return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST ||
656
6
         
Type == R_MICROMIPS_LO165
||
Type == R_MICROMIPS_GOT_OFST5
;
657
6
}
658
659
// Return true if the symbol is a PIC function.
660
135
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
661
135
  if (!Sym->isFunc())
662
69
    return false;
663
66
664
66
  if (Sym->StOther & STO_MIPS_PIC)
665
7
    return true;
666
59
667
59
  if (!Sym->Section)
668
0
    return false;
669
59
670
59
  ObjFile<ELFT> *File =
671
59
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
672
59
  if (!File)
673
1
    return false;
674
58
675
58
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
676
58
}
bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)1, false> >(lld::elf::Defined const*)
Line
Count
Source
660
3
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
661
3
  if (!Sym->isFunc())
662
0
    return false;
663
3
664
3
  if (Sym->StOther & STO_MIPS_PIC)
665
0
    return true;
666
3
667
3
  if (!Sym->Section)
668
0
    return false;
669
3
670
3
  ObjFile<ELFT> *File =
671
3
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
672
3
  if (!File)
673
0
    return false;
674
3
675
3
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
676
3
}
bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)0, false> >(lld::elf::Defined const*)
Line
Count
Source
660
113
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
661
113
  if (!Sym->isFunc())
662
50
    return false;
663
63
664
63
  if (Sym->StOther & STO_MIPS_PIC)
665
7
    return true;
666
56
667
56
  if (!Sym->Section)
668
0
    return false;
669
56
670
56
  ObjFile<ELFT> *File =
671
56
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
672
56
  if (!File)
673
1
    return false;
674
55
675
55
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
676
55
}
Unexecuted instantiation: bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)1, true> >(lld::elf::Defined const*)
bool lld::elf::isMipsPIC<llvm::object::ELFType<(llvm::support::endianness)0, true> >(lld::elf::Defined const*)
Line
Count
Source
660
19
template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) {
661
19
  if (!Sym->isFunc())
662
19
    return false;
663
0
664
0
  if (Sym->StOther & STO_MIPS_PIC)
665
0
    return true;
666
0
667
0
  if (!Sym->Section)
668
0
    return false;
669
0
670
0
  ObjFile<ELFT> *File =
671
0
      cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>();
672
0
  if (!File)
673
0
    return false;
674
0
675
0
  return File->getObj().getHeader()->e_flags & EF_MIPS_PIC;
676
0
}
677
678
175
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
679
175
  static MIPS<ELFT> Target;
680
175
  return &Target;
681
175
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)1, false> >()
Line
Count
Source
678
17
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
679
17
  static MIPS<ELFT> Target;
680
17
  return &Target;
681
17
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)0, false> >()
Line
Count
Source
678
118
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
679
118
  static MIPS<ELFT> Target;
680
118
  return &Target;
681
118
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)1, true> >()
Line
Count
Source
678
2
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
679
2
  static MIPS<ELFT> Target;
680
2
  return &Target;
681
2
}
lld::elf::TargetInfo* lld::elf::getMipsTargetInfo<llvm::object::ELFType<(llvm::support::endianness)0, true> >()
Line
Count
Source
678
38
template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
679
38
  static MIPS<ELFT> Target;
680
38
  return &Target;
681
38
}
682
683
template TargetInfo *elf::getMipsTargetInfo<ELF32LE>();
684
template TargetInfo *elf::getMipsTargetInfo<ELF32BE>();
685
template TargetInfo *elf::getMipsTargetInfo<ELF64LE>();
686
template TargetInfo *elf::getMipsTargetInfo<ELF64BE>();
687
688
template bool elf::isMipsPIC<ELF32LE>(const Defined *);
689
template bool elf::isMipsPIC<ELF32BE>(const Defined *);
690
template bool elf::isMipsPIC<ELF64LE>(const Defined *);
691
template bool elf::isMipsPIC<ELF64BE>(const Defined *);