Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/PPC64.cpp
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1
//===- PPC64.cpp ----------------------------------------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "Symbols.h"
10
#include "SyntheticSections.h"
11
#include "Target.h"
12
#include "lld/Common/ErrorHandler.h"
13
#include "llvm/Support/Endian.h"
14
15
using namespace llvm;
16
using namespace llvm::object;
17
using namespace llvm::support::endian;
18
using namespace llvm::ELF;
19
using namespace lld;
20
using namespace lld::elf;
21
22
static uint64_t ppc64TocOffset = 0x8000;
23
static uint64_t dynamicThreadPointerOffset = 0x8000;
24
25
// The instruction encoding of bits 21-30 from the ISA for the Xform and Dform
26
// instructions that can be used as part of the initial exec TLS sequence.
27
enum XFormOpcd {
28
  LBZX = 87,
29
  LHZX = 279,
30
  LWZX = 23,
31
  LDX = 21,
32
  STBX = 215,
33
  STHX = 407,
34
  STWX = 151,
35
  STDX = 149,
36
  ADD = 266,
37
};
38
39
enum DFormOpcd {
40
  LBZ = 34,
41
  LBZU = 35,
42
  LHZ = 40,
43
  LHZU = 41,
44
  LHAU = 43,
45
  LWZ = 32,
46
  LWZU = 33,
47
  LFSU = 49,
48
  LD = 58,
49
  LFDU = 51,
50
  STB = 38,
51
  STBU = 39,
52
  STH = 44,
53
  STHU = 45,
54
  STW = 36,
55
  STWU = 37,
56
  STFSU = 53,
57
  STFDU = 55,
58
  STD = 62,
59
  ADDI = 14
60
};
61
62
186
uint64_t elf::getPPC64TocBase() {
63
186
  // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
64
186
  // TOC starts where the first of these sections starts. We always create a
65
186
  // .got when we see a relocation that uses it, so for us the start is always
66
186
  // the .got.
67
186
  uint64_t tocVA = in.got->getVA();
68
186
69
186
  // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
70
186
  // thus permitting a full 64 Kbytes segment. Note that the glibc startup
71
186
  // code (crt1.o) assumes that you can get from the TOC base to the
72
186
  // start of the .toc section with only a single (signed) 16-bit relocation.
73
186
  return tocVA + ppc64TocOffset;
74
186
}
75
76
284
unsigned elf::getPPC64GlobalEntryToLocalEntryOffset(uint8_t stOther) {
77
284
  // The offset is encoded into the 3 most significant bits of the st_other
78
284
  // field, with some special values described in section 3.4.1 of the ABI:
79
284
  // 0   --> Zero offset between the GEP and LEP, and the function does NOT use
80
284
  //         the TOC pointer (r2). r2 will hold the same value on returning from
81
284
  //         the function as it did on entering the function.
82
284
  // 1   --> Zero offset between the GEP and LEP, and r2 should be treated as a
83
284
  //         caller-saved register for all callers.
84
284
  // 2-6 --> The  binary logarithm of the offset eg:
85
284
  //         2 --> 2^2 = 4 bytes -->  1 instruction.
86
284
  //         6 --> 2^6 = 64 bytes --> 16 instructions.
87
284
  // 7   --> Reserved.
88
284
  uint8_t gepToLep = (stOther >> 5) & 7;
89
284
  if (gepToLep < 2)
90
210
    return 0;
91
74
92
74
  // The value encoded in the st_other bits is the
93
74
  // log-base-2(offset).
94
74
  if (gepToLep < 7)
95
74
    return 1 << gepToLep;
96
0
97
0
  error("reserved value of 7 in the 3 most-significant-bits of st_other");
98
0
  return 0;
99
0
}
100
101
993
bool elf::isPPC64SmallCodeModelTocReloc(RelType type) {
102
993
  // The only small code model relocations that access the .toc section.
103
993
  return type == R_PPC64_TOC16 || type == R_PPC64_TOC16_DS;
104
993
}
105
106
// Find the R_PPC64_ADDR64 in .rela.toc with matching offset.
107
template <typename ELFT>
108
static std::pair<Defined *, int64_t>
109
70
getRelaTocSymAndAddend(InputSectionBase *tocSec, uint64_t offset) {
110
70
  if (tocSec->numRelocations == 0)
111
0
    return {};
112
70
113
70
  // .rela.toc contains exclusively R_PPC64_ADDR64 relocations sorted by
114
70
  // r_offset: 0, 8, 16, etc. For a given Offset, Offset / 8 gives us the
115
70
  // relocation index in most cases.
116
70
  //
117
70
  // In rare cases a TOC entry may store a constant that doesn't need an
118
70
  // R_PPC64_ADDR64, the corresponding r_offset is therefore missing. Offset / 8
119
70
  // points to a relocation with larger r_offset. Do a linear probe then.
120
70
  // Constants are extremely uncommon in .toc and the extra number of array
121
70
  // accesses can be seen as a small constant.
122
70
  ArrayRef<typename ELFT::Rela> relas = tocSec->template relas<ELFT>();
123
70
  uint64_t index = std::min<uint64_t>(offset / 8, relas.size() - 1);
124
70
  for (;;) {
125
70
    if (relas[index].r_offset == offset) {
126
66
      Symbol &sym = tocSec->getFile<ELFT>()->getRelocTargetSym(relas[index]);
127
66
      return {dyn_cast<Defined>(&sym), getAddend<ELFT>(relas[index])};
128
66
    }
129
4
    if (relas[index].r_offset < offset || index == 0)
130
4
      break;
131
0
    --index;
132
0
  }
133
70
  
return {}4
;
134
70
}
PPC64.cpp:std::__1::pair<lld::elf::Defined*, long long> getRelaTocSymAndAddend<llvm::object::ELFType<(llvm::support::endianness)1, true> >(lld::elf::InputSectionBase*, unsigned long long)
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109
48
getRelaTocSymAndAddend(InputSectionBase *tocSec, uint64_t offset) {
110
48
  if (tocSec->numRelocations == 0)
111
0
    return {};
112
48
113
48
  // .rela.toc contains exclusively R_PPC64_ADDR64 relocations sorted by
114
48
  // r_offset: 0, 8, 16, etc. For a given Offset, Offset / 8 gives us the
115
48
  // relocation index in most cases.
116
48
  //
117
48
  // In rare cases a TOC entry may store a constant that doesn't need an
118
48
  // R_PPC64_ADDR64, the corresponding r_offset is therefore missing. Offset / 8
119
48
  // points to a relocation with larger r_offset. Do a linear probe then.
120
48
  // Constants are extremely uncommon in .toc and the extra number of array
121
48
  // accesses can be seen as a small constant.
122
48
  ArrayRef<typename ELFT::Rela> relas = tocSec->template relas<ELFT>();
123
48
  uint64_t index = std::min<uint64_t>(offset / 8, relas.size() - 1);
124
48
  for (;;) {
125
48
    if (relas[index].r_offset == offset) {
126
44
      Symbol &sym = tocSec->getFile<ELFT>()->getRelocTargetSym(relas[index]);
127
44
      return {dyn_cast<Defined>(&sym), getAddend<ELFT>(relas[index])};
128
44
    }
129
4
    if (relas[index].r_offset < offset || index == 0)
130
4
      break;
131
0
    --index;
132
0
  }
133
48
  
return {}4
;
134
48
}
PPC64.cpp:std::__1::pair<lld::elf::Defined*, long long> getRelaTocSymAndAddend<llvm::object::ELFType<(llvm::support::endianness)0, true> >(lld::elf::InputSectionBase*, unsigned long long)
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109
22
getRelaTocSymAndAddend(InputSectionBase *tocSec, uint64_t offset) {
110
22
  if (tocSec->numRelocations == 0)
111
0
    return {};
112
22
113
22
  // .rela.toc contains exclusively R_PPC64_ADDR64 relocations sorted by
114
22
  // r_offset: 0, 8, 16, etc. For a given Offset, Offset / 8 gives us the
115
22
  // relocation index in most cases.
116
22
  //
117
22
  // In rare cases a TOC entry may store a constant that doesn't need an
118
22
  // R_PPC64_ADDR64, the corresponding r_offset is therefore missing. Offset / 8
119
22
  // points to a relocation with larger r_offset. Do a linear probe then.
120
22
  // Constants are extremely uncommon in .toc and the extra number of array
121
22
  // accesses can be seen as a small constant.
122
22
  ArrayRef<typename ELFT::Rela> relas = tocSec->template relas<ELFT>();
123
22
  uint64_t index = std::min<uint64_t>(offset / 8, relas.size() - 1);
124
22
  for (;;) {
125
22
    if (relas[index].r_offset == offset) {
126
22
      Symbol &sym = tocSec->getFile<ELFT>()->getRelocTargetSym(relas[index]);
127
22
      return {dyn_cast<Defined>(&sym), getAddend<ELFT>(relas[index])};
128
22
    }
129
0
    if (relas[index].r_offset < offset || index == 0)
130
0
      break;
131
0
    --index;
132
0
  }
133
22
  
return {}0
;
134
22
}
135
136
// When accessing a symbol defined in another translation unit, compilers
137
// reserve a .toc entry, allocate a local label and generate toc-indirect
138
// instuctions:
139
//
140
//   addis 3, 2, .LC0@toc@ha  # R_PPC64_TOC16_HA
141
//   ld    3, .LC0@toc@l(3)   # R_PPC64_TOC16_LO_DS, load the address from a .toc entry
142
//   ld/lwa 3, 0(3)           # load the value from the address
143
//
144
//   .section .toc,"aw",@progbits
145
//   .LC0: .tc var[TC],var
146
//
147
// If var is defined, non-preemptable and addressable with a 32-bit signed
148
// offset from the toc base, the address of var can be computed by adding an
149
// offset to the toc base, saving a load.
150
//
151
//   addis 3,2,var@toc@ha     # this may be relaxed to a nop,
152
//   addi  3,3,var@toc@l      # then this becomes addi 3,2,var@toc
153
//   ld/lwa 3, 0(3)           # load the value from the address
154
//
155
// Returns true if the relaxation is performed.
156
bool elf::tryRelaxPPC64TocIndirection(RelType type, const Relocation &rel,
157
117
                                      uint8_t *bufLoc) {
158
117
  assert(config->tocOptimize);
159
117
  if (rel.addend < 0)
160
0
    return false;
161
117
162
117
  // If the symbol is not the .toc section, this isn't a toc-indirection.
163
117
  Defined *defSym = dyn_cast<Defined>(rel.sym);
164
117
  if (!defSym || !defSym->isSection() || 
defSym->section->name != ".toc"95
)
165
47
    return false;
166
70
167
70
  Defined *d;
168
70
  int64_t addend;
169
70
  auto *tocISB = cast<InputSectionBase>(defSym->section);
170
70
  std::tie(d, addend) =
171
70
      config->isLE ? 
getRelaTocSymAndAddend<ELF64LE>(tocISB, rel.addend)48
172
70
                   : 
getRelaTocSymAndAddend<ELF64BE>(tocISB, rel.addend)22
;
173
70
174
70
  // Only non-preemptable defined symbols can be relaxed.
175
70
  if (!d || 
d->isPreemptible58
)
176
16
    return false;
177
54
178
54
  // Two instructions can materialize a 32-bit signed offset from the toc base.
179
54
  uint64_t tocRelative = d->getVA(addend) - getPPC64TocBase();
180
54
  if (!isInt<32>(tocRelative))
181
0
    return false;
182
54
183
54
  // Add PPC64TocOffset that will be subtracted by relocateOne().
184
54
  target->relaxGot(bufLoc, type, tocRelative + ppc64TocOffset);
185
54
  return true;
186
54
}
187
188
namespace {
189
class PPC64 final : public TargetInfo {
190
public:
191
  PPC64();
192
  int getTlsGdRelaxSkip(RelType type) const override;
193
  uint32_t calcEFlags() const override;
194
  RelExpr getRelExpr(RelType type, const Symbol &s,
195
                     const uint8_t *loc) const override;
196
  RelType getDynRel(RelType type) const override;
197
  void writePltHeader(uint8_t *buf) const override;
198
  void writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, uint64_t pltEntryAddr,
199
                int32_t index, unsigned relOff) const override;
200
  void relocateOne(uint8_t *loc, RelType type, uint64_t val) const override;
201
  void writeGotHeader(uint8_t *buf) const override;
202
  bool needsThunk(RelExpr expr, RelType type, const InputFile *file,
203
                  uint64_t branchAddr, const Symbol &s) const override;
204
  uint32_t getThunkSectionSpacing() const override;
205
  bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override;
206
  RelExpr adjustRelaxExpr(RelType type, const uint8_t *data,
207
                          RelExpr expr) const override;
208
  void relaxGot(uint8_t *loc, RelType type, uint64_t val) const override;
209
  void relaxTlsGdToIe(uint8_t *loc, RelType type, uint64_t val) const override;
210
  void relaxTlsGdToLe(uint8_t *loc, RelType type, uint64_t val) const override;
211
  void relaxTlsLdToLe(uint8_t *loc, RelType type, uint64_t val) const override;
212
  void relaxTlsIeToLe(uint8_t *loc, RelType type, uint64_t val) const override;
213
214
  bool adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end,
215
                                        uint8_t stOther) const override;
216
};
217
} // namespace
218
219
// Relocation masks following the #lo(value), #hi(value), #ha(value),
220
// #higher(value), #highera(value), #highest(value), and #highesta(value)
221
// macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
222
// document.
223
441
static uint16_t lo(uint64_t v) { return v; }
224
18
static uint16_t hi(uint64_t v) { return v >> 16; }
225
388
static uint16_t ha(uint64_t v) { return (v + 0x8000) >> 16; }
226
5
static uint16_t higher(uint64_t v) { return v >> 32; }
227
6
static uint16_t highera(uint64_t v) { return (v + 0x8000) >> 32; }
228
5
static uint16_t highest(uint64_t v) { return v >> 48; }
229
6
static uint16_t highesta(uint64_t v) { return (v + 0x8000) >> 48; }
230
231
// Extracts the 'PO' field of an instruction encoding.
232
235
static uint8_t getPrimaryOpCode(uint32_t encoding) { return (encoding >> 26); }
233
234
105
static bool isDQFormInstruction(uint32_t encoding) {
235
105
  switch (getPrimaryOpCode(encoding)) {
236
105
  default:
237
89
    return false;
238
105
  case 56:
239
2
    // The only instruction with a primary opcode of 56 is `lq`.
240
2
    return true;
241
105
  case 61:
242
14
    // There are both DS and DQ instruction forms with this primary opcode.
243
14
    // Namely `lxv` and `stxv` are the DQ-forms that use it.
244
14
    // The DS 'XO' bits being set to 01 is restricted to DQ form.
245
14
    return (encoding & 3) == 0x1;
246
105
  }
247
105
}
248
249
39
static bool isInstructionUpdateForm(uint32_t encoding) {
250
39
  switch (getPrimaryOpCode(encoding)) {
251
39
  default:
252
25
    return false;
253
39
  case LBZU:
254
0
  case LHAU:
255
0
  case LHZU:
256
0
  case LWZU:
257
0
  case LFSU:
258
0
  case LFDU:
259
0
  case STBU:
260
0
  case STHU:
261
0
  case STWU:
262
0
  case STFSU:
263
0
  case STFDU:
264
0
    return true;
265
0
    // LWA has the same opcode as LD, and the DS bits is what differentiates
266
0
    // between LD/LDU/LWA
267
14
  case LD:
268
14
  case STD:
269
14
    return (encoding & 3) == 1;
270
39
  }
271
39
}
272
273
// There are a number of places when we either want to read or write an
274
// instruction when handling a half16 relocation type. On big-endian the buffer
275
// pointer is pointing into the middle of the word we want to extract, and on
276
// little-endian it is pointing to the start of the word. These 2 helpers are to
277
// simplify reading and writing in that context.
278
118
static void writeFromHalf16(uint8_t *loc, uint32_t insn) {
279
118
  write32(config->isLE ? 
loc94
:
loc - 224
, insn);
280
118
}
281
282
152
static uint32_t readFromHalf16(const uint8_t *loc) {
283
152
  return read32(config->isLE ? 
loc111
:
loc - 241
);
284
152
}
285
286
155
PPC64::PPC64() {
287
155
  gotRel = R_PPC64_GLOB_DAT;
288
155
  noneRel = R_PPC64_NONE;
289
155
  pltRel = R_PPC64_JMP_SLOT;
290
155
  relativeRel = R_PPC64_RELATIVE;
291
155
  iRelativeRel = R_PPC64_IRELATIVE;
292
155
  symbolicRel = R_PPC64_ADDR64;
293
155
  pltEntrySize = 4;
294
155
  gotBaseSymInGotPlt = false;
295
155
  gotHeaderEntriesNum = 1;
296
155
  gotPltHeaderEntriesNum = 2;
297
155
  pltHeaderSize = 60;
298
155
  needsThunks = true;
299
155
300
155
  tlsModuleIndexRel = R_PPC64_DTPMOD64;
301
155
  tlsOffsetRel = R_PPC64_DTPREL64;
302
155
303
155
  tlsGotRel = R_PPC64_TPREL64;
304
155
305
155
  needsMoreStackNonSplit = false;
306
155
307
155
  // We need 64K pages (at least under glibc/Linux, the loader won't
308
155
  // set different permissions on a finer granularity than that).
309
155
  defaultMaxPageSize = 65536;
310
155
311
155
  // The PPC64 ELF ABI v1 spec, says:
312
155
  //
313
155
  //   It is normally desirable to put segments with different characteristics
314
155
  //   in separate 256 Mbyte portions of the address space, to give the
315
155
  //   operating system full paging flexibility in the 64-bit address space.
316
155
  //
317
155
  // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
318
155
  // use 0x10000000 as the starting address.
319
155
  defaultImageBase = 0x10000000;
320
155
321
155
  write32(trapInstr.data(), 0x7fe00008);
322
155
}
323
324
22
int PPC64::getTlsGdRelaxSkip(RelType type) const {
325
22
  // A __tls_get_addr call instruction is marked with 2 relocations:
326
22
  //
327
22
  //   R_PPC64_TLSGD / R_PPC64_TLSLD: marker relocation
328
22
  //   R_PPC64_REL24: __tls_get_addr
329
22
  //
330
22
  // After the relaxation we no longer call __tls_get_addr and should skip both
331
22
  // relocations to not create a false dependence on __tls_get_addr being
332
22
  // defined.
333
22
  if (type == R_PPC64_TLSGD || 
type == R_PPC64_TLSLD16
)
334
8
    return 2;
335
14
  return 1;
336
14
}
337
338
205
static uint32_t getEFlags(InputFile *file) {
339
205
  if (config->ekind == ELF64BEKind)
340
77
    return cast<ObjFile<ELF64BE>>(file)->getObj().getHeader()->e_flags;
341
128
  return cast<ObjFile<ELF64LE>>(file)->getObj().getHeader()->e_flags;
342
128
}
343
344
// This file implements v2 ABI. This function makes sure that all
345
// object files have v2 or an unspecified version as an ABI version.
346
152
uint32_t PPC64::calcEFlags() const {
347
205
  for (InputFile *f : objectFiles) {
348
205
    uint32_t flag = getEFlags(f);
349
205
    if (flag == 1)
350
1
      error(toString(f) + ": ABI version 1 is not supported");
351
204
    else if (flag > 2)
352
1
      error(toString(f) + ": unrecognized e_flags: " + Twine(flag));
353
205
  }
354
152
  return 2;
355
152
}
356
357
54
void PPC64::relaxGot(uint8_t *loc, RelType type, uint64_t val) const {
358
54
  switch (type) {
359
54
  case R_PPC64_TOC16_HA:
360
27
    // Convert "addis reg, 2, .LC0@toc@h" to "addis reg, 2, var@toc@h" or "nop".
361
27
    relocateOne(loc, type, val);
362
27
    break;
363
54
  case R_PPC64_TOC16_LO_DS: {
364
27
    // Convert "ld reg, .LC0@toc@l(reg)" to "addi reg, reg, var@toc@l" or
365
27
    // "addi reg, 2, var@toc".
366
27
    uint32_t insn = readFromHalf16(loc);
367
27
    if (getPrimaryOpCode(insn) != LD)
368
0
      error("expected a 'ld' for got-indirect to toc-relative relaxing");
369
27
    writeFromHalf16(loc, (insn & 0x03ffffff) | 0x38000000);
370
27
    relocateOne(loc, R_PPC64_TOC16_LO, val);
371
27
    break;
372
54
  }
373
54
  default:
374
0
    llvm_unreachable("unexpected relocation type");
375
54
  }
376
54
}
377
378
11
void PPC64::relaxTlsGdToLe(uint8_t *loc, RelType type, uint64_t val) const {
379
11
  // Reference: 3.7.4.2 of the 64-bit ELF V2 abi supplement.
380
11
  // The general dynamic code sequence for a global `x` will look like:
381
11
  // Instruction                    Relocation                Symbol
382
11
  // addis r3, r2, x@got@tlsgd@ha   R_PPC64_GOT_TLSGD16_HA      x
383
11
  // addi  r3, r3, x@got@tlsgd@l    R_PPC64_GOT_TLSGD16_LO      x
384
11
  // bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSGD               x
385
11
  //                                R_PPC64_REL24               __tls_get_addr
386
11
  // nop                            None                       None
387
11
388
11
  // Relaxing to local exec entails converting:
389
11
  // addis r3, r2, x@got@tlsgd@ha    into      nop
390
11
  // addi  r3, r3, x@got@tlsgd@l     into      addis r3, r13, x@tprel@ha
391
11
  // bl __tls_get_addr(x@tlsgd)      into      nop
392
11
  // nop                             into      addi r3, r3, x@tprel@l
393
11
394
11
  switch (type) {
395
11
  case R_PPC64_GOT_TLSGD16_HA:
396
3
    writeFromHalf16(loc, 0x60000000); // nop
397
3
    break;
398
11
  case R_PPC64_GOT_TLSGD16:
399
4
  case R_PPC64_GOT_TLSGD16_LO:
400
4
    writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13
401
4
    relocateOne(loc, R_PPC64_TPREL16_HA, val);
402
4
    break;
403
4
  case R_PPC64_TLSGD:
404
4
    write32(loc, 0x60000000);     // nop
405
4
    write32(loc + 4, 0x38630000); // addi r3, r3
406
4
    // Since we are relocating a half16 type relocation and Loc + 4 points to
407
4
    // the start of an instruction we need to advance the buffer by an extra
408
4
    // 2 bytes on BE.
409
4
    relocateOne(loc + 4 + (config->ekind == ELF64BEKind ? 
20
: 0),
410
4
                R_PPC64_TPREL16_LO, val);
411
4
    break;
412
4
  default:
413
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
414
11
  }
415
11
}
416
417
10
void PPC64::relaxTlsLdToLe(uint8_t *loc, RelType type, uint64_t val) const {
418
10
  // Reference: 3.7.4.3 of the 64-bit ELF V2 abi supplement.
419
10
  // The local dynamic code sequence for a global `x` will look like:
420
10
  // Instruction                    Relocation                Symbol
421
10
  // addis r3, r2, x@got@tlsld@ha   R_PPC64_GOT_TLSLD16_HA      x
422
10
  // addi  r3, r3, x@got@tlsld@l    R_PPC64_GOT_TLSLD16_LO      x
423
10
  // bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSLD               x
424
10
  //                                R_PPC64_REL24               __tls_get_addr
425
10
  // nop                            None                       None
426
10
427
10
  // Relaxing to local exec entails converting:
428
10
  // addis r3, r2, x@got@tlsld@ha   into      nop
429
10
  // addi  r3, r3, x@got@tlsld@l    into      addis r3, r13, 0
430
10
  // bl __tls_get_addr(x@tlsgd)     into      nop
431
10
  // nop                            into      addi r3, r3, 4096
432
10
433
10
  switch (type) {
434
10
  case R_PPC64_GOT_TLSLD16_HA:
435
2
    writeFromHalf16(loc, 0x60000000); // nop
436
2
    break;
437
10
  case R_PPC64_GOT_TLSLD16_LO:
438
2
    writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13, 0
439
2
    break;
440
10
  case R_PPC64_TLSLD:
441
2
    write32(loc, 0x60000000);     // nop
442
2
    write32(loc + 4, 0x38631000); // addi r3, r3, 4096
443
2
    break;
444
10
  case R_PPC64_DTPREL16:
445
4
  case R_PPC64_DTPREL16_HA:
446
4
  case R_PPC64_DTPREL16_HI:
447
4
  case R_PPC64_DTPREL16_DS:
448
4
  case R_PPC64_DTPREL16_LO:
449
4
  case R_PPC64_DTPREL16_LO_DS:
450
4
    relocateOne(loc, type, val);
451
4
    break;
452
4
  default:
453
0
    llvm_unreachable("unsupported relocation for TLS LD to LE relaxation");
454
10
  }
455
10
}
456
457
27
unsigned elf::getPPCDFormOp(unsigned secondaryOp) {
458
27
  switch (secondaryOp) {
459
27
  case LBZX:
460
3
    return LBZ;
461
27
  case LHZX:
462
3
    return LHZ;
463
27
  case LWZX:
464
3
    return LWZ;
465
27
  case LDX:
466
2
    return LD;
467
27
  case STBX:
468
3
    return STB;
469
27
  case STHX:
470
3
    return STH;
471
27
  case STWX:
472
3
    return STW;
473
27
  case STDX:
474
4
    return STD;
475
27
  case ADD:
476
3
    return ADDI;
477
27
  default:
478
0
    return 0;
479
27
  }
480
27
}
481
482
58
void PPC64::relaxTlsIeToLe(uint8_t *loc, RelType type, uint64_t val) const {
483
58
  // The initial exec code sequence for a global `x` will look like:
484
58
  // Instruction                    Relocation                Symbol
485
58
  // addis r9, r2, x@got@tprel@ha   R_PPC64_GOT_TPREL16_HA      x
486
58
  // ld    r9, x@got@tprel@l(r9)    R_PPC64_GOT_TPREL16_LO_DS   x
487
58
  // add r9, r9, x@tls              R_PPC64_TLS                 x
488
58
489
58
  // Relaxing to local exec entails converting:
490
58
  // addis r9, r2, x@got@tprel@ha       into        nop
491
58
  // ld r9, x@got@tprel@l(r9)           into        addis r9, r13, x@tprel@ha
492
58
  // add r9, r9, x@tls                  into        addi r9, r9, x@tprel@l
493
58
494
58
  // x@tls R_PPC64_TLS is a relocation which does not compute anything,
495
58
  // it is replaced with r13 (thread pointer).
496
58
497
58
  // The add instruction in the initial exec sequence has multiple variations
498
58
  // that need to be handled. If we are building an address it will use an add
499
58
  // instruction, if we are accessing memory it will use any of the X-form
500
58
  // indexed load or store instructions.
501
58
502
58
  unsigned offset = (config->ekind == ELF64BEKind) ? 
229
:
029
;
503
58
  switch (type) {
504
58
  case R_PPC64_GOT_TPREL16_HA:
505
18
    write32(loc - offset, 0x60000000); // nop
506
18
    break;
507
58
  case R_PPC64_GOT_TPREL16_LO_DS:
508
20
  case R_PPC64_GOT_TPREL16_DS: {
509
20
    uint32_t regNo = read32(loc - offset) & 0x03E00000; // bits 6-10
510
20
    write32(loc - offset, 0x3C0D0000 | regNo);          // addis RegNo, r13
511
20
    relocateOne(loc, R_PPC64_TPREL16_HA, val);
512
20
    break;
513
20
  }
514
20
  case R_PPC64_TLS: {
515
20
    uint32_t primaryOp = getPrimaryOpCode(read32(loc));
516
20
    if (primaryOp != 31)
517
0
      error("unrecognized instruction for IE to LE R_PPC64_TLS");
518
20
    uint32_t secondaryOp = (read32(loc) & 0x000007FE) >> 1; // bits 21-30
519
20
    uint32_t dFormOp = getPPCDFormOp(secondaryOp);
520
20
    if (dFormOp == 0)
521
0
      error("unrecognized instruction for IE to LE R_PPC64_TLS");
522
20
    write32(loc, ((dFormOp << 26) | (read32(loc) & 0x03FFFFFF)));
523
20
    relocateOne(loc + offset, R_PPC64_TPREL16_LO, val);
524
20
    break;
525
20
  }
526
20
  default:
527
0
    llvm_unreachable("unknown relocation for IE to LE");
528
20
    
break0
;
529
58
  }
530
58
}
531
532
RelExpr PPC64::getRelExpr(RelType type, const Symbol &s,
533
995
                          const uint8_t *loc) const {
534
995
  switch (type) {
535
995
  case R_PPC64_GOT16:
536
24
  case R_PPC64_GOT16_DS:
537
24
  case R_PPC64_GOT16_HA:
538
24
  case R_PPC64_GOT16_HI:
539
24
  case R_PPC64_GOT16_LO:
540
24
  case R_PPC64_GOT16_LO_DS:
541
24
    return R_GOT_OFF;
542
35
  case R_PPC64_TOC16:
543
35
  case R_PPC64_TOC16_DS:
544
35
  case R_PPC64_TOC16_HI:
545
35
  case R_PPC64_TOC16_LO:
546
35
    return R_GOTREL;
547
162
  case R_PPC64_TOC16_HA:
548
162
  case R_PPC64_TOC16_LO_DS:
549
162
    return config->tocOptimize ? 
R_PPC64_RELAX_TOC117
:
R_GOTREL45
;
550
162
  case R_PPC64_TOC:
551
4
    return R_PPC64_TOCBASE;
552
162
  case R_PPC64_REL14:
553
143
  case R_PPC64_REL24:
554
143
    return R_PPC64_CALL_PLT;
555
282
  case R_PPC64_REL16_LO:
556
282
  case R_PPC64_REL16_HA:
557
282
  case R_PPC64_REL32:
558
282
  case R_PPC64_REL64:
559
282
    return R_PC;
560
282
  case R_PPC64_GOT_TLSGD16:
561
15
  case R_PPC64_GOT_TLSGD16_HA:
562
15
  case R_PPC64_GOT_TLSGD16_HI:
563
15
  case R_PPC64_GOT_TLSGD16_LO:
564
15
    return R_TLSGD_GOT;
565
24
  case R_PPC64_GOT_TLSLD16:
566
24
  case R_PPC64_GOT_TLSLD16_HA:
567
24
  case R_PPC64_GOT_TLSLD16_HI:
568
24
  case R_PPC64_GOT_TLSLD16_LO:
569
24
    return R_TLSLD_GOT;
570
76
  case R_PPC64_GOT_TPREL16_HA:
571
76
  case R_PPC64_GOT_TPREL16_LO_DS:
572
76
  case R_PPC64_GOT_TPREL16_DS:
573
76
  case R_PPC64_GOT_TPREL16_HI:
574
76
    return R_GOT_OFF;
575
76
  case R_PPC64_GOT_DTPREL16_HA:
576
16
  case R_PPC64_GOT_DTPREL16_LO_DS:
577
16
  case R_PPC64_GOT_DTPREL16_DS:
578
16
  case R_PPC64_GOT_DTPREL16_HI:
579
16
    return R_TLSLD_GOT_OFF;
580
16
  case R_PPC64_TPREL16:
581
14
  case R_PPC64_TPREL16_HA:
582
14
  case R_PPC64_TPREL16_LO:
583
14
  case R_PPC64_TPREL16_HI:
584
14
  case R_PPC64_TPREL16_DS:
585
14
  case R_PPC64_TPREL16_LO_DS:
586
14
  case R_PPC64_TPREL16_HIGHER:
587
14
  case R_PPC64_TPREL16_HIGHERA:
588
14
  case R_PPC64_TPREL16_HIGHEST:
589
14
  case R_PPC64_TPREL16_HIGHESTA:
590
14
    return R_TLS;
591
35
  case R_PPC64_DTPREL16:
592
35
  case R_PPC64_DTPREL16_DS:
593
35
  case R_PPC64_DTPREL16_HA:
594
35
  case R_PPC64_DTPREL16_HI:
595
35
  case R_PPC64_DTPREL16_HIGHER:
596
35
  case R_PPC64_DTPREL16_HIGHERA:
597
35
  case R_PPC64_DTPREL16_HIGHEST:
598
35
  case R_PPC64_DTPREL16_HIGHESTA:
599
35
  case R_PPC64_DTPREL16_LO:
600
35
  case R_PPC64_DTPREL16_LO_DS:
601
35
  case R_PPC64_DTPREL64:
602
35
    return R_DTPREL;
603
35
  case R_PPC64_TLSGD:
604
9
    return R_TLSDESC_CALL;
605
35
  case R_PPC64_TLSLD:
606
10
    return R_TLSLD_HINT;
607
40
  case R_PPC64_TLS:
608
40
    return R_TLSIE_HINT;
609
106
  default:
610
106
    return R_ABS;
611
995
  }
612
995
}
613
614
29
RelType PPC64::getDynRel(RelType type) const {
615
29
  if (type == R_PPC64_ADDR64 || 
type == R_PPC64_TOC3
)
616
28
    return R_PPC64_ADDR64;
617
1
  return R_PPC64_NONE;
618
1
}
619
620
92
void PPC64::writeGotHeader(uint8_t *buf) const {
621
92
  write64(buf, getPPC64TocBase());
622
92
}
623
624
21
void PPC64::writePltHeader(uint8_t *buf) const {
625
21
  // The generic resolver stub goes first.
626
21
  write32(buf +  0, 0x7c0802a6); // mflr r0
627
21
  write32(buf +  4, 0x429f0005); // bcl  20,4*cr7+so,8 <_glink+0x8>
628
21
  write32(buf +  8, 0x7d6802a6); // mflr r11
629
21
  write32(buf + 12, 0x7c0803a6); // mtlr r0
630
21
  write32(buf + 16, 0x7d8b6050); // subf r12, r11, r12
631
21
  write32(buf + 20, 0x380cffcc); // subi r0,r12,52
632
21
  write32(buf + 24, 0x7800f082); // srdi r0,r0,62,2
633
21
  write32(buf + 28, 0xe98b002c); // ld   r12,44(r11)
634
21
  write32(buf + 32, 0x7d6c5a14); // add  r11,r12,r11
635
21
  write32(buf + 36, 0xe98b0000); // ld   r12,0(r11)
636
21
  write32(buf + 40, 0xe96b0008); // ld   r11,8(r11)
637
21
  write32(buf + 44, 0x7d8903a6); // mtctr   r12
638
21
  write32(buf + 48, 0x4e800420); // bctr
639
21
640
21
  // The 'bcl' instruction will set the link register to the address of the
641
21
  // following instruction ('mflr r11'). Here we store the offset from that
642
21
  // instruction  to the first entry in the GotPlt section.
643
21
  int64_t gotPltOffset = in.gotPlt->getVA() - (in.plt->getVA() + 8);
644
21
  write64(buf + 52, gotPltOffset);
645
21
}
646
647
void PPC64::writePlt(uint8_t *buf, uint64_t gotPltEntryAddr,
648
                     uint64_t pltEntryAddr, int32_t index,
649
27
                     unsigned relOff) const {
650
27
  int32_t offset = pltHeaderSize + index * pltEntrySize;
651
27
  // bl __glink_PLTresolve
652
27
  write32(buf, 0x48000000 | ((-offset) & 0x03FFFFFc));
653
27
}
654
655
908
static std::pair<RelType, uint64_t> toAddr16Rel(RelType type, uint64_t val) {
656
908
  // Relocations relative to the toc-base need to be adjusted by the Toc offset.
657
908
  uint64_t tocBiasedVal = val - ppc64TocOffset;
658
908
  // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset.
659
908
  uint64_t dtpBiasedVal = val - dynamicThreadPointerOffset;
660
908
661
908
  switch (type) {
662
908
  // TOC biased relocation.
663
908
  case R_PPC64_GOT16:
664
7
  case R_PPC64_GOT_TLSGD16:
665
7
  case R_PPC64_GOT_TLSLD16:
666
7
  case R_PPC64_TOC16:
667
7
    return {R_PPC64_ADDR16, tocBiasedVal};
668
25
  case R_PPC64_GOT16_DS:
669
25
  case R_PPC64_TOC16_DS:
670
25
  case R_PPC64_GOT_TPREL16_DS:
671
25
  case R_PPC64_GOT_DTPREL16_DS:
672
25
    return {R_PPC64_ADDR16_DS, tocBiasedVal};
673
126
  case R_PPC64_GOT16_HA:
674
126
  case R_PPC64_GOT_TLSGD16_HA:
675
126
  case R_PPC64_GOT_TLSLD16_HA:
676
126
  case R_PPC64_GOT_TPREL16_HA:
677
126
  case R_PPC64_GOT_DTPREL16_HA:
678
126
  case R_PPC64_TOC16_HA:
679
126
    return {R_PPC64_ADDR16_HA, tocBiasedVal};
680
126
  case R_PPC64_GOT16_HI:
681
12
  case R_PPC64_GOT_TLSGD16_HI:
682
12
  case R_PPC64_GOT_TLSLD16_HI:
683
12
  case R_PPC64_GOT_TPREL16_HI:
684
12
  case R_PPC64_GOT_DTPREL16_HI:
685
12
  case R_PPC64_TOC16_HI:
686
12
    return {R_PPC64_ADDR16_HI, tocBiasedVal};
687
59
  case R_PPC64_GOT16_LO:
688
59
  case R_PPC64_GOT_TLSGD16_LO:
689
59
  case R_PPC64_GOT_TLSLD16_LO:
690
59
  case R_PPC64_TOC16_LO:
691
59
    return {R_PPC64_ADDR16_LO, tocBiasedVal};
692
74
  case R_PPC64_GOT16_LO_DS:
693
74
  case R_PPC64_TOC16_LO_DS:
694
74
  case R_PPC64_GOT_TPREL16_LO_DS:
695
74
  case R_PPC64_GOT_DTPREL16_LO_DS:
696
74
    return {R_PPC64_ADDR16_LO_DS, tocBiasedVal};
697
74
698
74
  // Dynamic Thread pointer biased relocation types.
699
74
  case R_PPC64_DTPREL16:
700
2
    return {R_PPC64_ADDR16, dtpBiasedVal};
701
74
  case R_PPC64_DTPREL16_DS:
702
2
    return {R_PPC64_ADDR16_DS, dtpBiasedVal};
703
74
  case R_PPC64_DTPREL16_HA:
704
7
    return {R_PPC64_ADDR16_HA, dtpBiasedVal};
705
74
  case R_PPC64_DTPREL16_HI:
706
2
    return {R_PPC64_ADDR16_HI, dtpBiasedVal};
707
74
  case R_PPC64_DTPREL16_HIGHER:
708
2
    return {R_PPC64_ADDR16_HIGHER, dtpBiasedVal};
709
74
  case R_PPC64_DTPREL16_HIGHERA:
710
3
    return {R_PPC64_ADDR16_HIGHERA, dtpBiasedVal};
711
74
  case R_PPC64_DTPREL16_HIGHEST:
712
2
    return {R_PPC64_ADDR16_HIGHEST, dtpBiasedVal};
713
74
  case R_PPC64_DTPREL16_HIGHESTA:
714
3
    return {R_PPC64_ADDR16_HIGHESTA, dtpBiasedVal};
715
74
  case R_PPC64_DTPREL16_LO:
716
7
    return {R_PPC64_ADDR16_LO, dtpBiasedVal};
717
74
  case R_PPC64_DTPREL16_LO_DS:
718
2
    return {R_PPC64_ADDR16_LO_DS, dtpBiasedVal};
719
74
  case R_PPC64_DTPREL64:
720
11
    return {R_PPC64_ADDR64, dtpBiasedVal};
721
74
722
562
  default:
723
562
    return {type, val};
724
908
  }
725
908
}
726
727
908
static bool isTocOptType(RelType type) {
728
908
  switch (type) {
729
908
  case R_PPC64_GOT16_HA:
730
188
  case R_PPC64_GOT16_LO_DS:
731
188
  case R_PPC64_TOC16_HA:
732
188
  case R_PPC64_TOC16_LO_DS:
733
188
  case R_PPC64_TOC16_LO:
734
188
    return true;
735
720
  default:
736
720
    return false;
737
908
  }
738
908
}
739
740
908
void PPC64::relocateOne(uint8_t *loc, RelType type, uint64_t val) const {
741
908
  // We need to save the original relocation type to use in diagnostics, and
742
908
  // use the original type to determine if we should toc-optimize the
743
908
  // instructions being relocated.
744
908
  RelType originalType = type;
745
908
  bool shouldTocOptimize =  isTocOptType(type);
746
908
  // For dynamic thread pointer relative, toc-relative, and got-indirect
747
908
  // relocations, proceed in terms of the corresponding ADDR16 relocation type.
748
908
  std::tie(type, val) = toAddr16Rel(type, val);
749
908
750
908
  switch (type) {
751
908
  case R_PPC64_ADDR14: {
752
0
    checkAlignment(loc, val, 4, type);
753
0
    // Preserve the AA/LK bits in the branch instruction
754
0
    uint8_t aalk = loc[3];
755
0
    write16(loc + 2, (aalk & 3) | (val & 0xfffc));
756
0
    break;
757
908
  }
758
908
  case R_PPC64_ADDR16:
759
15
    checkIntUInt(loc, val, 16, originalType);
760
15
    write16(loc, val);
761
15
    break;
762
908
  case R_PPC64_ADDR32:
763
6
    checkIntUInt(loc, val, 32, originalType);
764
6
    write32(loc, val);
765
6
    break;
766
908
  case R_PPC64_ADDR16_DS:
767
28
  case R_PPC64_TPREL16_DS: {
768
28
    checkInt(loc, val, 16, originalType);
769
28
    // DQ-form instructions use bits 28-31 as part of the instruction encoding
770
28
    // DS-form instructions only use bits 30-31.
771
28
    uint16_t mask = isDQFormInstruction(readFromHalf16(loc)) ? 
0xf0
: 0x3;
772
28
    checkAlignment(loc, lo(val), mask + 1, originalType);
773
28
    write16(loc, (read16(loc) & mask) | lo(val));
774
28
  } break;
775
297
  case R_PPC64_ADDR16_HA:
776
297
  case R_PPC64_REL16_HA:
777
297
  case R_PPC64_TPREL16_HA:
778
297
    if (config->tocOptimize && 
shouldTocOptimize252
&&
ha(val) == 065
)
779
39
      writeFromHalf16(loc, 0x60000000);
780
258
    else
781
258
      write16(loc, ha(val));
782
297
    break;
783
297
  case R_PPC64_ADDR16_HI:
784
18
  case R_PPC64_REL16_HI:
785
18
  case R_PPC64_TPREL16_HI:
786
18
    write16(loc, hi(val));
787
18
    break;
788
18
  case R_PPC64_ADDR16_HIGHER:
789
5
  case R_PPC64_TPREL16_HIGHER:
790
5
    write16(loc, higher(val));
791
5
    break;
792
6
  case R_PPC64_ADDR16_HIGHERA:
793
6
  case R_PPC64_TPREL16_HIGHERA:
794
6
    write16(loc, highera(val));
795
6
    break;
796
6
  case R_PPC64_ADDR16_HIGHEST:
797
5
  case R_PPC64_TPREL16_HIGHEST:
798
5
    write16(loc, highest(val));
799
5
    break;
800
6
  case R_PPC64_ADDR16_HIGHESTA:
801
6
  case R_PPC64_TPREL16_HIGHESTA:
802
6
    write16(loc, highesta(val));
803
6
    break;
804
231
  case R_PPC64_ADDR16_LO:
805
231
  case R_PPC64_REL16_LO:
806
231
  case R_PPC64_TPREL16_LO:
807
231
    // When the high-adjusted part of a toc relocation evalutes to 0, it is
808
231
    // changed into a nop. The lo part then needs to be updated to use the
809
231
    // toc-pointer register r2, as the base register.
810
231
    if (config->tocOptimize && 
shouldTocOptimize203
&&
ha(val) == 036
) {
811
18
      uint32_t insn = readFromHalf16(loc);
812
18
      if (isInstructionUpdateForm(insn))
813
0
        error(getErrorLocation(loc) +
814
0
              "can't toc-optimize an update instruction: 0x" +
815
0
              utohexstr(insn));
816
18
      writeFromHalf16(loc, (insn & 0xffe00000) | 0x00020000 | lo(val));
817
213
    } else {
818
213
      write16(loc, lo(val));
819
213
    }
820
231
    break;
821
231
  case R_PPC64_ADDR16_LO_DS:
822
77
  case R_PPC64_TPREL16_LO_DS: {
823
77
    // DQ-form instructions use bits 28-31 as part of the instruction encoding
824
77
    // DS-form instructions only use bits 30-31.
825
77
    uint32_t insn = readFromHalf16(loc);
826
77
    uint16_t mask = isDQFormInstruction(insn) ? 
0xf12
:
0x365
;
827
77
    checkAlignment(loc, lo(val), mask + 1, originalType);
828
77
    if (config->tocOptimize && 
shouldTocOptimize56
&&
ha(val) == 029
) {
829
21
      // When the high-adjusted part of a toc relocation evalutes to 0, it is
830
21
      // changed into a nop. The lo part then needs to be updated to use the toc
831
21
      // pointer register r2, as the base register.
832
21
      if (isInstructionUpdateForm(insn))
833
0
        error(getErrorLocation(loc) +
834
0
              "Can't toc-optimize an update instruction: 0x" +
835
0
              Twine::utohexstr(insn));
836
21
      insn &= 0xffe00000 | mask;
837
21
      writeFromHalf16(loc, insn | 0x00020000 | lo(val));
838
56
    } else {
839
56
      write16(loc, (read16(loc) & mask) | lo(val));
840
56
    }
841
77
  } break;
842
77
  case R_PPC64_TPREL16:
843
1
    checkInt(loc, val, 16, originalType);
844
1
    write16(loc, val);
845
1
    break;
846
77
  case R_PPC64_REL32:
847
12
    checkInt(loc, val, 32, type);
848
12
    write32(loc, val);
849
12
    break;
850
77
  case R_PPC64_ADDR64:
851
64
  case R_PPC64_REL64:
852
64
  case R_PPC64_TOC:
853
64
    write64(loc, val);
854
64
    break;
855
64
  case R_PPC64_REL14: {
856
0
    uint32_t mask = 0x0000FFFC;
857
0
    checkInt(loc, val, 16, type);
858
0
    checkAlignment(loc, val, 4, type);
859
0
    write32(loc, (read32(loc) & ~mask) | (val & mask));
860
0
    break;
861
64
  }
862
137
  case R_PPC64_REL24: {
863
137
    uint32_t mask = 0x03FFFFFC;
864
137
    checkInt(loc, val, 26, type);
865
137
    checkAlignment(loc, val, 4, type);
866
137
    write32(loc, (read32(loc) & ~mask) | (val & mask));
867
137
    break;
868
64
  }
869
64
  case R_PPC64_DTPREL64:
870
0
    write64(loc, val - dynamicThreadPointerOffset);
871
0
    break;
872
64
  default:
873
0
    error(getErrorLocation(loc) + "unrecognized relocation " + toString(type));
874
908
  }
875
908
}
876
877
bool PPC64::needsThunk(RelExpr expr, RelType type, const InputFile *file,
878
978
                       uint64_t branchAddr, const Symbol &s) const {
879
978
  if (type != R_PPC64_REL14 && type != R_PPC64_REL24)
880
829
    return false;
881
149
882
149
  // If a function is in the Plt it needs to be called with a call-stub.
883
149
  if (s.isInPlt())
884
35
    return true;
885
114
886
114
  // If a symbol is a weak undefined and we are compiling an executable
887
114
  // it doesn't need a range-extending thunk since it can't be called.
888
114
  if (s.isUndefWeak() && 
!config->shared2
)
889
2
    return false;
890
112
891
112
  // If the offset exceeds the range of the branch type then it will need
892
112
  // a range-extending thunk.
893
112
  // See the comment in getRelocTargetVA() about R_PPC64_CALL.
894
112
  return !inBranchRange(type, branchAddr,
895
112
                        s.getVA() +
896
112
                            getPPC64GlobalEntryToLocalEntryOffset(s.stOther));
897
112
}
898
899
298
uint32_t PPC64::getThunkSectionSpacing() const {
900
298
  // See comment in Arch/ARM.cpp for a more detailed explanation of
901
298
  // getThunkSectionSpacing(). For PPC64 we pick the constant here based on
902
298
  // R_PPC64_REL24, which is used by unconditional branch instructions.
903
298
  // 0x2000000 = (1 << 24-1) * 4
904
298
  return 0x2000000;
905
298
}
906
907
210
bool PPC64::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
908
210
  int64_t offset = dst - src;
909
210
  if (type == R_PPC64_REL14)
910
0
    return isInt<16>(offset);
911
210
  if (type == R_PPC64_REL24)
912
210
    return isInt<26>(offset);
913
0
  llvm_unreachable("unsupported relocation type used in branch");
914
0
}
915
916
RelExpr PPC64::adjustRelaxExpr(RelType type, const uint8_t *data,
917
26
                               RelExpr expr) const {
918
26
  if (expr == R_RELAX_TLS_GD_TO_IE)
919
5
    return R_RELAX_TLS_GD_TO_IE_GOT_OFF;
920
21
  if (expr == R_RELAX_TLS_LD_TO_LE)
921
10
    return R_RELAX_TLS_LD_TO_LE_ABS;
922
11
  return expr;
923
11
}
924
925
// Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement.
926
// The general dynamic code sequence for a global `x` uses 4 instructions.
927
// Instruction                    Relocation                Symbol
928
// addis r3, r2, x@got@tlsgd@ha   R_PPC64_GOT_TLSGD16_HA      x
929
// addi  r3, r3, x@got@tlsgd@l    R_PPC64_GOT_TLSGD16_LO      x
930
// bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSGD               x
931
//                                R_PPC64_REL24               __tls_get_addr
932
// nop                            None                       None
933
//
934
// Relaxing to initial-exec entails:
935
// 1) Convert the addis/addi pair that builds the address of the tls_index
936
//    struct for 'x' to an addis/ld pair that loads an offset from a got-entry.
937
// 2) Convert the call to __tls_get_addr to a nop.
938
// 3) Convert the nop following the call to an add of the loaded offset to the
939
//    thread pointer.
940
// Since the nop must directly follow the call, the R_PPC64_TLSGD relocation is
941
// used as the relaxation hint for both steps 2 and 3.
942
5
void PPC64::relaxTlsGdToIe(uint8_t *loc, RelType type, uint64_t val) const {
943
5
  switch (type) {
944
5
  case R_PPC64_GOT_TLSGD16_HA:
945
1
    // This is relaxed from addis rT, r2, sym@got@tlsgd@ha to
946
1
    //                      addis rT, r2, sym@got@tprel@ha.
947
1
    relocateOne(loc, R_PPC64_GOT_TPREL16_HA, val);
948
1
    return;
949
5
  case R_PPC64_GOT_TLSGD16:
950
2
  case R_PPC64_GOT_TLSGD16_LO: {
951
2
    // Relax from addi  r3, rA, sym@got@tlsgd@l to
952
2
    //            ld r3, sym@got@tprel@l(rA)
953
2
    uint32_t ra = (readFromHalf16(loc) & (0x1f << 16));
954
2
    writeFromHalf16(loc, 0xe8600000 | ra);
955
2
    relocateOne(loc, R_PPC64_GOT_TPREL16_LO_DS, val);
956
2
    return;
957
2
  }
958
2
  case R_PPC64_TLSGD:
959
2
    write32(loc, 0x60000000);     // bl __tls_get_addr(sym@tlsgd) --> nop
960
2
    write32(loc + 4, 0x7c636A14); // nop --> add r3, r3, r13
961
2
    return;
962
2
  default:
963
0
    llvm_unreachable("unsupported relocation for TLS GD to IE relaxation");
964
5
  }
965
5
}
966
967
// The prologue for a split-stack function is expected to look roughly
968
// like this:
969
//    .Lglobal_entry_point:
970
//      # TOC pointer initalization.
971
//      ...
972
//    .Llocal_entry_point:
973
//      # load the __private_ss member of the threads tcbhead.
974
//      ld r0,-0x7000-64(r13)
975
//      # subtract the functions stack size from the stack pointer.
976
//      addis r12, r1, ha(-stack-frame size)
977
//      addi  r12, r12, l(-stack-frame size)
978
//      # compare needed to actual and branch to allocate_more_stack if more
979
//      # space is needed, otherwise fallthrough to 'normal' function body.
980
//      cmpld cr7,r12,r0
981
//      blt- cr7, .Lallocate_more_stack
982
//
983
// -) The allocate_more_stack block might be placed after the split-stack
984
//    prologue and the `blt-` replaced with a `bge+ .Lnormal_func_body`
985
//    instead.
986
// -) If either the addis or addi is not needed due to the stack size being
987
//    smaller then 32K or a multiple of 64K they will be replaced with a nop,
988
//    but there will always be 2 instructions the linker can overwrite for the
989
//    adjusted stack size.
990
//
991
// The linkers job here is to increase the stack size used in the addis/addi
992
// pair by split-stack-size-adjust.
993
// addis r12, r1, ha(-stack-frame size - split-stack-adjust-size)
994
// addi  r12, r12, l(-stack-frame size - split-stack-adjust-size)
995
bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end,
996
22
                                             uint8_t stOther) const {
997
22
  // If the caller has a global entry point adjust the buffer past it. The start
998
22
  // of the split-stack prologue will be at the local entry point.
999
22
  loc += getPPC64GlobalEntryToLocalEntryOffset(stOther);
1000
22
1001
22
  // At the very least we expect to see a load of some split-stack data from the
1002
22
  // tcb, and 2 instructions that calculate the ending stack address this
1003
22
  // function will require. If there is not enough room for at least 3
1004
22
  // instructions it can't be a split-stack prologue.
1005
22
  if (loc + 12 >= end)
1006
0
    return false;
1007
22
1008
22
  // First instruction must be `ld r0, -0x7000-64(r13)`
1009
22
  if (read32(loc) != 0xe80d8fc0)
1010
0
    return false;
1011
22
1012
22
  int16_t hiImm = 0;
1013
22
  int16_t loImm = 0;
1014
22
  // First instruction can be either an addis if the frame size is larger then
1015
22
  // 32K, or an addi if the size is less then 32K.
1016
22
  int32_t firstInstr = read32(loc + 4);
1017
22
  if (getPrimaryOpCode(firstInstr) == 15) {
1018
12
    hiImm = firstInstr & 0xFFFF;
1019
12
  } else 
if (10
getPrimaryOpCode(firstInstr) == 1410
) {
1020
10
    loImm = firstInstr & 0xFFFF;
1021
10
  } else {
1022
0
    return false;
1023
0
  }
1024
22
1025
22
  // Second instruction is either an addi or a nop. If the first instruction was
1026
22
  // an addi then LoImm is set and the second instruction must be a nop.
1027
22
  uint32_t secondInstr = read32(loc + 8);
1028
22
  if (!loImm && 
getPrimaryOpCode(secondInstr) == 1412
) {
1029
10
    loImm = secondInstr & 0xFFFF;
1030
12
  } else if (secondInstr != 0x60000000) {
1031
0
    return false;
1032
0
  }
1033
22
1034
22
  // The register operands of the first instruction should be the stack-pointer
1035
22
  // (r1) as the input (RA) and r12 as the output (RT). If the second
1036
22
  // instruction is not a nop, then it should use r12 as both input and output.
1037
22
  auto checkRegOperands = [](uint32_t instr, uint8_t expectedRT,
1038
30
                             uint8_t expectedRA) {
1039
30
    return ((instr & 0x3E00000) >> 21 == expectedRT) &&
1040
30
           
((instr & 0x1F0000) >> 16 == expectedRA)28
;
1041
30
  };
1042
22
  if (!checkRegOperands(firstInstr, 12, 1))
1043
2
    return false;
1044
20
  if (secondInstr != 0x60000000 && 
!checkRegOperands(secondInstr, 12, 12)8
)
1045
0
    return false;
1046
20
1047
20
  int32_t stackFrameSize = (hiImm * 65536) + loImm;
1048
20
  // Check that the adjusted size doesn't overflow what we can represent with 2
1049
20
  // instructions.
1050
20
  if (stackFrameSize < config->splitStackAdjustSize + INT32_MIN) {
1051
4
    error(getErrorLocation(loc) + "split-stack prologue adjustment overflows");
1052
4
    return false;
1053
4
  }
1054
16
1055
16
  int32_t adjustedStackFrameSize =
1056
16
      stackFrameSize - config->splitStackAdjustSize;
1057
16
1058
16
  loImm = adjustedStackFrameSize & 0xFFFF;
1059
16
  hiImm = (adjustedStackFrameSize + 0x8000) >> 16;
1060
16
  if (hiImm) {
1061
10
    write32(loc + 4, 0x3D810000 | (uint16_t)hiImm);
1062
10
    // If the low immediate is zero the second instruction will be a nop.
1063
10
    secondInstr = loImm ? 
0x398C0000 | (uint16_t)loImm8
:
0x600000002
;
1064
10
    write32(loc + 8, secondInstr);
1065
10
  } else {
1066
6
    // addi r12, r1, imm
1067
6
    write32(loc + 4, (0x39810000) | (uint16_t)loImm);
1068
6
    write32(loc + 8, 0x60000000);
1069
6
  }
1070
16
1071
16
  return true;
1072
16
}
1073
1074
307
TargetInfo *elf::getPPC64TargetInfo() {
1075
307
  static PPC64 target;
1076
307
  return &target;
1077
307
}