Coverage Report

Created: 2018-10-20 06:24

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/PPC64.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- PPC64.cpp ----------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#include "Symbols.h"
11
#include "SyntheticSections.h"
12
#include "Target.h"
13
#include "lld/Common/ErrorHandler.h"
14
#include "llvm/Support/Endian.h"
15
16
using namespace llvm;
17
using namespace llvm::object;
18
using namespace llvm::support::endian;
19
using namespace llvm::ELF;
20
using namespace lld;
21
using namespace lld::elf;
22
23
static uint64_t PPC64TocOffset = 0x8000;
24
static uint64_t DynamicThreadPointerOffset = 0x8000;
25
26
// The instruction encoding of bits 21-30 from the ISA for the Xform and Dform
27
// instructions that can be used as part of the initial exec TLS sequence.
28
enum XFormOpcd {
29
  LBZX = 87,
30
  LHZX = 279,
31
  LWZX = 23,
32
  LDX = 21,
33
  STBX = 215,
34
  STHX = 407,
35
  STWX = 151,
36
  STDX = 149,
37
  ADD = 266,
38
};
39
40
enum DFormOpcd {
41
  LBZ = 34,
42
  LBZU = 35,
43
  LHZ = 40,
44
  LHZU = 41,
45
  LHAU = 43,
46
  LWZ = 32,
47
  LWZU = 33,
48
  LFSU = 49,
49
  LD = 58,
50
  LFDU = 51,
51
  STB = 38,
52
  STBU = 39,
53
  STH = 44,
54
  STHU = 45,
55
  STW = 36,
56
  STWU = 37,
57
  STFSU = 53,
58
  STFDU = 55,
59
  STD = 62,
60
  ADDI = 14
61
};
62
63
105
uint64_t elf::getPPC64TocBase() {
64
105
  // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
65
105
  // TOC starts where the first of these sections starts. We always create a
66
105
  // .got when we see a relocation that uses it, so for us the start is always
67
105
  // the .got.
68
105
  uint64_t TocVA = In.Got->getVA();
69
105
70
105
  // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
71
105
  // thus permitting a full 64 Kbytes segment. Note that the glibc startup
72
105
  // code (crt1.o) assumes that you can get from the TOC base to the
73
105
  // start of the .toc section with only a single (signed) 16-bit relocation.
74
105
  return TocVA + PPC64TocOffset;
75
105
}
76
77
78
159
unsigned elf::getPPC64GlobalEntryToLocalEntryOffset(uint8_t StOther) {
79
159
  // The offset is encoded into the 3 most significant bits of the st_other
80
159
  // field, with some special values described in section 3.4.1 of the ABI:
81
159
  // 0   --> Zero offset between the GEP and LEP, and the function does NOT use
82
159
  //         the TOC pointer (r2). r2 will hold the same value on returning from
83
159
  //         the function as it did on entering the function.
84
159
  // 1   --> Zero offset between the GEP and LEP, and r2 should be treated as a
85
159
  //         caller-saved register for all callers.
86
159
  // 2-6 --> The  binary logarithm of the offset eg:
87
159
  //         2 --> 2^2 = 4 bytes -->  1 instruction.
88
159
  //         6 --> 2^6 = 64 bytes --> 16 instructions.
89
159
  // 7   --> Reserved.
90
159
  uint8_t GepToLep = (StOther >> 5) & 7;
91
159
  if (GepToLep < 2)
92
117
    return 0;
93
42
94
42
  // The value encoded in the st_other bits is the
95
42
  // log-base-2(offset).
96
42
  if (GepToLep < 7)
97
42
    return 1 << GepToLep;
98
0
99
0
  error("reserved value of 7 in the 3 most-significant-bits of st_other");
100
0
  return 0;
101
0
}
102
103
namespace {
104
class PPC64 final : public TargetInfo {
105
public:
106
  PPC64();
107
  uint32_t calcEFlags() const override;
108
  RelExpr getRelExpr(RelType Type, const Symbol &S,
109
                     const uint8_t *Loc) const override;
110
  void writePltHeader(uint8_t *Buf) const override;
111
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
112
                int32_t Index, unsigned RelOff) const override;
113
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
114
  void writeGotHeader(uint8_t *Buf) const override;
115
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
116
                  uint64_t BranchAddr, const Symbol &S) const override;
117
  RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
118
                          RelExpr Expr) const override;
119
  void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
120
  void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
121
  void relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
122
  void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
123
124
  bool adjustPrologueForCrossSplitStack(uint8_t *Loc, uint8_t *End,
125
                                        uint8_t StOther) const override;
126
};
127
} // namespace
128
129
// Relocation masks following the #lo(value), #hi(value), #ha(value),
130
// #higher(value), #highera(value), #highest(value), and #highesta(value)
131
// macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
132
// document.
133
310
static uint16_t lo(uint64_t V) { return V; }
134
16
static uint16_t hi(uint64_t V) { return V >> 16; }
135
287
static uint16_t ha(uint64_t V) { return (V + 0x8000) >> 16; }
136
5
static uint16_t higher(uint64_t V) { return V >> 32; }
137
5
static uint16_t highera(uint64_t V) { return (V + 0x8000) >> 32; }
138
5
static uint16_t highest(uint64_t V) { return V >> 48; }
139
5
static uint16_t highesta(uint64_t V) { return (V + 0x8000) >> 48; }
140
141
// Extracts the 'PO' field of an instruction encoding.
142
154
static uint8_t getPrimaryOpCode(uint32_t Encoding) { return (Encoding >> 26); }
143
144
60
static bool isDQFormInstruction(uint32_t Encoding) {
145
60
  switch (getPrimaryOpCode(Encoding)) {
146
60
  default:
147
44
    return false;
148
60
  case 56:
149
2
    // The only instruction with a primary opcode of 56 is `lq`.
150
2
    return true;
151
60
  case 61:
152
14
    // There are both DS and DQ instruction forms with this primary opcode.
153
14
    // Namely `lxv` and `stxv` are the DQ-forms that use it.
154
14
    // The DS 'XO' bits being set to 01 is restricted to DQ form.
155
14
    return (Encoding & 3) == 0x1;
156
60
  }
157
60
}
158
159
30
static bool isInstructionUpdateForm(uint32_t Encoding) {
160
30
  switch (getPrimaryOpCode(Encoding)) {
161
30
  default:
162
16
    return false;
163
30
  case LBZU:
164
0
  case LHAU:
165
0
  case LHZU:
166
0
  case LWZU:
167
0
  case LFSU:
168
0
  case LFDU:
169
0
  case STBU:
170
0
  case STHU:
171
0
  case STWU:
172
0
  case STFSU:
173
0
  case STFDU:
174
0
    return true;
175
0
    // LWA has the same opcode as LD, and the DS bits is what differentiates
176
0
    // between LD/LDU/LWA
177
14
  case LD:
178
14
  case STD:
179
14
    return (Encoding & 3) == 1;
180
30
  }
181
30
}
182
183
// There are a number of places when we either want to read or write an
184
// instruction when handling a half16 relocation type. On big-endian the buffer
185
// pointer is pointing into the middle of the word we want to extract, and on
186
// little-endian it is pointing to the start of the word. These 2 helpers are to
187
// simplify reading and writing in that context.
188
74
static void writeInstrFromHalf16(uint8_t *Loc, uint32_t Instr) {
189
74
  write32(Loc - (Config->EKind == ELF64BEKind ? 
219
:
055
), Instr);
190
74
}
191
192
75
static uint32_t readInstrFromHalf16(const uint8_t *Loc) {
193
75
  return read32(Loc - (Config->EKind == ELF64BEKind ? 
222
:
053
));
194
75
}
195
196
134
PPC64::PPC64() {
197
134
  GotRel = R_PPC64_GLOB_DAT;
198
134
  NoneRel = R_PPC64_NONE;
199
134
  PltRel = R_PPC64_JMP_SLOT;
200
134
  RelativeRel = R_PPC64_RELATIVE;
201
134
  IRelativeRel = R_PPC64_IRELATIVE;
202
134
  GotEntrySize = 8;
203
134
  PltEntrySize = 4;
204
134
  GotPltEntrySize = 8;
205
134
  GotBaseSymInGotPlt = false;
206
134
  GotBaseSymOff = 0x8000;
207
134
  GotHeaderEntriesNum = 1;
208
134
  GotPltHeaderEntriesNum = 2;
209
134
  PltHeaderSize = 60;
210
134
  NeedsThunks = true;
211
134
  TcbSize = 8;
212
134
  TlsTpOffset = 0x7000;
213
134
214
134
  TlsModuleIndexRel = R_PPC64_DTPMOD64;
215
134
  TlsOffsetRel = R_PPC64_DTPREL64;
216
134
217
134
  TlsGotRel = R_PPC64_TPREL64;
218
134
219
134
  NeedsMoreStackNonSplit = false;
220
134
221
134
  // We need 64K pages (at least under glibc/Linux, the loader won't
222
134
  // set different permissions on a finer granularity than that).
223
134
  DefaultMaxPageSize = 65536;
224
134
225
134
  // The PPC64 ELF ABI v1 spec, says:
226
134
  //
227
134
  //   It is normally desirable to put segments with different characteristics
228
134
  //   in separate 256 Mbyte portions of the address space, to give the
229
134
  //   operating system full paging flexibility in the 64-bit address space.
230
134
  //
231
134
  // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
232
134
  // use 0x10000000 as the starting address.
233
134
  DefaultImageBase = 0x10000000;
234
134
235
134
  TrapInstr =
236
134
      (Config->IsLE == sys::IsLittleEndianHost) ? 
0x7fe0000871
:
0x0800e07f63
;
237
134
}
238
239
161
static uint32_t getEFlags(InputFile *File) {
240
161
  if (Config->EKind == ELF64BEKind)
241
75
    return cast<ObjFile<ELF64BE>>(File)->getObj().getHeader()->e_flags;
242
86
  return cast<ObjFile<ELF64LE>>(File)->getObj().getHeader()->e_flags;
243
86
}
244
245
// This file implements v2 ABI. This function makes sure that all
246
// object files have v2 or an unspecified version as an ABI version.
247
131
uint32_t PPC64::calcEFlags() const {
248
161
  for (InputFile *F : ObjectFiles) {
249
161
    uint32_t Flag = getEFlags(F);
250
161
    if (Flag == 1)
251
1
      error(toString(F) + ": ABI version 1 is not supported");
252
160
    else if (Flag > 2)
253
1
      error(toString(F) + ": unrecognized e_flags: " + Twine(Flag));
254
161
  }
255
131
  return 2;
256
131
}
257
258
10
void PPC64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
259
10
  // Reference: 3.7.4.2 of the 64-bit ELF V2 abi supplement.
260
10
  // The general dynamic code sequence for a global `x` will look like:
261
10
  // Instruction                    Relocation                Symbol
262
10
  // addis r3, r2, x@got@tlsgd@ha   R_PPC64_GOT_TLSGD16_HA      x
263
10
  // addi  r3, r3, x@got@tlsgd@l    R_PPC64_GOT_TLSGD16_LO      x
264
10
  // bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSGD               x
265
10
  //                                R_PPC64_REL24               __tls_get_addr
266
10
  // nop                            None                       None
267
10
268
10
  // Relaxing to local exec entails converting:
269
10
  // addis r3, r2, x@got@tlsgd@ha    into      nop
270
10
  // addi  r3, r3, x@got@tlsgd@l     into      addis r3, r13, x@tprel@ha
271
10
  // bl __tls_get_addr(x@tlsgd)      into      nop
272
10
  // nop                             into      addi r3, r3, x@tprel@l
273
10
274
10
  switch (Type) {
275
10
  case R_PPC64_GOT_TLSGD16_HA:
276
2
    writeInstrFromHalf16(Loc, 0x60000000); // nop
277
2
    break;
278
10
  case R_PPC64_GOT_TLSGD16:
279
4
  case R_PPC64_GOT_TLSGD16_LO:
280
4
    writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13
281
4
    relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
282
4
    break;
283
4
  case R_PPC64_TLSGD:
284
4
    write32(Loc, 0x60000000);     // nop
285
4
    write32(Loc + 4, 0x38630000); // addi r3, r3
286
4
    // Since we are relocating a half16 type relocation and Loc + 4 points to
287
4
    // the start of an instruction we need to advance the buffer by an extra
288
4
    // 2 bytes on BE.
289
4
    relocateOne(Loc + 4 + (Config->EKind == ELF64BEKind ? 
22
:
02
),
290
4
                R_PPC64_TPREL16_LO, Val);
291
4
    break;
292
4
  default:
293
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
294
10
  }
295
10
}
296
297
10
void PPC64::relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
298
10
  // Reference: 3.7.4.3 of the 64-bit ELF V2 abi supplement.
299
10
  // The local dynamic code sequence for a global `x` will look like:
300
10
  // Instruction                    Relocation                Symbol
301
10
  // addis r3, r2, x@got@tlsld@ha   R_PPC64_GOT_TLSLD16_HA      x
302
10
  // addi  r3, r3, x@got@tlsld@l    R_PPC64_GOT_TLSLD16_LO      x
303
10
  // bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSLD               x
304
10
  //                                R_PPC64_REL24               __tls_get_addr
305
10
  // nop                            None                       None
306
10
307
10
  // Relaxing to local exec entails converting:
308
10
  // addis r3, r2, x@got@tlsld@ha   into      nop
309
10
  // addi  r3, r3, x@got@tlsld@l    into      addis r3, r13, 0
310
10
  // bl __tls_get_addr(x@tlsgd)     into      nop
311
10
  // nop                            into      addi r3, r3, 4096
312
10
313
10
  switch (Type) {
314
10
  case R_PPC64_GOT_TLSLD16_HA:
315
2
    writeInstrFromHalf16(Loc, 0x60000000); // nop
316
2
    break;
317
10
  case R_PPC64_GOT_TLSLD16_LO:
318
2
    writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13, 0
319
2
    break;
320
10
  case R_PPC64_TLSLD:
321
2
    write32(Loc, 0x60000000);     // nop
322
2
    write32(Loc + 4, 0x38631000); // addi r3, r3, 4096
323
2
    break;
324
10
  case R_PPC64_DTPREL16:
325
4
  case R_PPC64_DTPREL16_HA:
326
4
  case R_PPC64_DTPREL16_HI:
327
4
  case R_PPC64_DTPREL16_DS:
328
4
  case R_PPC64_DTPREL16_LO:
329
4
  case R_PPC64_DTPREL16_LO_DS:
330
4
  case R_PPC64_GOT_DTPREL16_HA:
331
4
  case R_PPC64_GOT_DTPREL16_LO_DS:
332
4
  case R_PPC64_GOT_DTPREL16_DS:
333
4
  case R_PPC64_GOT_DTPREL16_HI:
334
4
    relocateOne(Loc, Type, Val);
335
4
    break;
336
4
  default:
337
0
    llvm_unreachable("unsupported relocation for TLS LD to LE relaxation");
338
10
  }
339
10
}
340
341
20
static unsigned getDFormOp(unsigned SecondaryOp) {
342
20
  switch (SecondaryOp) {
343
20
  case LBZX:
344
2
    return LBZ;
345
20
  case LHZX:
346
2
    return LHZ;
347
20
  case LWZX:
348
2
    return LWZ;
349
20
  case LDX:
350
2
    return LD;
351
20
  case STBX:
352
2
    return STB;
353
20
  case STHX:
354
2
    return STH;
355
20
  case STWX:
356
2
    return STW;
357
20
  case STDX:
358
4
    return STD;
359
20
  case ADD:
360
2
    return ADDI;
361
20
  default:
362
0
    error("unrecognized instruction for IE to LE R_PPC64_TLS");
363
0
    return 0;
364
20
  }
365
20
}
366
367
58
void PPC64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
368
58
  // The initial exec code sequence for a global `x` will look like:
369
58
  // Instruction                    Relocation                Symbol
370
58
  // addis r9, r2, x@got@tprel@ha   R_PPC64_GOT_TPREL16_HA      x
371
58
  // ld    r9, x@got@tprel@l(r9)    R_PPC64_GOT_TPREL16_LO_DS   x
372
58
  // add r9, r9, x@tls              R_PPC64_TLS                 x
373
58
374
58
  // Relaxing to local exec entails converting:
375
58
  // addis r9, r2, x@got@tprel@ha       into        nop
376
58
  // ld r9, x@got@tprel@l(r9)           into        addis r9, r13, x@tprel@ha
377
58
  // add r9, r9, x@tls                  into        addi r9, r9, x@tprel@l
378
58
379
58
  // x@tls R_PPC64_TLS is a relocation which does not compute anything,
380
58
  // it is replaced with r13 (thread pointer).
381
58
382
58
  // The add instruction in the initial exec sequence has multiple variations
383
58
  // that need to be handled. If we are building an address it will use an add
384
58
  // instruction, if we are accessing memory it will use any of the X-form
385
58
  // indexed load or store instructions.
386
58
387
58
  unsigned Offset = (Config->EKind == ELF64BEKind) ? 
229
:
029
;
388
58
  switch (Type) {
389
58
  case R_PPC64_GOT_TPREL16_HA:
390
18
    write32(Loc - Offset, 0x60000000); // nop
391
18
    break;
392
58
  case R_PPC64_GOT_TPREL16_LO_DS:
393
20
  case R_PPC64_GOT_TPREL16_DS: {
394
20
    uint32_t RegNo = read32(Loc - Offset) & 0x03E00000; // bits 6-10
395
20
    write32(Loc - Offset, 0x3C0D0000 | RegNo);          // addis RegNo, r13
396
20
    relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
397
20
    break;
398
20
  }
399
20
  case R_PPC64_TLS: {
400
20
    uint32_t PrimaryOp = getPrimaryOpCode(read32(Loc));
401
20
    if (PrimaryOp != 31)
402
0
      error("unrecognized instruction for IE to LE R_PPC64_TLS");
403
20
    uint32_t SecondaryOp = (read32(Loc) & 0x000007FE) >> 1; // bits 21-30
404
20
    uint32_t DFormOp = getDFormOp(SecondaryOp);
405
20
    write32(Loc, ((DFormOp << 26) | (read32(Loc) & 0x03FFFFFF)));
406
20
    relocateOne(Loc + Offset, R_PPC64_TPREL16_LO, Val);
407
20
    break;
408
20
  }
409
20
  default:
410
0
    llvm_unreachable("unknown relocation for IE to LE");
411
20
    
break0
;
412
58
  }
413
58
}
414
415
RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S,
416
751
                          const uint8_t *Loc) const {
417
751
  switch (Type) {
418
751
  case R_PPC64_TOC16:
419
116
  case R_PPC64_TOC16_DS:
420
116
  case R_PPC64_TOC16_HA:
421
116
  case R_PPC64_TOC16_HI:
422
116
  case R_PPC64_TOC16_LO:
423
116
  case R_PPC64_TOC16_LO_DS:
424
116
    return R_GOTREL;
425
116
  case R_PPC64_TOC:
426
0
    return R_PPC_TOC;
427
139
  case R_PPC64_REL24:
428
139
    return R_PPC_CALL_PLT;
429
256
  case R_PPC64_REL16_LO:
430
256
  case R_PPC64_REL16_HA:
431
256
  case R_PPC64_REL32:
432
256
  case R_PPC64_REL64:
433
256
    return R_PC;
434
256
  case R_PPC64_GOT_TLSGD16:
435
26
  case R_PPC64_GOT_TLSGD16_HA:
436
26
  case R_PPC64_GOT_TLSGD16_HI:
437
26
  case R_PPC64_GOT_TLSGD16_LO:
438
26
    return R_TLSGD_GOT;
439
26
  case R_PPC64_GOT_TLSLD16:
440
24
  case R_PPC64_GOT_TLSLD16_HA:
441
24
  case R_PPC64_GOT_TLSLD16_HI:
442
24
  case R_PPC64_GOT_TLSLD16_LO:
443
24
    return R_TLSLD_GOT;
444
46
  case R_PPC64_GOT_TPREL16_HA:
445
46
  case R_PPC64_GOT_TPREL16_LO_DS:
446
46
  case R_PPC64_GOT_TPREL16_DS:
447
46
  case R_PPC64_GOT_TPREL16_HI:
448
46
    return R_GOT_OFF;
449
46
  case R_PPC64_GOT_DTPREL16_HA:
450
8
  case R_PPC64_GOT_DTPREL16_LO_DS:
451
8
  case R_PPC64_GOT_DTPREL16_DS:
452
8
  case R_PPC64_GOT_DTPREL16_HI:
453
8
    return R_TLSLD_GOT_OFF;
454
14
  case R_PPC64_TPREL16:
455
14
  case R_PPC64_TPREL16_HA:
456
14
  case R_PPC64_TPREL16_LO:
457
14
  case R_PPC64_TPREL16_HI:
458
14
  case R_PPC64_TPREL16_DS:
459
14
  case R_PPC64_TPREL16_LO_DS:
460
14
  case R_PPC64_TPREL16_HIGHER:
461
14
  case R_PPC64_TPREL16_HIGHERA:
462
14
  case R_PPC64_TPREL16_HIGHEST:
463
14
  case R_PPC64_TPREL16_HIGHESTA:
464
14
    return R_TLS;
465
30
  case R_PPC64_DTPREL16:
466
30
  case R_PPC64_DTPREL16_DS:
467
30
  case R_PPC64_DTPREL16_HA:
468
30
  case R_PPC64_DTPREL16_HI:
469
30
  case R_PPC64_DTPREL16_HIGHER:
470
30
  case R_PPC64_DTPREL16_HIGHERA:
471
30
  case R_PPC64_DTPREL16_HIGHEST:
472
30
  case R_PPC64_DTPREL16_HIGHESTA:
473
30
  case R_PPC64_DTPREL16_LO:
474
30
  case R_PPC64_DTPREL16_LO_DS:
475
30
  case R_PPC64_DTPREL64:
476
30
    return R_ABS;
477
30
  case R_PPC64_TLSGD:
478
12
    return R_TLSDESC_CALL;
479
30
  case R_PPC64_TLSLD:
480
10
    return R_TLSLD_HINT;
481
30
  case R_PPC64_TLS:
482
22
    return R_TLSIE_HINT;
483
48
  default:
484
48
    return R_ABS;
485
751
  }
486
751
}
487
488
76
void PPC64::writeGotHeader(uint8_t *Buf) const {
489
76
  write64(Buf, getPPC64TocBase());
490
76
}
491
492
25
void PPC64::writePltHeader(uint8_t *Buf) const {
493
25
  // The generic resolver stub goes first.
494
25
  write32(Buf +  0, 0x7c0802a6); // mflr r0
495
25
  write32(Buf +  4, 0x429f0005); // bcl  20,4*cr7+so,8 <_glink+0x8>
496
25
  write32(Buf +  8, 0x7d6802a6); // mflr r11
497
25
  write32(Buf + 12, 0x7c0803a6); // mtlr r0
498
25
  write32(Buf + 16, 0x7d8b6050); // subf r12, r11, r12
499
25
  write32(Buf + 20, 0x380cffcc); // subi r0,r12,52
500
25
  write32(Buf + 24, 0x7800f082); // srdi r0,r0,62,2
501
25
  write32(Buf + 28, 0xe98b002c); // ld   r12,44(r11)
502
25
  write32(Buf + 32, 0x7d6c5a14); // add  r11,r12,r11
503
25
  write32(Buf + 36, 0xe98b0000); // ld   r12,0(r11)
504
25
  write32(Buf + 40, 0xe96b0008); // ld   r11,8(r11)
505
25
  write32(Buf + 44, 0x7d8903a6); // mtctr   r12
506
25
  write32(Buf + 48, 0x4e800420); // bctr
507
25
508
25
  // The 'bcl' instruction will set the link register to the address of the
509
25
  // following instruction ('mflr r11'). Here we store the offset from that
510
25
  // instruction  to the first entry in the GotPlt section.
511
25
  int64_t GotPltOffset = In.GotPlt->getVA() - (In.Plt->getVA() + 8);
512
25
  write64(Buf + 52, GotPltOffset);
513
25
}
514
515
void PPC64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
516
                     uint64_t PltEntryAddr, int32_t Index,
517
29
                     unsigned RelOff) const {
518
29
 int32_t Offset = PltHeaderSize + Index * PltEntrySize;
519
29
 // bl __glink_PLTresolve
520
29
 write32(Buf, 0x48000000 | ((-Offset) & 0x03FFFFFc));
521
29
}
522
523
681
static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) {
524
681
  // Relocations relative to the toc-base need to be adjusted by the Toc offset.
525
681
  uint64_t TocBiasedVal = Val - PPC64TocOffset;
526
681
  // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset.
527
681
  uint64_t DTPBiasedVal = Val - DynamicThreadPointerOffset;
528
681
529
681
  switch (Type) {
530
681
  // TOC biased relocation.
531
681
  case R_PPC64_GOT_TLSGD16:
532
4
  case R_PPC64_GOT_TLSLD16:
533
4
  case R_PPC64_TOC16:
534
4
    return {R_PPC64_ADDR16, TocBiasedVal};
535
4
  case R_PPC64_TOC16_DS:
536
4
  case R_PPC64_GOT_TPREL16_DS:
537
4
  case R_PPC64_GOT_DTPREL16_DS:
538
4
    return {R_PPC64_ADDR16_DS, TocBiasedVal};
539
76
  case R_PPC64_GOT_TLSGD16_HA:
540
76
  case R_PPC64_GOT_TLSLD16_HA:
541
76
  case R_PPC64_GOT_TPREL16_HA:
542
76
  case R_PPC64_GOT_DTPREL16_HA:
543
76
  case R_PPC64_TOC16_HA:
544
76
    return {R_PPC64_ADDR16_HA, TocBiasedVal};
545
76
  case R_PPC64_GOT_TLSGD16_HI:
546
10
  case R_PPC64_GOT_TLSLD16_HI:
547
10
  case R_PPC64_GOT_TPREL16_HI:
548
10
  case R_PPC64_GOT_DTPREL16_HI:
549
10
  case R_PPC64_TOC16_HI:
550
10
    return {R_PPC64_ADDR16_HI, TocBiasedVal};
551
28
  case R_PPC64_GOT_TLSGD16_LO:
552
28
  case R_PPC64_GOT_TLSLD16_LO:
553
28
  case R_PPC64_TOC16_LO:
554
28
    return {R_PPC64_ADDR16_LO, TocBiasedVal};
555
50
  case R_PPC64_TOC16_LO_DS:
556
50
  case R_PPC64_GOT_TPREL16_LO_DS:
557
50
  case R_PPC64_GOT_DTPREL16_LO_DS:
558
50
    return {R_PPC64_ADDR16_LO_DS, TocBiasedVal};
559
50
560
50
  // Dynamic Thread pointer biased relocation types.
561
50
  case R_PPC64_DTPREL16:
562
2
    return {R_PPC64_ADDR16, DTPBiasedVal};
563
50
  case R_PPC64_DTPREL16_DS:
564
2
    return {R_PPC64_ADDR16_DS, DTPBiasedVal};
565
50
  case R_PPC64_DTPREL16_HA:
566
6
    return {R_PPC64_ADDR16_HA, DTPBiasedVal};
567
50
  case R_PPC64_DTPREL16_HI:
568
2
    return {R_PPC64_ADDR16_HI, DTPBiasedVal};
569
50
  case R_PPC64_DTPREL16_HIGHER:
570
2
    return {R_PPC64_ADDR16_HIGHER, DTPBiasedVal};
571
50
  case R_PPC64_DTPREL16_HIGHERA:
572
2
    return {R_PPC64_ADDR16_HIGHERA, DTPBiasedVal};
573
50
  case R_PPC64_DTPREL16_HIGHEST:
574
2
    return {R_PPC64_ADDR16_HIGHEST, DTPBiasedVal};
575
50
  case R_PPC64_DTPREL16_HIGHESTA:
576
2
    return {R_PPC64_ADDR16_HIGHESTA, DTPBiasedVal};
577
50
  case R_PPC64_DTPREL16_LO:
578
6
    return {R_PPC64_ADDR16_LO, DTPBiasedVal};
579
50
  case R_PPC64_DTPREL16_LO_DS:
580
2
    return {R_PPC64_ADDR16_LO_DS, DTPBiasedVal};
581
50
  case R_PPC64_DTPREL64:
582
4
    return {R_PPC64_ADDR64, DTPBiasedVal};
583
50
584
477
  default:
585
477
    return {Type, Val};
586
681
  }
587
681
}
588
589
681
static bool isTocRelType(RelType Type) {
590
681
  return Type == R_PPC64_TOC16_HA || 
Type == R_PPC64_TOC16_LO_DS625
||
591
681
         
Type == R_PPC64_TOC16_LO585
;
592
681
}
593
594
681
void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
595
681
  // For a TOC-relative relocation, proceed in terms of the corresponding
596
681
  // ADDR16 relocation type.
597
681
  bool IsTocRelType = isTocRelType(Type);
598
681
  std::tie(Type, Val) = toAddr16Rel(Type, Val);
599
681
600
681
  switch (Type) {
601
681
  case R_PPC64_ADDR14: {
602
0
    checkAlignment(Loc, Val, 4, Type);
603
0
    // Preserve the AA/LK bits in the branch instruction
604
0
    uint8_t AALK = Loc[3];
605
0
    write16(Loc + 2, (AALK & 3) | (Val & 0xfffc));
606
0
    break;
607
681
  }
608
681
  case R_PPC64_ADDR16:
609
9
  case R_PPC64_TPREL16:
610
9
    checkInt(Loc, Val, 16, Type);
611
9
    write16(Loc, Val);
612
9
    break;
613
9
  case R_PPC64_ADDR16_DS:
614
7
  case R_PPC64_TPREL16_DS: {
615
7
    checkInt(Loc, Val, 16, Type);
616
7
    // DQ-form instructions use bits 28-31 as part of the instruction encoding
617
7
    // DS-form instructions only use bits 30-31.
618
7
    uint16_t Mask = isDQFormInstruction(readInstrFromHalf16(Loc)) ? 
0xF0
: 0x3;
619
7
    checkAlignment(Loc, lo(Val), Mask + 1, Type);
620
7
    write16(Loc, (read16(Loc) & Mask) | lo(Val));
621
7
  } break;
622
236
  case R_PPC64_ADDR16_HA:
623
236
  case R_PPC64_REL16_HA:
624
236
  case R_PPC64_TPREL16_HA:
625
236
    if (Config->TocOptimize && 
IsTocRelType212
&&
ha(Val) == 038
)
626
28
      writeInstrFromHalf16(Loc, 0x60000000);
627
208
    else
628
208
      write16(Loc, ha(Val));
629
236
    break;
630
236
  case R_PPC64_ADDR16_HI:
631
16
  case R_PPC64_REL16_HI:
632
16
  case R_PPC64_TPREL16_HI:
633
16
    write16(Loc, hi(Val));
634
16
    break;
635
16
  case R_PPC64_ADDR16_HIGHER:
636
5
  case R_PPC64_TPREL16_HIGHER:
637
5
    write16(Loc, higher(Val));
638
5
    break;
639
5
  case R_PPC64_ADDR16_HIGHERA:
640
5
  case R_PPC64_TPREL16_HIGHERA:
641
5
    write16(Loc, highera(Val));
642
5
    break;
643
5
  case R_PPC64_ADDR16_HIGHEST:
644
5
  case R_PPC64_TPREL16_HIGHEST:
645
5
    write16(Loc, highest(Val));
646
5
    break;
647
5
  case R_PPC64_ADDR16_HIGHESTA:
648
5
  case R_PPC64_TPREL16_HIGHESTA:
649
5
    write16(Loc, highesta(Val));
650
5
    break;
651
190
  case R_PPC64_ADDR16_LO:
652
190
  case R_PPC64_REL16_LO:
653
190
  case R_PPC64_TPREL16_LO:
654
190
    // When the high-adjusted part of a toc relocation evalutes to 0, it is
655
190
    // changed into a nop. The lo part then needs to be updated to use the
656
190
    // toc-pointer register r2, as the base register.
657
190
    if (Config->TocOptimize && 
IsTocRelType176
&&
ha(Val) == 011
) {
658
9
      uint32_t Instr = readInstrFromHalf16(Loc);
659
9
      if (isInstructionUpdateForm(Instr))
660
0
        error(getErrorLocation(Loc) +
661
0
              "can't toc-optimize an update instruction: 0x" +
662
0
              utohexstr(Instr));
663
9
      Instr = (Instr & 0xFFE00000) | 0x00020000;
664
9
      writeInstrFromHalf16(Loc, Instr);
665
9
    }
666
190
    write16(Loc, lo(Val));
667
190
    break;
668
190
  case R_PPC64_ADDR16_LO_DS:
669
53
  case R_PPC64_TPREL16_LO_DS: {
670
53
    // DQ-form instructions use bits 28-31 as part of the instruction encoding
671
53
    // DS-form instructions only use bits 30-31.
672
53
    uint32_t Inst = readInstrFromHalf16(Loc);
673
53
    uint16_t Mask = isDQFormInstruction(Inst) ? 
0xF12
:
0x341
;
674
53
    checkAlignment(Loc, lo(Val), Mask + 1, Type);
675
53
    if (Config->TocOptimize && 
IsTocRelType42
&&
ha(Val) == 029
) {
676
21
      // When the high-adjusted part of a toc relocation evalutes to 0, it is
677
21
      // changed into a nop. The lo part then needs to be updated to use the toc
678
21
      // pointer register r2, as the base register.
679
21
      if (isInstructionUpdateForm(Inst))
680
0
        error(getErrorLocation(Loc) +
681
0
              "Can't toc-optimize an update instruction: 0x" +
682
0
              Twine::utohexstr(Inst));
683
21
      Inst = (Inst & 0xFFE0000F) | 0x00020000;
684
21
      writeInstrFromHalf16(Loc, Inst);
685
21
    }
686
53
    write16(Loc, (read16(Loc) & Mask) | lo(Val));
687
53
  } break;
688
53
  case R_PPC64_ADDR32:
689
4
  case R_PPC64_REL32:
690
4
    checkInt(Loc, Val, 32, Type);
691
4
    write32(Loc, Val);
692
4
    break;
693
14
  case R_PPC64_ADDR64:
694
14
  case R_PPC64_REL64:
695
14
  case R_PPC64_TOC:
696
14
    write64(Loc, Val);
697
14
    break;
698
131
  case R_PPC64_REL24: {
699
131
    uint32_t Mask = 0x03FFFFFC;
700
131
    checkInt(Loc, Val, 26, Type);
701
131
    checkAlignment(Loc, Val, 4, Type);
702
131
    write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
703
131
    break;
704
14
  }
705
14
  case R_PPC64_DTPREL64:
706
0
    write64(Loc, Val - DynamicThreadPointerOffset);
707
0
    break;
708
14
  default:
709
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
710
681
  }
711
681
}
712
713
bool PPC64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
714
827
                       uint64_t BranchAddr, const Symbol &S) const {
715
827
  // If a function is in the plt it needs to be called through
716
827
  // a call stub.
717
827
  return Type == R_PPC64_REL24 && 
S.isInPlt()145
;
718
827
}
719
720
RelExpr PPC64::adjustRelaxExpr(RelType Type, const uint8_t *Data,
721
38
                               RelExpr Expr) const {
722
38
  if (Expr == R_RELAX_TLS_GD_TO_IE)
723
18
    return R_RELAX_TLS_GD_TO_IE_GOT_OFF;
724
20
  if (Expr == R_RELAX_TLS_LD_TO_LE)
725
10
    return R_RELAX_TLS_LD_TO_LE_ABS;
726
10
  return Expr;
727
10
}
728
729
// Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement.
730
// The general dynamic code sequence for a global `x` uses 4 instructions.
731
// Instruction                    Relocation                Symbol
732
// addis r3, r2, x@got@tlsgd@ha   R_PPC64_GOT_TLSGD16_HA      x
733
// addi  r3, r3, x@got@tlsgd@l    R_PPC64_GOT_TLSGD16_LO      x
734
// bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSGD               x
735
//                                R_PPC64_REL24               __tls_get_addr
736
// nop                            None                       None
737
//
738
// Relaxing to initial-exec entails:
739
// 1) Convert the addis/addi pair that builds the address of the tls_index
740
//    struct for 'x' to an addis/ld pair that loads an offset from a got-entry.
741
// 2) Convert the call to __tls_get_addr to a nop.
742
// 3) Convert the nop following the call to an add of the loaded offset to the
743
//    thread pointer.
744
// Since the nop must directly follow the call, the R_PPC64_TLSGD relocation is
745
// used as the relaxation hint for both steps 2 and 3.
746
18
void PPC64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
747
18
  switch (Type) {
748
18
  case R_PPC64_GOT_TLSGD16_HA:
749
6
    // This is relaxed from addis rT, r2, sym@got@tlsgd@ha to
750
6
    //                      addis rT, r2, sym@got@tprel@ha.
751
6
    relocateOne(Loc, R_PPC64_GOT_TPREL16_HA, Val);
752
6
    return;
753
18
  case R_PPC64_GOT_TLSGD16_LO: {
754
6
    // Relax from addi  r3, rA, sym@got@tlsgd@l to
755
6
    //            ld r3, sym@got@tprel@l(rA)
756
6
    uint32_t InputRegister = (readInstrFromHalf16(Loc) & (0x1f << 16));
757
6
    writeInstrFromHalf16(Loc, 0xE8600000 | InputRegister);
758
6
    relocateOne(Loc, R_PPC64_GOT_TPREL16_LO_DS, Val);
759
6
    return;
760
18
  }
761
18
  case R_PPC64_TLSGD:
762
6
    write32(Loc, 0x60000000);     // bl __tls_get_addr(sym@tlsgd) --> nop
763
6
    write32(Loc + 4, 0x7c636A14); // nop --> add r3, r3, r13
764
6
    return;
765
18
  default:
766
0
    llvm_unreachable("unsupported relocation for TLS GD to IE relaxation");
767
18
  }
768
18
}
769
770
// The prologue for a split-stack function is expected to look roughly
771
// like this:
772
//    .Lglobal_entry_point:
773
//      # TOC pointer initalization.
774
//      ...
775
//    .Llocal_entry_point:
776
//      # load the __private_ss member of the threads tcbhead.
777
//      ld r0,-0x7000-64(r13)
778
//      # subtract the functions stack size from the stack pointer.
779
//      addis r12, r1, ha(-stack-frame size)
780
//      addi  r12, r12, l(-stack-frame size)
781
//      # compare needed to actual and branch to allocate_more_stack if more
782
//      # space is needed, otherwise fallthrough to 'normal' function body.
783
//      cmpld cr7,r12,r0
784
//      blt- .Lallocate_more_stack
785
//
786
// -) The allocate_more_stack block might be placed after the split-stack
787
//    prologue and the `blt-` replaced with a `bge+ .Lnormal_func_body`
788
//    instead.
789
// -) If either the addis or addi is not needed due to the stack size being
790
//    smaller then 32K or a multiple of 64K they will be replaced with a nop,
791
//    but there will always be 2 instructions the linker can overwrite for the
792
//    adjusted stack size.
793
//
794
// The linkers job here is to increase the stack size used in the addis/addi
795
// pair by split-stack-size-adjust.
796
// addis r12, r1, ha(-stack-frame size - split-stack-adjust-size)
797
// addi  r12, r12, l(-stack-frame size - split-stack-adjust-size)
798
bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *Loc, uint8_t *End,
799
22
                                             uint8_t StOther) const {
800
22
  // If the caller has a global entry point adjust the buffer past it. The start
801
22
  // of the split-stack prologue will be at the local entry point.
802
22
  Loc += getPPC64GlobalEntryToLocalEntryOffset(StOther);
803
22
804
22
  // At the very least we expect to see a load of some split-stack data from the
805
22
  // tcb, and 2 instructions that calculate the ending stack address this
806
22
  // function will require. If there is not enough room for at least 3
807
22
  // instructions it can't be a split-stack prologue.
808
22
  if (Loc + 12 >= End)
809
0
    return false;
810
22
811
22
  // First instruction must be `ld r0, -0x7000-64(r13)`
812
22
  if (read32(Loc) != 0xe80d8fc0)
813
0
    return false;
814
22
815
22
  int16_t HiImm = 0;
816
22
  int16_t LoImm = 0;
817
22
  // First instruction can be either an addis if the frame size is larger then
818
22
  // 32K, or an addi if the size is less then 32K.
819
22
  int32_t FirstInstr = read32(Loc + 4);
820
22
  if (getPrimaryOpCode(FirstInstr) == 15) {
821
12
    HiImm = FirstInstr & 0xFFFF;
822
12
  } else 
if (10
getPrimaryOpCode(FirstInstr) == 1410
) {
823
10
    LoImm = FirstInstr & 0xFFFF;
824
10
  } else {
825
0
    return false;
826
0
  }
827
22
828
22
  // Second instruction is either an addi or a nop. If the first instruction was
829
22
  // an addi then LoImm is set and the second instruction must be a nop.
830
22
  uint32_t SecondInstr = read32(Loc + 8);
831
22
  if (!LoImm && 
getPrimaryOpCode(SecondInstr) == 1412
) {
832
10
    LoImm = SecondInstr & 0xFFFF;
833
12
  } else if (SecondInstr != 0x60000000) {
834
0
    return false;
835
0
  }
836
22
837
22
  // The register operands of the first instruction should be the stack-pointer
838
22
  // (r1) as the input (RA) and r12 as the output (RT). If the second
839
22
  // instruction is not a nop, then it should use r12 as both input and output.
840
22
  auto CheckRegOperands =
841
30
      [](uint32_t Instr, uint8_t ExpectedRT, uint8_t ExpectedRA) {
842
30
        return ((Instr & 0x3E00000) >> 21 == ExpectedRT) &&
843
30
               
((Instr & 0x1F0000) >> 16 == ExpectedRA)28
;
844
30
      };
845
22
  if (!CheckRegOperands(FirstInstr, 12, 1))
846
2
    return false;
847
20
  if (SecondInstr != 0x60000000 && 
!CheckRegOperands(SecondInstr, 12, 12)8
)
848
0
    return false;
849
20
850
20
  int32_t StackFrameSize = (HiImm * 65536) + LoImm;
851
20
  // Check that the adjusted size doesn't overflow what we can represent with 2
852
20
  // instructions.
853
20
  if (StackFrameSize < -2147483648 + Config->SplitStackAdjustSize) {
854
4
    error(getErrorLocation(Loc) + "split-stack prologue adjustment overflows");
855
4
    return false;
856
4
  }
857
16
858
16
  int32_t AdjustedStackFrameSize =
859
16
      StackFrameSize - Config->SplitStackAdjustSize;
860
16
861
16
  LoImm = AdjustedStackFrameSize & 0xFFFF;
862
16
  HiImm = (AdjustedStackFrameSize + 0x8000) >> 16;
863
16
  if (HiImm) {
864
10
    write32(Loc + 4, 0x3D810000 | (uint16_t)HiImm);
865
10
    // If the low immediate is zero the second instruction will be a nop.
866
10
    SecondInstr =
867
10
        LoImm ? 
0x398C0000 | (uint16_t)LoImm8
:
0x600000002
;
868
10
    write32(Loc + 8, SecondInstr);
869
10
  } else {
870
6
    // addi r12, r1, imm
871
6
    write32(Loc + 4, (0x39810000) | (uint16_t)LoImm);
872
6
    write32(Loc + 8, 0x60000000);
873
6
  }
874
16
875
16
  return true;
876
16
}
877
878
134
TargetInfo *elf::getPPC64TargetInfo() {
879
134
  static PPC64 Target;
880
134
  return &Target;
881
134
  }