Coverage Report

Created: 2019-05-19 14:56

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/PPC64.cpp
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1
//===- PPC64.cpp ----------------------------------------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "Symbols.h"
10
#include "SyntheticSections.h"
11
#include "Target.h"
12
#include "lld/Common/ErrorHandler.h"
13
#include "llvm/Support/Endian.h"
14
15
using namespace llvm;
16
using namespace llvm::object;
17
using namespace llvm::support::endian;
18
using namespace llvm::ELF;
19
using namespace lld;
20
using namespace lld::elf;
21
22
static uint64_t PPC64TocOffset = 0x8000;
23
static uint64_t DynamicThreadPointerOffset = 0x8000;
24
25
// The instruction encoding of bits 21-30 from the ISA for the Xform and Dform
26
// instructions that can be used as part of the initial exec TLS sequence.
27
enum XFormOpcd {
28
  LBZX = 87,
29
  LHZX = 279,
30
  LWZX = 23,
31
  LDX = 21,
32
  STBX = 215,
33
  STHX = 407,
34
  STWX = 151,
35
  STDX = 149,
36
  ADD = 266,
37
};
38
39
enum DFormOpcd {
40
  LBZ = 34,
41
  LBZU = 35,
42
  LHZ = 40,
43
  LHZU = 41,
44
  LHAU = 43,
45
  LWZ = 32,
46
  LWZU = 33,
47
  LFSU = 49,
48
  LD = 58,
49
  LFDU = 51,
50
  STB = 38,
51
  STBU = 39,
52
  STH = 44,
53
  STHU = 45,
54
  STW = 36,
55
  STWU = 37,
56
  STFSU = 53,
57
  STFDU = 55,
58
  STD = 62,
59
  ADDI = 14
60
};
61
62
187
uint64_t elf::getPPC64TocBase() {
63
187
  // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
64
187
  // TOC starts where the first of these sections starts. We always create a
65
187
  // .got when we see a relocation that uses it, so for us the start is always
66
187
  // the .got.
67
187
  uint64_t TocVA = In.Got->getVA();
68
187
69
187
  // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
70
187
  // thus permitting a full 64 Kbytes segment. Note that the glibc startup
71
187
  // code (crt1.o) assumes that you can get from the TOC base to the
72
187
  // start of the .toc section with only a single (signed) 16-bit relocation.
73
187
  return TocVA + PPC64TocOffset;
74
187
}
75
76
293
unsigned elf::getPPC64GlobalEntryToLocalEntryOffset(uint8_t StOther) {
77
293
  // The offset is encoded into the 3 most significant bits of the st_other
78
293
  // field, with some special values described in section 3.4.1 of the ABI:
79
293
  // 0   --> Zero offset between the GEP and LEP, and the function does NOT use
80
293
  //         the TOC pointer (r2). r2 will hold the same value on returning from
81
293
  //         the function as it did on entering the function.
82
293
  // 1   --> Zero offset between the GEP and LEP, and r2 should be treated as a
83
293
  //         caller-saved register for all callers.
84
293
  // 2-6 --> The  binary logarithm of the offset eg:
85
293
  //         2 --> 2^2 = 4 bytes -->  1 instruction.
86
293
  //         6 --> 2^6 = 64 bytes --> 16 instructions.
87
293
  // 7   --> Reserved.
88
293
  uint8_t GepToLep = (StOther >> 5) & 7;
89
293
  if (GepToLep < 2)
90
219
    return 0;
91
74
92
74
  // The value encoded in the st_other bits is the
93
74
  // log-base-2(offset).
94
74
  if (GepToLep < 7)
95
74
    return 1 << GepToLep;
96
0
97
0
  error("reserved value of 7 in the 3 most-significant-bits of st_other");
98
0
  return 0;
99
0
}
100
101
989
bool elf::isPPC64SmallCodeModelTocReloc(RelType Type) {
102
989
  // The only small code model relocations that access the .toc section.
103
989
  return Type == R_PPC64_TOC16 || Type == R_PPC64_TOC16_DS;
104
989
}
105
106
// Find the R_PPC64_ADDR64 in .rela.toc with matching offset.
107
template <typename ELFT>
108
static std::pair<Defined *, int64_t>
109
70
getRelaTocSymAndAddend(InputSectionBase *TocSec, uint64_t Offset) {
110
70
  if (TocSec->NumRelocations == 0)
111
0
    return {};
112
70
113
70
  // .rela.toc contains exclusively R_PPC64_ADDR64 relocations sorted by
114
70
  // r_offset: 0, 8, 16, etc. For a given Offset, Offset / 8 gives us the
115
70
  // relocation index in most cases.
116
70
  //
117
70
  // In rare cases a TOC entry may store a constant that doesn't need an
118
70
  // R_PPC64_ADDR64, the corresponding r_offset is therefore missing. Offset / 8
119
70
  // points to a relocation with larger r_offset. Do a linear probe then.
120
70
  // Constants are extremely uncommon in .toc and the extra number of array
121
70
  // accesses can be seen as a small constant.
122
70
  ArrayRef<typename ELFT::Rela> Relas = TocSec->template relas<ELFT>();
123
70
  uint64_t Index = std::min<uint64_t>(Offset / 8, Relas.size() - 1);
124
70
  for (;;) {
125
70
    if (Relas[Index].r_offset == Offset) {
126
66
      Symbol &Sym = TocSec->getFile<ELFT>()->getRelocTargetSym(Relas[Index]);
127
66
      return {dyn_cast<Defined>(&Sym), getAddend<ELFT>(Relas[Index])};
128
66
    }
129
4
    if (Relas[Index].r_offset < Offset || Index == 0)
130
4
      break;
131
0
    --Index;
132
0
  }
133
70
  
return {}4
;
134
70
}
PPC64.cpp:std::__1::pair<lld::elf::Defined*, long long> getRelaTocSymAndAddend<llvm::object::ELFType<(llvm::support::endianness)1, true> >(lld::elf::InputSectionBase*, unsigned long long)
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109
48
getRelaTocSymAndAddend(InputSectionBase *TocSec, uint64_t Offset) {
110
48
  if (TocSec->NumRelocations == 0)
111
0
    return {};
112
48
113
48
  // .rela.toc contains exclusively R_PPC64_ADDR64 relocations sorted by
114
48
  // r_offset: 0, 8, 16, etc. For a given Offset, Offset / 8 gives us the
115
48
  // relocation index in most cases.
116
48
  //
117
48
  // In rare cases a TOC entry may store a constant that doesn't need an
118
48
  // R_PPC64_ADDR64, the corresponding r_offset is therefore missing. Offset / 8
119
48
  // points to a relocation with larger r_offset. Do a linear probe then.
120
48
  // Constants are extremely uncommon in .toc and the extra number of array
121
48
  // accesses can be seen as a small constant.
122
48
  ArrayRef<typename ELFT::Rela> Relas = TocSec->template relas<ELFT>();
123
48
  uint64_t Index = std::min<uint64_t>(Offset / 8, Relas.size() - 1);
124
48
  for (;;) {
125
48
    if (Relas[Index].r_offset == Offset) {
126
44
      Symbol &Sym = TocSec->getFile<ELFT>()->getRelocTargetSym(Relas[Index]);
127
44
      return {dyn_cast<Defined>(&Sym), getAddend<ELFT>(Relas[Index])};
128
44
    }
129
4
    if (Relas[Index].r_offset < Offset || Index == 0)
130
4
      break;
131
0
    --Index;
132
0
  }
133
48
  
return {}4
;
134
48
}
PPC64.cpp:std::__1::pair<lld::elf::Defined*, long long> getRelaTocSymAndAddend<llvm::object::ELFType<(llvm::support::endianness)0, true> >(lld::elf::InputSectionBase*, unsigned long long)
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Source
109
22
getRelaTocSymAndAddend(InputSectionBase *TocSec, uint64_t Offset) {
110
22
  if (TocSec->NumRelocations == 0)
111
0
    return {};
112
22
113
22
  // .rela.toc contains exclusively R_PPC64_ADDR64 relocations sorted by
114
22
  // r_offset: 0, 8, 16, etc. For a given Offset, Offset / 8 gives us the
115
22
  // relocation index in most cases.
116
22
  //
117
22
  // In rare cases a TOC entry may store a constant that doesn't need an
118
22
  // R_PPC64_ADDR64, the corresponding r_offset is therefore missing. Offset / 8
119
22
  // points to a relocation with larger r_offset. Do a linear probe then.
120
22
  // Constants are extremely uncommon in .toc and the extra number of array
121
22
  // accesses can be seen as a small constant.
122
22
  ArrayRef<typename ELFT::Rela> Relas = TocSec->template relas<ELFT>();
123
22
  uint64_t Index = std::min<uint64_t>(Offset / 8, Relas.size() - 1);
124
22
  for (;;) {
125
22
    if (Relas[Index].r_offset == Offset) {
126
22
      Symbol &Sym = TocSec->getFile<ELFT>()->getRelocTargetSym(Relas[Index]);
127
22
      return {dyn_cast<Defined>(&Sym), getAddend<ELFT>(Relas[Index])};
128
22
    }
129
0
    if (Relas[Index].r_offset < Offset || Index == 0)
130
0
      break;
131
0
    --Index;
132
0
  }
133
22
  
return {}0
;
134
22
}
135
136
// When accessing a symbol defined in another translation unit, compilers
137
// reserve a .toc entry, allocate a local label and generate toc-indirect
138
// instuctions:
139
//
140
//   addis 3, 2, .LC0@toc@ha  # R_PPC64_TOC16_HA
141
//   ld    3, .LC0@toc@l(3)   # R_PPC64_TOC16_LO_DS, load the address from a .toc entry
142
//   ld/lwa 3, 0(3)           # load the value from the address
143
//
144
//   .section .toc,"aw",@progbits
145
//   .LC0: .tc var[TC],var
146
//
147
// If var is defined, non-preemptable and addressable with a 32-bit signed
148
// offset from the toc base, the address of var can be computed by adding an
149
// offset to the toc base, saving a load.
150
//
151
//   addis 3,2,var@toc@ha     # this may be relaxed to a nop,
152
//   addi  3,3,var@toc@l      # then this becomes addi 3,2,var@toc
153
//   ld/lwa 3, 0(3)           # load the value from the address
154
//
155
// Returns true if the relaxation is performed.
156
bool elf::tryRelaxPPC64TocIndirection(RelType Type, const Relocation &Rel,
157
117
                                      uint8_t *BufLoc) {
158
117
  assert(Config->TocOptimize);
159
117
  if (Rel.Addend < 0)
160
0
    return false;
161
117
162
117
  // If the symbol is not the .toc section, this isn't a toc-indirection.
163
117
  Defined *DefSym = dyn_cast<Defined>(Rel.Sym);
164
117
  if (!DefSym || !DefSym->isSection() || 
DefSym->Section->Name != ".toc"95
)
165
47
    return false;
166
70
167
70
  Defined *D;
168
70
  int64_t Addend;
169
70
  auto *TocISB = cast<InputSectionBase>(DefSym->Section);
170
70
  std::tie(D, Addend) =
171
70
      Config->IsLE ? 
getRelaTocSymAndAddend<ELF64LE>(TocISB, Rel.Addend)48
172
70
                   : 
getRelaTocSymAndAddend<ELF64BE>(TocISB, Rel.Addend)22
;
173
70
174
70
  // Only non-preemptable defined symbols can be relaxed.
175
70
  if (!D || 
D->IsPreemptible58
)
176
16
    return false;
177
54
178
54
  // Two instructions can materialize a 32-bit signed offset from the toc base.
179
54
  uint64_t TocRelative = D->getVA(Addend) - getPPC64TocBase();
180
54
  if (!isInt<32>(TocRelative))
181
0
    return false;
182
54
183
54
  // Add PPC64TocOffset that will be subtracted by relocateOne().
184
54
  Target->relaxGot(BufLoc, Type, TocRelative + PPC64TocOffset);
185
54
  return true;
186
54
}
187
188
namespace {
189
class PPC64 final : public TargetInfo {
190
public:
191
  PPC64();
192
  int getTlsGdRelaxSkip(RelType Type) const override;
193
  uint32_t calcEFlags() const override;
194
  RelExpr getRelExpr(RelType Type, const Symbol &S,
195
                     const uint8_t *Loc) const override;
196
  void writePltHeader(uint8_t *Buf) const override;
197
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
198
                int32_t Index, unsigned RelOff) const override;
199
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
200
  void writeGotHeader(uint8_t *Buf) const override;
201
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
202
                  uint64_t BranchAddr, const Symbol &S) const override;
203
  uint32_t getThunkSectionSpacing() const override;
204
  bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
205
  RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
206
                          RelExpr Expr) const override;
207
  void relaxGot(uint8_t *Loc, RelType Type, uint64_t Val) const override;
208
  void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
209
  void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
210
  void relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
211
  void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
212
213
  bool adjustPrologueForCrossSplitStack(uint8_t *Loc, uint8_t *End,
214
                                        uint8_t StOther) const override;
215
};
216
} // namespace
217
218
// Relocation masks following the #lo(value), #hi(value), #ha(value),
219
// #higher(value), #highera(value), #highest(value), and #highesta(value)
220
// macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
221
// document.
222
431
static uint16_t lo(uint64_t V) { return V; }
223
20
static uint16_t hi(uint64_t V) { return V >> 16; }
224
397
static uint16_t ha(uint64_t V) { return (V + 0x8000) >> 16; }
225
5
static uint16_t higher(uint64_t V) { return V >> 32; }
226
6
static uint16_t highera(uint64_t V) { return (V + 0x8000) >> 32; }
227
5
static uint16_t highest(uint64_t V) { return V >> 48; }
228
6
static uint16_t highesta(uint64_t V) { return (V + 0x8000) >> 48; }
229
230
// Extracts the 'PO' field of an instruction encoding.
231
219
static uint8_t getPrimaryOpCode(uint32_t Encoding) { return (Encoding >> 26); }
232
233
89
static bool isDQFormInstruction(uint32_t Encoding) {
234
89
  switch (getPrimaryOpCode(Encoding)) {
235
89
  default:
236
73
    return false;
237
89
  case 56:
238
2
    // The only instruction with a primary opcode of 56 is `lq`.
239
2
    return true;
240
89
  case 61:
241
14
    // There are both DS and DQ instruction forms with this primary opcode.
242
14
    // Namely `lxv` and `stxv` are the DQ-forms that use it.
243
14
    // The DS 'XO' bits being set to 01 is restricted to DQ form.
244
14
    return (Encoding & 3) == 0x1;
245
89
  }
246
89
}
247
248
39
static bool isInstructionUpdateForm(uint32_t Encoding) {
249
39
  switch (getPrimaryOpCode(Encoding)) {
250
39
  default:
251
25
    return false;
252
39
  case LBZU:
253
0
  case LHAU:
254
0
  case LHZU:
255
0
  case LWZU:
256
0
  case LFSU:
257
0
  case LFDU:
258
0
  case STBU:
259
0
  case STHU:
260
0
  case STWU:
261
0
  case STFSU:
262
0
  case STFDU:
263
0
    return true;
264
0
    // LWA has the same opcode as LD, and the DS bits is what differentiates
265
0
    // between LD/LDU/LWA
266
14
  case LD:
267
14
  case STD:
268
14
    return (Encoding & 3) == 1;
269
39
  }
270
39
}
271
272
// There are a number of places when we either want to read or write an
273
// instruction when handling a half16 relocation type. On big-endian the buffer
274
// pointer is pointing into the middle of the word we want to extract, and on
275
// little-endian it is pointing to the start of the word. These 2 helpers are to
276
// simplify reading and writing in that context.
277
121
static void writeInstrFromHalf16(uint8_t *Loc, uint32_t Instr) {
278
121
  write32(Loc - (Config->EKind == ELF64BEKind ? 
230
:
091
), Instr);
279
121
}
280
281
140
static uint32_t readInstrFromHalf16(const uint8_t *Loc) {
282
140
  return read32(Loc - (Config->EKind == ELF64BEKind ? 
237
:
0103
));
283
140
}
284
285
159
PPC64::PPC64() {
286
159
  GotRel = R_PPC64_GLOB_DAT;
287
159
  NoneRel = R_PPC64_NONE;
288
159
  PltRel = R_PPC64_JMP_SLOT;
289
159
  RelativeRel = R_PPC64_RELATIVE;
290
159
  IRelativeRel = R_PPC64_IRELATIVE;
291
159
  GotEntrySize = 8;
292
159
  PltEntrySize = 4;
293
159
  GotPltEntrySize = 8;
294
159
  GotBaseSymInGotPlt = false;
295
159
  GotHeaderEntriesNum = 1;
296
159
  GotPltHeaderEntriesNum = 2;
297
159
  PltHeaderSize = 60;
298
159
  NeedsThunks = true;
299
159
300
159
  TlsModuleIndexRel = R_PPC64_DTPMOD64;
301
159
  TlsOffsetRel = R_PPC64_DTPREL64;
302
159
303
159
  TlsGotRel = R_PPC64_TPREL64;
304
159
305
159
  NeedsMoreStackNonSplit = false;
306
159
307
159
  // We need 64K pages (at least under glibc/Linux, the loader won't
308
159
  // set different permissions on a finer granularity than that).
309
159
  DefaultMaxPageSize = 65536;
310
159
311
159
  // The PPC64 ELF ABI v1 spec, says:
312
159
  //
313
159
  //   It is normally desirable to put segments with different characteristics
314
159
  //   in separate 256 Mbyte portions of the address space, to give the
315
159
  //   operating system full paging flexibility in the 64-bit address space.
316
159
  //
317
159
  // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
318
159
  // use 0x10000000 as the starting address.
319
159
  DefaultImageBase = 0x10000000;
320
159
321
159
  write32(TrapInstr.data(), 0x7fe00008);
322
159
}
323
324
34
int PPC64::getTlsGdRelaxSkip(RelType Type) const {
325
34
  // A __tls_get_addr call instruction is marked with 2 relocations:
326
34
  //
327
34
  //   R_PPC64_TLSGD / R_PPC64_TLSLD: marker relocation
328
34
  //   R_PPC64_REL24: __tls_get_addr
329
34
  //
330
34
  // After the relaxation we no longer call __tls_get_addr and should skip both
331
34
  // relocations to not create a false dependence on __tls_get_addr being
332
34
  // defined.
333
34
  if (Type == R_PPC64_TLSGD || 
Type == R_PPC64_TLSLD24
)
334
12
    return 2;
335
22
  return 1;
336
22
}
337
338
206
static uint32_t getEFlags(InputFile *File) {
339
206
  if (Config->EKind == ELF64BEKind)
340
86
    return cast<ObjFile<ELF64BE>>(File)->getObj().getHeader()->e_flags;
341
120
  return cast<ObjFile<ELF64LE>>(File)->getObj().getHeader()->e_flags;
342
120
}
343
344
// This file implements v2 ABI. This function makes sure that all
345
// object files have v2 or an unspecified version as an ABI version.
346
156
uint32_t PPC64::calcEFlags() const {
347
206
  for (InputFile *F : ObjectFiles) {
348
206
    uint32_t Flag = getEFlags(F);
349
206
    if (Flag == 1)
350
1
      error(toString(F) + ": ABI version 1 is not supported");
351
205
    else if (Flag > 2)
352
1
      error(toString(F) + ": unrecognized e_flags: " + Twine(Flag));
353
206
  }
354
156
  return 2;
355
156
}
356
357
54
void PPC64::relaxGot(uint8_t *Loc, RelType Type, uint64_t Val) const {
358
54
  switch (Type) {
359
54
  case R_PPC64_TOC16_HA:
360
27
    // Convert "addis reg, 2, .LC0@toc@h" to "addis reg, 2, var@toc@h" or "nop".
361
27
    relocateOne(Loc, Type, Val);
362
27
    break;
363
54
  case R_PPC64_TOC16_LO_DS: {
364
27
    // Convert "ld reg, .LC0@toc@l(reg)" to "addi reg, reg, var@toc@l" or
365
27
    // "addi reg, 2, var@toc".
366
27
    uint32_t Instr = readInstrFromHalf16(Loc);
367
27
    if (getPrimaryOpCode(Instr) != LD)
368
0
      error("expected a 'ld' for got-indirect to toc-relative relaxing");
369
27
    writeInstrFromHalf16(Loc, (Instr & 0x03FFFFFF) | 0x38000000);
370
27
    relocateOne(Loc, R_PPC64_TOC16_LO, Val);
371
27
    break;
372
54
  }
373
54
  default:
374
0
    llvm_unreachable("unexpected relocation type");
375
54
  }
376
54
}
377
378
10
void PPC64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
379
10
  // Reference: 3.7.4.2 of the 64-bit ELF V2 abi supplement.
380
10
  // The general dynamic code sequence for a global `x` will look like:
381
10
  // Instruction                    Relocation                Symbol
382
10
  // addis r3, r2, x@got@tlsgd@ha   R_PPC64_GOT_TLSGD16_HA      x
383
10
  // addi  r3, r3, x@got@tlsgd@l    R_PPC64_GOT_TLSGD16_LO      x
384
10
  // bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSGD               x
385
10
  //                                R_PPC64_REL24               __tls_get_addr
386
10
  // nop                            None                       None
387
10
388
10
  // Relaxing to local exec entails converting:
389
10
  // addis r3, r2, x@got@tlsgd@ha    into      nop
390
10
  // addi  r3, r3, x@got@tlsgd@l     into      addis r3, r13, x@tprel@ha
391
10
  // bl __tls_get_addr(x@tlsgd)      into      nop
392
10
  // nop                             into      addi r3, r3, x@tprel@l
393
10
394
10
  switch (Type) {
395
10
  case R_PPC64_GOT_TLSGD16_HA:
396
2
    writeInstrFromHalf16(Loc, 0x60000000); // nop
397
2
    break;
398
10
  case R_PPC64_GOT_TLSGD16:
399
4
  case R_PPC64_GOT_TLSGD16_LO:
400
4
    writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13
401
4
    relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
402
4
    break;
403
4
  case R_PPC64_TLSGD:
404
4
    write32(Loc, 0x60000000);     // nop
405
4
    write32(Loc + 4, 0x38630000); // addi r3, r3
406
4
    // Since we are relocating a half16 type relocation and Loc + 4 points to
407
4
    // the start of an instruction we need to advance the buffer by an extra
408
4
    // 2 bytes on BE.
409
4
    relocateOne(Loc + 4 + (Config->EKind == ELF64BEKind ? 
22
:
02
),
410
4
                R_PPC64_TPREL16_LO, Val);
411
4
    break;
412
4
  default:
413
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
414
10
  }
415
10
}
416
417
10
void PPC64::relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
418
10
  // Reference: 3.7.4.3 of the 64-bit ELF V2 abi supplement.
419
10
  // The local dynamic code sequence for a global `x` will look like:
420
10
  // Instruction                    Relocation                Symbol
421
10
  // addis r3, r2, x@got@tlsld@ha   R_PPC64_GOT_TLSLD16_HA      x
422
10
  // addi  r3, r3, x@got@tlsld@l    R_PPC64_GOT_TLSLD16_LO      x
423
10
  // bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSLD               x
424
10
  //                                R_PPC64_REL24               __tls_get_addr
425
10
  // nop                            None                       None
426
10
427
10
  // Relaxing to local exec entails converting:
428
10
  // addis r3, r2, x@got@tlsld@ha   into      nop
429
10
  // addi  r3, r3, x@got@tlsld@l    into      addis r3, r13, 0
430
10
  // bl __tls_get_addr(x@tlsgd)     into      nop
431
10
  // nop                            into      addi r3, r3, 4096
432
10
433
10
  switch (Type) {
434
10
  case R_PPC64_GOT_TLSLD16_HA:
435
2
    writeInstrFromHalf16(Loc, 0x60000000); // nop
436
2
    break;
437
10
  case R_PPC64_GOT_TLSLD16_LO:
438
2
    writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13, 0
439
2
    break;
440
10
  case R_PPC64_TLSLD:
441
2
    write32(Loc, 0x60000000);     // nop
442
2
    write32(Loc + 4, 0x38631000); // addi r3, r3, 4096
443
2
    break;
444
10
  case R_PPC64_DTPREL16:
445
4
  case R_PPC64_DTPREL16_HA:
446
4
  case R_PPC64_DTPREL16_HI:
447
4
  case R_PPC64_DTPREL16_DS:
448
4
  case R_PPC64_DTPREL16_LO:
449
4
  case R_PPC64_DTPREL16_LO_DS:
450
4
  case R_PPC64_GOT_DTPREL16_HA:
451
4
  case R_PPC64_GOT_DTPREL16_LO_DS:
452
4
  case R_PPC64_GOT_DTPREL16_DS:
453
4
  case R_PPC64_GOT_DTPREL16_HI:
454
4
    relocateOne(Loc, Type, Val);
455
4
    break;
456
4
  default:
457
0
    llvm_unreachable("unsupported relocation for TLS LD to LE relaxation");
458
10
  }
459
10
}
460
461
20
static unsigned getDFormOp(unsigned SecondaryOp) {
462
20
  switch (SecondaryOp) {
463
20
  case LBZX:
464
2
    return LBZ;
465
20
  case LHZX:
466
2
    return LHZ;
467
20
  case LWZX:
468
2
    return LWZ;
469
20
  case LDX:
470
2
    return LD;
471
20
  case STBX:
472
2
    return STB;
473
20
  case STHX:
474
2
    return STH;
475
20
  case STWX:
476
2
    return STW;
477
20
  case STDX:
478
4
    return STD;
479
20
  case ADD:
480
2
    return ADDI;
481
20
  default:
482
0
    error("unrecognized instruction for IE to LE R_PPC64_TLS");
483
0
    return 0;
484
20
  }
485
20
}
486
487
58
void PPC64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
488
58
  // The initial exec code sequence for a global `x` will look like:
489
58
  // Instruction                    Relocation                Symbol
490
58
  // addis r9, r2, x@got@tprel@ha   R_PPC64_GOT_TPREL16_HA      x
491
58
  // ld    r9, x@got@tprel@l(r9)    R_PPC64_GOT_TPREL16_LO_DS   x
492
58
  // add r9, r9, x@tls              R_PPC64_TLS                 x
493
58
494
58
  // Relaxing to local exec entails converting:
495
58
  // addis r9, r2, x@got@tprel@ha       into        nop
496
58
  // ld r9, x@got@tprel@l(r9)           into        addis r9, r13, x@tprel@ha
497
58
  // add r9, r9, x@tls                  into        addi r9, r9, x@tprel@l
498
58
499
58
  // x@tls R_PPC64_TLS is a relocation which does not compute anything,
500
58
  // it is replaced with r13 (thread pointer).
501
58
502
58
  // The add instruction in the initial exec sequence has multiple variations
503
58
  // that need to be handled. If we are building an address it will use an add
504
58
  // instruction, if we are accessing memory it will use any of the X-form
505
58
  // indexed load or store instructions.
506
58
507
58
  unsigned Offset = (Config->EKind == ELF64BEKind) ? 
229
:
029
;
508
58
  switch (Type) {
509
58
  case R_PPC64_GOT_TPREL16_HA:
510
18
    write32(Loc - Offset, 0x60000000); // nop
511
18
    break;
512
58
  case R_PPC64_GOT_TPREL16_LO_DS:
513
20
  case R_PPC64_GOT_TPREL16_DS: {
514
20
    uint32_t RegNo = read32(Loc - Offset) & 0x03E00000; // bits 6-10
515
20
    write32(Loc - Offset, 0x3C0D0000 | RegNo);          // addis RegNo, r13
516
20
    relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
517
20
    break;
518
20
  }
519
20
  case R_PPC64_TLS: {
520
20
    uint32_t PrimaryOp = getPrimaryOpCode(read32(Loc));
521
20
    if (PrimaryOp != 31)
522
0
      error("unrecognized instruction for IE to LE R_PPC64_TLS");
523
20
    uint32_t SecondaryOp = (read32(Loc) & 0x000007FE) >> 1; // bits 21-30
524
20
    uint32_t DFormOp = getDFormOp(SecondaryOp);
525
20
    write32(Loc, ((DFormOp << 26) | (read32(Loc) & 0x03FFFFFF)));
526
20
    relocateOne(Loc + Offset, R_PPC64_TPREL16_LO, Val);
527
20
    break;
528
20
  }
529
20
  default:
530
0
    llvm_unreachable("unknown relocation for IE to LE");
531
20
    
break0
;
532
58
  }
533
58
}
534
535
RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S,
536
991
                          const uint8_t *Loc) const {
537
991
  switch (Type) {
538
991
  case R_PPC64_GOT16:
539
24
  case R_PPC64_GOT16_DS:
540
24
  case R_PPC64_GOT16_HA:
541
24
  case R_PPC64_GOT16_HI:
542
24
  case R_PPC64_GOT16_LO:
543
24
  case R_PPC64_GOT16_LO_DS:
544
24
    return R_GOT_OFF;
545
35
  case R_PPC64_TOC16:
546
35
  case R_PPC64_TOC16_DS:
547
35
  case R_PPC64_TOC16_HI:
548
35
  case R_PPC64_TOC16_LO:
549
35
    return R_GOTREL;
550
162
  case R_PPC64_TOC16_HA:
551
162
  case R_PPC64_TOC16_LO_DS:
552
162
    return Config->TocOptimize ? 
R_PPC64_RELAX_TOC117
:
R_GOTREL45
;
553
162
  case R_PPC64_TOC:
554
0
    return R_PPC_TOC;
555
162
  case R_PPC64_REL14:
556
148
  case R_PPC64_REL24:
557
148
    return R_PPC_CALL_PLT;
558
326
  case R_PPC64_REL16_LO:
559
326
  case R_PPC64_REL16_HA:
560
326
  case R_PPC64_REL32:
561
326
  case R_PPC64_REL64:
562
326
    return R_PC;
563
326
  case R_PPC64_GOT_TLSGD16:
564
26
  case R_PPC64_GOT_TLSGD16_HA:
565
26
  case R_PPC64_GOT_TLSGD16_HI:
566
26
  case R_PPC64_GOT_TLSGD16_LO:
567
26
    return R_TLSGD_GOT;
568
26
  case R_PPC64_GOT_TLSLD16:
569
24
  case R_PPC64_GOT_TLSLD16_HA:
570
24
  case R_PPC64_GOT_TLSLD16_HI:
571
24
  case R_PPC64_GOT_TLSLD16_LO:
572
24
    return R_TLSLD_GOT;
573
46
  case R_PPC64_GOT_TPREL16_HA:
574
46
  case R_PPC64_GOT_TPREL16_LO_DS:
575
46
  case R_PPC64_GOT_TPREL16_DS:
576
46
  case R_PPC64_GOT_TPREL16_HI:
577
46
    return R_GOT_OFF;
578
46
  case R_PPC64_GOT_DTPREL16_HA:
579
8
  case R_PPC64_GOT_DTPREL16_LO_DS:
580
8
  case R_PPC64_GOT_DTPREL16_DS:
581
8
  case R_PPC64_GOT_DTPREL16_HI:
582
8
    return R_TLSLD_GOT_OFF;
583
14
  case R_PPC64_TPREL16:
584
14
  case R_PPC64_TPREL16_HA:
585
14
  case R_PPC64_TPREL16_LO:
586
14
  case R_PPC64_TPREL16_HI:
587
14
  case R_PPC64_TPREL16_DS:
588
14
  case R_PPC64_TPREL16_LO_DS:
589
14
  case R_PPC64_TPREL16_HIGHER:
590
14
  case R_PPC64_TPREL16_HIGHERA:
591
14
  case R_PPC64_TPREL16_HIGHEST:
592
14
  case R_PPC64_TPREL16_HIGHESTA:
593
14
    return R_TLS;
594
35
  case R_PPC64_DTPREL16:
595
35
  case R_PPC64_DTPREL16_DS:
596
35
  case R_PPC64_DTPREL16_HA:
597
35
  case R_PPC64_DTPREL16_HI:
598
35
  case R_PPC64_DTPREL16_HIGHER:
599
35
  case R_PPC64_DTPREL16_HIGHERA:
600
35
  case R_PPC64_DTPREL16_HIGHEST:
601
35
  case R_PPC64_DTPREL16_HIGHESTA:
602
35
  case R_PPC64_DTPREL16_LO:
603
35
  case R_PPC64_DTPREL16_LO_DS:
604
35
  case R_PPC64_DTPREL64:
605
35
    return R_DTPREL;
606
35
  case R_PPC64_TLSGD:
607
12
    return R_TLSDESC_CALL;
608
35
  case R_PPC64_TLSLD:
609
10
    return R_TLSLD_HINT;
610
35
  case R_PPC64_TLS:
611
22
    return R_TLSIE_HINT;
612
99
  default:
613
99
    return R_ABS;
614
991
  }
615
991
}
616
617
94
void PPC64::writeGotHeader(uint8_t *Buf) const {
618
94
  write64(Buf, getPPC64TocBase());
619
94
}
620
621
24
void PPC64::writePltHeader(uint8_t *Buf) const {
622
24
  // The generic resolver stub goes first.
623
24
  write32(Buf +  0, 0x7c0802a6); // mflr r0
624
24
  write32(Buf +  4, 0x429f0005); // bcl  20,4*cr7+so,8 <_glink+0x8>
625
24
  write32(Buf +  8, 0x7d6802a6); // mflr r11
626
24
  write32(Buf + 12, 0x7c0803a6); // mtlr r0
627
24
  write32(Buf + 16, 0x7d8b6050); // subf r12, r11, r12
628
24
  write32(Buf + 20, 0x380cffcc); // subi r0,r12,52
629
24
  write32(Buf + 24, 0x7800f082); // srdi r0,r0,62,2
630
24
  write32(Buf + 28, 0xe98b002c); // ld   r12,44(r11)
631
24
  write32(Buf + 32, 0x7d6c5a14); // add  r11,r12,r11
632
24
  write32(Buf + 36, 0xe98b0000); // ld   r12,0(r11)
633
24
  write32(Buf + 40, 0xe96b0008); // ld   r11,8(r11)
634
24
  write32(Buf + 44, 0x7d8903a6); // mtctr   r12
635
24
  write32(Buf + 48, 0x4e800420); // bctr
636
24
637
24
  // The 'bcl' instruction will set the link register to the address of the
638
24
  // following instruction ('mflr r11'). Here we store the offset from that
639
24
  // instruction  to the first entry in the GotPlt section.
640
24
  int64_t GotPltOffset = In.GotPlt->getVA() - (In.Plt->getVA() + 8);
641
24
  write64(Buf + 52, GotPltOffset);
642
24
}
643
644
void PPC64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
645
                     uint64_t PltEntryAddr, int32_t Index,
646
30
                     unsigned RelOff) const {
647
30
  int32_t Offset = PltHeaderSize + Index * PltEntrySize;
648
30
  // bl __glink_PLTresolve
649
30
  write32(Buf, 0x48000000 | ((-Offset) & 0x03FFFFFc));
650
30
}
651
652
911
static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) {
653
911
  // Relocations relative to the toc-base need to be adjusted by the Toc offset.
654
911
  uint64_t TocBiasedVal = Val - PPC64TocOffset;
655
911
  // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset.
656
911
  uint64_t DTPBiasedVal = Val - DynamicThreadPointerOffset;
657
911
658
911
  switch (Type) {
659
911
  // TOC biased relocation.
660
911
  case R_PPC64_GOT16:
661
8
  case R_PPC64_GOT_TLSGD16:
662
8
  case R_PPC64_GOT_TLSLD16:
663
8
  case R_PPC64_TOC16:
664
8
    return {R_PPC64_ADDR16, TocBiasedVal};
665
23
  case R_PPC64_GOT16_DS:
666
23
  case R_PPC64_TOC16_DS:
667
23
  case R_PPC64_GOT_TPREL16_DS:
668
23
  case R_PPC64_GOT_DTPREL16_DS:
669
23
    return {R_PPC64_ADDR16_DS, TocBiasedVal};
670
113
  case R_PPC64_GOT16_HA:
671
113
  case R_PPC64_GOT_TLSGD16_HA:
672
113
  case R_PPC64_GOT_TLSLD16_HA:
673
113
  case R_PPC64_GOT_TPREL16_HA:
674
113
  case R_PPC64_GOT_DTPREL16_HA:
675
113
  case R_PPC64_TOC16_HA:
676
113
    return {R_PPC64_ADDR16_HA, TocBiasedVal};
677
113
  case R_PPC64_GOT16_HI:
678
14
  case R_PPC64_GOT_TLSGD16_HI:
679
14
  case R_PPC64_GOT_TLSLD16_HI:
680
14
  case R_PPC64_GOT_TPREL16_HI:
681
14
  case R_PPC64_GOT_DTPREL16_HI:
682
14
  case R_PPC64_TOC16_HI:
683
14
    return {R_PPC64_ADDR16_HI, TocBiasedVal};
684
59
  case R_PPC64_GOT16_LO:
685
59
  case R_PPC64_GOT_TLSGD16_LO:
686
59
  case R_PPC64_GOT_TLSLD16_LO:
687
59
  case R_PPC64_TOC16_LO:
688
59
    return {R_PPC64_ADDR16_LO, TocBiasedVal};
689
60
  case R_PPC64_GOT16_LO_DS:
690
60
  case R_PPC64_TOC16_LO_DS:
691
60
  case R_PPC64_GOT_TPREL16_LO_DS:
692
60
  case R_PPC64_GOT_DTPREL16_LO_DS:
693
60
    return {R_PPC64_ADDR16_LO_DS, TocBiasedVal};
694
60
695
60
  // Dynamic Thread pointer biased relocation types.
696
60
  case R_PPC64_DTPREL16:
697
2
    return {R_PPC64_ADDR16, DTPBiasedVal};
698
60
  case R_PPC64_DTPREL16_DS:
699
2
    return {R_PPC64_ADDR16_DS, DTPBiasedVal};
700
60
  case R_PPC64_DTPREL16_HA:
701
7
    return {R_PPC64_ADDR16_HA, DTPBiasedVal};
702
60
  case R_PPC64_DTPREL16_HI:
703
2
    return {R_PPC64_ADDR16_HI, DTPBiasedVal};
704
60
  case R_PPC64_DTPREL16_HIGHER:
705
2
    return {R_PPC64_ADDR16_HIGHER, DTPBiasedVal};
706
60
  case R_PPC64_DTPREL16_HIGHERA:
707
3
    return {R_PPC64_ADDR16_HIGHERA, DTPBiasedVal};
708
60
  case R_PPC64_DTPREL16_HIGHEST:
709
2
    return {R_PPC64_ADDR16_HIGHEST, DTPBiasedVal};
710
60
  case R_PPC64_DTPREL16_HIGHESTA:
711
3
    return {R_PPC64_ADDR16_HIGHESTA, DTPBiasedVal};
712
60
  case R_PPC64_DTPREL16_LO:
713
7
    return {R_PPC64_ADDR16_LO, DTPBiasedVal};
714
60
  case R_PPC64_DTPREL16_LO_DS:
715
2
    return {R_PPC64_ADDR16_LO_DS, DTPBiasedVal};
716
60
  case R_PPC64_DTPREL64:
717
5
    return {R_PPC64_ADDR64, DTPBiasedVal};
718
60
719
597
  default:
720
597
    return {Type, Val};
721
911
  }
722
911
}
723
724
911
static bool isTocOptType(RelType Type) {
725
911
  switch (Type) {
726
911
  case R_PPC64_GOT16_HA:
727
188
  case R_PPC64_GOT16_LO_DS:
728
188
  case R_PPC64_TOC16_HA:
729
188
  case R_PPC64_TOC16_LO_DS:
730
188
  case R_PPC64_TOC16_LO:
731
188
    return true;
732
723
  default:
733
723
    return false;
734
911
  }
735
911
}
736
737
911
void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
738
911
  // We need to save the original relocation type to use in diagnostics, and
739
911
  // use the original type to determine if we should toc-optimize the
740
911
  // instructions being relocated.
741
911
  RelType OriginalType = Type;
742
911
  bool ShouldTocOptimize =  isTocOptType(Type);
743
911
  // For dynamic thread pointer relative, toc-relative, and got-indirect
744
911
  // relocations, proceed in terms of the corresponding ADDR16 relocation type.
745
911
  std::tie(Type, Val) = toAddr16Rel(Type, Val);
746
911
747
911
  switch (Type) {
748
911
  case R_PPC64_ADDR14: {
749
0
    checkAlignment(Loc, Val, 4, Type);
750
0
    // Preserve the AA/LK bits in the branch instruction
751
0
    uint8_t AALK = Loc[3];
752
0
    write16(Loc + 2, (AALK & 3) | (Val & 0xfffc));
753
0
    break;
754
911
  }
755
911
  case R_PPC64_ADDR16:
756
13
  case R_PPC64_TPREL16:
757
13
    checkInt(Loc, Val, 16, OriginalType);
758
13
    write16(Loc, Val);
759
13
    break;
760
26
  case R_PPC64_ADDR16_DS:
761
26
  case R_PPC64_TPREL16_DS: {
762
26
    checkInt(Loc, Val, 16, OriginalType);
763
26
    // DQ-form instructions use bits 28-31 as part of the instruction encoding
764
26
    // DS-form instructions only use bits 30-31.
765
26
    uint16_t Mask = isDQFormInstruction(readInstrFromHalf16(Loc)) ? 
0xF0
: 0x3;
766
26
    checkAlignment(Loc, lo(Val), Mask + 1, OriginalType);
767
26
    write16(Loc, (read16(Loc) & Mask) | lo(Val));
768
26
  } break;
769
306
  case R_PPC64_ADDR16_HA:
770
306
  case R_PPC64_REL16_HA:
771
306
  case R_PPC64_TPREL16_HA:
772
306
    if (Config->TocOptimize && 
ShouldTocOptimize261
&&
ha(Val) == 065
)
773
39
      writeInstrFromHalf16(Loc, 0x60000000);
774
267
    else
775
267
      write16(Loc, ha(Val));
776
306
    break;
777
306
  case R_PPC64_ADDR16_HI:
778
20
  case R_PPC64_REL16_HI:
779
20
  case R_PPC64_TPREL16_HI:
780
20
    write16(Loc, hi(Val));
781
20
    break;
782
20
  case R_PPC64_ADDR16_HIGHER:
783
5
  case R_PPC64_TPREL16_HIGHER:
784
5
    write16(Loc, higher(Val));
785
5
    break;
786
6
  case R_PPC64_ADDR16_HIGHERA:
787
6
  case R_PPC64_TPREL16_HIGHERA:
788
6
    write16(Loc, highera(Val));
789
6
    break;
790
6
  case R_PPC64_ADDR16_HIGHEST:
791
5
  case R_PPC64_TPREL16_HIGHEST:
792
5
    write16(Loc, highest(Val));
793
5
    break;
794
6
  case R_PPC64_ADDR16_HIGHESTA:
795
6
  case R_PPC64_TPREL16_HIGHESTA:
796
6
    write16(Loc, highesta(Val));
797
6
    break;
798
253
  case R_PPC64_ADDR16_LO:
799
253
  case R_PPC64_REL16_LO:
800
253
  case R_PPC64_TPREL16_LO:
801
253
    // When the high-adjusted part of a toc relocation evalutes to 0, it is
802
253
    // changed into a nop. The lo part then needs to be updated to use the
803
253
    // toc-pointer register r2, as the base register.
804
253
    if (Config->TocOptimize && 
ShouldTocOptimize225
&&
ha(Val) == 036
) {
805
18
      uint32_t Instr = readInstrFromHalf16(Loc);
806
18
      if (isInstructionUpdateForm(Instr))
807
0
        error(getErrorLocation(Loc) +
808
0
              "can't toc-optimize an update instruction: 0x" +
809
0
              utohexstr(Instr));
810
18
      Instr = (Instr & 0xFFE00000) | 0x00020000;
811
18
      writeInstrFromHalf16(Loc, Instr);
812
18
    }
813
253
    write16(Loc, lo(Val));
814
253
    break;
815
253
  case R_PPC64_ADDR16_LO_DS:
816
63
  case R_PPC64_TPREL16_LO_DS: {
817
63
    // DQ-form instructions use bits 28-31 as part of the instruction encoding
818
63
    // DS-form instructions only use bits 30-31.
819
63
    uint32_t Inst = readInstrFromHalf16(Loc);
820
63
    uint16_t Mask = isDQFormInstruction(Inst) ? 
0xF12
:
0x351
;
821
63
    checkAlignment(Loc, lo(Val), Mask + 1, OriginalType);
822
63
    if (Config->TocOptimize && 
ShouldTocOptimize42
&&
ha(Val) == 029
) {
823
21
      // When the high-adjusted part of a toc relocation evalutes to 0, it is
824
21
      // changed into a nop. The lo part then needs to be updated to use the toc
825
21
      // pointer register r2, as the base register.
826
21
      if (isInstructionUpdateForm(Inst))
827
0
        error(getErrorLocation(Loc) +
828
0
              "Can't toc-optimize an update instruction: 0x" +
829
0
              Twine::utohexstr(Inst));
830
21
      Inst = (Inst & 0xFFE0000F) | 0x00020000;
831
21
      writeInstrFromHalf16(Loc, Inst);
832
21
    }
833
63
    write16(Loc, (read16(Loc) & Mask) | lo(Val));
834
63
  } break;
835
63
  case R_PPC64_ADDR32:
836
12
  case R_PPC64_REL32:
837
12
    checkInt(Loc, Val, 32, Type);
838
12
    write32(Loc, Val);
839
12
    break;
840
54
  case R_PPC64_ADDR64:
841
54
  case R_PPC64_REL64:
842
54
  case R_PPC64_TOC:
843
54
    write64(Loc, Val);
844
54
    break;
845
54
  case R_PPC64_REL14: {
846
2
    uint32_t Mask = 0x0000FFFC;
847
2
    checkInt(Loc, Val, 16, Type);
848
2
    checkAlignment(Loc, Val, 4, Type);
849
2
    write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
850
2
    break;
851
54
  }
852
140
  case R_PPC64_REL24: {
853
140
    uint32_t Mask = 0x03FFFFFC;
854
140
    checkInt(Loc, Val, 26, Type);
855
140
    checkAlignment(Loc, Val, 4, Type);
856
140
    write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
857
140
    break;
858
54
  }
859
54
  case R_PPC64_DTPREL64:
860
0
    write64(Loc, Val - DynamicThreadPointerOffset);
861
0
    break;
862
54
  default:
863
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
864
911
  }
865
911
}
866
867
bool PPC64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
868
1.03k
                       uint64_t BranchAddr, const Symbol &S) const {
869
1.03k
  if (Type != R_PPC64_REL14 && 
Type != R_PPC64_REL241.03k
)
870
879
    return false;
871
154
872
154
  // If a function is in the Plt it needs to be called with a call-stub.
873
154
  if (S.isInPlt())
874
36
    return true;
875
118
876
118
  // If a symbol is a weak undefined and we are compiling an executable
877
118
  // it doesn't need a range-extending thunk since it can't be called.
878
118
  if (S.isUndefWeak() && 
!Config->Shared2
)
879
2
    return false;
880
116
881
116
  // If the offset exceeds the range of the branch type then it will need
882
116
  // a range-extending thunk.
883
116
  // See the comment in getRelocTargetVA() about R_PPC64_CALL.
884
116
  return !inBranchRange(Type, BranchAddr,
885
116
                        S.getVA() +
886
116
                            getPPC64GlobalEntryToLocalEntryOffset(S.StOther));
887
116
}
888
889
308
uint32_t PPC64::getThunkSectionSpacing() const {
890
308
  // See comment in Arch/ARM.cpp for a more detailed explanation of
891
308
  // getThunkSectionSpacing(). For PPC64 we pick the constant here based on
892
308
  // R_PPC64_REL24, which is used by unconditional branch instructions.
893
308
  // 0x2000000 = (1 << 24-1) * 4
894
308
  return 0x2000000;
895
308
}
896
897
216
bool PPC64::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
898
216
  int64_t Offset = Dst - Src;
899
216
  if (Type == R_PPC64_REL14)
900
2
    return isInt<16>(Offset);
901
214
  if (Type == R_PPC64_REL24)
902
214
    return isInt<26>(Offset);
903
0
  llvm_unreachable("unsupported relocation type used in branch");
904
0
}
905
906
RelExpr PPC64::adjustRelaxExpr(RelType Type, const uint8_t *Data,
907
38
                               RelExpr Expr) const {
908
38
  if (Expr == R_RELAX_TLS_GD_TO_IE)
909
18
    return R_RELAX_TLS_GD_TO_IE_GOT_OFF;
910
20
  if (Expr == R_RELAX_TLS_LD_TO_LE)
911
10
    return R_RELAX_TLS_LD_TO_LE_ABS;
912
10
  return Expr;
913
10
}
914
915
// Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement.
916
// The general dynamic code sequence for a global `x` uses 4 instructions.
917
// Instruction                    Relocation                Symbol
918
// addis r3, r2, x@got@tlsgd@ha   R_PPC64_GOT_TLSGD16_HA      x
919
// addi  r3, r3, x@got@tlsgd@l    R_PPC64_GOT_TLSGD16_LO      x
920
// bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSGD               x
921
//                                R_PPC64_REL24               __tls_get_addr
922
// nop                            None                       None
923
//
924
// Relaxing to initial-exec entails:
925
// 1) Convert the addis/addi pair that builds the address of the tls_index
926
//    struct for 'x' to an addis/ld pair that loads an offset from a got-entry.
927
// 2) Convert the call to __tls_get_addr to a nop.
928
// 3) Convert the nop following the call to an add of the loaded offset to the
929
//    thread pointer.
930
// Since the nop must directly follow the call, the R_PPC64_TLSGD relocation is
931
// used as the relaxation hint for both steps 2 and 3.
932
18
void PPC64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
933
18
  switch (Type) {
934
18
  case R_PPC64_GOT_TLSGD16_HA:
935
6
    // This is relaxed from addis rT, r2, sym@got@tlsgd@ha to
936
6
    //                      addis rT, r2, sym@got@tprel@ha.
937
6
    relocateOne(Loc, R_PPC64_GOT_TPREL16_HA, Val);
938
6
    return;
939
18
  case R_PPC64_GOT_TLSGD16_LO: {
940
6
    // Relax from addi  r3, rA, sym@got@tlsgd@l to
941
6
    //            ld r3, sym@got@tprel@l(rA)
942
6
    uint32_t InputRegister = (readInstrFromHalf16(Loc) & (0x1f << 16));
943
6
    writeInstrFromHalf16(Loc, 0xE8600000 | InputRegister);
944
6
    relocateOne(Loc, R_PPC64_GOT_TPREL16_LO_DS, Val);
945
6
    return;
946
18
  }
947
18
  case R_PPC64_TLSGD:
948
6
    write32(Loc, 0x60000000);     // bl __tls_get_addr(sym@tlsgd) --> nop
949
6
    write32(Loc + 4, 0x7c636A14); // nop --> add r3, r3, r13
950
6
    return;
951
18
  default:
952
0
    llvm_unreachable("unsupported relocation for TLS GD to IE relaxation");
953
18
  }
954
18
}
955
956
// The prologue for a split-stack function is expected to look roughly
957
// like this:
958
//    .Lglobal_entry_point:
959
//      # TOC pointer initalization.
960
//      ...
961
//    .Llocal_entry_point:
962
//      # load the __private_ss member of the threads tcbhead.
963
//      ld r0,-0x7000-64(r13)
964
//      # subtract the functions stack size from the stack pointer.
965
//      addis r12, r1, ha(-stack-frame size)
966
//      addi  r12, r12, l(-stack-frame size)
967
//      # compare needed to actual and branch to allocate_more_stack if more
968
//      # space is needed, otherwise fallthrough to 'normal' function body.
969
//      cmpld cr7,r12,r0
970
//      blt- cr7, .Lallocate_more_stack
971
//
972
// -) The allocate_more_stack block might be placed after the split-stack
973
//    prologue and the `blt-` replaced with a `bge+ .Lnormal_func_body`
974
//    instead.
975
// -) If either the addis or addi is not needed due to the stack size being
976
//    smaller then 32K or a multiple of 64K they will be replaced with a nop,
977
//    but there will always be 2 instructions the linker can overwrite for the
978
//    adjusted stack size.
979
//
980
// The linkers job here is to increase the stack size used in the addis/addi
981
// pair by split-stack-size-adjust.
982
// addis r12, r1, ha(-stack-frame size - split-stack-adjust-size)
983
// addi  r12, r12, l(-stack-frame size - split-stack-adjust-size)
984
bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *Loc, uint8_t *End,
985
22
                                             uint8_t StOther) const {
986
22
  // If the caller has a global entry point adjust the buffer past it. The start
987
22
  // of the split-stack prologue will be at the local entry point.
988
22
  Loc += getPPC64GlobalEntryToLocalEntryOffset(StOther);
989
22
990
22
  // At the very least we expect to see a load of some split-stack data from the
991
22
  // tcb, and 2 instructions that calculate the ending stack address this
992
22
  // function will require. If there is not enough room for at least 3
993
22
  // instructions it can't be a split-stack prologue.
994
22
  if (Loc + 12 >= End)
995
0
    return false;
996
22
997
22
  // First instruction must be `ld r0, -0x7000-64(r13)`
998
22
  if (read32(Loc) != 0xe80d8fc0)
999
0
    return false;
1000
22
1001
22
  int16_t HiImm = 0;
1002
22
  int16_t LoImm = 0;
1003
22
  // First instruction can be either an addis if the frame size is larger then
1004
22
  // 32K, or an addi if the size is less then 32K.
1005
22
  int32_t FirstInstr = read32(Loc + 4);
1006
22
  if (getPrimaryOpCode(FirstInstr) == 15) {
1007
12
    HiImm = FirstInstr & 0xFFFF;
1008
12
  } else 
if (10
getPrimaryOpCode(FirstInstr) == 1410
) {
1009
10
    LoImm = FirstInstr & 0xFFFF;
1010
10
  } else {
1011
0
    return false;
1012
0
  }
1013
22
1014
22
  // Second instruction is either an addi or a nop. If the first instruction was
1015
22
  // an addi then LoImm is set and the second instruction must be a nop.
1016
22
  uint32_t SecondInstr = read32(Loc + 8);
1017
22
  if (!LoImm && 
getPrimaryOpCode(SecondInstr) == 1412
) {
1018
10
    LoImm = SecondInstr & 0xFFFF;
1019
12
  } else if (SecondInstr != 0x60000000) {
1020
0
    return false;
1021
0
  }
1022
22
1023
22
  // The register operands of the first instruction should be the stack-pointer
1024
22
  // (r1) as the input (RA) and r12 as the output (RT). If the second
1025
22
  // instruction is not a nop, then it should use r12 as both input and output.
1026
22
  auto CheckRegOperands = [](uint32_t Instr, uint8_t ExpectedRT,
1027
30
                             uint8_t ExpectedRA) {
1028
30
    return ((Instr & 0x3E00000) >> 21 == ExpectedRT) &&
1029
30
           
((Instr & 0x1F0000) >> 16 == ExpectedRA)28
;
1030
30
  };
1031
22
  if (!CheckRegOperands(FirstInstr, 12, 1))
1032
2
    return false;
1033
20
  if (SecondInstr != 0x60000000 && 
!CheckRegOperands(SecondInstr, 12, 12)8
)
1034
0
    return false;
1035
20
1036
20
  int32_t StackFrameSize = (HiImm * 65536) + LoImm;
1037
20
  // Check that the adjusted size doesn't overflow what we can represent with 2
1038
20
  // instructions.
1039
20
  if (StackFrameSize < Config->SplitStackAdjustSize + INT32_MIN) {
1040
4
    error(getErrorLocation(Loc) + "split-stack prologue adjustment overflows");
1041
4
    return false;
1042
4
  }
1043
16
1044
16
  int32_t AdjustedStackFrameSize =
1045
16
      StackFrameSize - Config->SplitStackAdjustSize;
1046
16
1047
16
  LoImm = AdjustedStackFrameSize & 0xFFFF;
1048
16
  HiImm = (AdjustedStackFrameSize + 0x8000) >> 16;
1049
16
  if (HiImm) {
1050
10
    write32(Loc + 4, 0x3D810000 | (uint16_t)HiImm);
1051
10
    // If the low immediate is zero the second instruction will be a nop.
1052
10
    SecondInstr = LoImm ? 
0x398C0000 | (uint16_t)LoImm8
:
0x600000002
;
1053
10
    write32(Loc + 8, SecondInstr);
1054
10
  } else {
1055
6
    // addi r12, r1, imm
1056
6
    write32(Loc + 4, (0x39810000) | (uint16_t)LoImm);
1057
6
    write32(Loc + 8, 0x60000000);
1058
6
  }
1059
16
1060
16
  return true;
1061
16
}
1062
1063
159
TargetInfo *elf::getPPC64TargetInfo() {
1064
159
  static PPC64 Target;
1065
159
  return &Target;
1066
159
}