Coverage Report

Created: 2018-08-19 14:04

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/PPC64.cpp
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Source (jump to first uncovered line)
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//===- PPC64.cpp ----------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#include "Symbols.h"
11
#include "SyntheticSections.h"
12
#include "Target.h"
13
#include "lld/Common/ErrorHandler.h"
14
#include "llvm/Support/Endian.h"
15
16
using namespace llvm;
17
using namespace llvm::object;
18
using namespace llvm::support::endian;
19
using namespace llvm::ELF;
20
using namespace lld;
21
using namespace lld::elf;
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23
static uint64_t PPC64TocOffset = 0x8000;
24
static uint64_t DynamicThreadPointerOffset = 0x8000;
25
26
55
uint64_t elf::getPPC64TocBase() {
27
55
  // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
28
55
  // TOC starts where the first of these sections starts. We always create a
29
55
  // .got when we see a relocation that uses it, so for us the start is always
30
55
  // the .got.
31
55
  uint64_t TocVA = InX::Got->getVA();
32
55
33
55
  // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
34
55
  // thus permitting a full 64 Kbytes segment. Note that the glibc startup
35
55
  // code (crt1.o) assumes that you can get from the TOC base to the
36
55
  // start of the .toc section with only a single (signed) 16-bit relocation.
37
55
  return TocVA + PPC64TocOffset;
38
55
}
39
40
namespace {
41
class PPC64 final : public TargetInfo {
42
public:
43
  PPC64();
44
  uint32_t calcEFlags() const override;
45
  RelExpr getRelExpr(RelType Type, const Symbol &S,
46
                     const uint8_t *Loc) const override;
47
  void writePltHeader(uint8_t *Buf) const override;
48
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
49
                int32_t Index, unsigned RelOff) const override;
50
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
51
  void writeGotHeader(uint8_t *Buf) const override;
52
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
53
                  uint64_t BranchAddr, const Symbol &S) const override;
54
  RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
55
                          RelExpr Expr) const override;
56
  void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
57
  void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
58
  void relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
59
};
60
} // namespace
61
62
// Relocation masks following the #lo(value), #hi(value), #ha(value),
63
// #higher(value), #highera(value), #highest(value), and #highesta(value)
64
// macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
65
// document.
66
106
static uint16_t lo(uint64_t V) { return V; }
67
16
static uint16_t hi(uint64_t V) { return V >> 16; }
68
99
static uint16_t ha(uint64_t V) { return (V + 0x8000) >> 16; }
69
5
static uint16_t higher(uint64_t V) { return V >> 32; }
70
5
static uint16_t highera(uint64_t V) { return (V + 0x8000) >> 32; }
71
5
static uint16_t highest(uint64_t V) { return V >> 48; }
72
5
static uint16_t highesta(uint64_t V) { return (V + 0x8000) >> 48; }
73
74
86
PPC64::PPC64() {
75
86
  GotRel = R_PPC64_GLOB_DAT;
76
86
  PltRel = R_PPC64_JMP_SLOT;
77
86
  RelativeRel = R_PPC64_RELATIVE;
78
86
  IRelativeRel = R_PPC64_IRELATIVE;
79
86
  GotEntrySize = 8;
80
86
  PltEntrySize = 4;
81
86
  GotPltEntrySize = 8;
82
86
  GotBaseSymInGotPlt = false;
83
86
  GotBaseSymOff = 0x8000;
84
86
  GotHeaderEntriesNum = 1;
85
86
  GotPltHeaderEntriesNum = 2;
86
86
  PltHeaderSize = 60;
87
86
  NeedsThunks = true;
88
86
  TcbSize = 8;
89
86
  TlsTpOffset = 0x7000;
90
86
91
86
  TlsModuleIndexRel = R_PPC64_DTPMOD64;
92
86
  TlsOffsetRel = R_PPC64_DTPREL64;
93
86
94
86
  TlsGotRel = R_PPC64_TPREL64;
95
86
96
86
  // We need 64K pages (at least under glibc/Linux, the loader won't
97
86
  // set different permissions on a finer granularity than that).
98
86
  DefaultMaxPageSize = 65536;
99
86
100
86
  // The PPC64 ELF ABI v1 spec, says:
101
86
  //
102
86
  //   It is normally desirable to put segments with different characteristics
103
86
  //   in separate 256 Mbyte portions of the address space, to give the
104
86
  //   operating system full paging flexibility in the 64-bit address space.
105
86
  //
106
86
  // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
107
86
  // use 0x10000000 as the starting address.
108
86
  DefaultImageBase = 0x10000000;
109
86
110
86
  TrapInstr =
111
86
      (Config->IsLE == sys::IsLittleEndianHost) ? 
0x7fe0000843
:
0x0800e07f43
;
112
86
}
113
114
91
static uint32_t getEFlags(InputFile *File) {
115
91
  if (Config->EKind == ELF64BEKind)
116
44
    return cast<ObjFile<ELF64BE>>(File)->getObj().getHeader()->e_flags;
117
47
  return cast<ObjFile<ELF64LE>>(File)->getObj().getHeader()->e_flags;
118
47
}
119
120
// This file implements v2 ABI. This function makes sure that all
121
// object files have v2 or an unspecified version as an ABI version.
122
83
uint32_t PPC64::calcEFlags() const {
123
91
  for (InputFile *F : ObjectFiles) {
124
91
    uint32_t Flag = getEFlags(F);
125
91
    if (Flag == 1)
126
1
      error(toString(F) + ": ABI version 1 is not supported");
127
90
    else if (Flag > 2)
128
1
      error(toString(F) + ": unrecognized e_flags: " + Twine(Flag));
129
91
  }
130
83
  return 2;
131
83
}
132
133
6
void PPC64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
134
6
  // Reference: 3.7.4.2 of the 64-bit ELF V2 abi supplement.
135
6
  // The general dynamic code sequence for a global `x` will look like:
136
6
  // Instruction                    Relocation                Symbol
137
6
  // addis r3, r2, x@got@tlsgd@ha   R_PPC64_GOT_TLSGD16_HA      x
138
6
  // addi  r3, r3, x@got@tlsgd@l    R_PPC64_GOT_TLSGD16_LO      x
139
6
  // bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSGD               x
140
6
  //                                R_PPC64_REL24               __tls_get_addr
141
6
  // nop                            None                       None
142
6
143
6
  // Relaxing to local exec entails converting:
144
6
  // addis r3, r2, x@got@tlsgd@ha    into      nop
145
6
  // addi  r3, r3, x@got@tlsgd@l     into      addis r3, r13, x@tprel@ha
146
6
  // bl __tls_get_addr(x@tlsgd)      into      nop
147
6
  // nop                             into      addi r3, r3, x@tprel@l
148
6
149
6
  uint32_t EndianOffset = Config->EKind == ELF64BEKind ? 
2U3
:
0U3
;
150
6
151
6
  switch (Type) {
152
6
  case R_PPC64_GOT_TLSGD16_HA:
153
2
    write32(Loc - EndianOffset, 0x60000000); // nop
154
2
    break;
155
6
  case R_PPC64_GOT_TLSGD16_LO:
156
2
    write32(Loc - EndianOffset, 0x3c6d0000); // addis r3, r13
157
2
    relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
158
2
    break;
159
6
  case R_PPC64_TLSGD:
160
2
    write32(Loc, 0x60000000);     // nop
161
2
    write32(Loc + 4, 0x38630000); // addi r3, r3
162
2
    relocateOne(Loc + 4 + EndianOffset, R_PPC64_TPREL16_LO, Val);
163
2
    break;
164
6
  default:
165
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
166
6
  }
167
6
}
168
169
170
10
void PPC64::relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
171
10
  // Reference: 3.7.4.3 of the 64-bit ELF V2 abi supplement.
172
10
  // The local dynamic code sequence for a global `x` will look like:
173
10
  // Instruction                    Relocation                Symbol
174
10
  // addis r3, r2, x@got@tlsld@ha   R_PPC64_GOT_TLSLD16_HA      x
175
10
  // addi  r3, r3, x@got@tlsld@l    R_PPC64_GOT_TLSLD16_LO      x
176
10
  // bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSLD               x
177
10
  //                                R_PPC64_REL24               __tls_get_addr
178
10
  // nop                            None                       None
179
10
180
10
  // Relaxing to local exec entails converting:
181
10
  // addis r3, r2, x@got@tlsld@ha   into      nop
182
10
  // addi  r3, r3, x@got@tlsld@l    into      addis r3, r13, 0
183
10
  // bl __tls_get_addr(x@tlsgd)     into      nop
184
10
  // nop                            into      addi r3, r3, 4096
185
10
186
10
  uint32_t EndianOffset = Config->EKind == ELF64BEKind ? 
2U5
:
0U5
;
187
10
  switch (Type) {
188
10
  case R_PPC64_GOT_TLSLD16_HA:
189
2
    write32(Loc - EndianOffset, 0x60000000); // nop
190
2
    break;
191
10
  case R_PPC64_GOT_TLSLD16_LO:
192
2
    write32(Loc - EndianOffset, 0x3c6d0000); // addis r3, r13, 0
193
2
    break;
194
10
  case R_PPC64_TLSLD:
195
2
    write32(Loc, 0x60000000);     // nop
196
2
    write32(Loc + 4, 0x38631000); // addi r3, r3, 4096
197
2
    break;
198
10
  case R_PPC64_DTPREL16:
199
4
  case R_PPC64_DTPREL16_HA:
200
4
  case R_PPC64_DTPREL16_HI:
201
4
  case R_PPC64_DTPREL16_DS:
202
4
  case R_PPC64_DTPREL16_LO:
203
4
  case R_PPC64_DTPREL16_LO_DS:
204
4
  case R_PPC64_GOT_DTPREL16_HA:
205
4
  case R_PPC64_GOT_DTPREL16_LO_DS:
206
4
  case R_PPC64_GOT_DTPREL16_DS:
207
4
  case R_PPC64_GOT_DTPREL16_HI:
208
4
    relocateOne(Loc, Type, Val);
209
4
    break;
210
4
  default:
211
0
    llvm_unreachable("unsupported relocation for TLS LD to LE relaxation");
212
10
  }
213
10
}
214
215
RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S,
216
362
                          const uint8_t *Loc) const {
217
362
  switch (Type) {
218
362
  case R_PPC64_TOC16:
219
28
  case R_PPC64_TOC16_DS:
220
28
  case R_PPC64_TOC16_HA:
221
28
  case R_PPC64_TOC16_HI:
222
28
  case R_PPC64_TOC16_LO:
223
28
  case R_PPC64_TOC16_LO_DS:
224
28
    return R_GOTREL;
225
28
  case R_PPC64_TOC:
226
0
    return R_PPC_TOC;
227
42
  case R_PPC64_REL24:
228
42
    return R_PPC_CALL_PLT;
229
114
  case R_PPC64_REL16_LO:
230
114
  case R_PPC64_REL16_HA:
231
114
  case R_PPC64_REL32:
232
114
  case R_PPC64_REL64:
233
114
    return R_PC;
234
114
  case R_PPC64_GOT_TLSGD16:
235
24
  case R_PPC64_GOT_TLSGD16_HA:
236
24
  case R_PPC64_GOT_TLSGD16_HI:
237
24
  case R_PPC64_GOT_TLSGD16_LO:
238
24
    return R_TLSGD_GOT;
239
24
  case R_PPC64_GOT_TLSLD16:
240
24
  case R_PPC64_GOT_TLSLD16_HA:
241
24
  case R_PPC64_GOT_TLSLD16_HI:
242
24
  case R_PPC64_GOT_TLSLD16_LO:
243
24
    return R_TLSLD_GOT;
244
24
  case R_PPC64_GOT_TPREL16_HA:
245
8
  case R_PPC64_GOT_TPREL16_LO_DS:
246
8
  case R_PPC64_GOT_TPREL16_DS:
247
8
  case R_PPC64_GOT_TPREL16_HI:
248
8
    return R_GOT_OFF;
249
8
  case R_PPC64_GOT_DTPREL16_HA:
250
8
  case R_PPC64_GOT_DTPREL16_LO_DS:
251
8
  case R_PPC64_GOT_DTPREL16_DS:
252
8
  case R_PPC64_GOT_DTPREL16_HI:
253
8
    return R_TLSLD_GOT_OFF;
254
14
  case R_PPC64_TPREL16:
255
14
  case R_PPC64_TPREL16_HA:
256
14
  case R_PPC64_TPREL16_LO:
257
14
  case R_PPC64_TPREL16_HI:
258
14
  case R_PPC64_TPREL16_DS:
259
14
  case R_PPC64_TPREL16_LO_DS:
260
14
  case R_PPC64_TPREL16_HIGHER:
261
14
  case R_PPC64_TPREL16_HIGHERA:
262
14
  case R_PPC64_TPREL16_HIGHEST:
263
14
  case R_PPC64_TPREL16_HIGHESTA:
264
14
    return R_TLS;
265
30
  case R_PPC64_DTPREL16:
266
30
  case R_PPC64_DTPREL16_DS:
267
30
  case R_PPC64_DTPREL16_HA:
268
30
  case R_PPC64_DTPREL16_HI:
269
30
  case R_PPC64_DTPREL16_HIGHER:
270
30
  case R_PPC64_DTPREL16_HIGHERA:
271
30
  case R_PPC64_DTPREL16_HIGHEST:
272
30
  case R_PPC64_DTPREL16_HIGHESTA:
273
30
  case R_PPC64_DTPREL16_LO:
274
30
  case R_PPC64_DTPREL16_LO_DS:
275
30
  case R_PPC64_DTPREL64:
276
30
    return R_ABS;
277
30
  case R_PPC64_TLSGD:
278
10
    return R_TLSDESC_CALL;
279
30
  case R_PPC64_TLSLD:
280
10
    return R_TLSLD_HINT;
281
30
  case R_PPC64_TLS:
282
2
    return R_HINT;
283
48
  default:
284
48
    return R_ABS;
285
362
  }
286
362
}
287
288
33
void PPC64::writeGotHeader(uint8_t *Buf) const {
289
33
  write64(Buf, getPPC64TocBase());
290
33
}
291
292
20
void PPC64::writePltHeader(uint8_t *Buf) const {
293
20
  // The generic resolver stub goes first.
294
20
  write32(Buf +  0, 0x7c0802a6); // mflr r0
295
20
  write32(Buf +  4, 0x429f0005); // bcl  20,4*cr7+so,8 <_glink+0x8>
296
20
  write32(Buf +  8, 0x7d6802a6); // mflr r11
297
20
  write32(Buf + 12, 0x7c0803a6); // mtlr r0
298
20
  write32(Buf + 16, 0x7d8b6050); // subf r12, r11, r12
299
20
  write32(Buf + 20, 0x380cffcc); // subi r0,r12,52
300
20
  write32(Buf + 24, 0x7800f082); // srdi r0,r0,62,2
301
20
  write32(Buf + 28, 0xe98b002c); // ld   r12,44(r11)
302
20
  write32(Buf + 32, 0x7d6c5a14); // add  r11,r12,r11
303
20
  write32(Buf + 36, 0xe98b0000); // ld   r12,0(r11)
304
20
  write32(Buf + 40, 0xe96b0008); // ld   r11,8(r11)
305
20
  write32(Buf + 44, 0x7d8903a6); // mtctr   r12
306
20
  write32(Buf + 48, 0x4e800420); // bctr
307
20
308
20
  // The 'bcl' instruction will set the link register to the address of the
309
20
  // following instruction ('mflr r11'). Here we store the offset from that
310
20
  // instruction  to the first entry in the GotPlt section.
311
20
  int64_t GotPltOffset = InX::GotPlt->getVA() - (InX::Plt->getVA() + 8);
312
20
  write64(Buf + 52, GotPltOffset);
313
20
}
314
315
void PPC64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
316
                     uint64_t PltEntryAddr, int32_t Index,
317
22
                     unsigned RelOff) const {
318
22
 int32_t Offset = PltHeaderSize + Index * PltEntrySize;
319
22
 // bl __glink_PLTresolve
320
22
 write32(Buf, 0x48000000 | ((-Offset) & 0x03FFFFFc));
321
22
}
322
323
313
static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) {
324
313
  // Relocations relative to the toc-base need to be adjusted by the Toc offset.
325
313
  uint64_t TocBiasedVal = Val - PPC64TocOffset;
326
313
  // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset.
327
313
  uint64_t DTPBiasedVal = Val - DynamicThreadPointerOffset;
328
313
329
313
  switch (Type) {
330
313
  // TOC biased relocation.
331
313
  case R_PPC64_GOT_TLSGD16:
332
4
  case R_PPC64_GOT_TLSLD16:
333
4
  case R_PPC64_TOC16:
334
4
    return {R_PPC64_ADDR16, TocBiasedVal};
335
4
  case R_PPC64_TOC16_DS:
336
4
  case R_PPC64_GOT_TPREL16_DS:
337
4
  case R_PPC64_GOT_DTPREL16_DS:
338
4
    return {R_PPC64_ADDR16_DS, TocBiasedVal};
339
32
  case R_PPC64_GOT_TLSGD16_HA:
340
32
  case R_PPC64_GOT_TLSLD16_HA:
341
32
  case R_PPC64_GOT_TPREL16_HA:
342
32
  case R_PPC64_GOT_DTPREL16_HA:
343
32
  case R_PPC64_TOC16_HA:
344
32
    return {R_PPC64_ADDR16_HA, TocBiasedVal};
345
32
  case R_PPC64_GOT_TLSGD16_HI:
346
10
  case R_PPC64_GOT_TLSLD16_HI:
347
10
  case R_PPC64_GOT_TPREL16_HI:
348
10
  case R_PPC64_GOT_DTPREL16_HI:
349
10
  case R_PPC64_TOC16_HI:
350
10
    return {R_PPC64_ADDR16_HI, TocBiasedVal};
351
14
  case R_PPC64_GOT_TLSGD16_LO:
352
14
  case R_PPC64_GOT_TLSLD16_LO:
353
14
  case R_PPC64_TOC16_LO:
354
14
    return {R_PPC64_ADDR16_LO, TocBiasedVal};
355
20
  case R_PPC64_TOC16_LO_DS:
356
20
  case R_PPC64_GOT_TPREL16_LO_DS:
357
20
  case R_PPC64_GOT_DTPREL16_LO_DS:
358
20
    return {R_PPC64_ADDR16_LO_DS, TocBiasedVal};
359
20
360
20
  // Dynamic Thread pointer biased relocation types.
361
20
  case R_PPC64_DTPREL16:
362
2
    return {R_PPC64_ADDR16, DTPBiasedVal};
363
20
  case R_PPC64_DTPREL16_DS:
364
2
    return {R_PPC64_ADDR16_DS, DTPBiasedVal};
365
20
  case R_PPC64_DTPREL16_HA:
366
6
    return {R_PPC64_ADDR16_HA, DTPBiasedVal};
367
20
  case R_PPC64_DTPREL16_HI:
368
2
    return {R_PPC64_ADDR16_HI, DTPBiasedVal};
369
20
  case R_PPC64_DTPREL16_HIGHER:
370
2
    return {R_PPC64_ADDR16_HIGHER, DTPBiasedVal};
371
20
  case R_PPC64_DTPREL16_HIGHERA:
372
2
    return {R_PPC64_ADDR16_HIGHERA, DTPBiasedVal};
373
20
  case R_PPC64_DTPREL16_HIGHEST:
374
2
    return {R_PPC64_ADDR16_HIGHEST, DTPBiasedVal};
375
20
  case R_PPC64_DTPREL16_HIGHESTA:
376
2
    return {R_PPC64_ADDR16_HIGHESTA, DTPBiasedVal};
377
20
  case R_PPC64_DTPREL16_LO:
378
6
    return {R_PPC64_ADDR16_LO, DTPBiasedVal};
379
20
  case R_PPC64_DTPREL16_LO_DS:
380
2
    return {R_PPC64_ADDR16_LO_DS, DTPBiasedVal};
381
20
  case R_PPC64_DTPREL64:
382
4
    return {R_PPC64_ADDR64, DTPBiasedVal};
383
20
384
197
  default:
385
197
    return {Type, Val};
386
313
  }
387
313
}
388
389
313
void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
390
313
  // For a TOC-relative relocation, proceed in terms of the corresponding
391
313
  // ADDR16 relocation type.
392
313
  std::tie(Type, Val) = toAddr16Rel(Type, Val);
393
313
394
313
  switch (Type) {
395
313
  case R_PPC64_ADDR14: {
396
0
    checkAlignment(Loc, Val, 4, Type);
397
0
    // Preserve the AA/LK bits in the branch instruction
398
0
    uint8_t AALK = Loc[3];
399
0
    write16(Loc + 2, (AALK & 3) | (Val & 0xfffc));
400
0
    break;
401
313
  }
402
313
  case R_PPC64_ADDR16:
403
9
  case R_PPC64_TPREL16:
404
9
    checkInt(Loc, Val, 16, Type);
405
9
    write16(Loc, Val);
406
9
    break;
407
9
  case R_PPC64_ADDR16_DS:
408
7
  case R_PPC64_TPREL16_DS:
409
7
    checkInt(Loc, Val, 16, Type);
410
7
    write16(Loc, (read16(Loc) & 3) | (Val & ~3));
411
7
    break;
412
100
  case R_PPC64_ADDR16_HA:
413
100
  case R_PPC64_REL16_HA:
414
100
  case R_PPC64_TPREL16_HA:
415
100
    write16(Loc, ha(Val));
416
100
    break;
417
100
  case R_PPC64_ADDR16_HI:
418
16
  case R_PPC64_REL16_HI:
419
16
  case R_PPC64_TPREL16_HI:
420
16
    write16(Loc, hi(Val));
421
16
    break;
422
16
  case R_PPC64_ADDR16_HIGHER:
423
5
  case R_PPC64_TPREL16_HIGHER:
424
5
    write16(Loc, higher(Val));
425
5
    break;
426
5
  case R_PPC64_ADDR16_HIGHERA:
427
5
  case R_PPC64_TPREL16_HIGHERA:
428
5
    write16(Loc, highera(Val));
429
5
    break;
430
5
  case R_PPC64_ADDR16_HIGHEST:
431
5
  case R_PPC64_TPREL16_HIGHEST:
432
5
    write16(Loc, highest(Val));
433
5
    break;
434
5
  case R_PPC64_ADDR16_HIGHESTA:
435
5
  case R_PPC64_TPREL16_HIGHESTA:
436
5
    write16(Loc, highesta(Val));
437
5
    break;
438
83
  case R_PPC64_ADDR16_LO:
439
83
  case R_PPC64_REL16_LO:
440
83
  case R_PPC64_TPREL16_LO:
441
83
    write16(Loc, lo(Val));
442
83
    break;
443
83
  case R_PPC64_ADDR16_LO_DS:
444
23
  case R_PPC64_TPREL16_LO_DS:
445
23
    write16(Loc, (read16(Loc) & 3) | (lo(Val) & ~3));
446
23
    break;
447
23
  case R_PPC64_ADDR32:
448
4
  case R_PPC64_REL32:
449
4
    checkInt(Loc, Val, 32, Type);
450
4
    write32(Loc, Val);
451
4
    break;
452
14
  case R_PPC64_ADDR64:
453
14
  case R_PPC64_REL64:
454
14
  case R_PPC64_TOC:
455
14
    write64(Loc, Val);
456
14
    break;
457
38
  case R_PPC64_REL24: {
458
38
    uint32_t Mask = 0x03FFFFFC;
459
38
    checkInt(Loc, Val, 24, Type);
460
38
    write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
461
38
    break;
462
14
  }
463
14
  case R_PPC64_DTPREL64:
464
0
    write64(Loc, Val - DynamicThreadPointerOffset);
465
0
    break;
466
14
  default:
467
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
468
313
  }
469
313
}
470
471
bool PPC64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
472
418
                       uint64_t BranchAddr, const Symbol &S) const {
473
418
  // If a function is in the plt it needs to be called through
474
418
  // a call stub.
475
418
  return Type == R_PPC64_REL24 && 
S.isInPlt()46
;
476
418
}
477
478
RelExpr PPC64::adjustRelaxExpr(RelType Type, const uint8_t *Data,
479
34
                               RelExpr Expr) const {
480
34
  if (Expr == R_RELAX_TLS_GD_TO_IE)
481
18
    return R_RELAX_TLS_GD_TO_IE_GOT_OFF;
482
16
  if (Expr == R_RELAX_TLS_LD_TO_LE)
483
10
    return R_RELAX_TLS_LD_TO_LE_ABS;
484
6
  return Expr;
485
6
}
486
487
// Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement.
488
// The general dynamic code sequence for a global `x` uses 4 instructions.
489
// Instruction                    Relocation                Symbol
490
// addis r3, r2, x@got@tlsgd@ha   R_PPC64_GOT_TLSGD16_HA      x
491
// addi  r3, r3, x@got@tlsgd@l    R_PPC64_GOT_TLSGD16_LO      x
492
// bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSGD               x
493
//                                R_PPC64_REL24               __tls_get_addr
494
// nop                            None                       None
495
//
496
// Relaxing to initial-exec entails:
497
// 1) Convert the addis/addi pair that builds the address of the tls_index
498
//    struct for 'x' to an addis/ld pair that loads an offset from a got-entry.
499
// 2) Convert the call to __tls_get_addr to a nop.
500
// 3) Convert the nop following the call to an add of the loaded offset to the
501
//    thread pointer.
502
// Since the nop must directly follow the call, the R_PPC64_TLSGD relocation is
503
// used as the relaxation hint for both steps 2 and 3.
504
18
void PPC64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
505
18
  switch (Type) {
506
18
  case R_PPC64_GOT_TLSGD16_HA:
507
6
    // This is relaxed from addis rT, r2, sym@got@tlsgd@ha to
508
6
    //                      addis rT, r2, sym@got@tprel@ha.
509
6
    relocateOne(Loc, R_PPC64_GOT_TPREL16_HA, Val);
510
6
    return;
511
18
  case R_PPC64_GOT_TLSGD16_LO: {
512
6
    // Relax from addi  r3, rA, sym@got@tlsgd@l to
513
6
    //            ld r3, sym@got@tprel@l(rA)
514
6
    uint32_t EndianOffset = Config->EKind == ELF64BEKind ? 
2U3
:
0U3
;
515
6
    uint32_t InputRegister = (read32(Loc - EndianOffset) & (0x1f << 16));
516
6
    write32(Loc - EndianOffset, 0xE8600000 | InputRegister);
517
6
    relocateOne(Loc, R_PPC64_GOT_TPREL16_LO_DS, Val);
518
6
    return;
519
18
  }
520
18
  case R_PPC64_TLSGD:
521
6
    write32(Loc, 0x60000000);     // bl __tls_get_addr(sym@tlsgd) --> nop
522
6
    write32(Loc + 4, 0x7c636A14); // nop --> add r3, r3, r13
523
6
    return;
524
18
  default:
525
0
    llvm_unreachable("unsupported relocation for TLS GD to IE relaxation");
526
18
  }
527
18
}
528
529
86
TargetInfo *elf::getPPC64TargetInfo() {
530
86
  static PPC64 Target;
531
86
  return &Target;
532
86
}