Coverage Report

Created: 2019-01-18 03:29

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/PPC64.cpp
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Source (jump to first uncovered line)
1
//===- PPC64.cpp ----------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#include "Symbols.h"
11
#include "SyntheticSections.h"
12
#include "Target.h"
13
#include "lld/Common/ErrorHandler.h"
14
#include "llvm/Support/Endian.h"
15
16
using namespace llvm;
17
using namespace llvm::object;
18
using namespace llvm::support::endian;
19
using namespace llvm::ELF;
20
using namespace lld;
21
using namespace lld::elf;
22
23
static uint64_t PPC64TocOffset = 0x8000;
24
static uint64_t DynamicThreadPointerOffset = 0x8000;
25
26
// The instruction encoding of bits 21-30 from the ISA for the Xform and Dform
27
// instructions that can be used as part of the initial exec TLS sequence.
28
enum XFormOpcd {
29
  LBZX = 87,
30
  LHZX = 279,
31
  LWZX = 23,
32
  LDX = 21,
33
  STBX = 215,
34
  STHX = 407,
35
  STWX = 151,
36
  STDX = 149,
37
  ADD = 266,
38
};
39
40
enum DFormOpcd {
41
  LBZ = 34,
42
  LBZU = 35,
43
  LHZ = 40,
44
  LHZU = 41,
45
  LHAU = 43,
46
  LWZ = 32,
47
  LWZU = 33,
48
  LFSU = 49,
49
  LD = 58,
50
  LFDU = 51,
51
  STB = 38,
52
  STBU = 39,
53
  STH = 44,
54
  STHU = 45,
55
  STW = 36,
56
  STWU = 37,
57
  STFSU = 53,
58
  STFDU = 55,
59
  STD = 62,
60
  ADDI = 14
61
};
62
63
124
uint64_t elf::getPPC64TocBase() {
64
124
  // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
65
124
  // TOC starts where the first of these sections starts. We always create a
66
124
  // .got when we see a relocation that uses it, so for us the start is always
67
124
  // the .got.
68
124
  uint64_t TocVA = In.Got->getVA();
69
124
70
124
  // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
71
124
  // thus permitting a full 64 Kbytes segment. Note that the glibc startup
72
124
  // code (crt1.o) assumes that you can get from the TOC base to the
73
124
  // start of the .toc section with only a single (signed) 16-bit relocation.
74
124
  return TocVA + PPC64TocOffset;
75
124
}
76
77
174
unsigned elf::getPPC64GlobalEntryToLocalEntryOffset(uint8_t StOther) {
78
174
  // The offset is encoded into the 3 most significant bits of the st_other
79
174
  // field, with some special values described in section 3.4.1 of the ABI:
80
174
  // 0   --> Zero offset between the GEP and LEP, and the function does NOT use
81
174
  //         the TOC pointer (r2). r2 will hold the same value on returning from
82
174
  //         the function as it did on entering the function.
83
174
  // 1   --> Zero offset between the GEP and LEP, and r2 should be treated as a
84
174
  //         caller-saved register for all callers.
85
174
  // 2-6 --> The  binary logarithm of the offset eg:
86
174
  //         2 --> 2^2 = 4 bytes -->  1 instruction.
87
174
  //         6 --> 2^6 = 64 bytes --> 16 instructions.
88
174
  // 7   --> Reserved.
89
174
  uint8_t GepToLep = (StOther >> 5) & 7;
90
174
  if (GepToLep < 2)
91
129
    return 0;
92
45
93
45
  // The value encoded in the st_other bits is the
94
45
  // log-base-2(offset).
95
45
  if (GepToLep < 7)
96
45
    return 1 << GepToLep;
97
0
98
0
  error("reserved value of 7 in the 3 most-significant-bits of st_other");
99
0
  return 0;
100
0
}
101
102
namespace {
103
class PPC64 final : public TargetInfo {
104
public:
105
  PPC64();
106
  uint32_t calcEFlags() const override;
107
  RelExpr getRelExpr(RelType Type, const Symbol &S,
108
                     const uint8_t *Loc) const override;
109
  void writePltHeader(uint8_t *Buf) const override;
110
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
111
                int32_t Index, unsigned RelOff) const override;
112
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
113
  void writeGotHeader(uint8_t *Buf) const override;
114
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
115
                  uint64_t BranchAddr, const Symbol &S) const override;
116
  bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
117
  RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
118
                          RelExpr Expr) const override;
119
  void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
120
  void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
121
  void relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
122
  void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
123
124
  bool adjustPrologueForCrossSplitStack(uint8_t *Loc, uint8_t *End,
125
                                        uint8_t StOther) const override;
126
};
127
} // namespace
128
129
// Relocation masks following the #lo(value), #hi(value), #ha(value),
130
// #higher(value), #highera(value), #highest(value), and #highesta(value)
131
// macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
132
// document.
133
358
static uint16_t lo(uint64_t V) { return V; }
134
20
static uint16_t hi(uint64_t V) { return V >> 16; }
135
315
static uint16_t ha(uint64_t V) { return (V + 0x8000) >> 16; }
136
5
static uint16_t higher(uint64_t V) { return V >> 32; }
137
5
static uint16_t highera(uint64_t V) { return (V + 0x8000) >> 32; }
138
5
static uint16_t highest(uint64_t V) { return V >> 48; }
139
5
static uint16_t highesta(uint64_t V) { return (V + 0x8000) >> 48; }
140
141
// Extracts the 'PO' field of an instruction encoding.
142
174
static uint8_t getPrimaryOpCode(uint32_t Encoding) { return (Encoding >> 26); }
143
144
76
static bool isDQFormInstruction(uint32_t Encoding) {
145
76
  switch (getPrimaryOpCode(Encoding)) {
146
76
  default:
147
60
    return false;
148
76
  case 56:
149
2
    // The only instruction with a primary opcode of 56 is `lq`.
150
2
    return true;
151
76
  case 61:
152
14
    // There are both DS and DQ instruction forms with this primary opcode.
153
14
    // Namely `lxv` and `stxv` are the DQ-forms that use it.
154
14
    // The DS 'XO' bits being set to 01 is restricted to DQ form.
155
14
    return (Encoding & 3) == 0x1;
156
76
  }
157
76
}
158
159
34
static bool isInstructionUpdateForm(uint32_t Encoding) {
160
34
  switch (getPrimaryOpCode(Encoding)) {
161
34
  default:
162
16
    return false;
163
34
  case LBZU:
164
0
  case LHAU:
165
0
  case LHZU:
166
0
  case LWZU:
167
0
  case LFSU:
168
0
  case LFDU:
169
0
  case STBU:
170
0
  case STHU:
171
0
  case STWU:
172
0
  case STFSU:
173
0
  case STFDU:
174
0
    return true;
175
0
    // LWA has the same opcode as LD, and the DS bits is what differentiates
176
0
    // between LD/LDU/LWA
177
18
  case LD:
178
18
  case STD:
179
18
    return (Encoding & 3) == 1;
180
34
  }
181
34
}
182
183
// There are a number of places when we either want to read or write an
184
// instruction when handling a half16 relocation type. On big-endian the buffer
185
// pointer is pointing into the middle of the word we want to extract, and on
186
// little-endian it is pointing to the start of the word. These 2 helpers are to
187
// simplify reading and writing in that context.
188
82
static void writeInstrFromHalf16(uint8_t *Loc, uint32_t Instr) {
189
82
  write32(Loc - (Config->EKind == ELF64BEKind ? 
223
:
059
), Instr);
190
82
}
191
192
91
static uint32_t readInstrFromHalf16(const uint8_t *Loc) {
193
91
  return read32(Loc - (Config->EKind == ELF64BEKind ? 
229
:
062
));
194
91
}
195
196
145
PPC64::PPC64() {
197
145
  GotRel = R_PPC64_GLOB_DAT;
198
145
  NoneRel = R_PPC64_NONE;
199
145
  PltRel = R_PPC64_JMP_SLOT;
200
145
  RelativeRel = R_PPC64_RELATIVE;
201
145
  IRelativeRel = R_PPC64_IRELATIVE;
202
145
  GotEntrySize = 8;
203
145
  PltEntrySize = 4;
204
145
  GotPltEntrySize = 8;
205
145
  GotBaseSymInGotPlt = false;
206
145
  GotBaseSymOff = 0x8000;
207
145
  GotHeaderEntriesNum = 1;
208
145
  GotPltHeaderEntriesNum = 2;
209
145
  PltHeaderSize = 60;
210
145
  NeedsThunks = true;
211
145
212
145
  TlsModuleIndexRel = R_PPC64_DTPMOD64;
213
145
  TlsOffsetRel = R_PPC64_DTPREL64;
214
145
215
145
  TlsGotRel = R_PPC64_TPREL64;
216
145
217
145
  NeedsMoreStackNonSplit = false;
218
145
219
145
  // We need 64K pages (at least under glibc/Linux, the loader won't
220
145
  // set different permissions on a finer granularity than that).
221
145
  DefaultMaxPageSize = 65536;
222
145
223
145
  // The PPC64 ELF ABI v1 spec, says:
224
145
  //
225
145
  //   It is normally desirable to put segments with different characteristics
226
145
  //   in separate 256 Mbyte portions of the address space, to give the
227
145
  //   operating system full paging flexibility in the 64-bit address space.
228
145
  //
229
145
  // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
230
145
  // use 0x10000000 as the starting address.
231
145
  DefaultImageBase = 0x10000000;
232
145
233
145
  write32(TrapInstr.data(), 0x7fe00008);
234
145
}
235
236
172
static uint32_t getEFlags(InputFile *File) {
237
172
  if (Config->EKind == ELF64BEKind)
238
80
    return cast<ObjFile<ELF64BE>>(File)->getObj().getHeader()->e_flags;
239
92
  return cast<ObjFile<ELF64LE>>(File)->getObj().getHeader()->e_flags;
240
92
}
241
242
// This file implements v2 ABI. This function makes sure that all
243
// object files have v2 or an unspecified version as an ABI version.
244
142
uint32_t PPC64::calcEFlags() const {
245
172
  for (InputFile *F : ObjectFiles) {
246
172
    uint32_t Flag = getEFlags(F);
247
172
    if (Flag == 1)
248
1
      error(toString(F) + ": ABI version 1 is not supported");
249
171
    else if (Flag > 2)
250
1
      error(toString(F) + ": unrecognized e_flags: " + Twine(Flag));
251
172
  }
252
142
  return 2;
253
142
}
254
255
10
void PPC64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
256
10
  // Reference: 3.7.4.2 of the 64-bit ELF V2 abi supplement.
257
10
  // The general dynamic code sequence for a global `x` will look like:
258
10
  // Instruction                    Relocation                Symbol
259
10
  // addis r3, r2, x@got@tlsgd@ha   R_PPC64_GOT_TLSGD16_HA      x
260
10
  // addi  r3, r3, x@got@tlsgd@l    R_PPC64_GOT_TLSGD16_LO      x
261
10
  // bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSGD               x
262
10
  //                                R_PPC64_REL24               __tls_get_addr
263
10
  // nop                            None                       None
264
10
265
10
  // Relaxing to local exec entails converting:
266
10
  // addis r3, r2, x@got@tlsgd@ha    into      nop
267
10
  // addi  r3, r3, x@got@tlsgd@l     into      addis r3, r13, x@tprel@ha
268
10
  // bl __tls_get_addr(x@tlsgd)      into      nop
269
10
  // nop                             into      addi r3, r3, x@tprel@l
270
10
271
10
  switch (Type) {
272
10
  case R_PPC64_GOT_TLSGD16_HA:
273
2
    writeInstrFromHalf16(Loc, 0x60000000); // nop
274
2
    break;
275
10
  case R_PPC64_GOT_TLSGD16:
276
4
  case R_PPC64_GOT_TLSGD16_LO:
277
4
    writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13
278
4
    relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
279
4
    break;
280
4
  case R_PPC64_TLSGD:
281
4
    write32(Loc, 0x60000000);     // nop
282
4
    write32(Loc + 4, 0x38630000); // addi r3, r3
283
4
    // Since we are relocating a half16 type relocation and Loc + 4 points to
284
4
    // the start of an instruction we need to advance the buffer by an extra
285
4
    // 2 bytes on BE.
286
4
    relocateOne(Loc + 4 + (Config->EKind == ELF64BEKind ? 
22
:
02
),
287
4
                R_PPC64_TPREL16_LO, Val);
288
4
    break;
289
4
  default:
290
0
    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
291
10
  }
292
10
}
293
294
10
void PPC64::relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
295
10
  // Reference: 3.7.4.3 of the 64-bit ELF V2 abi supplement.
296
10
  // The local dynamic code sequence for a global `x` will look like:
297
10
  // Instruction                    Relocation                Symbol
298
10
  // addis r3, r2, x@got@tlsld@ha   R_PPC64_GOT_TLSLD16_HA      x
299
10
  // addi  r3, r3, x@got@tlsld@l    R_PPC64_GOT_TLSLD16_LO      x
300
10
  // bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSLD               x
301
10
  //                                R_PPC64_REL24               __tls_get_addr
302
10
  // nop                            None                       None
303
10
304
10
  // Relaxing to local exec entails converting:
305
10
  // addis r3, r2, x@got@tlsld@ha   into      nop
306
10
  // addi  r3, r3, x@got@tlsld@l    into      addis r3, r13, 0
307
10
  // bl __tls_get_addr(x@tlsgd)     into      nop
308
10
  // nop                            into      addi r3, r3, 4096
309
10
310
10
  switch (Type) {
311
10
  case R_PPC64_GOT_TLSLD16_HA:
312
2
    writeInstrFromHalf16(Loc, 0x60000000); // nop
313
2
    break;
314
10
  case R_PPC64_GOT_TLSLD16_LO:
315
2
    writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13, 0
316
2
    break;
317
10
  case R_PPC64_TLSLD:
318
2
    write32(Loc, 0x60000000);     // nop
319
2
    write32(Loc + 4, 0x38631000); // addi r3, r3, 4096
320
2
    break;
321
10
  case R_PPC64_DTPREL16:
322
4
  case R_PPC64_DTPREL16_HA:
323
4
  case R_PPC64_DTPREL16_HI:
324
4
  case R_PPC64_DTPREL16_DS:
325
4
  case R_PPC64_DTPREL16_LO:
326
4
  case R_PPC64_DTPREL16_LO_DS:
327
4
  case R_PPC64_GOT_DTPREL16_HA:
328
4
  case R_PPC64_GOT_DTPREL16_LO_DS:
329
4
  case R_PPC64_GOT_DTPREL16_DS:
330
4
  case R_PPC64_GOT_DTPREL16_HI:
331
4
    relocateOne(Loc, Type, Val);
332
4
    break;
333
4
  default:
334
0
    llvm_unreachable("unsupported relocation for TLS LD to LE relaxation");
335
10
  }
336
10
}
337
338
20
static unsigned getDFormOp(unsigned SecondaryOp) {
339
20
  switch (SecondaryOp) {
340
20
  case LBZX:
341
2
    return LBZ;
342
20
  case LHZX:
343
2
    return LHZ;
344
20
  case LWZX:
345
2
    return LWZ;
346
20
  case LDX:
347
2
    return LD;
348
20
  case STBX:
349
2
    return STB;
350
20
  case STHX:
351
2
    return STH;
352
20
  case STWX:
353
2
    return STW;
354
20
  case STDX:
355
4
    return STD;
356
20
  case ADD:
357
2
    return ADDI;
358
20
  default:
359
0
    error("unrecognized instruction for IE to LE R_PPC64_TLS");
360
0
    return 0;
361
20
  }
362
20
}
363
364
58
void PPC64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
365
58
  // The initial exec code sequence for a global `x` will look like:
366
58
  // Instruction                    Relocation                Symbol
367
58
  // addis r9, r2, x@got@tprel@ha   R_PPC64_GOT_TPREL16_HA      x
368
58
  // ld    r9, x@got@tprel@l(r9)    R_PPC64_GOT_TPREL16_LO_DS   x
369
58
  // add r9, r9, x@tls              R_PPC64_TLS                 x
370
58
371
58
  // Relaxing to local exec entails converting:
372
58
  // addis r9, r2, x@got@tprel@ha       into        nop
373
58
  // ld r9, x@got@tprel@l(r9)           into        addis r9, r13, x@tprel@ha
374
58
  // add r9, r9, x@tls                  into        addi r9, r9, x@tprel@l
375
58
376
58
  // x@tls R_PPC64_TLS is a relocation which does not compute anything,
377
58
  // it is replaced with r13 (thread pointer).
378
58
379
58
  // The add instruction in the initial exec sequence has multiple variations
380
58
  // that need to be handled. If we are building an address it will use an add
381
58
  // instruction, if we are accessing memory it will use any of the X-form
382
58
  // indexed load or store instructions.
383
58
384
58
  unsigned Offset = (Config->EKind == ELF64BEKind) ? 
229
:
029
;
385
58
  switch (Type) {
386
58
  case R_PPC64_GOT_TPREL16_HA:
387
18
    write32(Loc - Offset, 0x60000000); // nop
388
18
    break;
389
58
  case R_PPC64_GOT_TPREL16_LO_DS:
390
20
  case R_PPC64_GOT_TPREL16_DS: {
391
20
    uint32_t RegNo = read32(Loc - Offset) & 0x03E00000; // bits 6-10
392
20
    write32(Loc - Offset, 0x3C0D0000 | RegNo);          // addis RegNo, r13
393
20
    relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
394
20
    break;
395
20
  }
396
20
  case R_PPC64_TLS: {
397
20
    uint32_t PrimaryOp = getPrimaryOpCode(read32(Loc));
398
20
    if (PrimaryOp != 31)
399
0
      error("unrecognized instruction for IE to LE R_PPC64_TLS");
400
20
    uint32_t SecondaryOp = (read32(Loc) & 0x000007FE) >> 1; // bits 21-30
401
20
    uint32_t DFormOp = getDFormOp(SecondaryOp);
402
20
    write32(Loc, ((DFormOp << 26) | (read32(Loc) & 0x03FFFFFF)));
403
20
    relocateOne(Loc + Offset, R_PPC64_TPREL16_LO, Val);
404
20
    break;
405
20
  }
406
20
  default:
407
0
    llvm_unreachable("unknown relocation for IE to LE");
408
20
    
break0
;
409
58
  }
410
58
}
411
412
RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S,
413
831
                          const uint8_t *Loc) const {
414
831
  switch (Type) {
415
831
  case R_PPC64_GOT16:
416
24
  case R_PPC64_GOT16_DS:
417
24
  case R_PPC64_GOT16_HA:
418
24
  case R_PPC64_GOT16_HI:
419
24
  case R_PPC64_GOT16_LO:
420
24
  case R_PPC64_GOT16_LO_DS:
421
24
    return R_GOT_OFF;
422
132
  case R_PPC64_TOC16:
423
132
  case R_PPC64_TOC16_DS:
424
132
  case R_PPC64_TOC16_HA:
425
132
  case R_PPC64_TOC16_HI:
426
132
  case R_PPC64_TOC16_LO:
427
132
  case R_PPC64_TOC16_LO_DS:
428
132
    return R_GOTREL;
429
132
  case R_PPC64_TOC:
430
0
    return R_PPC_TOC;
431
147
  case R_PPC64_REL14:
432
147
  case R_PPC64_REL24:
433
147
    return R_PPC_CALL_PLT;
434
280
  case R_PPC64_REL16_LO:
435
280
  case R_PPC64_REL16_HA:
436
280
  case R_PPC64_REL32:
437
280
  case R_PPC64_REL64:
438
280
    return R_PC;
439
280
  case R_PPC64_GOT_TLSGD16:
440
26
  case R_PPC64_GOT_TLSGD16_HA:
441
26
  case R_PPC64_GOT_TLSGD16_HI:
442
26
  case R_PPC64_GOT_TLSGD16_LO:
443
26
    return R_TLSGD_GOT;
444
26
  case R_PPC64_GOT_TLSLD16:
445
24
  case R_PPC64_GOT_TLSLD16_HA:
446
24
  case R_PPC64_GOT_TLSLD16_HI:
447
24
  case R_PPC64_GOT_TLSLD16_LO:
448
24
    return R_TLSLD_GOT;
449
46
  case R_PPC64_GOT_TPREL16_HA:
450
46
  case R_PPC64_GOT_TPREL16_LO_DS:
451
46
  case R_PPC64_GOT_TPREL16_DS:
452
46
  case R_PPC64_GOT_TPREL16_HI:
453
46
    return R_GOT_OFF;
454
46
  case R_PPC64_GOT_DTPREL16_HA:
455
8
  case R_PPC64_GOT_DTPREL16_LO_DS:
456
8
  case R_PPC64_GOT_DTPREL16_DS:
457
8
  case R_PPC64_GOT_DTPREL16_HI:
458
8
    return R_TLSLD_GOT_OFF;
459
14
  case R_PPC64_TPREL16:
460
14
  case R_PPC64_TPREL16_HA:
461
14
  case R_PPC64_TPREL16_LO:
462
14
  case R_PPC64_TPREL16_HI:
463
14
  case R_PPC64_TPREL16_DS:
464
14
  case R_PPC64_TPREL16_LO_DS:
465
14
  case R_PPC64_TPREL16_HIGHER:
466
14
  case R_PPC64_TPREL16_HIGHERA:
467
14
  case R_PPC64_TPREL16_HIGHEST:
468
14
  case R_PPC64_TPREL16_HIGHESTA:
469
14
    return R_TLS;
470
30
  case R_PPC64_DTPREL16:
471
30
  case R_PPC64_DTPREL16_DS:
472
30
  case R_PPC64_DTPREL16_HA:
473
30
  case R_PPC64_DTPREL16_HI:
474
30
  case R_PPC64_DTPREL16_HIGHER:
475
30
  case R_PPC64_DTPREL16_HIGHERA:
476
30
  case R_PPC64_DTPREL16_HIGHEST:
477
30
  case R_PPC64_DTPREL16_HIGHESTA:
478
30
  case R_PPC64_DTPREL16_LO:
479
30
  case R_PPC64_DTPREL16_LO_DS:
480
30
  case R_PPC64_DTPREL64:
481
30
    return R_ABS;
482
30
  case R_PPC64_TLSGD:
483
12
    return R_TLSDESC_CALL;
484
30
  case R_PPC64_TLSLD:
485
10
    return R_TLSLD_HINT;
486
30
  case R_PPC64_TLS:
487
22
    return R_TLSIE_HINT;
488
56
  default:
489
56
    return R_ABS;
490
831
  }
491
831
}
492
493
85
void PPC64::writeGotHeader(uint8_t *Buf) const {
494
85
  write64(Buf, getPPC64TocBase());
495
85
}
496
497
28
void PPC64::writePltHeader(uint8_t *Buf) const {
498
28
  // The generic resolver stub goes first.
499
28
  write32(Buf +  0, 0x7c0802a6); // mflr r0
500
28
  write32(Buf +  4, 0x429f0005); // bcl  20,4*cr7+so,8 <_glink+0x8>
501
28
  write32(Buf +  8, 0x7d6802a6); // mflr r11
502
28
  write32(Buf + 12, 0x7c0803a6); // mtlr r0
503
28
  write32(Buf + 16, 0x7d8b6050); // subf r12, r11, r12
504
28
  write32(Buf + 20, 0x380cffcc); // subi r0,r12,52
505
28
  write32(Buf + 24, 0x7800f082); // srdi r0,r0,62,2
506
28
  write32(Buf + 28, 0xe98b002c); // ld   r12,44(r11)
507
28
  write32(Buf + 32, 0x7d6c5a14); // add  r11,r12,r11
508
28
  write32(Buf + 36, 0xe98b0000); // ld   r12,0(r11)
509
28
  write32(Buf + 40, 0xe96b0008); // ld   r11,8(r11)
510
28
  write32(Buf + 44, 0x7d8903a6); // mtctr   r12
511
28
  write32(Buf + 48, 0x4e800420); // bctr
512
28
513
28
  // The 'bcl' instruction will set the link register to the address of the
514
28
  // following instruction ('mflr r11'). Here we store the offset from that
515
28
  // instruction  to the first entry in the GotPlt section.
516
28
  int64_t GotPltOffset = In.GotPlt->getVA() - (In.Plt->getVA() + 8);
517
28
  write64(Buf + 52, GotPltOffset);
518
28
}
519
520
void PPC64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
521
                     uint64_t PltEntryAddr, int32_t Index,
522
32
                     unsigned RelOff) const {
523
32
  int32_t Offset = PltHeaderSize + Index * PltEntrySize;
524
32
  // bl __glink_PLTresolve
525
32
  write32(Buf, 0x48000000 | ((-Offset) & 0x03FFFFFc));
526
32
}
527
528
757
static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) {
529
757
  // Relocations relative to the toc-base need to be adjusted by the Toc offset.
530
757
  uint64_t TocBiasedVal = Val - PPC64TocOffset;
531
757
  // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset.
532
757
  uint64_t DTPBiasedVal = Val - DynamicThreadPointerOffset;
533
757
534
757
  switch (Type) {
535
757
  // TOC biased relocation.
536
757
  case R_PPC64_GOT16:
537
8
  case R_PPC64_GOT_TLSGD16:
538
8
  case R_PPC64_GOT_TLSLD16:
539
8
  case R_PPC64_TOC16:
540
8
    return {R_PPC64_ADDR16, TocBiasedVal};
541
8
  case R_PPC64_GOT16_DS:
542
8
  case R_PPC64_TOC16_DS:
543
8
  case R_PPC64_GOT_TPREL16_DS:
544
8
  case R_PPC64_GOT_DTPREL16_DS:
545
8
    return {R_PPC64_ADDR16_DS, TocBiasedVal};
546
88
  case R_PPC64_GOT16_HA:
547
88
  case R_PPC64_GOT_TLSGD16_HA:
548
88
  case R_PPC64_GOT_TLSLD16_HA:
549
88
  case R_PPC64_GOT_TPREL16_HA:
550
88
  case R_PPC64_GOT_DTPREL16_HA:
551
88
  case R_PPC64_TOC16_HA:
552
88
    return {R_PPC64_ADDR16_HA, TocBiasedVal};
553
88
  case R_PPC64_GOT16_HI:
554
14
  case R_PPC64_GOT_TLSGD16_HI:
555
14
  case R_PPC64_GOT_TLSLD16_HI:
556
14
  case R_PPC64_GOT_TPREL16_HI:
557
14
  case R_PPC64_GOT_DTPREL16_HI:
558
14
  case R_PPC64_TOC16_HI:
559
14
    return {R_PPC64_ADDR16_HI, TocBiasedVal};
560
32
  case R_PPC64_GOT16_LO:
561
32
  case R_PPC64_GOT_TLSGD16_LO:
562
32
  case R_PPC64_GOT_TLSLD16_LO:
563
32
  case R_PPC64_TOC16_LO:
564
32
    return {R_PPC64_ADDR16_LO, TocBiasedVal};
565
62
  case R_PPC64_GOT16_LO_DS:
566
62
  case R_PPC64_TOC16_LO_DS:
567
62
  case R_PPC64_GOT_TPREL16_LO_DS:
568
62
  case R_PPC64_GOT_DTPREL16_LO_DS:
569
62
    return {R_PPC64_ADDR16_LO_DS, TocBiasedVal};
570
62
571
62
  // Dynamic Thread pointer biased relocation types.
572
62
  case R_PPC64_DTPREL16:
573
2
    return {R_PPC64_ADDR16, DTPBiasedVal};
574
62
  case R_PPC64_DTPREL16_DS:
575
2
    return {R_PPC64_ADDR16_DS, DTPBiasedVal};
576
62
  case R_PPC64_DTPREL16_HA:
577
6
    return {R_PPC64_ADDR16_HA, DTPBiasedVal};
578
62
  case R_PPC64_DTPREL16_HI:
579
2
    return {R_PPC64_ADDR16_HI, DTPBiasedVal};
580
62
  case R_PPC64_DTPREL16_HIGHER:
581
2
    return {R_PPC64_ADDR16_HIGHER, DTPBiasedVal};
582
62
  case R_PPC64_DTPREL16_HIGHERA:
583
2
    return {R_PPC64_ADDR16_HIGHERA, DTPBiasedVal};
584
62
  case R_PPC64_DTPREL16_HIGHEST:
585
2
    return {R_PPC64_ADDR16_HIGHEST, DTPBiasedVal};
586
62
  case R_PPC64_DTPREL16_HIGHESTA:
587
2
    return {R_PPC64_ADDR16_HIGHESTA, DTPBiasedVal};
588
62
  case R_PPC64_DTPREL16_LO:
589
6
    return {R_PPC64_ADDR16_LO, DTPBiasedVal};
590
62
  case R_PPC64_DTPREL16_LO_DS:
591
2
    return {R_PPC64_ADDR16_LO_DS, DTPBiasedVal};
592
62
  case R_PPC64_DTPREL64:
593
4
    return {R_PPC64_ADDR64, DTPBiasedVal};
594
62
595
513
  default:
596
513
    return {Type, Val};
597
757
  }
598
757
}
599
600
757
static bool isTocOptType(RelType Type) {
601
757
  switch (Type) {
602
757
  case R_PPC64_GOT16_HA:
603
138
  case R_PPC64_GOT16_LO_DS:
604
138
  case R_PPC64_TOC16_HA:
605
138
  case R_PPC64_TOC16_LO_DS:
606
138
  case R_PPC64_TOC16_LO:
607
138
    return true;
608
619
  default:
609
619
    return false;
610
757
  }
611
757
}
612
613
757
void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
614
757
  // We need to save the original relocation type to use in diagnostics, and
615
757
  // use the original type to determine if we should toc-optimize the
616
757
  // instructions being relocated.
617
757
  RelType OriginalType = Type;
618
757
  bool ShouldTocOptimize =  isTocOptType(Type);
619
757
  // For dynamic thread pointer relative, toc-relative, and got-indirect
620
757
  // relocations, proceed in terms of the corresponding ADDR16 relocation type.
621
757
  std::tie(Type, Val) = toAddr16Rel(Type, Val);
622
757
623
757
  switch (Type) {
624
757
  case R_PPC64_ADDR14: {
625
0
    checkAlignment(Loc, Val, 4, Type);
626
0
    // Preserve the AA/LK bits in the branch instruction
627
0
    uint8_t AALK = Loc[3];
628
0
    write16(Loc + 2, (AALK & 3) | (Val & 0xfffc));
629
0
    break;
630
757
  }
631
757
  case R_PPC64_ADDR16:
632
13
  case R_PPC64_TPREL16:
633
13
    checkInt(Loc, Val, 16, OriginalType);
634
13
    write16(Loc, Val);
635
13
    break;
636
13
  case R_PPC64_ADDR16_DS:
637
11
  case R_PPC64_TPREL16_DS: {
638
11
    checkInt(Loc, Val, 16, OriginalType);
639
11
    // DQ-form instructions use bits 28-31 as part of the instruction encoding
640
11
    // DS-form instructions only use bits 30-31.
641
11
    uint16_t Mask = isDQFormInstruction(readInstrFromHalf16(Loc)) ? 
0xF0
: 0x3;
642
11
    checkAlignment(Loc, lo(Val), Mask + 1, OriginalType);
643
11
    write16(Loc, (read16(Loc) & Mask) | lo(Val));
644
11
  } break;
645
261
  case R_PPC64_ADDR16_HA:
646
261
  case R_PPC64_REL16_HA:
647
261
  case R_PPC64_TPREL16_HA:
648
261
    if (Config->TocOptimize && 
ShouldTocOptimize220
&&
ha(Val) == 042
)
649
32
      writeInstrFromHalf16(Loc, 0x60000000);
650
229
    else
651
229
      write16(Loc, ha(Val));
652
261
    break;
653
261
  case R_PPC64_ADDR16_HI:
654
20
  case R_PPC64_REL16_HI:
655
20
  case R_PPC64_TPREL16_HI:
656
20
    write16(Loc, hi(Val));
657
20
    break;
658
20
  case R_PPC64_ADDR16_HIGHER:
659
5
  case R_PPC64_TPREL16_HIGHER:
660
5
    write16(Loc, higher(Val));
661
5
    break;
662
5
  case R_PPC64_ADDR16_HIGHERA:
663
5
  case R_PPC64_TPREL16_HIGHERA:
664
5
    write16(Loc, highera(Val));
665
5
    break;
666
5
  case R_PPC64_ADDR16_HIGHEST:
667
5
  case R_PPC64_TPREL16_HIGHEST:
668
5
    write16(Loc, highest(Val));
669
5
    break;
670
5
  case R_PPC64_ADDR16_HIGHESTA:
671
5
  case R_PPC64_TPREL16_HIGHESTA:
672
5
    write16(Loc, highesta(Val));
673
5
    break;
674
206
  case R_PPC64_ADDR16_LO:
675
206
  case R_PPC64_REL16_LO:
676
206
  case R_PPC64_TPREL16_LO:
677
206
    // When the high-adjusted part of a toc relocation evalutes to 0, it is
678
206
    // changed into a nop. The lo part then needs to be updated to use the
679
206
    // toc-pointer register r2, as the base register.
680
206
    if (Config->TocOptimize && 
ShouldTocOptimize182
&&
ha(Val) == 011
) {
681
9
      uint32_t Instr = readInstrFromHalf16(Loc);
682
9
      if (isInstructionUpdateForm(Instr))
683
0
        error(getErrorLocation(Loc) +
684
0
              "can't toc-optimize an update instruction: 0x" +
685
0
              utohexstr(Instr));
686
9
      Instr = (Instr & 0xFFE00000) | 0x00020000;
687
9
      writeInstrFromHalf16(Loc, Instr);
688
9
    }
689
206
    write16(Loc, lo(Val));
690
206
    break;
691
206
  case R_PPC64_ADDR16_LO_DS:
692
65
  case R_PPC64_TPREL16_LO_DS: {
693
65
    // DQ-form instructions use bits 28-31 as part of the instruction encoding
694
65
    // DS-form instructions only use bits 30-31.
695
65
    uint32_t Inst = readInstrFromHalf16(Loc);
696
65
    uint16_t Mask = isDQFormInstruction(Inst) ? 
0xF12
:
0x353
;
697
65
    checkAlignment(Loc, lo(Val), Mask + 1, OriginalType);
698
65
    if (Config->TocOptimize && 
ShouldTocOptimize46
&&
ha(Val) == 033
) {
699
25
      // When the high-adjusted part of a toc relocation evalutes to 0, it is
700
25
      // changed into a nop. The lo part then needs to be updated to use the toc
701
25
      // pointer register r2, as the base register.
702
25
      if (isInstructionUpdateForm(Inst))
703
0
        error(getErrorLocation(Loc) +
704
0
              "Can't toc-optimize an update instruction: 0x" +
705
0
              Twine::utohexstr(Inst));
706
25
      Inst = (Inst & 0xFFE0000F) | 0x00020000;
707
25
      writeInstrFromHalf16(Loc, Inst);
708
25
    }
709
65
    write16(Loc, (read16(Loc) & Mask) | lo(Val));
710
65
  } break;
711
65
  case R_PPC64_ADDR32:
712
4
  case R_PPC64_REL32:
713
4
    checkInt(Loc, Val, 32, Type);
714
4
    write32(Loc, Val);
715
4
    break;
716
18
  case R_PPC64_ADDR64:
717
18
  case R_PPC64_REL64:
718
18
  case R_PPC64_TOC:
719
18
    write64(Loc, Val);
720
18
    break;
721
18
  case R_PPC64_REL14: {
722
2
    uint32_t Mask = 0x0000FFFC;
723
2
    checkInt(Loc, Val, 16, Type);
724
2
    checkAlignment(Loc, Val, 4, Type);
725
2
    write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
726
2
    break;
727
18
  }
728
137
  case R_PPC64_REL24: {
729
137
    uint32_t Mask = 0x03FFFFFC;
730
137
    checkInt(Loc, Val, 26, Type);
731
137
    checkAlignment(Loc, Val, 4, Type);
732
137
    write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
733
137
    break;
734
18
  }
735
18
  case R_PPC64_DTPREL64:
736
0
    write64(Loc, Val - DynamicThreadPointerOffset);
737
0
    break;
738
18
  default:
739
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
740
757
  }
741
757
}
742
743
bool PPC64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
744
927
                       uint64_t BranchAddr, const Symbol &S) const {
745
927
  if (Type != R_PPC64_REL14 && 
Type != R_PPC64_REL24925
)
746
774
    return false;
747
153
748
153
  // If a function is in the Plt it needs to be called with a call-stub.
749
153
  if (S.isInPlt())
750
38
    return true;
751
115
752
115
  // If a symbol is a weak undefined and we are compiling an executable
753
115
  // it doesn't need a range-extending thunk since it can't be called.
754
115
  if (S.isUndefWeak() && 
!Config->Shared2
)
755
2
    return false;
756
113
757
113
  // If the offset exceeds the range of the branch type then it will need
758
113
  // a range-extending thunk.
759
113
  return !inBranchRange(Type, BranchAddr, S.getVA());
760
113
}
761
762
206
bool PPC64::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
763
206
  int64_t Offset = Dst - Src;
764
206
  if (Type == R_PPC64_REL14)
765
2
    return isInt<16>(Offset);
766
204
  if (Type == R_PPC64_REL24)
767
204
    return isInt<26>(Offset);
768
0
  llvm_unreachable("unsupported relocation type used in branch");
769
0
}
770
771
RelExpr PPC64::adjustRelaxExpr(RelType Type, const uint8_t *Data,
772
38
                               RelExpr Expr) const {
773
38
  if (Expr == R_RELAX_TLS_GD_TO_IE)
774
18
    return R_RELAX_TLS_GD_TO_IE_GOT_OFF;
775
20
  if (Expr == R_RELAX_TLS_LD_TO_LE)
776
10
    return R_RELAX_TLS_LD_TO_LE_ABS;
777
10
  return Expr;
778
10
}
779
780
// Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement.
781
// The general dynamic code sequence for a global `x` uses 4 instructions.
782
// Instruction                    Relocation                Symbol
783
// addis r3, r2, x@got@tlsgd@ha   R_PPC64_GOT_TLSGD16_HA      x
784
// addi  r3, r3, x@got@tlsgd@l    R_PPC64_GOT_TLSGD16_LO      x
785
// bl __tls_get_addr(x@tlsgd)     R_PPC64_TLSGD               x
786
//                                R_PPC64_REL24               __tls_get_addr
787
// nop                            None                       None
788
//
789
// Relaxing to initial-exec entails:
790
// 1) Convert the addis/addi pair that builds the address of the tls_index
791
//    struct for 'x' to an addis/ld pair that loads an offset from a got-entry.
792
// 2) Convert the call to __tls_get_addr to a nop.
793
// 3) Convert the nop following the call to an add of the loaded offset to the
794
//    thread pointer.
795
// Since the nop must directly follow the call, the R_PPC64_TLSGD relocation is
796
// used as the relaxation hint for both steps 2 and 3.
797
18
void PPC64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
798
18
  switch (Type) {
799
18
  case R_PPC64_GOT_TLSGD16_HA:
800
6
    // This is relaxed from addis rT, r2, sym@got@tlsgd@ha to
801
6
    //                      addis rT, r2, sym@got@tprel@ha.
802
6
    relocateOne(Loc, R_PPC64_GOT_TPREL16_HA, Val);
803
6
    return;
804
18
  case R_PPC64_GOT_TLSGD16_LO: {
805
6
    // Relax from addi  r3, rA, sym@got@tlsgd@l to
806
6
    //            ld r3, sym@got@tprel@l(rA)
807
6
    uint32_t InputRegister = (readInstrFromHalf16(Loc) & (0x1f << 16));
808
6
    writeInstrFromHalf16(Loc, 0xE8600000 | InputRegister);
809
6
    relocateOne(Loc, R_PPC64_GOT_TPREL16_LO_DS, Val);
810
6
    return;
811
18
  }
812
18
  case R_PPC64_TLSGD:
813
6
    write32(Loc, 0x60000000);     // bl __tls_get_addr(sym@tlsgd) --> nop
814
6
    write32(Loc + 4, 0x7c636A14); // nop --> add r3, r3, r13
815
6
    return;
816
18
  default:
817
0
    llvm_unreachable("unsupported relocation for TLS GD to IE relaxation");
818
18
  }
819
18
}
820
821
// The prologue for a split-stack function is expected to look roughly
822
// like this:
823
//    .Lglobal_entry_point:
824
//      # TOC pointer initalization.
825
//      ...
826
//    .Llocal_entry_point:
827
//      # load the __private_ss member of the threads tcbhead.
828
//      ld r0,-0x7000-64(r13)
829
//      # subtract the functions stack size from the stack pointer.
830
//      addis r12, r1, ha(-stack-frame size)
831
//      addi  r12, r12, l(-stack-frame size)
832
//      # compare needed to actual and branch to allocate_more_stack if more
833
//      # space is needed, otherwise fallthrough to 'normal' function body.
834
//      cmpld cr7,r12,r0
835
//      blt- cr7, .Lallocate_more_stack
836
//
837
// -) The allocate_more_stack block might be placed after the split-stack
838
//    prologue and the `blt-` replaced with a `bge+ .Lnormal_func_body`
839
//    instead.
840
// -) If either the addis or addi is not needed due to the stack size being
841
//    smaller then 32K or a multiple of 64K they will be replaced with a nop,
842
//    but there will always be 2 instructions the linker can overwrite for the
843
//    adjusted stack size.
844
//
845
// The linkers job here is to increase the stack size used in the addis/addi
846
// pair by split-stack-size-adjust.
847
// addis r12, r1, ha(-stack-frame size - split-stack-adjust-size)
848
// addi  r12, r12, l(-stack-frame size - split-stack-adjust-size)
849
bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *Loc, uint8_t *End,
850
22
                                             uint8_t StOther) const {
851
22
  // If the caller has a global entry point adjust the buffer past it. The start
852
22
  // of the split-stack prologue will be at the local entry point.
853
22
  Loc += getPPC64GlobalEntryToLocalEntryOffset(StOther);
854
22
855
22
  // At the very least we expect to see a load of some split-stack data from the
856
22
  // tcb, and 2 instructions that calculate the ending stack address this
857
22
  // function will require. If there is not enough room for at least 3
858
22
  // instructions it can't be a split-stack prologue.
859
22
  if (Loc + 12 >= End)
860
0
    return false;
861
22
862
22
  // First instruction must be `ld r0, -0x7000-64(r13)`
863
22
  if (read32(Loc) != 0xe80d8fc0)
864
0
    return false;
865
22
866
22
  int16_t HiImm = 0;
867
22
  int16_t LoImm = 0;
868
22
  // First instruction can be either an addis if the frame size is larger then
869
22
  // 32K, or an addi if the size is less then 32K.
870
22
  int32_t FirstInstr = read32(Loc + 4);
871
22
  if (getPrimaryOpCode(FirstInstr) == 15) {
872
12
    HiImm = FirstInstr & 0xFFFF;
873
12
  } else 
if (10
getPrimaryOpCode(FirstInstr) == 1410
) {
874
10
    LoImm = FirstInstr & 0xFFFF;
875
10
  } else {
876
0
    return false;
877
0
  }
878
22
879
22
  // Second instruction is either an addi or a nop. If the first instruction was
880
22
  // an addi then LoImm is set and the second instruction must be a nop.
881
22
  uint32_t SecondInstr = read32(Loc + 8);
882
22
  if (!LoImm && 
getPrimaryOpCode(SecondInstr) == 1412
) {
883
10
    LoImm = SecondInstr & 0xFFFF;
884
12
  } else if (SecondInstr != 0x60000000) {
885
0
    return false;
886
0
  }
887
22
888
22
  // The register operands of the first instruction should be the stack-pointer
889
22
  // (r1) as the input (RA) and r12 as the output (RT). If the second
890
22
  // instruction is not a nop, then it should use r12 as both input and output.
891
22
  auto CheckRegOperands = [](uint32_t Instr, uint8_t ExpectedRT,
892
30
                             uint8_t ExpectedRA) {
893
30
    return ((Instr & 0x3E00000) >> 21 == ExpectedRT) &&
894
30
           
((Instr & 0x1F0000) >> 16 == ExpectedRA)28
;
895
30
  };
896
22
  if (!CheckRegOperands(FirstInstr, 12, 1))
897
2
    return false;
898
20
  if (SecondInstr != 0x60000000 && 
!CheckRegOperands(SecondInstr, 12, 12)8
)
899
0
    return false;
900
20
901
20
  int32_t StackFrameSize = (HiImm * 65536) + LoImm;
902
20
  // Check that the adjusted size doesn't overflow what we can represent with 2
903
20
  // instructions.
904
20
  if (StackFrameSize < Config->SplitStackAdjustSize + INT32_MIN) {
905
4
    error(getErrorLocation(Loc) + "split-stack prologue adjustment overflows");
906
4
    return false;
907
4
  }
908
16
909
16
  int32_t AdjustedStackFrameSize =
910
16
      StackFrameSize - Config->SplitStackAdjustSize;
911
16
912
16
  LoImm = AdjustedStackFrameSize & 0xFFFF;
913
16
  HiImm = (AdjustedStackFrameSize + 0x8000) >> 16;
914
16
  if (HiImm) {
915
10
    write32(Loc + 4, 0x3D810000 | (uint16_t)HiImm);
916
10
    // If the low immediate is zero the second instruction will be a nop.
917
10
    SecondInstr = LoImm ? 
0x398C0000 | (uint16_t)LoImm8
:
0x600000002
;
918
10
    write32(Loc + 8, SecondInstr);
919
10
  } else {
920
6
    // addi r12, r1, imm
921
6
    write32(Loc + 4, (0x39810000) | (uint16_t)LoImm);
922
6
    write32(Loc + 8, 0x60000000);
923
6
  }
924
16
925
16
  return true;
926
16
}
927
928
145
TargetInfo *elf::getPPC64TargetInfo() {
929
145
  static PPC64 Target;
930
145
  return &Target;
931
145
}