Coverage Report

Created: 2018-06-18 20:01

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/tools/lld/ELF/Arch/PPC64.cpp
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Source (jump to first uncovered line)
1
//===- PPC64.cpp ----------------------------------------------------------===//
2
//
3
//                             The LLVM Linker
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#include "Symbols.h"
11
#include "SyntheticSections.h"
12
#include "Target.h"
13
#include "lld/Common/ErrorHandler.h"
14
#include "llvm/Support/Endian.h"
15
16
using namespace llvm;
17
using namespace llvm::object;
18
using namespace llvm::support::endian;
19
using namespace llvm::ELF;
20
using namespace lld;
21
using namespace lld::elf;
22
23
static uint64_t PPC64TocOffset = 0x8000;
24
static uint64_t DynamicThreadPointerOffset = 0x8000;
25
26
49
uint64_t elf::getPPC64TocBase() {
27
49
  // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
28
49
  // TOC starts where the first of these sections starts. We always create a
29
49
  // .got when we see a relocation that uses it, so for us the start is always
30
49
  // the .got.
31
49
  uint64_t TocVA = InX::Got->getVA();
32
49
33
49
  // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
34
49
  // thus permitting a full 64 Kbytes segment. Note that the glibc startup
35
49
  // code (crt1.o) assumes that you can get from the TOC base to the
36
49
  // start of the .toc section with only a single (signed) 16-bit relocation.
37
49
  return TocVA + PPC64TocOffset;
38
49
}
39
40
namespace {
41
class PPC64 final : public TargetInfo {
42
public:
43
  PPC64();
44
  uint32_t calcEFlags() const override;
45
  RelExpr getRelExpr(RelType Type, const Symbol &S,
46
                     const uint8_t *Loc) const override;
47
  void writePltHeader(uint8_t *Buf) const override;
48
  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
49
                int32_t Index, unsigned RelOff) const override;
50
  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
51
  void writeGotHeader(uint8_t *Buf) const override;
52
  bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
53
                  uint64_t BranchAddr, const Symbol &S) const override;
54
};
55
} // namespace
56
57
// Relocation masks following the #lo(value), #hi(value), #ha(value),
58
// #higher(value), #highera(value), #highest(value), and #highesta(value)
59
// macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
60
// document.
61
86
static uint16_t lo(uint64_t V) { return V; }
62
14
static uint16_t hi(uint64_t V) { return V >> 16; }
63
80
static uint16_t ha(uint64_t V) { return (V + 0x8000) >> 16; }
64
5
static uint16_t higher(uint64_t V) { return V >> 32; }
65
5
static uint16_t highera(uint64_t V) { return (V + 0x8000) >> 32; }
66
5
static uint16_t highest(uint64_t V) { return V >> 48; }
67
5
static uint16_t highesta(uint64_t V) { return (V + 0x8000) >> 48; }
68
69
76
PPC64::PPC64() {
70
76
  GotRel = R_PPC64_GLOB_DAT;
71
76
  PltRel = R_PPC64_JMP_SLOT;
72
76
  RelativeRel = R_PPC64_RELATIVE;
73
76
  IRelativeRel = R_PPC64_IRELATIVE;
74
76
  GotEntrySize = 8;
75
76
  PltEntrySize = 4;
76
76
  GotPltEntrySize = 8;
77
76
  GotBaseSymInGotPlt = false;
78
76
  GotBaseSymOff = 0x8000;
79
76
  GotHeaderEntriesNum = 1;
80
76
  GotPltHeaderEntriesNum = 2;
81
76
  PltHeaderSize = 60;
82
76
  NeedsThunks = true;
83
76
  TcbSize = 8;
84
76
  TlsTpOffset = 0x7000;
85
76
86
76
  TlsModuleIndexRel = R_PPC64_DTPMOD64;
87
76
  TlsOffsetRel = R_PPC64_DTPREL64;
88
76
89
76
  TlsGotRel = R_PPC64_TPREL64;
90
76
91
76
  // We need 64K pages (at least under glibc/Linux, the loader won't
92
76
  // set different permissions on a finer granularity than that).
93
76
  DefaultMaxPageSize = 65536;
94
76
95
76
  // The PPC64 ELF ABI v1 spec, says:
96
76
  //
97
76
  //   It is normally desirable to put segments with different characteristics
98
76
  //   in separate 256 Mbyte portions of the address space, to give the
99
76
  //   operating system full paging flexibility in the 64-bit address space.
100
76
  //
101
76
  // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
102
76
  // use 0x10000000 as the starting address.
103
76
  DefaultImageBase = 0x10000000;
104
76
105
76
  TrapInstr =
106
76
      (Config->IsLE == sys::IsLittleEndianHost) ? 
0x7fe0000837
:
0x0800e07f39
;
107
76
}
108
109
156
static uint32_t getEFlags(InputFile *File) {
110
156
  // Get the e_flag from the input file and issue an error if incompatible
111
156
  // e_flag encountered.
112
156
  uint32_t EFlags;
113
156
  switch (Config->EKind) {
114
156
  case ELF64BEKind:
115
77
    EFlags = cast<ObjFile<ELF64BE>>(File)->getObj().getHeader()->e_flags;
116
77
    break;
117
156
  case ELF64LEKind:
118
79
    EFlags = cast<ObjFile<ELF64LE>>(File)->getObj().getHeader()->e_flags;
119
79
    break;
120
156
  default:
121
0
    llvm_unreachable("unknown Config->EKind");
122
156
  }
123
156
  if (EFlags > 2) {
124
0
    error("incompatible e_flags: " +  toString(File));
125
0
    return 0;
126
0
  }
127
156
  return EFlags;
128
156
}
129
130
73
uint32_t PPC64::calcEFlags() const {
131
73
  assert(!ObjectFiles.empty());
132
73
133
73
  uint32_t NonZeroFlag;
134
75
  for (InputFile *F : makeArrayRef(ObjectFiles)) {
135
75
    NonZeroFlag = getEFlags(F);
136
75
    if (NonZeroFlag)
137
46
      break;
138
75
  }
139
73
140
73
  // Verify that all input files have either the same e_flags, or zero.
141
81
  for (InputFile *F : makeArrayRef(ObjectFiles)) {
142
81
    uint32_t Flag = getEFlags(F);
143
81
    if (Flag == 0 || 
Flag == NonZeroFlag52
)
144
81
      continue;
145
0
    error(toString(F) + ": ABI version " + Twine(Flag) +
146
0
          " is not compatible with ABI version " + Twine(NonZeroFlag) +
147
0
          " output");
148
0
    return 0;
149
0
  }
150
73
151
73
  if (NonZeroFlag == 1) {
152
0
    error("PPC64 V1 ABI not supported");
153
0
    return 0;
154
0
  }
155
73
156
73
  return 2;
157
73
}
158
159
RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S,
160
304
                          const uint8_t *Loc) const {
161
304
  switch (Type) {
162
304
  case R_PPC64_TOC16:
163
28
  case R_PPC64_TOC16_DS:
164
28
  case R_PPC64_TOC16_HA:
165
28
  case R_PPC64_TOC16_HI:
166
28
  case R_PPC64_TOC16_LO:
167
28
  case R_PPC64_TOC16_LO_DS:
168
28
    return R_GOTREL;
169
28
  case R_PPC64_TOC:
170
0
    return R_PPC_TOC;
171
42
  case R_PPC64_REL24:
172
42
    return R_PPC_CALL_PLT;
173
98
  case R_PPC64_REL16_LO:
174
98
  case R_PPC64_REL16_HA:
175
98
  case R_PPC64_REL32:
176
98
  case R_PPC64_REL64:
177
98
    return R_PC;
178
98
  case R_PPC64_GOT_TLSGD16:
179
8
  case R_PPC64_GOT_TLSGD16_HA:
180
8
  case R_PPC64_GOT_TLSGD16_HI:
181
8
  case R_PPC64_GOT_TLSGD16_LO:
182
8
    return R_TLSGD_GOT;
183
20
  case R_PPC64_GOT_TLSLD16:
184
20
  case R_PPC64_GOT_TLSLD16_HA:
185
20
  case R_PPC64_GOT_TLSLD16_HI:
186
20
  case R_PPC64_GOT_TLSLD16_LO:
187
20
    return R_TLSLD_GOT;
188
20
  case R_PPC64_GOT_TPREL16_HA:
189
8
  case R_PPC64_GOT_TPREL16_LO_DS:
190
8
  case R_PPC64_GOT_TPREL16_DS:
191
8
  case R_PPC64_GOT_TPREL16_HI:
192
8
    return R_GOT_OFF;
193
14
  case R_PPC64_TPREL16:
194
14
  case R_PPC64_TPREL16_HA:
195
14
  case R_PPC64_TPREL16_LO:
196
14
  case R_PPC64_TPREL16_HI:
197
14
  case R_PPC64_TPREL16_DS:
198
14
  case R_PPC64_TPREL16_LO_DS:
199
14
  case R_PPC64_TPREL16_HIGHER:
200
14
  case R_PPC64_TPREL16_HIGHERA:
201
14
  case R_PPC64_TPREL16_HIGHEST:
202
14
  case R_PPC64_TPREL16_HIGHESTA:
203
14
    return R_TLS;
204
26
  case R_PPC64_DTPREL16:
205
26
  case R_PPC64_DTPREL16_DS:
206
26
  case R_PPC64_DTPREL16_HA:
207
26
  case R_PPC64_DTPREL16_HI:
208
26
  case R_PPC64_DTPREL16_HIGHER:
209
26
  case R_PPC64_DTPREL16_HIGHERA:
210
26
  case R_PPC64_DTPREL16_HIGHEST:
211
26
  case R_PPC64_DTPREL16_HIGHESTA:
212
26
  case R_PPC64_DTPREL16_LO:
213
26
  case R_PPC64_DTPREL16_LO_DS:
214
26
  case R_PPC64_DTPREL64:
215
26
    return R_ABS;
216
26
  case R_PPC64_TLSGD:
217
12
  case R_PPC64_TLSLD:
218
12
  case R_PPC64_TLS:
219
12
    return R_HINT;
220
48
  default:
221
48
    return R_ABS;
222
304
  }
223
304
}
224
225
27
void PPC64::writeGotHeader(uint8_t *Buf) const {
226
27
  write64(Buf, getPPC64TocBase());
227
27
}
228
229
20
void PPC64::writePltHeader(uint8_t *Buf) const {
230
20
  // The generic resolver stub goes first.
231
20
  write32(Buf +  0, 0x7c0802a6); // mflr r0
232
20
  write32(Buf +  4, 0x429f0005); // bcl  20,4*cr7+so,8 <_glink+0x8>
233
20
  write32(Buf +  8, 0x7d6802a6); // mflr r11
234
20
  write32(Buf + 12, 0x7c0803a6); // mtlr r0
235
20
  write32(Buf + 16, 0x7d8b6050); // subf r12, r11, r12
236
20
  write32(Buf + 20, 0x380cffcc); // subi r0,r12,52
237
20
  write32(Buf + 24, 0x7800f082); // srdi r0,r0,62,2
238
20
  write32(Buf + 28, 0xe98b002c); // ld   r12,44(r11)
239
20
  write32(Buf + 32, 0x7d6c5a14); // add  r11,r12,r11
240
20
  write32(Buf + 36, 0xe98b0000); // ld   r12,0(r11)
241
20
  write32(Buf + 40, 0xe96b0008); // ld   r11,8(r11)
242
20
  write32(Buf + 44, 0x7d8903a6); // mtctr   r12
243
20
  write32(Buf + 48, 0x4e800420); // bctr
244
20
245
20
  // The 'bcl' instruction will set the link register to the address of the
246
20
  // following instruction ('mflr r11'). Here we store the offset from that
247
20
  // instruction  to the first entry in the GotPlt section.
248
20
  int64_t GotPltOffset = InX::GotPlt->getVA() - (InX::Plt->getVA() + 8);
249
20
  write64(Buf + 52, GotPltOffset);
250
20
}
251
252
void PPC64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
253
                     uint64_t PltEntryAddr, int32_t Index,
254
22
                     unsigned RelOff) const {
255
22
 int32_t Offset = PltHeaderSize + Index * PltEntrySize;
256
22
 // bl __glink_PLTresolve
257
22
 write32(Buf, 0x48000000 | ((-Offset) & 0x03FFFFFc));
258
22
}
259
260
268
static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) {
261
268
  // Relocations relative to the toc-base need to be adjusted by the Toc offset.
262
268
  uint64_t TocBiasedVal = Val - PPC64TocOffset;
263
268
  // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset.
264
268
  uint64_t DTPBiasedVal = Val - DynamicThreadPointerOffset;
265
268
266
268
  switch (Type) {
267
268
  // TOC biased relocation.
268
268
  case R_PPC64_GOT_TLSGD16:
269
4
  case R_PPC64_GOT_TLSLD16:
270
4
  case R_PPC64_TOC16:
271
4
    return {R_PPC64_ADDR16, TocBiasedVal};
272
4
  case R_PPC64_TOC16_DS:
273
2
  case R_PPC64_GOT_TPREL16_DS:
274
2
    return {R_PPC64_ADDR16_DS, TocBiasedVal};
275
24
  case R_PPC64_GOT_TLSGD16_HA:
276
24
  case R_PPC64_GOT_TLSLD16_HA:
277
24
  case R_PPC64_GOT_TPREL16_HA:
278
24
  case R_PPC64_TOC16_HA:
279
24
    return {R_PPC64_ADDR16_HA, TocBiasedVal};
280
24
  case R_PPC64_GOT_TLSGD16_HI:
281
8
  case R_PPC64_GOT_TLSLD16_HI:
282
8
  case R_PPC64_GOT_TPREL16_HI:
283
8
  case R_PPC64_TOC16_HI:
284
8
    return {R_PPC64_ADDR16_HI, TocBiasedVal};
285
14
  case R_PPC64_GOT_TLSGD16_LO:
286
14
  case R_PPC64_GOT_TLSLD16_LO:
287
14
  case R_PPC64_TOC16_LO:
288
14
    return {R_PPC64_ADDR16_LO, TocBiasedVal};
289
14
  case R_PPC64_TOC16_LO_DS:
290
12
  case R_PPC64_GOT_TPREL16_LO_DS:
291
12
    return {R_PPC64_ADDR16_LO_DS, TocBiasedVal};
292
12
293
12
  // Dynamic Thread pointer biased relocation types.
294
12
  case R_PPC64_DTPREL16:
295
2
    return {R_PPC64_ADDR16, DTPBiasedVal};
296
12
  case R_PPC64_DTPREL16_DS:
297
2
    return {R_PPC64_ADDR16_DS, DTPBiasedVal};
298
12
  case R_PPC64_DTPREL16_HA:
299
4
    return {R_PPC64_ADDR16_HA, DTPBiasedVal};
300
12
  case R_PPC64_DTPREL16_HI:
301
2
    return {R_PPC64_ADDR16_HI, DTPBiasedVal};
302
12
  case R_PPC64_DTPREL16_HIGHER:
303
2
    return {R_PPC64_ADDR16_HIGHER, DTPBiasedVal};
304
12
  case R_PPC64_DTPREL16_HIGHERA:
305
2
    return {R_PPC64_ADDR16_HIGHERA, DTPBiasedVal};
306
12
  case R_PPC64_DTPREL16_HIGHEST:
307
2
    return {R_PPC64_ADDR16_HIGHEST, DTPBiasedVal};
308
12
  case R_PPC64_DTPREL16_HIGHESTA:
309
2
    return {R_PPC64_ADDR16_HIGHESTA, DTPBiasedVal};
310
12
  case R_PPC64_DTPREL16_LO:
311
4
    return {R_PPC64_ADDR16_LO, DTPBiasedVal};
312
12
  case R_PPC64_DTPREL16_LO_DS:
313
2
    return {R_PPC64_ADDR16_LO_DS, DTPBiasedVal};
314
12
  case R_PPC64_DTPREL64:
315
2
    return {R_PPC64_ADDR64, DTPBiasedVal};
316
12
317
178
  default:
318
178
    return {Type, Val};
319
268
  }
320
268
}
321
322
268
void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
323
268
  // For a TOC-relative relocation, proceed in terms of the corresponding
324
268
  // ADDR16 relocation type.
325
268
  std::tie(Type, Val) = toAddr16Rel(Type, Val);
326
268
327
268
  switch (Type) {
328
268
  case R_PPC64_ADDR14: {
329
0
    checkAlignment(Loc, Val, 4, Type);
330
0
    // Preserve the AA/LK bits in the branch instruction
331
0
    uint8_t AALK = Loc[3];
332
0
    write16(Loc + 2, (AALK & 3) | (Val & 0xfffc));
333
0
    break;
334
268
  }
335
268
  case R_PPC64_ADDR16:
336
9
  case R_PPC64_TPREL16:
337
9
    checkInt(Loc, Val, 16, Type);
338
9
    write16(Loc, Val);
339
9
    break;
340
9
  case R_PPC64_ADDR16_DS:
341
5
  case R_PPC64_TPREL16_DS:
342
5
    checkInt(Loc, Val, 16, Type);
343
5
    write16(Loc, (read16(Loc) & 3) | (Val & ~3));
344
5
    break;
345
80
  case R_PPC64_ADDR16_HA:
346
80
  case R_PPC64_REL16_HA:
347
80
  case R_PPC64_TPREL16_HA:
348
80
    write16(Loc, ha(Val));
349
80
    break;
350
80
  case R_PPC64_ADDR16_HI:
351
14
  case R_PPC64_REL16_HI:
352
14
  case R_PPC64_TPREL16_HI:
353
14
    write16(Loc, hi(Val));
354
14
    break;
355
14
  case R_PPC64_ADDR16_HIGHER:
356
5
  case R_PPC64_TPREL16_HIGHER:
357
5
    write16(Loc, higher(Val));
358
5
    break;
359
5
  case R_PPC64_ADDR16_HIGHERA:
360
5
  case R_PPC64_TPREL16_HIGHERA:
361
5
    write16(Loc, highera(Val));
362
5
    break;
363
5
  case R_PPC64_ADDR16_HIGHEST:
364
5
  case R_PPC64_TPREL16_HIGHEST:
365
5
    write16(Loc, highest(Val));
366
5
    break;
367
5
  case R_PPC64_ADDR16_HIGHESTA:
368
5
  case R_PPC64_TPREL16_HIGHESTA:
369
5
    write16(Loc, highesta(Val));
370
5
    break;
371
71
  case R_PPC64_ADDR16_LO:
372
71
  case R_PPC64_REL16_LO:
373
71
  case R_PPC64_TPREL16_LO:
374
71
    write16(Loc, lo(Val));
375
71
    break;
376
71
  case R_PPC64_ADDR16_LO_DS:
377
15
  case R_PPC64_TPREL16_LO_DS:
378
15
    write16(Loc, (read16(Loc) & 3) | (lo(Val) & ~3));
379
15
    break;
380
15
  case R_PPC64_ADDR32:
381
4
  case R_PPC64_REL32:
382
4
    checkInt(Loc, Val, 32, Type);
383
4
    write32(Loc, Val);
384
4
    break;
385
12
  case R_PPC64_ADDR64:
386
12
  case R_PPC64_REL64:
387
12
  case R_PPC64_TOC:
388
12
    write64(Loc, Val);
389
12
    break;
390
38
  case R_PPC64_REL24: {
391
38
    uint32_t Mask = 0x03FFFFFC;
392
38
    checkInt(Loc, Val, 24, Type);
393
38
    write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
394
38
    break;
395
12
  }
396
12
  default:
397
0
    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
398
268
  }
399
268
}
400
401
bool PPC64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
402
352
                       uint64_t BranchAddr, const Symbol &S) const {
403
352
  // If a function is in the plt it needs to be called through
404
352
  // a call stub.
405
352
  return Type == R_PPC64_REL24 && 
S.isInPlt()46
;
406
352
}
407
408
76
TargetInfo *elf::getPPC64TargetInfo() {
409
76
  static PPC64 Target;
410
76
  return &Target;
411
76
}