Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/include/llvm/CodeGen/FastISel.h
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//===- FastISel.h - Definition of the FastISel class ------------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines the FastISel class.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_FASTISEL_H
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#define LLVM_CODEGEN_FASTISEL_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/CallSite.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/Target/TargetLowering.h"
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#include <algorithm>
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#include <cstdint>
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#include <utility>
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namespace llvm {
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class AllocaInst;
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class BasicBlock;
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class CallInst;
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class Constant;
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class ConstantFP;
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class DataLayout;
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class FunctionLoweringInfo;
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class LoadInst;
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class MachineConstantPool;
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class MachineFrameInfo;
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class MachineFunction;
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class MachineInstr;
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class MachineMemOperand;
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class MachineOperand;
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class MachineRegisterInfo;
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class MCContext;
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class MCInstrDesc;
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class MCSymbol;
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class TargetInstrInfo;
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class TargetLibraryInfo;
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class TargetMachine;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class Type;
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class User;
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class Value;
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/// \brief This is a fast-path instruction selection class that generates poor
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/// code and doesn't support illegal types or non-trivial lowering, but runs
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/// quickly.
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class FastISel {
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public:
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  using ArgListEntry = TargetLoweringBase::ArgListEntry;
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  using ArgListTy = TargetLoweringBase::ArgListTy;
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  struct CallLoweringInfo {
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    Type *RetTy = nullptr;
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    bool RetSExt : 1;
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    bool RetZExt : 1;
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    bool IsVarArg : 1;
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    bool IsInReg : 1;
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    bool DoesNotReturn : 1;
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    bool IsReturnValueUsed : 1;
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    bool IsPatchPoint : 1;
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    // \brief IsTailCall Should be modified by implementations of FastLowerCall
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    // that perform tail call conversions.
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    bool IsTailCall = false;
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    unsigned NumFixedArgs = -1;
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    CallingConv::ID CallConv = CallingConv::C;
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    const Value *Callee = nullptr;
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    MCSymbol *Symbol = nullptr;
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    ArgListTy Args;
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    ImmutableCallSite *CS = nullptr;
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    MachineInstr *Call = nullptr;
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    unsigned ResultReg = 0;
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    unsigned NumResultRegs = 0;
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    SmallVector<Value *, 16> OutVals;
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    SmallVector<ISD::ArgFlagsTy, 16> OutFlags;
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    SmallVector<unsigned, 16> OutRegs;
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    SmallVector<ISD::InputArg, 4> Ins;
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    SmallVector<unsigned, 4> InRegs;
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    CallLoweringInfo()
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        : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
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1.99k
          DoesNotReturn(false), IsReturnValueUsed(true), IsPatchPoint(false) {}
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    CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
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                                const Value *Target, ArgListTy &&ArgsList,
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                                ImmutableCallSite &Call) {
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      RetTy = ResultTy;
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      Callee = Target;
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1.91k
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      IsInReg = Call.hasRetAttr(Attribute::InReg);
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      DoesNotReturn = Call.doesNotReturn();
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      IsVarArg = FuncTy->isVarArg();
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      IsReturnValueUsed = !Call.getInstruction()->use_empty();
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      RetSExt = Call.hasRetAttr(Attribute::SExt);
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      RetZExt = Call.hasRetAttr(Attribute::ZExt);
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      CallConv = Call.getCallingConv();
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      Args = std::move(ArgsList);
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      NumFixedArgs = FuncTy->getNumParams();
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      CS = &Call;
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1.91k
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      return *this;
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    }
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    CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
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                                MCSymbol *Target, ArgListTy &&ArgsList,
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                                ImmutableCallSite &Call,
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                                unsigned FixedArgs = ~0U) {
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      RetTy = ResultTy;
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      Callee = Call.getCalledValue();
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      Symbol = Target;
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27
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      IsInReg = Call.hasRetAttr(Attribute::InReg);
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      DoesNotReturn = Call.doesNotReturn();
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      IsVarArg = FuncTy->isVarArg();
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      IsReturnValueUsed = !Call.getInstruction()->use_empty();
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      RetSExt = Call.hasRetAttr(Attribute::SExt);
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      RetZExt = Call.hasRetAttr(Attribute::ZExt);
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      CallConv = Call.getCallingConv();
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      Args = std::move(ArgsList);
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      NumFixedArgs = (FixedArgs == ~0U) ? 
FuncTy->getNumParams()0
:
FixedArgs27
;
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      CS = &Call;
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      return *this;
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    }
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    CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
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                                const Value *Target, ArgListTy &&ArgsList,
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                                unsigned FixedArgs = ~0U) {
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      RetTy = ResultTy;
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      Callee = Target;
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      CallConv = CC;
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      Args = std::move(ArgsList);
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      NumFixedArgs = (FixedArgs == ~0U) ? 
Args.size()0
:
FixedArgs39
;
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      return *this;
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    }
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    CallLoweringInfo &setCallee(const DataLayout &DL, MCContext &Ctx,
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                                CallingConv::ID CC, Type *ResultTy,
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                                StringRef Target, ArgListTy &&ArgsList,
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                                unsigned FixedArgs = ~0U);
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    CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
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                                MCSymbol *Target, ArgListTy &&ArgsList,
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16
                                unsigned FixedArgs = ~0U) {
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16
      RetTy = ResultTy;
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      Symbol = Target;
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16
      CallConv = CC;
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16
      Args = std::move(ArgsList);
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16
      NumFixedArgs = (FixedArgs == ~0U) ? 
Args.size()16
:
FixedArgs0
;
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      return *this;
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16
    }
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    CallLoweringInfo &setTailCall(bool Value = true) {
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      IsTailCall = Value;
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      return *this;
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    }
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    CallLoweringInfo &setIsPatchPoint(bool Value = true) {
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      IsPatchPoint = Value;
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      return *this;
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    }
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    ArgListTy &getArgs() { return Args; }
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    void clearOuts() {
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      OutVals.clear();
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      OutFlags.clear();
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      OutRegs.clear();
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    }
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    void clearIns() {
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      Ins.clear();
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      InRegs.clear();
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    }
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  };
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protected:
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  DenseMap<const Value *, unsigned> LocalValueMap;
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  FunctionLoweringInfo &FuncInfo;
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  MachineFunction *MF;
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  MachineRegisterInfo &MRI;
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  MachineFrameInfo &MFI;
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  MachineConstantPool &MCP;
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  DebugLoc DbgLoc;
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  const TargetMachine &TM;
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  const DataLayout &DL;
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  const TargetInstrInfo &TII;
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  const TargetLowering &TLI;
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  const TargetRegisterInfo &TRI;
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  const TargetLibraryInfo *LibInfo;
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  bool SkipTargetIndependentISel;
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  /// \brief The position of the last instruction for materializing constants
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  /// for use in the current block. It resets to EmitStartPt when it makes sense
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  /// (for example, it's usually profitable to avoid function calls between the
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  /// definition and the use)
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  MachineInstr *LastLocalValue;
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  /// \brief The top most instruction in the current block that is allowed for
225
  /// emitting local variables. LastLocalValue resets to EmitStartPt when it
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  /// makes sense (for example, on function calls)
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  MachineInstr *EmitStartPt;
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public:
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  virtual ~FastISel();
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  /// \brief Return the position of the last instruction emitted for
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  /// materializing constants for use in the current block.
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  MachineInstr *getLastLocalValue() { return LastLocalValue; }
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  /// \brief Update the position of the last instruction emitted for
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  /// materializing constants for use in the current block.
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  void setLastLocalValue(MachineInstr *I) {
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    EmitStartPt = I;
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    LastLocalValue = I;
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  }
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  /// \brief Set the current block to which generated machine instructions will
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  /// be appended, and clear the local CSE map.
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  void startNewBlock();
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  /// \brief Return current debug location information.
248
0
  DebugLoc getCurDebugLoc() const { return DbgLoc; }
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  /// \brief Do "fast" instruction selection for function arguments and append
251
  /// the machine instructions to the current block. Returns true when
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  /// successful.
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  bool lowerArguments();
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  /// \brief Do "fast" instruction selection for the given LLVM IR instruction
256
  /// and append the generated machine instructions to the current block.
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  /// Returns true if selection was successful.
258
  bool selectInstruction(const Instruction *I);
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  /// \brief Do "fast" instruction selection for the given LLVM IR operator
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  /// (Instruction or ConstantExpr), and append generated machine instructions
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  /// to the current block. Return true if selection was successful.
263
  bool selectOperator(const User *I, unsigned Opcode);
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  /// \brief Create a virtual register and arrange for it to be assigned the
266
  /// value for the given LLVM value.
267
  unsigned getRegForValue(const Value *V);
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  /// \brief Look up the value to see if its value is already cached in a
270
  /// register. It may be defined by instructions across blocks or defined
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  /// locally.
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  unsigned lookUpRegForValue(const Value *V);
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  /// \brief This is a wrapper around getRegForValue that also takes care of
275
  /// truncating or sign-extending the given getelementptr index value.
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  std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
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  /// \brief We're checking to see if we can fold \p LI into \p FoldInst. Note
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  /// that we could have a sequence where multiple LLVM IR instructions are
280
  /// folded into the same machineinstr.  For example we could have:
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  ///
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  ///   A: x = load i32 *P
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  ///   B: y = icmp A, 42
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  ///   C: br y, ...
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  ///
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  /// In this scenario, \p LI is "A", and \p FoldInst is "C".  We know about "B"
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  /// (and any other folded instructions) because it is between A and C.
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  ///
289
  /// If we succeed folding, return true.
290
  bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst);
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  /// \brief The specified machine instr operand is a vreg, and that vreg is
293
  /// being provided by the specified load instruction.  If possible, try to
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  /// fold the load as an operand to the instruction, returning true if
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  /// possible.
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  ///
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  /// This method should be implemented by targets.
298
  virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/,
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465
                                   const LoadInst * /*LI*/) {
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465
    return false;
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465
  }
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  /// \brief Reset InsertPt to prepare for inserting instructions into the
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  /// current block.
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  void recomputeInsertPt();
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  /// \brief Remove all dead instructions between the I and E.
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  void removeDeadCode(MachineBasicBlock::iterator I,
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                      MachineBasicBlock::iterator E);
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311
  struct SavePoint {
312
    MachineBasicBlock::iterator InsertPt;
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    DebugLoc DL;
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  };
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  /// \brief Prepare InsertPt to begin inserting instructions into the local
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  /// value area and return the old insert position.
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  SavePoint enterLocalValueArea();
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  /// \brief Reset InsertPt to the given old insert position.
321
  void leaveLocalValueArea(SavePoint Old);
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protected:
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  explicit FastISel(FunctionLoweringInfo &FuncInfo,
325
                    const TargetLibraryInfo *LibInfo,
326
                    bool SkipTargetIndependentISel = false);
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328
  /// \brief This method is called by target-independent code when the normal
329
  /// FastISel process fails to select an instruction. This gives targets a
330
  /// chance to emit code for anything that doesn't fit into FastISel's
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  /// framework. It returns true if it was successful.
332
  virtual bool fastSelectInstruction(const Instruction *I) = 0;
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  /// \brief This method is called by target-independent code to do target-
335
  /// specific argument lowering. It returns true if it was successful.
336
  virtual bool fastLowerArguments();
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  /// \brief This method is called by target-independent code to do target-
339
  /// specific call lowering. It returns true if it was successful.
340
  virtual bool fastLowerCall(CallLoweringInfo &CLI);
341
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  /// \brief This method is called by target-independent code to do target-
343
  /// specific intrinsic lowering. It returns true if it was successful.
344
  virtual bool fastLowerIntrinsicCall(const IntrinsicInst *II);
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346
  /// \brief This method is called by target-independent code to request that an
347
  /// instruction with the given type and opcode be emitted.
348
  virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
349
350
  /// \brief This method is called by target-independent code to request that an
351
  /// instruction with the given type, opcode, and register operand be emitted.
352
  virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
353
                              bool Op0IsKill);
354
355
  /// \brief This method is called by target-independent code to request that an
356
  /// instruction with the given type, opcode, and register operands be emitted.
357
  virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
358
                               bool Op0IsKill, unsigned Op1, bool Op1IsKill);
359
360
  /// \brief This method is called by target-independent code to request that an
361
  /// instruction with the given type, opcode, and register and immediate
362
  /// operands be emitted.
363
  virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
364
                               bool Op0IsKill, uint64_t Imm);
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366
  /// \brief This method is a wrapper of fastEmit_ri.
367
  ///
368
  /// It first tries to emit an instruction with an immediate operand using
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  /// fastEmit_ri.  If that fails, it materializes the immediate into a register
370
  /// and try fastEmit_rr instead.
371
  unsigned fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill,
372
                        uint64_t Imm, MVT ImmType);
373
374
  /// \brief This method is called by target-independent code to request that an
375
  /// instruction with the given type, opcode, and immediate operand be emitted.
376
  virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
377
378
  /// \brief This method is called by target-independent code to request that an
379
  /// instruction with the given type, opcode, and floating-point immediate
380
  /// operand be emitted.
381
  virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
382
                              const ConstantFP *FPImm);
383
384
  /// \brief Emit a MachineInstr with no operands and a result register in the
385
  /// given register class.
386
  unsigned fastEmitInst_(unsigned MachineInstOpcode,
387
                         const TargetRegisterClass *RC);
388
389
  /// \brief Emit a MachineInstr with one register operand and a result register
390
  /// in the given register class.
391
  unsigned fastEmitInst_r(unsigned MachineInstOpcode,
392
                          const TargetRegisterClass *RC, unsigned Op0,
393
                          bool Op0IsKill);
394
395
  /// \brief Emit a MachineInstr with two register operands and a result
396
  /// register in the given register class.
397
  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
398
                           const TargetRegisterClass *RC, unsigned Op0,
399
                           bool Op0IsKill, unsigned Op1, bool Op1IsKill);
400
401
  /// \brief Emit a MachineInstr with three register operands and a result
402
  /// register in the given register class.
403
  unsigned fastEmitInst_rrr(unsigned MachineInstOpcode,
404
                            const TargetRegisterClass *RC, unsigned Op0,
405
                            bool Op0IsKill, unsigned Op1, bool Op1IsKill,
406
                            unsigned Op2, bool Op2IsKill);
407
408
  /// \brief Emit a MachineInstr with a register operand, an immediate, and a
409
  /// result register in the given register class.
410
  unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
411
                           const TargetRegisterClass *RC, unsigned Op0,
412
                           bool Op0IsKill, uint64_t Imm);
413
414
  /// \brief Emit a MachineInstr with one register operand and two immediate
415
  /// operands.
416
  unsigned fastEmitInst_rii(unsigned MachineInstOpcode,
417
                            const TargetRegisterClass *RC, unsigned Op0,
418
                            bool Op0IsKill, uint64_t Imm1, uint64_t Imm2);
419
420
  /// \brief Emit a MachineInstr with a floating point immediate, and a result
421
  /// register in the given register class.
422
  unsigned fastEmitInst_f(unsigned MachineInstOpcode,
423
                          const TargetRegisterClass *RC,
424
                          const ConstantFP *FPImm);
425
426
  /// \brief Emit a MachineInstr with two register operands, an immediate, and a
427
  /// result register in the given register class.
428
  unsigned fastEmitInst_rri(unsigned MachineInstOpcode,
429
                            const TargetRegisterClass *RC, unsigned Op0,
430
                            bool Op0IsKill, unsigned Op1, bool Op1IsKill,
431
                            uint64_t Imm);
432
433
  /// \brief Emit a MachineInstr with a single immediate operand, and a result
434
  /// register in the given register class.
435
  unsigned fastEmitInst_i(unsigned MachineInstrOpcode,
436
                          const TargetRegisterClass *RC, uint64_t Imm);
437
438
  /// \brief Emit a MachineInstr for an extract_subreg from a specified index of
439
  /// a superregister to a specified type.
440
  unsigned fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill,
441
                                      uint32_t Idx);
442
443
  /// \brief Emit MachineInstrs to compute the value of Op with all but the
444
  /// least significant bit set to zero.
445
  unsigned fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill);
446
447
  /// \brief Emit an unconditional branch to the given block, unless it is the
448
  /// immediate (fall-through) successor, and update the CFG.
449
  void fastEmitBranch(MachineBasicBlock *MBB, const DebugLoc &DL);
450
451
  /// Emit an unconditional branch to \p FalseMBB, obtains the branch weight
452
  /// and adds TrueMBB and FalseMBB to the successor list.
453
  void finishCondBranch(const BasicBlock *BranchBB, MachineBasicBlock *TrueMBB,
454
                        MachineBasicBlock *FalseMBB);
455
456
  /// \brief Update the value map to include the new mapping for this
457
  /// instruction, or insert an extra copy to get the result in a previous
458
  /// determined register.
459
  ///
460
  /// NOTE: This is only necessary because we might select a block that uses a
461
  /// value before we select the block that defines the value. It might be
462
  /// possible to fix this by selecting blocks in reverse postorder.
463
  void updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs = 1);
464
465
  unsigned createResultReg(const TargetRegisterClass *RC);
466
467
  /// \brief Try to constrain Op so that it is usable by argument OpNum of the
468
  /// provided MCInstrDesc. If this fails, create a new virtual register in the
469
  /// correct class and COPY the value there.
470
  unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
471
                                    unsigned OpNum);
472
473
  /// \brief Emit a constant in a register using target-specific logic, such as
474
  /// constant pool loads.
475
0
  virtual unsigned fastMaterializeConstant(const Constant *C) { return 0; }
476
477
  /// \brief Emit an alloca address in a register using target-specific logic.
478
0
  virtual unsigned fastMaterializeAlloca(const AllocaInst *C) { return 0; }
479
480
  /// \brief Emit the floating-point constant +0.0 in a register using target-
481
  /// specific logic.
482
0
  virtual unsigned fastMaterializeFloatZero(const ConstantFP *CF) {
483
0
    return 0;
484
0
  }
485
486
  /// \brief Check if \c Add is an add that can be safely folded into \c GEP.
487
  ///
488
  /// \c Add can be folded into \c GEP if:
489
  /// - \c Add is an add,
490
  /// - \c Add's size matches \c GEP's,
491
  /// - \c Add is in the same basic block as \c GEP, and
492
  /// - \c Add has a constant operand.
493
  bool canFoldAddIntoGEP(const User *GEP, const Value *Add);
494
495
  /// \brief Test whether the given value has exactly one use.
496
  bool hasTrivialKill(const Value *V);
497
498
  /// \brief Create a machine mem operand from the given instruction.
499
  MachineMemOperand *createMachineMemOperandFor(const Instruction *I) const;
500
501
  CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const;
502
503
  bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs);
504
  bool lowerCallTo(const CallInst *CI, const char *SymbolName,
505
                   unsigned NumArgs);
506
  bool lowerCallTo(CallLoweringInfo &CLI);
507
508
1
  bool isCommutativeIntrinsic(IntrinsicInst const *II) {
509
1
    switch (II->getIntrinsicID()) {
510
1
    case Intrinsic::sadd_with_overflow:
511
1
    case Intrinsic::uadd_with_overflow:
512
1
    case Intrinsic::smul_with_overflow:
513
1
    case Intrinsic::umul_with_overflow:
514
1
      return true;
515
0
    default:
516
0
      return false;
517
1
    }
518
1
  }
519
520
  bool lowerCall(const CallInst *I);
521
  /// \brief Select and emit code for a binary operator instruction, which has
522
  /// an opcode which directly corresponds to the given ISD opcode.
523
  bool selectBinaryOp(const User *I, unsigned ISDOpcode);
524
  bool selectFNeg(const User *I);
525
  bool selectGetElementPtr(const User *I);
526
  bool selectStackmap(const CallInst *I);
527
  bool selectPatchpoint(const CallInst *I);
528
  bool selectCall(const User *Call);
529
  bool selectIntrinsicCall(const IntrinsicInst *II);
530
  bool selectBitCast(const User *I);
531
  bool selectCast(const User *I, unsigned Opcode);
532
  bool selectExtractValue(const User *I);
533
  bool selectInsertValue(const User *I);
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  bool selectXRayCustomEvent(const CallInst *II);
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private:
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  /// \brief Handle PHI nodes in successor blocks.
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  ///
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  /// Emit code to ensure constants are copied into registers when needed.
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  /// Remember the virtual registers that need to be added to the Machine PHI
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  /// nodes as input.  We cannot just directly add them, because expansion might
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  /// result in multiple MBB's for one BB.  As such, the start of the BB might
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  /// correspond to a different MBB than the end.
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  bool handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
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  /// \brief Helper for materializeRegForValue to materialize a constant in a
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  /// target-independent way.
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  unsigned materializeConstant(const Value *V, MVT VT);
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  /// \brief Helper for getRegForVale. This function is called when the value
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  /// isn't already available in a register and must be materialized with new
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  /// instructions.
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  unsigned materializeRegForValue(const Value *V, MVT VT);
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  /// \brief Clears LocalValueMap and moves the area for the new local variables
556
  /// to the beginning of the block. It helps to avoid spilling cached variables
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  /// across heavy instructions like calls.
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  void flushLocalValueMap();
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  /// \brief Removes dead local value instructions after SavedLastLocalvalue.
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  void removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue);
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  /// \brief Insertion point before trying to select the current instruction.
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  MachineBasicBlock::iterator SavedInsertPt;
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566
  /// \brief Add a stackmap or patchpoint intrinsic call's live variable
567
  /// operands to a stackmap or patchpoint machine instruction.
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  bool addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
569
                           const CallInst *CI, unsigned StartIdx);
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  bool lowerCallOperands(const CallInst *CI, unsigned ArgIdx, unsigned NumArgs,
571
                         const Value *Callee, bool ForceRetVoidTy,
572
                         CallLoweringInfo &CLI);
573
};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_FASTISEL_H