Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
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//===- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ----*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the IRTranslator pass.
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/// This pass is responsible for translating LLVM IR into MachineInstr.
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/// It uses target hooks to lower the ABI but aside from that, the pass
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/// generated code is generic. This is the default translator used for
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/// GlobalISel.
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///
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/// \todo Replace the comments with actual doxygen comments.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
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#define LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Types.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/IR/Intrinsics.h"
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#include <memory>
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#include <utility>
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namespace llvm {
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class AllocaInst;
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class BasicBlock;
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class CallInst;
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class CallLowering;
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class Constant;
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class DataLayout;
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class Instruction;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class MachineRegisterInfo;
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class OptimizationRemarkEmitter;
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class PHINode;
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class TargetPassConfig;
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class User;
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class Value;
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// Technically the pass should run on an hypothetical MachineModule,
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// since it should translate Global into some sort of MachineGlobal.
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// The MachineGlobal should ultimately just be a transfer of ownership of
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// the interesting bits that are relevant to represent a global value.
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// That being said, we could investigate what would it cost to just duplicate
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// the information from the LLVM IR.
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// The idea is that ultimately we would be able to free up the memory used
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// by the LLVM IR as soon as the translation is over.
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class IRTranslator : public MachineFunctionPass {
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public:
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  static char ID;
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private:
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  /// Interface used to lower the everything related to calls.
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  const CallLowering *CLI;
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  /// Mapping of the values of the current LLVM IR function
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  /// to the related virtual registers.
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  ValueToVReg ValToVReg;
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  // N.b. it's not completely obvious that this will be sufficient for every
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  // LLVM IR construct (with "invoke" being the obvious candidate to mess up our
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  // lives.
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  DenseMap<const BasicBlock *, MachineBasicBlock *> BBToMBB;
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  // One BasicBlock can be translated to multiple MachineBasicBlocks.  For such
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  // BasicBlocks translated to multiple MachineBasicBlocks, MachinePreds retains
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  // a mapping between the edges arriving at the BasicBlock to the corresponding
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  // created MachineBasicBlocks. Some BasicBlocks that get translated to a
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  // single MachineBasicBlock may also end up in this Map.
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  using CFGEdge = std::pair<const BasicBlock *, const BasicBlock *>;
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  DenseMap<CFGEdge, SmallVector<MachineBasicBlock *, 1>> MachinePreds;
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  // List of stubbed PHI instructions, for values and basic blocks to be filled
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  // in once all MachineBasicBlocks have been created.
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  SmallVector<std::pair<const PHINode *, MachineInstr *>, 4> PendingPHIs;
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  /// Record of what frame index has been allocated to specified allocas for
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  /// this function.
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  DenseMap<const AllocaInst *, int> FrameIndices;
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  /// \name Methods for translating form LLVM IR to MachineInstr.
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  /// \see ::translate for general information on the translate methods.
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  /// @{
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  /// Translate \p Inst into its corresponding MachineInstr instruction(s).
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  /// Insert the newly translated instruction(s) right where the CurBuilder
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  /// is set.
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  ///
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  /// The general algorithm is:
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  /// 1. Look for a virtual register for each operand or
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  ///    create one.
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  /// 2 Update the ValToVReg accordingly.
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  /// 2.alt. For constant arguments, if they are compile time constants,
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  ///   produce an immediate in the right operand and do not touch
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  ///   ValToReg. Actually we will go with a virtual register for each
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  ///   constants because it may be expensive to actually materialize the
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  ///   constant. Moreover, if the constant spans on several instructions,
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  ///   CSE may not catch them.
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  ///   => Update ValToVReg and remember that we saw a constant in Constants.
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  ///   We will materialize all the constants in finalize.
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  /// Note: we would need to do something so that we can recognize such operand
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  ///       as constants.
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  /// 3. Create the generic instruction.
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  ///
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  /// \return true if the translation succeeded.
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  bool translate(const Instruction &Inst);
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  /// Materialize \p C into virtual-register \p Reg. The generic instructions
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  /// performing this materialization will be inserted into the entry block of
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  /// the function.
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  ///
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  /// \return true if the materialization succeeded.
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  bool translate(const Constant &C, unsigned Reg);
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  /// Translate an LLVM bitcast into generic IR. Either a COPY or a G_BITCAST is
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  /// emitted.
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  bool translateBitCast(const User &U, MachineIRBuilder &MIRBuilder);
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  /// Translate an LLVM load instruction into generic IR.
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  bool translateLoad(const User &U, MachineIRBuilder &MIRBuilder);
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  /// Translate an LLVM store instruction into generic IR.
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  bool translateStore(const User &U, MachineIRBuilder &MIRBuilder);
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  /// Translate an LLVM string intrinsic (memcpy, memset, ...).
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  bool translateMemfunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
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                        unsigned Intrinsic);
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  void getStackGuard(unsigned DstReg, MachineIRBuilder &MIRBuilder);
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  bool translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
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                                  MachineIRBuilder &MIRBuilder);
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  bool translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
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                               MachineIRBuilder &MIRBuilder);
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  bool translateInlineAsm(const CallInst &CI, MachineIRBuilder &MIRBuilder);
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  /// Translate call instruction.
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  /// \pre \p U is a call instruction.
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  bool translateCall(const User &U, MachineIRBuilder &MIRBuilder);
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  bool translateInvoke(const User &U, MachineIRBuilder &MIRBuilder);
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  bool translateLandingPad(const User &U, MachineIRBuilder &MIRBuilder);
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  /// Translate one of LLVM's cast instructions into MachineInstrs, with the
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  /// given generic Opcode.
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  bool translateCast(unsigned Opcode, const User &U,
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                     MachineIRBuilder &MIRBuilder);
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  /// Translate a phi instruction.
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  bool translatePHI(const User &U, MachineIRBuilder &MIRBuilder);
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  /// Translate a comparison (icmp or fcmp) instruction or constant.
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  bool translateCompare(const User &U, MachineIRBuilder &MIRBuilder);
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  /// Translate an integer compare instruction (or constant).
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953k
  bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) {
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953k
    return translateCompare(U, MIRBuilder);
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953k
  }
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  /// Translate a floating-point compare instruction (or constant).
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13.2k
  bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) {
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13.2k
    return translateCompare(U, MIRBuilder);
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13.2k
  }
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  /// Add remaining operands onto phis we've translated. Executed after all
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  /// MachineBasicBlocks for the function have been created.
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  void finishPendingPhis();
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  /// Translate \p Inst into a binary operation \p Opcode.
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  /// \pre \p U is a binary operation.
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  bool translateBinaryOp(unsigned Opcode, const User &U,
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                         MachineIRBuilder &MIRBuilder);
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  /// Translate branch (br) instruction.
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  /// \pre \p U is a branch instruction.
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  bool translateBr(const User &U, MachineIRBuilder &MIRBuilder);
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  bool translateSwitch(const User &U, MachineIRBuilder &MIRBuilder);
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  bool translateIndirectBr(const User &U, MachineIRBuilder &MIRBuilder);
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  bool translateExtractValue(const User &U, MachineIRBuilder &MIRBuilder);
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  bool translateInsertValue(const User &U, MachineIRBuilder &MIRBuilder);
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  bool translateSelect(const User &U, MachineIRBuilder &MIRBuilder);
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  bool translateGetElementPtr(const User &U, MachineIRBuilder &MIRBuilder);
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  bool translateAlloca(const User &U, MachineIRBuilder &MIRBuilder);
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  /// Translate return (ret) instruction.
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  /// The target needs to implement CallLowering::lowerReturn for
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  /// this to succeed.
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  /// \pre \p U is a return instruction.
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  bool translateRet(const User &U, MachineIRBuilder &MIRBuilder);
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  bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder);
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328k
  bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) {
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328k
    return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder);
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  }
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77.1k
  bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) {
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77.1k
    return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder);
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77.1k
  }
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89.8k
  bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) {
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89.8k
    return translateBinaryOp(TargetOpcode::G_AND, U, MIRBuilder);
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89.8k
  }
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77.5k
  bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) {
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77.5k
    return translateBinaryOp(TargetOpcode::G_MUL, U, MIRBuilder);
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77.5k
  }
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35.8k
  bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) {
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35.8k
    return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder);
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35.8k
  }
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9.38k
  bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) {
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9.38k
    return translateBinaryOp(TargetOpcode::G_XOR, U, MIRBuilder);
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9.38k
  }
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6.21k
  bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) {
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6.21k
    return translateBinaryOp(TargetOpcode::G_UDIV, U, MIRBuilder);
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6.21k
  }
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3.91k
  bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) {
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3.91k
    return translateBinaryOp(TargetOpcode::G_SDIV, U, MIRBuilder);
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  }
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  bool translateURem(const User &U, MachineIRBuilder &MIRBuilder) {
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    return translateBinaryOp(TargetOpcode::G_UREM, U, MIRBuilder);
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  }
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2.01k
  bool translateSRem(const User &U, MachineIRBuilder &MIRBuilder) {
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2.01k
    return translateBinaryOp(TargetOpcode::G_SREM, U, MIRBuilder);
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2.01k
  }
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24.9k
  bool translateIntToPtr(const User &U, MachineIRBuilder &MIRBuilder) {
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    return translateCast(TargetOpcode::G_INTTOPTR, U, MIRBuilder);
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  }
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49.9k
  bool translatePtrToInt(const User &U, MachineIRBuilder &MIRBuilder) {
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    return translateCast(TargetOpcode::G_PTRTOINT, U, MIRBuilder);
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49.9k
  }
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158k
  bool translateTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
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158k
    return translateCast(TargetOpcode::G_TRUNC, U, MIRBuilder);
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158k
  }
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3.89k
  bool translateFPTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
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3.89k
    return translateCast(TargetOpcode::G_FPTRUNC, U, MIRBuilder);
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3.89k
  }
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12.5k
  bool translateFPExt(const User &U, MachineIRBuilder &MIRBuilder) {
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12.5k
    return translateCast(TargetOpcode::G_FPEXT, U, MIRBuilder);
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  }
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2.87k
  bool translateFPToUI(const User &U, MachineIRBuilder &MIRBuilder) {
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2.87k
    return translateCast(TargetOpcode::G_FPTOUI, U, MIRBuilder);
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2.87k
  }
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2.05k
  bool translateFPToSI(const User &U, MachineIRBuilder &MIRBuilder) {
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2.05k
    return translateCast(TargetOpcode::G_FPTOSI, U, MIRBuilder);
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2.05k
  }
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13.8k
  bool translateUIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
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13.8k
    return translateCast(TargetOpcode::G_UITOFP, U, MIRBuilder);
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13.8k
  }
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22.8k
  bool translateSIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
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22.8k
    return translateCast(TargetOpcode::G_SITOFP, U, MIRBuilder);
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22.8k
  }
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6.52k
  bool translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder) {
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    return true;
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  }
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  bool translateSExt(const User &U, MachineIRBuilder &MIRBuilder) {
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    return translateCast(TargetOpcode::G_SEXT, U, MIRBuilder);
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  }
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92.0k
  bool translateZExt(const User &U, MachineIRBuilder &MIRBuilder) {
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92.0k
    return translateCast(TargetOpcode::G_ZEXT, U, MIRBuilder);
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92.0k
  }
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50.4k
  bool translateShl(const User &U, MachineIRBuilder &MIRBuilder) {
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50.4k
    return translateBinaryOp(TargetOpcode::G_SHL, U, MIRBuilder);
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  }
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34.1k
  bool translateLShr(const User &U, MachineIRBuilder &MIRBuilder) {
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34.1k
    return translateBinaryOp(TargetOpcode::G_LSHR, U, MIRBuilder);
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34.1k
  }
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12.2k
  bool translateAShr(const User &U, MachineIRBuilder &MIRBuilder) {
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12.2k
    return translateBinaryOp(TargetOpcode::G_ASHR, U, MIRBuilder);
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12.2k
  }
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26.0k
  bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) {
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26.0k
    return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder);
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  }
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22.0k
  bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) {
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22.0k
    return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder);
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22.0k
  }
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25.1k
  bool translateFDiv(const User &U, MachineIRBuilder &MIRBuilder) {
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25.1k
    return translateBinaryOp(TargetOpcode::G_FDIV, U, MIRBuilder);
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25.1k
  }
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7
  bool translateFRem(const User &U, MachineIRBuilder &MIRBuilder) {
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    return translateBinaryOp(TargetOpcode::G_FREM, U, MIRBuilder);
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  }
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  bool translateVAArg(const User &U, MachineIRBuilder &MIRBuilder);
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  bool translateInsertElement(const User &U, MachineIRBuilder &MIRBuilder);
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  bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder);
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  bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder);
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  // Stubs to keep the compiler happy while we implement the rest of the
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  // translation.
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0
  bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) {
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0
    return false;
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0
  }
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0
  bool translateCleanupRet(const User &U, MachineIRBuilder &MIRBuilder) {
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0
    return false;
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0
  }
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0
  bool translateCatchRet(const User &U, MachineIRBuilder &MIRBuilder) {
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0
    return false;
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0
  }
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0
  bool translateCatchSwitch(const User &U, MachineIRBuilder &MIRBuilder) {
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0
    return false;
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0
  }
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1.39k
  bool translateFence(const User &U, MachineIRBuilder &MIRBuilder) {
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1.39k
    return false;
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1.39k
  }
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0
  bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder) {
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0
    return false;
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0
  }
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0
  bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder) {
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0
    return false;
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0
  }
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0
  bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) {
337
0
    return false;
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0
  }
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0
  bool translateCleanupPad(const User &U, MachineIRBuilder &MIRBuilder) {
340
0
    return false;
341
0
  }
342
0
  bool translateCatchPad(const User &U, MachineIRBuilder &MIRBuilder) {
343
0
    return false;
344
0
  }
345
0
  bool translateUserOp1(const User &U, MachineIRBuilder &MIRBuilder) {
346
0
    return false;
347
0
  }
348
0
  bool translateUserOp2(const User &U, MachineIRBuilder &MIRBuilder) {
349
0
    return false;
350
0
  }
351
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  /// @}
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  // Builder for machine instruction a la IRBuilder.
355
  // I.e., compared to regular MIBuilder, this one also inserts the instruction
356
  // in the current block, it can creates block, etc., basically a kind of
357
  // IRBuilder, but for Machine IR.
358
  MachineIRBuilder CurBuilder;
359
360
  // Builder set to the entry block (just after ABI lowering instructions). Used
361
  // as a convenient location for Constants.
362
  MachineIRBuilder EntryBuilder;
363
364
  // The MachineFunction currently being translated.
365
  MachineFunction *MF;
366
367
  /// MachineRegisterInfo used to create virtual registers.
368
  MachineRegisterInfo *MRI = nullptr;
369
370
  const DataLayout *DL;
371
372
  /// Current target configuration. Controls how the pass handles errors.
373
  const TargetPassConfig *TPC;
374
375
  /// Current optimization remark emitter. Used to report failures.
376
  std::unique_ptr<OptimizationRemarkEmitter> ORE;
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378
  // * Insert all the code needed to materialize the constants
379
  // at the proper place. E.g., Entry block or dominator block
380
  // of each constant depending on how fancy we want to be.
381
  // * Clear the different maps.
382
  void finalizeFunction();
383
384
  /// Get the VReg that represents \p Val.
385
  /// If such VReg does not exist, it is created.
386
  unsigned getOrCreateVReg(const Value &Val);
387
388
  /// Get the frame index that represents \p Val.
389
  /// If such VReg does not exist, it is created.
390
  int getOrCreateFrameIndex(const AllocaInst &AI);
391
392
  /// Get the alignment of the given memory operation instruction. This will
393
  /// either be the explicitly specified value or the ABI-required alignment for
394
  /// the type being accessed (according to the Module's DataLayout).
395
  unsigned getMemOpAlignment(const Instruction &I);
396
397
  /// Get the MachineBasicBlock that represents \p BB. Specifically, the block
398
  /// returned will be the head of the translated block (suitable for branch
399
  /// destinations).
400
  MachineBasicBlock &getMBB(const BasicBlock &BB);
401
402
  /// Record \p NewPred as a Machine predecessor to `Edge.second`, corresponding
403
  /// to `Edge.first` at the IR level. This is used when IRTranslation creates
404
  /// multiple MachineBasicBlocks for a given IR block and the CFG is no longer
405
  /// represented simply by the IR-level CFG.
406
  void addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred);
407
408
  /// Returns the Machine IR predecessors for the given IR CFG edge. Usually
409
  /// this is just the single MachineBasicBlock corresponding to the predecessor
410
  /// in the IR. More complex lowering can result in multiple MachineBasicBlocks
411
  /// preceding the original though (e.g. switch instructions).
412
1.10M
  SmallVector<MachineBasicBlock *, 1> getMachinePredBBs(CFGEdge Edge) {
413
1.10M
    auto RemappedEdge = MachinePreds.find(Edge);
414
1.10M
    if (RemappedEdge != MachinePreds.end())
415
10.7k
      return RemappedEdge->second;
416
1.09M
    return SmallVector<MachineBasicBlock *, 4>(1, &getMBB(*Edge.first));
417
1.10M
  }
418
419
public:
420
  // Ctor, nothing fancy.
421
  IRTranslator();
422
423
5
  StringRef getPassName() const override { return "IRTranslator"; }
424
425
  void getAnalysisUsage(AnalysisUsage &AU) const override;
426
427
  // Algo:
428
  //   CallLowering = MF.subtarget.getCallLowering()
429
  //   F = MF.getParent()
430
  //   MIRBuilder.reset(MF)
431
  //   getMBB(F.getEntryBB())
432
  //   CallLowering->translateArguments(MIRBuilder, F, ValToVReg)
433
  //   for each bb in F
434
  //     getMBB(bb)
435
  //     for each inst in bb
436
  //       if (!translate(MIRBuilder, inst, ValToVReg, ConstantToSequence))
437
  //         report_fatal_error("Don't know how to translate input");
438
  //   finalize()
439
  bool runOnMachineFunction(MachineFunction &MF) override;
440
};
441
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} // end namespace llvm
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#endif // LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H