/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/CodeGen/MachineRegisterInfo.cpp
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1 | | //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // Implementation of the MachineRegisterInfo class. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "llvm/CodeGen/MachineRegisterInfo.h" |
15 | | #include "llvm/ADT/iterator_range.h" |
16 | | #include "llvm/CodeGen/LowLevelType.h" |
17 | | #include "llvm/CodeGen/MachineBasicBlock.h" |
18 | | #include "llvm/CodeGen/MachineFunction.h" |
19 | | #include "llvm/CodeGen/MachineInstr.h" |
20 | | #include "llvm/CodeGen/MachineInstrBuilder.h" |
21 | | #include "llvm/CodeGen/MachineOperand.h" |
22 | | #include "llvm/IR/Attributes.h" |
23 | | #include "llvm/IR/DebugLoc.h" |
24 | | #include "llvm/IR/Function.h" |
25 | | #include "llvm/MC/MCRegisterInfo.h" |
26 | | #include "llvm/Support/Casting.h" |
27 | | #include "llvm/Support/CommandLine.h" |
28 | | #include "llvm/Support/Compiler.h" |
29 | | #include "llvm/Support/ErrorHandling.h" |
30 | | #include "llvm/Support/raw_ostream.h" |
31 | | #include "llvm/Target/TargetInstrInfo.h" |
32 | | #include "llvm/Target/TargetRegisterInfo.h" |
33 | | #include "llvm/Target/TargetSubtargetInfo.h" |
34 | | #include <cassert> |
35 | | |
36 | | using namespace llvm; |
37 | | |
38 | | static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, |
39 | | cl::init(true), cl::desc("Enable subregister liveness tracking.")); |
40 | | |
41 | | // Pin the vtable to this file. |
42 | 0 | void MachineRegisterInfo::Delegate::anchor() {} |
43 | | |
44 | | MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF) |
45 | | : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() && |
46 | | EnableSubRegLiveness), |
47 | 661k | IsUpdatedCSRsInitialized(false) { |
48 | 661k | unsigned NumRegs = getTargetRegisterInfo()->getNumRegs(); |
49 | 661k | VRegInfo.reserve(256); |
50 | 661k | RegAllocHints.reserve(256); |
51 | 661k | UsedPhysRegMask.resize(NumRegs); |
52 | 661k | PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]()); |
53 | 661k | } |
54 | | |
55 | | /// setRegClass - Set the register class of the specified virtual register. |
56 | | /// |
57 | | void |
58 | 10.4M | MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { |
59 | 10.4M | assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); |
60 | 10.4M | VRegInfo[Reg].first = RC; |
61 | 10.4M | } |
62 | | |
63 | | void MachineRegisterInfo::setRegBank(unsigned Reg, |
64 | 4.66M | const RegisterBank &RegBank) { |
65 | 4.66M | VRegInfo[Reg].first = &RegBank; |
66 | 4.66M | } |
67 | | |
68 | | const TargetRegisterClass * |
69 | | MachineRegisterInfo::constrainRegClass(unsigned Reg, |
70 | | const TargetRegisterClass *RC, |
71 | 16.9M | unsigned MinNumRegs) { |
72 | 16.9M | const TargetRegisterClass *OldRC = getRegClass(Reg); |
73 | 16.9M | if (OldRC == RC) |
74 | 9.93M | return RC; |
75 | 6.99M | const TargetRegisterClass *NewRC = |
76 | 6.99M | getTargetRegisterInfo()->getCommonSubClass(OldRC, RC); |
77 | 6.99M | if (!NewRC || 6.99M NewRC == OldRC6.88M ) |
78 | 2.60M | return NewRC; |
79 | 4.39M | if (4.39M NewRC->getNumRegs() < MinNumRegs4.39M ) |
80 | 78 | return nullptr; |
81 | 4.39M | setRegClass(Reg, NewRC); |
82 | 4.39M | return NewRC; |
83 | 4.39M | } |
84 | | |
85 | | bool |
86 | 651k | MachineRegisterInfo::recomputeRegClass(unsigned Reg) { |
87 | 651k | const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); |
88 | 651k | const TargetRegisterClass *OldRC = getRegClass(Reg); |
89 | 651k | const TargetRegisterClass *NewRC = |
90 | 651k | getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF); |
91 | 651k | |
92 | 651k | // Stop early if there is no room to grow. |
93 | 651k | if (NewRC == OldRC) |
94 | 628k | return false; |
95 | 23.1k | |
96 | 23.1k | // Accumulate constraints from all uses. |
97 | 23.1k | for (MachineOperand &MO : reg_nodbg_operands(Reg)) 23.1k { |
98 | 61.7k | // Apply the effect of the given operand to NewRC. |
99 | 61.7k | MachineInstr *MI = MO.getParent(); |
100 | 61.7k | unsigned OpNo = &MO - &MI->getOperand(0); |
101 | 61.7k | NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, |
102 | 61.7k | getTargetRegisterInfo()); |
103 | 61.7k | if (!NewRC || 61.7k NewRC == OldRC61.7k ) |
104 | 12.6k | return false; |
105 | 10.4k | } |
106 | 10.4k | setRegClass(Reg, NewRC); |
107 | 10.4k | return true; |
108 | 10.4k | } |
109 | | |
110 | 29.4M | unsigned MachineRegisterInfo::createIncompleteVirtualRegister() { |
111 | 29.4M | unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); |
112 | 29.4M | VRegInfo.grow(Reg); |
113 | 29.4M | RegAllocHints.grow(Reg); |
114 | 29.4M | return Reg; |
115 | 29.4M | } |
116 | | |
117 | | /// createVirtualRegister - Create and return a new virtual register in the |
118 | | /// function with the specified register class. |
119 | | /// |
120 | | unsigned |
121 | 18.3M | MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ |
122 | 18.3M | assert(RegClass && "Cannot create register without RegClass!"); |
123 | 18.3M | assert(RegClass->isAllocatable() && |
124 | 18.3M | "Virtual register RegClass must be allocatable."); |
125 | 18.3M | |
126 | 18.3M | // New virtual register number. |
127 | 18.3M | unsigned Reg = createIncompleteVirtualRegister(); |
128 | 18.3M | VRegInfo[Reg].first = RegClass; |
129 | 18.3M | if (TheDelegate) |
130 | 771k | TheDelegate->MRI_NoteNewVirtualRegister(Reg); |
131 | 18.3M | return Reg; |
132 | 18.3M | } |
133 | | |
134 | 29.1M | LLT MachineRegisterInfo::getType(unsigned VReg) const { |
135 | 29.1M | VRegToTypeMap::const_iterator TypeIt = getVRegToType().find(VReg); |
136 | 29.1M | return TypeIt != getVRegToType().end() ? TypeIt->second29.1M : LLT{}53.8k ; |
137 | 29.1M | } |
138 | | |
139 | 7.25k | void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) { |
140 | 7.25k | // Check that VReg doesn't have a class. |
141 | 7.25k | assert((getRegClassOrRegBank(VReg).isNull() || |
142 | 7.25k | !getRegClassOrRegBank(VReg).is<const TargetRegisterClass *>()) && |
143 | 7.25k | "Can't set the size of a non-generic virtual register"); |
144 | 7.25k | getVRegToType()[VReg] = Ty; |
145 | 7.25k | } |
146 | | |
147 | | unsigned |
148 | 11.0M | MachineRegisterInfo::createGenericVirtualRegister(LLT Ty) { |
149 | 11.0M | // New virtual register number. |
150 | 11.0M | unsigned Reg = createIncompleteVirtualRegister(); |
151 | 11.0M | // FIXME: Should we use a dummy register class? |
152 | 11.0M | VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr); |
153 | 11.0M | getVRegToType()[Reg] = Ty; |
154 | 11.0M | if (TheDelegate) |
155 | 0 | TheDelegate->MRI_NoteNewVirtualRegister(Reg); |
156 | 11.0M | return Reg; |
157 | 11.0M | } |
158 | | |
159 | 0 | void MachineRegisterInfo::clearVirtRegTypes() { |
160 | 0 | getVRegToType().clear(); |
161 | 0 | } |
162 | | |
163 | | /// clearVirtRegs - Remove all virtual registers (after physreg assignment). |
164 | 1.09M | void MachineRegisterInfo::clearVirtRegs() { |
165 | | #ifndef NDEBUG |
166 | | for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { |
167 | | unsigned Reg = TargetRegisterInfo::index2VirtReg(i); |
168 | | if (!VRegInfo[Reg].second) |
169 | | continue; |
170 | | verifyUseList(Reg); |
171 | | llvm_unreachable("Remaining virtual register operands"); |
172 | | } |
173 | | #endif |
174 | | VRegInfo.clear(); |
175 | 1.09M | for (auto &I : LiveIns) |
176 | 1.61M | I.second = 0; |
177 | 1.09M | } |
178 | | |
179 | 0 | void MachineRegisterInfo::verifyUseList(unsigned Reg) const { |
180 | | #ifndef NDEBUG |
181 | | bool Valid = true; |
182 | | for (MachineOperand &M : reg_operands(Reg)) { |
183 | | MachineOperand *MO = &M; |
184 | | MachineInstr *MI = MO->getParent(); |
185 | | if (!MI) { |
186 | | errs() << PrintReg(Reg, getTargetRegisterInfo()) |
187 | | << " use list MachineOperand " << MO |
188 | | << " has no parent instruction.\n"; |
189 | | Valid = false; |
190 | | continue; |
191 | | } |
192 | | MachineOperand *MO0 = &MI->getOperand(0); |
193 | | unsigned NumOps = MI->getNumOperands(); |
194 | | if (!(MO >= MO0 && MO < MO0+NumOps)) { |
195 | | errs() << PrintReg(Reg, getTargetRegisterInfo()) |
196 | | << " use list MachineOperand " << MO |
197 | | << " doesn't belong to parent MI: " << *MI; |
198 | | Valid = false; |
199 | | } |
200 | | if (!MO->isReg()) { |
201 | | errs() << PrintReg(Reg, getTargetRegisterInfo()) |
202 | | << " MachineOperand " << MO << ": " << *MO |
203 | | << " is not a register\n"; |
204 | | Valid = false; |
205 | | } |
206 | | if (MO->getReg() != Reg) { |
207 | | errs() << PrintReg(Reg, getTargetRegisterInfo()) |
208 | | << " use-list MachineOperand " << MO << ": " |
209 | | << *MO << " is the wrong register\n"; |
210 | | Valid = false; |
211 | | } |
212 | | } |
213 | | assert(Valid && "Invalid use list"); |
214 | | #endif |
215 | | } |
216 | | |
217 | 1.15M | void MachineRegisterInfo::verifyUseLists() const { |
218 | | #ifndef NDEBUG |
219 | | for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) |
220 | | verifyUseList(TargetRegisterInfo::index2VirtReg(i)); |
221 | | for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i) |
222 | | verifyUseList(i); |
223 | | #endif |
224 | | } |
225 | | |
226 | | /// Add MO to the linked list of operands for its register. |
227 | 233M | void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) { |
228 | 233M | assert(!MO->isOnRegUseList() && "Already on list"); |
229 | 233M | MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); |
230 | 233M | MachineOperand *const Head = HeadRef; |
231 | 233M | |
232 | 233M | // Head points to the first list element. |
233 | 233M | // Next is NULL on the last list element. |
234 | 233M | // Prev pointers are circular, so Head->Prev == Last. |
235 | 233M | |
236 | 233M | // Head is NULL for an empty list. |
237 | 233M | if (!Head233M ) { |
238 | 38.4M | MO->Contents.Reg.Prev = MO; |
239 | 38.4M | MO->Contents.Reg.Next = nullptr; |
240 | 38.4M | HeadRef = MO; |
241 | 38.4M | return; |
242 | 38.4M | } |
243 | 233M | assert(MO->getReg() == Head->getReg() && "Different regs on the same list!"); |
244 | 194M | |
245 | 194M | // Insert MO between Last and Head in the circular Prev chain. |
246 | 194M | MachineOperand *Last = Head->Contents.Reg.Prev; |
247 | 194M | assert(Last && "Inconsistent use list"); |
248 | 194M | assert(MO->getReg() == Last->getReg() && "Different regs on the same list!"); |
249 | 194M | Head->Contents.Reg.Prev = MO; |
250 | 194M | MO->Contents.Reg.Prev = Last; |
251 | 194M | |
252 | 194M | // Def operands always precede uses. This allows def_iterator to stop early. |
253 | 194M | // Insert def operands at the front, and use operands at the back. |
254 | 194M | if (MO->isDef()194M ) { |
255 | 60.4M | // Insert def at the front. |
256 | 60.4M | MO->Contents.Reg.Next = Head; |
257 | 60.4M | HeadRef = MO; |
258 | 194M | } else { |
259 | 134M | // Insert use at the end. |
260 | 134M | MO->Contents.Reg.Next = nullptr; |
261 | 134M | Last->Contents.Reg.Next = MO; |
262 | 134M | } |
263 | 233M | } |
264 | | |
265 | | /// Remove MO from its use-def list. |
266 | 137M | void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) { |
267 | 137M | assert(MO->isOnRegUseList() && "Operand not on use list"); |
268 | 137M | MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); |
269 | 137M | MachineOperand *const Head = HeadRef; |
270 | 137M | assert(Head && "List already empty"); |
271 | 137M | |
272 | 137M | // Unlink this from the doubly linked list of operands. |
273 | 137M | MachineOperand *Next = MO->Contents.Reg.Next; |
274 | 137M | MachineOperand *Prev = MO->Contents.Reg.Prev; |
275 | 137M | |
276 | 137M | // Prev links are circular, next link is NULL instead of looping back to Head. |
277 | 137M | if (MO == Head) |
278 | 57.2M | HeadRef = Next; |
279 | 137M | else |
280 | 80.3M | Prev->Contents.Reg.Next = Next; |
281 | 137M | |
282 | 137M | (Next ? Next96.2M : Head41.3M )->Contents.Reg.Prev = Prev; |
283 | 137M | |
284 | 137M | MO->Contents.Reg.Prev = nullptr; |
285 | 137M | MO->Contents.Reg.Next = nullptr; |
286 | 137M | } |
287 | | |
288 | | /// Move NumOps operands from Src to Dst, updating use-def lists as needed. |
289 | | /// |
290 | | /// The Dst range is assumed to be uninitialized memory. (Or it may contain |
291 | | /// operands that won't be destroyed, which is OK because the MO destructor is |
292 | | /// trivial anyway). |
293 | | /// |
294 | | /// The Src and Dst ranges may overlap. |
295 | | void MachineRegisterInfo::moveOperands(MachineOperand *Dst, |
296 | | MachineOperand *Src, |
297 | 28.9M | unsigned NumOps) { |
298 | 28.9M | assert(Src != Dst && NumOps && "Noop moveOperands"); |
299 | 28.9M | |
300 | 28.9M | // Copy backwards if Dst is within the Src range. |
301 | 28.9M | int Stride = 1; |
302 | 28.9M | if (Dst >= Src && 28.9M Dst < Src + NumOps26.1M ) { |
303 | 4.92M | Stride = -1; |
304 | 4.92M | Dst += NumOps - 1; |
305 | 4.92M | Src += NumOps - 1; |
306 | 4.92M | } |
307 | 28.9M | |
308 | 28.9M | // Copy one operand at a time. |
309 | 51.4M | do { |
310 | 51.4M | new (Dst) MachineOperand(*Src); |
311 | 51.4M | |
312 | 51.4M | // Dst takes Src's place in the use-def chain. |
313 | 51.4M | if (Src->isReg()51.4M ) { |
314 | 45.9M | MachineOperand *&Head = getRegUseDefListHead(Src->getReg()); |
315 | 45.9M | MachineOperand *Prev = Src->Contents.Reg.Prev; |
316 | 45.9M | MachineOperand *Next = Src->Contents.Reg.Next; |
317 | 45.9M | assert(Head && "List empty, but operand is chained"); |
318 | 45.9M | assert(Prev && "Operand was not on use-def list"); |
319 | 45.9M | |
320 | 45.9M | // Prev links are circular, next link is NULL instead of looping back to |
321 | 45.9M | // Head. |
322 | 45.9M | if (Src == Head) |
323 | 16.9M | Head = Dst; |
324 | 45.9M | else |
325 | 29.0M | Prev->Contents.Reg.Next = Dst; |
326 | 45.9M | |
327 | 45.9M | // Update Prev pointer. This also works when Src was pointing to itself |
328 | 45.9M | // in a 1-element list. In that case Head == Dst. |
329 | 45.9M | (Next ? Next16.8M : Head29.0M )->Contents.Reg.Prev = Dst; |
330 | 45.9M | } |
331 | 51.4M | |
332 | 51.4M | Dst += Stride; |
333 | 51.4M | Src += Stride; |
334 | 51.4M | } while (--NumOps); |
335 | 28.9M | } |
336 | | |
337 | | /// replaceRegWith - Replace all instances of FromReg with ToReg in the |
338 | | /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), |
339 | | /// except that it also changes any definitions of the register as well. |
340 | | /// If ToReg is a physical register we apply the sub register to obtain the |
341 | | /// final/proper physical register. |
342 | 827k | void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { |
343 | 827k | assert(FromReg != ToReg && "Cannot replace a reg with itself"); |
344 | 827k | |
345 | 827k | const TargetRegisterInfo *TRI = getTargetRegisterInfo(); |
346 | 827k | |
347 | 827k | // TODO: This could be more efficient by bulk changing the operands. |
348 | 2.72M | for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E2.72M ; ) { |
349 | 1.90M | MachineOperand &O = *I; |
350 | 1.90M | ++I; |
351 | 1.90M | if (TargetRegisterInfo::isPhysicalRegister(ToReg)1.90M ) { |
352 | 35.1k | O.substPhysReg(ToReg, *TRI); |
353 | 1.90M | } else { |
354 | 1.86M | O.setReg(ToReg); |
355 | 1.86M | } |
356 | 1.90M | } |
357 | 827k | } |
358 | | |
359 | | /// getVRegDef - Return the machine instr that defines the specified virtual |
360 | | /// register or null if none is found. This assumes that the code is in SSA |
361 | | /// form, so there should only be one definition. |
362 | 122M | MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { |
363 | 122M | // Since we are in SSA form, we can use the first definition. |
364 | 122M | def_instr_iterator I = def_instr_begin(Reg); |
365 | 122M | assert((I.atEnd() || std::next(I) == def_instr_end()) && |
366 | 122M | "getVRegDef assumes a single definition or no definition"); |
367 | 122M | return !I.atEnd() ? &*I122M : nullptr21.4k ; |
368 | 122M | } |
369 | | |
370 | | /// getUniqueVRegDef - Return the unique machine instr that defines the |
371 | | /// specified virtual register or null if none is found. If there are |
372 | | /// multiple definitions or no definition, return null. |
373 | 3.96M | MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { |
374 | 3.96M | if (def_empty(Reg)3.96M ) return nullptr1.08k ; |
375 | 3.96M | def_instr_iterator I = def_instr_begin(Reg); |
376 | 3.96M | if (std::next(I) != def_instr_end()) |
377 | 2 | return nullptr; |
378 | 3.96M | return &*I; |
379 | 3.96M | } |
380 | | |
381 | 27.6M | bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { |
382 | 27.6M | use_nodbg_iterator UI = use_nodbg_begin(RegNo); |
383 | 27.6M | if (UI == use_nodbg_end()) |
384 | 7.75k | return false; |
385 | 27.6M | return ++UI == use_nodbg_end(); |
386 | 27.6M | } |
387 | | |
388 | | /// clearKillFlags - Iterate over all the uses of the given register and |
389 | | /// clear the kill flag from the MachineOperand. This function is used by |
390 | | /// optimization passes which extend register lifetimes and need only |
391 | | /// preserve conservative kill flag information. |
392 | 15.8M | void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { |
393 | 15.8M | for (MachineOperand &MO : use_operands(Reg)) |
394 | 32.9M | MO.setIsKill(false); |
395 | 15.8M | } |
396 | | |
397 | 2.05M | bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { |
398 | 5.60M | for (livein_iterator I = livein_begin(), E = livein_end(); I != E5.60M ; ++I3.54M ) |
399 | 3.55M | if (3.55M I->first == Reg || 3.55M I->second == Reg3.54M ) |
400 | 5.05k | return true; |
401 | 2.04M | return false; |
402 | 2.05M | } |
403 | | |
404 | | /// getLiveInPhysReg - If VReg is a live-in virtual register, return the |
405 | | /// corresponding live-in physical register. |
406 | 194 | unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { |
407 | 301 | for (livein_iterator I = livein_begin(), E = livein_end(); I != E301 ; ++I107 ) |
408 | 294 | if (294 I->second == VReg294 ) |
409 | 187 | return I->first; |
410 | 7 | return 0; |
411 | 194 | } |
412 | | |
413 | | /// getLiveInVirtReg - If PReg is a live-in physical register, return the |
414 | | /// corresponding live-in physical register. |
415 | 955k | unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { |
416 | 2.29M | for (livein_iterator I = livein_begin(), E = livein_end(); I != E2.29M ; ++I1.33M ) |
417 | 1.37M | if (1.37M I->first == PReg1.37M ) |
418 | 35.4k | return I->second; |
419 | 919k | return 0; |
420 | 955k | } |
421 | | |
422 | | /// EmitLiveInCopies - Emit copies to initialize livein virtual registers |
423 | | /// into the given entry block. |
424 | | void |
425 | | MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, |
426 | | const TargetRegisterInfo &TRI, |
427 | 436k | const TargetInstrInfo &TII) { |
428 | 436k | // Emit the copies into the top of the block. |
429 | 1.39M | for (unsigned i = 0, e = LiveIns.size(); i != e1.39M ; ++i958k ) |
430 | 958k | if (958k LiveIns[i].second958k ) { |
431 | 958k | if (use_empty(LiveIns[i].second)958k ) { |
432 | 92.6k | // The livein has no uses. Drop it. |
433 | 92.6k | // |
434 | 92.6k | // It would be preferable to have isel avoid creating live-in |
435 | 92.6k | // records for unused arguments in the first place, but it's |
436 | 92.6k | // complicated by the debug info code for arguments. |
437 | 92.6k | LiveIns.erase(LiveIns.begin() + i); |
438 | 92.6k | --i; --e; |
439 | 958k | } else { |
440 | 866k | // Emit a copy. |
441 | 866k | BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), |
442 | 866k | TII.get(TargetOpcode::COPY), LiveIns[i].second) |
443 | 866k | .addReg(LiveIns[i].first); |
444 | 866k | |
445 | 866k | // Add the register to the entry block live-in set. |
446 | 866k | EntryMBB->addLiveIn(LiveIns[i].first); |
447 | 866k | } |
448 | 958k | } else { |
449 | 3 | // Add the register to the entry block live-in set. |
450 | 3 | EntryMBB->addLiveIn(LiveIns[i].first); |
451 | 3 | } |
452 | 436k | } |
453 | | |
454 | 10.9M | LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const { |
455 | 10.9M | // Lane masks are only defined for vregs. |
456 | 10.9M | assert(TargetRegisterInfo::isVirtualRegister(Reg)); |
457 | 10.9M | const TargetRegisterClass &TRC = *getRegClass(Reg); |
458 | 10.9M | return TRC.getLaneMask(); |
459 | 10.9M | } |
460 | | |
461 | | #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) |
462 | | LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(unsigned Reg) const { |
463 | | for (MachineInstr &I : use_instructions(Reg)) |
464 | | I.dump(); |
465 | | } |
466 | | #endif |
467 | | |
468 | 1.19M | void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { |
469 | 1.19M | ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF); |
470 | 1.19M | assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() && |
471 | 1.19M | "Invalid ReservedRegs vector from target"); |
472 | 1.19M | } |
473 | | |
474 | 14.7M | bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const { |
475 | 14.7M | assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); |
476 | 14.7M | |
477 | 14.7M | const TargetRegisterInfo *TRI = getTargetRegisterInfo(); |
478 | 14.7M | if (TRI->isConstantPhysReg(PhysReg)) |
479 | 3.29M | return true; |
480 | 11.4M | |
481 | 11.4M | // Check if any overlapping register is modified, or allocatable so it may be |
482 | 11.4M | // used later. |
483 | 11.4M | for (MCRegAliasIterator AI(PhysReg, TRI, true); |
484 | 13.8M | AI.isValid()13.8M ; ++AI2.39M ) |
485 | 13.2M | if (13.2M !def_empty(*AI) || 13.2M isAllocatable(*AI)6.26M ) |
486 | 10.8M | return false; |
487 | 545k | return true; |
488 | 14.7M | } |
489 | | |
490 | | /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the |
491 | | /// specified register as undefined which causes the DBG_VALUE to be |
492 | | /// deleted during LiveDebugVariables analysis. |
493 | 1.37M | void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const { |
494 | 1.37M | // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.) |
495 | 1.37M | MachineRegisterInfo::use_instr_iterator nextI; |
496 | 1.37M | for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end(); |
497 | 1.58M | I != E1.58M ; I = nextI209k ) { |
498 | 209k | nextI = std::next(I); // I is invalidated by the setReg |
499 | 209k | MachineInstr *UseMI = &*I; |
500 | 209k | if (UseMI->isDebugValue()) |
501 | 3 | UseMI->getOperand(0).setReg(0U); |
502 | 209k | } |
503 | 1.37M | } |
504 | | |
505 | 196k | static const Function *getCalledFunction(const MachineInstr &MI) { |
506 | 331k | for (const MachineOperand &MO : MI.operands()) { |
507 | 331k | if (!MO.isGlobal()) |
508 | 157k | continue; |
509 | 173k | const Function *Func = dyn_cast<Function>(MO.getGlobal()); |
510 | 173k | if (Func != nullptr) |
511 | 173k | return Func; |
512 | 22.6k | } |
513 | 22.6k | return nullptr; |
514 | 22.6k | } |
515 | | |
516 | 1.59M | static bool isNoReturnDef(const MachineOperand &MO) { |
517 | 1.59M | // Anything which is not a noreturn function is a real def. |
518 | 1.59M | const MachineInstr &MI = *MO.getParent(); |
519 | 1.59M | if (!MI.isCall()) |
520 | 1.26M | return false; |
521 | 325k | const MachineBasicBlock &MBB = *MI.getParent(); |
522 | 325k | if (!MBB.succ_empty()) |
523 | 107k | return false; |
524 | 217k | const MachineFunction &MF = *MBB.getParent(); |
525 | 217k | // We need to keep correct unwind information even if the function will |
526 | 217k | // not return, since the runtime may need it. |
527 | 217k | if (MF.getFunction()->hasFnAttribute(Attribute::UWTable)) |
528 | 21.3k | return false; |
529 | 196k | const Function *Called = getCalledFunction(MI); |
530 | 173k | return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) || |
531 | 218 | !Called->hasFnAttribute(Attribute::NoUnwind)); |
532 | 1.59M | } |
533 | | |
534 | | bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg, |
535 | 13.1M | bool SkipNoReturnDef) const { |
536 | 13.1M | if (UsedPhysRegMask.test(PhysReg)) |
537 | 2.28k | return true; |
538 | 13.1M | const TargetRegisterInfo *TRI = getTargetRegisterInfo(); |
539 | 169M | for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid()169M ; ++AI156M ) { |
540 | 1.59M | for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) { |
541 | 1.59M | if (!SkipNoReturnDef && 1.59M isNoReturnDef(MO)1.59M ) |
542 | 26 | continue; |
543 | 1.59M | return true; |
544 | 1.59M | } |
545 | 157M | } |
546 | 11.5M | return false; |
547 | 13.1M | } |
548 | | |
549 | 5.98M | bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const { |
550 | 5.98M | if (UsedPhysRegMask.test(PhysReg)) |
551 | 27.3k | return true; |
552 | 5.95M | const TargetRegisterInfo *TRI = getTargetRegisterInfo(); |
553 | 149M | for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid(); |
554 | 143M | ++AliasReg143M ) { |
555 | 143M | if (!reg_nodbg_empty(*AliasReg)) |
556 | 94.2k | return true; |
557 | 143M | } |
558 | 5.85M | return false; |
559 | 5.98M | } |
560 | | |
561 | 579 | void MachineRegisterInfo::disableCalleeSavedRegister(unsigned Reg) { |
562 | 579 | |
563 | 579 | const TargetRegisterInfo *TRI = getTargetRegisterInfo(); |
564 | 579 | assert(Reg && (Reg < TRI->getNumRegs()) && |
565 | 579 | "Trying to disable an invalid register"); |
566 | 579 | |
567 | 579 | if (!IsUpdatedCSRsInitialized579 ) { |
568 | 132 | const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); |
569 | 1.98k | for (const MCPhysReg *I = CSR; *I1.98k ; ++I1.85k ) |
570 | 1.85k | UpdatedCSRs.push_back(*I); |
571 | 132 | |
572 | 132 | // Zero value represents the end of the register list |
573 | 132 | // (no more registers should be pushed). |
574 | 132 | UpdatedCSRs.push_back(0); |
575 | 132 | |
576 | 132 | IsUpdatedCSRsInitialized = true; |
577 | 132 | } |
578 | 579 | |
579 | 579 | // Remove the register (and its aliases from the list). |
580 | 3.37k | for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid()3.37k ; ++AI2.79k ) |
581 | 2.79k | UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI), |
582 | 2.79k | UpdatedCSRs.end()); |
583 | 579 | } |
584 | | |
585 | 5.52M | const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const { |
586 | 5.52M | if (IsUpdatedCSRsInitialized) |
587 | 1.26k | return UpdatedCSRs.data(); |
588 | 5.52M | |
589 | 5.52M | return getTargetRegisterInfo()->getCalleeSavedRegs(MF); |
590 | 5.52M | } |
591 | | |
592 | 17 | void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) { |
593 | 17 | if (IsUpdatedCSRsInitialized) |
594 | 0 | UpdatedCSRs.clear(); |
595 | 17 | |
596 | 17 | for (MCPhysReg Reg : CSRs) |
597 | 737 | UpdatedCSRs.push_back(Reg); |
598 | 17 | |
599 | 17 | // Zero value represents the end of the register list |
600 | 17 | // (no more registers should be pushed). |
601 | 17 | UpdatedCSRs.push_back(0); |
602 | 17 | IsUpdatedCSRsInitialized = true; |
603 | 17 | } |
604 | | |
605 | 2.20M | bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const { |
606 | 2.20M | const TargetRegisterInfo *TRI = getTargetRegisterInfo(); |
607 | 3.88M | for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid()3.88M ; ++Root1.68M ) { |
608 | 2.20M | bool IsRootReserved = true; |
609 | 2.20M | for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true); |
610 | 4.61M | Super.isValid()4.61M ; ++Super2.40M ) { |
611 | 4.08M | unsigned Reg = *Super; |
612 | 4.08M | if (!isReserved(Reg)4.08M ) { |
613 | 1.68M | IsRootReserved = false; |
614 | 1.68M | break; |
615 | 1.68M | } |
616 | 4.08M | } |
617 | 2.20M | if (IsRootReserved) |
618 | 524k | return true; |
619 | 2.20M | } |
620 | 1.68M | return false; |
621 | 2.20M | } |