/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
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1 | | //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | // \file |
9 | | //===----------------------------------------------------------------------===// |
10 | | |
11 | | #include "AMDGPUInstPrinter.h" |
12 | | #include "MCTargetDesc/AMDGPUMCTargetDesc.h" |
13 | | #include "SIDefines.h" |
14 | | #include "Utils/AMDGPUAsmUtils.h" |
15 | | #include "Utils/AMDGPUBaseInfo.h" |
16 | | #include "llvm/MC/MCExpr.h" |
17 | | #include "llvm/MC/MCInst.h" |
18 | | #include "llvm/MC/MCInstrDesc.h" |
19 | | #include "llvm/MC/MCInstrInfo.h" |
20 | | #include "llvm/MC/MCRegisterInfo.h" |
21 | | #include "llvm/MC/MCSubtargetInfo.h" |
22 | | #include "llvm/Support/ErrorHandling.h" |
23 | | #include "llvm/Support/MathExtras.h" |
24 | | #include "llvm/Support/raw_ostream.h" |
25 | | #include <cassert> |
26 | | |
27 | | using namespace llvm; |
28 | | using namespace llvm::AMDGPU; |
29 | | |
30 | | void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, |
31 | 563k | StringRef Annot, const MCSubtargetInfo &STI) { |
32 | 563k | OS.flush(); |
33 | 563k | printInstruction(MI, STI, OS); |
34 | 563k | printAnnotation(OS, Annot); |
35 | 563k | } |
36 | | |
37 | | void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo, |
38 | | const MCSubtargetInfo &STI, |
39 | 22.7k | raw_ostream &O) { |
40 | 22.7k | O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); |
41 | 22.7k | } |
42 | | |
43 | | void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, |
44 | 0 | raw_ostream &O) { |
45 | 0 | O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); |
46 | 0 | } |
47 | | |
48 | | void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, |
49 | | const MCSubtargetInfo &STI, |
50 | 5.50k | raw_ostream &O) { |
51 | 5.50k | // It's possible to end up with a 32-bit literal used with a 16-bit operand |
52 | 5.50k | // with ignored high bits. Print as 32-bit anyway in that case. |
53 | 5.50k | int64_t Imm = MI->getOperand(OpNo).getImm(); |
54 | 5.50k | if (isInt<16>(Imm) || 5.50k isUInt<16>(Imm)109 ) |
55 | 5.50k | O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); |
56 | 5.50k | else |
57 | 4 | printU32ImmOperand(MI, OpNo, STI, O); |
58 | 5.50k | } |
59 | | |
60 | | void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, |
61 | 2.77k | raw_ostream &O) { |
62 | 2.77k | O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); |
63 | 2.77k | } |
64 | | |
65 | | void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, |
66 | 5.34k | raw_ostream &O) { |
67 | 5.34k | O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); |
68 | 5.34k | } |
69 | | |
70 | | void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, |
71 | 27.7k | raw_ostream &O) { |
72 | 27.7k | O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); |
73 | 27.7k | } |
74 | | |
75 | | void AMDGPUInstPrinter::printS16ImmDecOperand(const MCInst *MI, unsigned OpNo, |
76 | 272 | raw_ostream &O) { |
77 | 272 | O << formatDec(static_cast<int16_t>(MI->getOperand(OpNo).getImm())); |
78 | 272 | } |
79 | | |
80 | | void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo, |
81 | | const MCSubtargetInfo &STI, |
82 | 29.6k | raw_ostream &O) { |
83 | 29.6k | O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); |
84 | 29.6k | } |
85 | | |
86 | | void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo, |
87 | 197k | raw_ostream &O, StringRef BitName) { |
88 | 197k | if (MI->getOperand(OpNo).getImm()197k ) { |
89 | 6.05k | O << ' ' << BitName; |
90 | 6.05k | } |
91 | 197k | } |
92 | | |
93 | | void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo, |
94 | 0 | raw_ostream &O) { |
95 | 0 | printNamedBit(MI, OpNo, O, "offen"); |
96 | 0 | } |
97 | | |
98 | | void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo, |
99 | 0 | raw_ostream &O) { |
100 | 0 | printNamedBit(MI, OpNo, O, "idxen"); |
101 | 0 | } |
102 | | |
103 | | void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo, |
104 | 0 | raw_ostream &O) { |
105 | 0 | printNamedBit(MI, OpNo, O, "addr64"); |
106 | 0 | } |
107 | | |
108 | | void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo, |
109 | 0 | raw_ostream &O) { |
110 | 0 | if (MI->getOperand(OpNo).getImm()0 ) { |
111 | 0 | O << " offset:"; |
112 | 0 | printU16ImmDecOperand(MI, OpNo, O); |
113 | 0 | } |
114 | 0 | } |
115 | | |
116 | | void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo, |
117 | | const MCSubtargetInfo &STI, |
118 | 56.5k | raw_ostream &O) { |
119 | 56.5k | uint16_t Imm = MI->getOperand(OpNo).getImm(); |
120 | 56.5k | if (Imm != 056.5k ) { |
121 | 27.6k | O << ((OpNo == 0)? "offset:"38 : " offset:"27.6k ); |
122 | 27.6k | printU16ImmDecOperand(MI, OpNo, O); |
123 | 27.6k | } |
124 | 56.5k | } |
125 | | |
126 | | void AMDGPUInstPrinter::printOffsetS13(const MCInst *MI, unsigned OpNo, |
127 | | const MCSubtargetInfo &STI, |
128 | 1.85k | raw_ostream &O) { |
129 | 1.85k | uint16_t Imm = MI->getOperand(OpNo).getImm(); |
130 | 1.85k | if (Imm != 01.85k ) { |
131 | 272 | O << ((OpNo == 0)? "offset:"0 : " offset:"272 ); |
132 | 272 | printS16ImmDecOperand(MI, OpNo, O); |
133 | 272 | } |
134 | 1.85k | } |
135 | | |
136 | | void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo, |
137 | | const MCSubtargetInfo &STI, |
138 | 3.06k | raw_ostream &O) { |
139 | 3.06k | if (MI->getOperand(OpNo).getImm()3.06k ) { |
140 | 2.28k | O << " offset0:"; |
141 | 2.28k | printU8ImmDecOperand(MI, OpNo, O); |
142 | 2.28k | } |
143 | 3.06k | } |
144 | | |
145 | | void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo, |
146 | | const MCSubtargetInfo &STI, |
147 | 3.06k | raw_ostream &O) { |
148 | 3.06k | if (MI->getOperand(OpNo).getImm()3.06k ) { |
149 | 2.85k | O << " offset1:"; |
150 | 2.85k | printU8ImmDecOperand(MI, OpNo, O); |
151 | 2.85k | } |
152 | 3.06k | } |
153 | | |
154 | | void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo, |
155 | | const MCSubtargetInfo &STI, |
156 | 14.7k | raw_ostream &O) { |
157 | 14.7k | printU32ImmOperand(MI, OpNo, STI, O); |
158 | 14.7k | } |
159 | | |
160 | | void AMDGPUInstPrinter::printSMRDOffset20(const MCInst *MI, unsigned OpNo, |
161 | | const MCSubtargetInfo &STI, |
162 | 14.7k | raw_ostream &O) { |
163 | 14.7k | printU32ImmOperand(MI, OpNo, STI, O); |
164 | 14.7k | } |
165 | | |
166 | | void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo, |
167 | | const MCSubtargetInfo &STI, |
168 | 39 | raw_ostream &O) { |
169 | 39 | printU32ImmOperand(MI, OpNo, STI, O); |
170 | 39 | } |
171 | | |
172 | | void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo, |
173 | 10.9k | const MCSubtargetInfo &STI, raw_ostream &O) { |
174 | 10.9k | printNamedBit(MI, OpNo, O, "gds"); |
175 | 10.9k | } |
176 | | |
177 | | void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo, |
178 | 80.3k | const MCSubtargetInfo &STI, raw_ostream &O) { |
179 | 80.3k | printNamedBit(MI, OpNo, O, "glc"); |
180 | 80.3k | } |
181 | | |
182 | | void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo, |
183 | 53.6k | const MCSubtargetInfo &STI, raw_ostream &O) { |
184 | 53.6k | printNamedBit(MI, OpNo, O, "slc"); |
185 | 53.6k | } |
186 | | |
187 | | void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo, |
188 | 39.9k | const MCSubtargetInfo &STI, raw_ostream &O) { |
189 | 39.9k | printNamedBit(MI, OpNo, O, "tfe"); |
190 | 39.9k | } |
191 | | |
192 | | void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo, |
193 | 3.11k | const MCSubtargetInfo &STI, raw_ostream &O) { |
194 | 3.11k | if (MI->getOperand(OpNo).getImm()3.11k ) { |
195 | 3.00k | O << " dmask:"; |
196 | 3.00k | printU16ImmOperand(MI, OpNo, STI, O); |
197 | 3.00k | } |
198 | 3.11k | } |
199 | | |
200 | | void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo, |
201 | 3.11k | const MCSubtargetInfo &STI, raw_ostream &O) { |
202 | 3.11k | printNamedBit(MI, OpNo, O, "unorm"); |
203 | 3.11k | } |
204 | | |
205 | | void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo, |
206 | 3.11k | const MCSubtargetInfo &STI, raw_ostream &O) { |
207 | 3.11k | printNamedBit(MI, OpNo, O, "da"); |
208 | 3.11k | } |
209 | | |
210 | | void AMDGPUInstPrinter::printR128(const MCInst *MI, unsigned OpNo, |
211 | 3.11k | const MCSubtargetInfo &STI, raw_ostream &O) { |
212 | 3.11k | printNamedBit(MI, OpNo, O, "r128"); |
213 | 3.11k | } |
214 | | |
215 | | void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo, |
216 | 3.11k | const MCSubtargetInfo &STI, raw_ostream &O) { |
217 | 3.11k | printNamedBit(MI, OpNo, O, "lwe"); |
218 | 3.11k | } |
219 | | |
220 | | void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo, |
221 | | const MCSubtargetInfo &STI, |
222 | 615 | raw_ostream &O) { |
223 | 615 | if (MI->getOperand(OpNo).getImm()) |
224 | 109 | O << " compr"; |
225 | 615 | } |
226 | | |
227 | | void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo, |
228 | | const MCSubtargetInfo &STI, |
229 | 615 | raw_ostream &O) { |
230 | 615 | if (MI->getOperand(OpNo).getImm()) |
231 | 113 | O << " vm"; |
232 | 615 | } |
233 | | |
234 | | void AMDGPUInstPrinter::printDFMT(const MCInst *MI, unsigned OpNo, |
235 | | const MCSubtargetInfo &STI, |
236 | 102 | raw_ostream &O) { |
237 | 102 | if (MI->getOperand(OpNo).getImm()102 ) { |
238 | 102 | O << " dfmt:"; |
239 | 102 | printU8ImmDecOperand(MI, OpNo, O); |
240 | 102 | } |
241 | 102 | } |
242 | | |
243 | | void AMDGPUInstPrinter::printNFMT(const MCInst *MI, unsigned OpNo, |
244 | | const MCSubtargetInfo &STI, |
245 | 102 | raw_ostream &O) { |
246 | 102 | if (MI->getOperand(OpNo).getImm()102 ) { |
247 | 102 | O << " nfmt:"; |
248 | 102 | printU8ImmDecOperand(MI, OpNo, O); |
249 | 102 | } |
250 | 102 | } |
251 | | |
252 | | void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O, |
253 | 982k | const MCRegisterInfo &MRI) { |
254 | 982k | switch (RegNo) { |
255 | 6.38k | case AMDGPU::VCC: |
256 | 6.38k | O << "vcc"; |
257 | 6.38k | return; |
258 | 0 | case AMDGPU::SCC: |
259 | 0 | O << "scc"; |
260 | 0 | return; |
261 | 3.83k | case AMDGPU::EXEC: |
262 | 3.83k | O << "exec"; |
263 | 3.83k | return; |
264 | 7.51k | case AMDGPU::M0: |
265 | 7.51k | O << "m0"; |
266 | 7.51k | return; |
267 | 0 | case AMDGPU::FLAT_SCR: |
268 | 0 | O << "flat_scratch"; |
269 | 0 | return; |
270 | 5.38k | case AMDGPU::VCC_LO: |
271 | 5.38k | O << "vcc_lo"; |
272 | 5.38k | return; |
273 | 5.38k | case AMDGPU::VCC_HI: |
274 | 5.38k | O << "vcc_hi"; |
275 | 5.38k | return; |
276 | 2.85k | case AMDGPU::TBA_LO: |
277 | 2.85k | O << "tba_lo"; |
278 | 2.85k | return; |
279 | 2.85k | case AMDGPU::TBA_HI: |
280 | 2.85k | O << "tba_hi"; |
281 | 2.85k | return; |
282 | 2.86k | case AMDGPU::TMA_LO: |
283 | 2.86k | O << "tma_lo"; |
284 | 2.86k | return; |
285 | 2.86k | case AMDGPU::TMA_HI: |
286 | 2.86k | O << "tma_hi"; |
287 | 2.86k | return; |
288 | 5.24k | case AMDGPU::EXEC_LO: |
289 | 5.24k | O << "exec_lo"; |
290 | 5.24k | return; |
291 | 5.24k | case AMDGPU::EXEC_HI: |
292 | 5.24k | O << "exec_hi"; |
293 | 5.24k | return; |
294 | 0 | case AMDGPU::FLAT_SCR_LO: |
295 | 0 | O << "flat_scratch_lo"; |
296 | 0 | return; |
297 | 0 | case AMDGPU::FLAT_SCR_HI: |
298 | 0 | O << "flat_scratch_hi"; |
299 | 0 | return; |
300 | 0 | case AMDGPU::FP_REG: |
301 | 0 | case AMDGPU::SP_REG: |
302 | 0 | case AMDGPU::SCRATCH_WAVE_OFFSET_REG: |
303 | 0 | case AMDGPU::PRIVATE_RSRC_REG: |
304 | 0 | llvm_unreachable("pseudo-register should not ever be emitted"); |
305 | 932k | default: |
306 | 932k | break; |
307 | 932k | } |
308 | 932k | |
309 | 932k | // The low 8 bits of the encoding value is the register index, for both VGPRs |
310 | 932k | // and SGPRs. |
311 | 932k | unsigned RegIdx = MRI.getEncodingValue(RegNo) & ((1 << 8) - 1); |
312 | 932k | |
313 | 932k | unsigned NumRegs; |
314 | 932k | if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(RegNo)932k ) { |
315 | 473k | O << 'v'; |
316 | 473k | NumRegs = 1; |
317 | 932k | } else if (458k MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(RegNo)458k ) { |
318 | 175k | O << 's'; |
319 | 175k | NumRegs = 1; |
320 | 458k | } else if (282k MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(RegNo)282k ) { |
321 | 76.6k | O <<'v'; |
322 | 76.6k | NumRegs = 2; |
323 | 282k | } else if (206k MRI.getRegClass(AMDGPU::SGPR_64RegClassID).contains(RegNo)206k ) { |
324 | 120k | O << 's'; |
325 | 120k | NumRegs = 2; |
326 | 206k | } else if (85.4k MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(RegNo)85.4k ) { |
327 | 12.3k | O << 'v'; |
328 | 12.3k | NumRegs = 4; |
329 | 85.4k | } else if (73.1k MRI.getRegClass(AMDGPU::SGPR_128RegClassID).contains(RegNo)73.1k ) { |
330 | 44.6k | O << 's'; |
331 | 44.6k | NumRegs = 4; |
332 | 73.1k | } else if (28.4k MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(RegNo)28.4k ) { |
333 | 939 | O << 'v'; |
334 | 939 | NumRegs = 3; |
335 | 28.4k | } else if (27.4k MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(RegNo)27.4k ) { |
336 | 52 | O << 'v'; |
337 | 52 | NumRegs = 8; |
338 | 27.4k | } else if (27.4k MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(RegNo)27.4k ) { |
339 | 3.55k | O << 's'; |
340 | 3.55k | NumRegs = 8; |
341 | 27.4k | } else if (23.8k MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(RegNo)23.8k ) { |
342 | 6 | O << 'v'; |
343 | 6 | NumRegs = 16; |
344 | 23.8k | } else if (23.8k MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(RegNo)23.8k ) { |
345 | 347 | O << 's'; |
346 | 347 | NumRegs = 16; |
347 | 23.8k | } else if (23.5k MRI.getRegClass(AMDGPU::TTMP_64RegClassID).contains(RegNo)23.5k ) { |
348 | 1.85k | O << "ttmp"; |
349 | 1.85k | NumRegs = 2; |
350 | 1.85k | // Trap temps start at offset 112. TODO: Get this from tablegen. |
351 | 1.85k | RegIdx -= 112; |
352 | 23.5k | } else if (21.6k MRI.getRegClass(AMDGPU::TTMP_128RegClassID).contains(RegNo)21.6k ) { |
353 | 432 | O << "ttmp"; |
354 | 432 | NumRegs = 4; |
355 | 432 | // Trap temps start at offset 112. TODO: Get this from tablegen. |
356 | 432 | RegIdx -= 112; |
357 | 21.6k | } else { |
358 | 21.2k | O << getRegisterName(RegNo); |
359 | 21.2k | return; |
360 | 21.2k | } |
361 | 911k | |
362 | 911k | if (911k NumRegs == 1911k ) { |
363 | 649k | O << RegIdx; |
364 | 649k | return; |
365 | 649k | } |
366 | 261k | |
367 | 261k | O << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']'; |
368 | 261k | } |
369 | | |
370 | | void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo, |
371 | 191k | const MCSubtargetInfo &STI, raw_ostream &O) { |
372 | 191k | if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3) |
373 | 62.0k | O << "_e64 "; |
374 | 129k | else if (129k MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP129k ) |
375 | 11.3k | O << "_dpp "; |
376 | 118k | else if (118k MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA118k ) |
377 | 17.5k | O << "_sdwa "; |
378 | 118k | else |
379 | 100k | O << "_e32 "; |
380 | 191k | |
381 | 191k | printOperand(MI, OpNo, STI, O); |
382 | 191k | } |
383 | | |
384 | | void AMDGPUInstPrinter::printImmediate16(uint32_t Imm, |
385 | | const MCSubtargetInfo &STI, |
386 | 8.35k | raw_ostream &O) { |
387 | 8.35k | int16_t SImm = static_cast<int16_t>(Imm); |
388 | 8.35k | if (SImm >= -16 && 8.35k SImm <= 646.54k ) { |
389 | 4.55k | O << SImm; |
390 | 4.55k | return; |
391 | 4.55k | } |
392 | 3.79k | |
393 | 3.79k | if (3.79k Imm == 0x3C003.79k ) |
394 | 50 | O<< "1.0"; |
395 | 3.74k | else if (3.74k Imm == 0xBC003.74k ) |
396 | 14 | O<< "-1.0"; |
397 | 3.73k | else if (3.73k Imm == 0x38003.73k ) |
398 | 1.35k | O<< "0.5"; |
399 | 2.37k | else if (2.37k Imm == 0xB8002.37k ) |
400 | 9 | O<< "-0.5"; |
401 | 2.36k | else if (2.36k Imm == 0x40002.36k ) |
402 | 90 | O<< "2.0"; |
403 | 2.27k | else if (2.27k Imm == 0xC0002.27k ) |
404 | 34 | O<< "-2.0"; |
405 | 2.24k | else if (2.24k Imm == 0x44002.24k ) |
406 | 27 | O<< "4.0"; |
407 | 2.21k | else if (2.21k Imm == 0xC4002.21k ) |
408 | 1.32k | O<< "-4.0"; |
409 | 892 | else if (892 Imm == 0x3118892 ) { |
410 | 13 | assert(STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]); |
411 | 13 | O << "0.15915494"; |
412 | 13 | } else |
413 | 879 | O << formatHex(static_cast<uint64_t>(Imm)); |
414 | 8.35k | } |
415 | | |
416 | | void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm, |
417 | | const MCSubtargetInfo &STI, |
418 | 228 | raw_ostream &O) { |
419 | 228 | uint16_t Lo16 = static_cast<uint16_t>(Imm); |
420 | 228 | printImmediate16(Lo16, STI, O); |
421 | 228 | } |
422 | | |
423 | | void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, |
424 | | const MCSubtargetInfo &STI, |
425 | 119k | raw_ostream &O) { |
426 | 119k | int32_t SImm = static_cast<int32_t>(Imm); |
427 | 119k | if (SImm >= -16 && 119k SImm <= 64114k ) { |
428 | 90.5k | O << SImm; |
429 | 90.5k | return; |
430 | 90.5k | } |
431 | 29.4k | |
432 | 29.4k | if (29.4k Imm == FloatToBits(0.0f)29.4k ) |
433 | 0 | O << "0.0"; |
434 | 29.4k | else if (29.4k Imm == FloatToBits(1.0f)29.4k ) |
435 | 704 | O << "1.0"; |
436 | 28.7k | else if (28.7k Imm == FloatToBits(-1.0f)28.7k ) |
437 | 111 | O << "-1.0"; |
438 | 28.6k | else if (28.6k Imm == FloatToBits(0.5f)28.6k ) |
439 | 3.66k | O << "0.5"; |
440 | 24.9k | else if (24.9k Imm == FloatToBits(-0.5f)24.9k ) |
441 | 21 | O << "-0.5"; |
442 | 24.9k | else if (24.9k Imm == FloatToBits(2.0f)24.9k ) |
443 | 288 | O << "2.0"; |
444 | 24.6k | else if (24.6k Imm == FloatToBits(-2.0f)24.6k ) |
445 | 71 | O << "-2.0"; |
446 | 24.5k | else if (24.5k Imm == FloatToBits(4.0f)24.5k ) |
447 | 272 | O << "4.0"; |
448 | 24.3k | else if (24.3k Imm == FloatToBits(-4.0f)24.3k ) |
449 | 3.51k | O << "-4.0"; |
450 | 20.8k | else if (20.8k Imm == 0x3e22f983 && |
451 | 89 | STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) |
452 | 57 | O << "0.15915494"; |
453 | 20.8k | else |
454 | 20.7k | O << formatHex(static_cast<uint64_t>(Imm)); |
455 | 119k | } |
456 | | |
457 | | void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, |
458 | | const MCSubtargetInfo &STI, |
459 | 8.91k | raw_ostream &O) { |
460 | 8.91k | int64_t SImm = static_cast<int64_t>(Imm); |
461 | 8.91k | if (SImm >= -16 && 8.91k SImm <= 647.23k ) { |
462 | 3.82k | O << SImm; |
463 | 3.82k | return; |
464 | 3.82k | } |
465 | 5.09k | |
466 | 5.09k | if (5.09k Imm == DoubleToBits(0.0)5.09k ) |
467 | 0 | O << "0.0"; |
468 | 5.09k | else if (5.09k Imm == DoubleToBits(1.0)5.09k ) |
469 | 152 | O << "1.0"; |
470 | 4.94k | else if (4.94k Imm == DoubleToBits(-1.0)4.94k ) |
471 | 33 | O << "-1.0"; |
472 | 4.90k | else if (4.90k Imm == DoubleToBits(0.5)4.90k ) |
473 | 1.66k | O << "0.5"; |
474 | 3.24k | else if (3.24k Imm == DoubleToBits(-0.5)3.24k ) |
475 | 4 | O << "-0.5"; |
476 | 3.24k | else if (3.24k Imm == DoubleToBits(2.0)3.24k ) |
477 | 44 | O << "2.0"; |
478 | 3.19k | else if (3.19k Imm == DoubleToBits(-2.0)3.19k ) |
479 | 4 | O << "-2.0"; |
480 | 3.19k | else if (3.19k Imm == DoubleToBits(4.0)3.19k ) |
481 | 35 | O << "4.0"; |
482 | 3.15k | else if (3.15k Imm == DoubleToBits(-4.0)3.15k ) |
483 | 1.63k | O << "-4.0"; |
484 | 1.51k | else if (1.51k Imm == 0x3fc45f306dc9c882 && |
485 | 15 | STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) |
486 | 15 | O << "0.15915494"; |
487 | 1.50k | else { |
488 | 1.50k | assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882); |
489 | 1.50k | |
490 | 1.50k | // In rare situations, we will have a 32-bit literal in a 64-bit |
491 | 1.50k | // operand. This is technically allowed for the encoding of s_mov_b64. |
492 | 1.50k | O << formatHex(static_cast<uint64_t>(Imm)); |
493 | 1.50k | } |
494 | 8.91k | } |
495 | | |
496 | | void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, |
497 | | const MCSubtargetInfo &STI, |
498 | 1.33M | raw_ostream &O) { |
499 | 1.33M | if (!STI.getFeatureBits()[AMDGPU::FeatureGCN]1.33M ) { |
500 | 212k | static_cast<R600InstPrinter*>(this)->printOperand(MI, OpNo, O); |
501 | 212k | return; |
502 | 212k | } |
503 | 1.12M | |
504 | 1.12M | if (1.12M OpNo >= MI->getNumOperands()1.12M ) { |
505 | 0 | O << "/*Missing OP" << OpNo << "*/"; |
506 | 0 | return; |
507 | 0 | } |
508 | 1.12M | |
509 | 1.12M | const MCOperand &Op = MI->getOperand(OpNo); |
510 | 1.12M | if (Op.isReg()1.12M ) { |
511 | 980k | printRegOperand(Op.getReg(), O, MRI); |
512 | 1.12M | } else if (140k Op.isImm()140k ) { |
513 | 137k | const MCInstrDesc &Desc = MII.get(MI->getOpcode()); |
514 | 137k | switch (Desc.OpInfo[OpNo].OperandType) { |
515 | 119k | case AMDGPU::OPERAND_REG_IMM_INT32: |
516 | 119k | case AMDGPU::OPERAND_REG_IMM_FP32: |
517 | 119k | case AMDGPU::OPERAND_REG_INLINE_C_INT32: |
518 | 119k | case AMDGPU::OPERAND_REG_INLINE_C_FP32: |
519 | 119k | case MCOI::OPERAND_IMMEDIATE: |
520 | 119k | printImmediate32(Op.getImm(), STI, O); |
521 | 119k | break; |
522 | 8.91k | case AMDGPU::OPERAND_REG_IMM_INT64: |
523 | 8.91k | case AMDGPU::OPERAND_REG_IMM_FP64: |
524 | 8.91k | case AMDGPU::OPERAND_REG_INLINE_C_INT64: |
525 | 8.91k | case AMDGPU::OPERAND_REG_INLINE_C_FP64: |
526 | 8.91k | printImmediate64(Op.getImm(), STI, O); |
527 | 8.91k | break; |
528 | 8.12k | case AMDGPU::OPERAND_REG_INLINE_C_INT16: |
529 | 8.12k | case AMDGPU::OPERAND_REG_INLINE_C_FP16: |
530 | 8.12k | case AMDGPU::OPERAND_REG_IMM_INT16: |
531 | 8.12k | case AMDGPU::OPERAND_REG_IMM_FP16: |
532 | 8.12k | printImmediate16(Op.getImm(), STI, O); |
533 | 8.12k | break; |
534 | 228 | case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: |
535 | 228 | case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: |
536 | 228 | printImmediateV216(Op.getImm(), STI, O); |
537 | 228 | break; |
538 | 152 | case MCOI::OPERAND_UNKNOWN: |
539 | 152 | case MCOI::OPERAND_PCREL: |
540 | 152 | O << formatDec(Op.getImm()); |
541 | 152 | break; |
542 | 0 | case MCOI::OPERAND_REGISTER: |
543 | 0 | // FIXME: This should be removed and handled somewhere else. Seems to come |
544 | 0 | // from a disassembler bug. |
545 | 0 | O << "/*invalid immediate*/"; |
546 | 0 | break; |
547 | 0 | default: |
548 | 0 | // We hit this for the immediate instruction bits that don't yet have a |
549 | 0 | // custom printer. |
550 | 0 | llvm_unreachable("unexpected immediate operand type"); |
551 | 140k | } |
552 | 2.68k | } else if (2.68k Op.isFPImm()2.68k ) { |
553 | 0 | // We special case 0.0 because otherwise it will be printed as an integer. |
554 | 0 | if (Op.getFPImm() == 0.0) |
555 | 0 | O << "0.0"; |
556 | 0 | else { |
557 | 0 | const MCInstrDesc &Desc = MII.get(MI->getOpcode()); |
558 | 0 | int RCID = Desc.OpInfo[OpNo].RegClass; |
559 | 0 | unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); |
560 | 0 | if (RCBits == 32) |
561 | 0 | printImmediate32(FloatToBits(Op.getFPImm()), STI, O); |
562 | 0 | else if (0 RCBits == 640 ) |
563 | 0 | printImmediate64(DoubleToBits(Op.getFPImm()), STI, O); |
564 | 0 | else |
565 | 0 | llvm_unreachable("Invalid register class size"); |
566 | 0 | } |
567 | 2.68k | } else if (2.68k Op.isExpr()2.68k ) { |
568 | 2.68k | const MCExpr *Exp = Op.getExpr(); |
569 | 2.68k | Exp->print(O, &MAI); |
570 | 2.68k | } else { |
571 | 0 | O << "/*INV_OP*/"; |
572 | 0 | } |
573 | 1.33M | } |
574 | | |
575 | | void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI, |
576 | | unsigned OpNo, |
577 | | const MCSubtargetInfo &STI, |
578 | 115k | raw_ostream &O) { |
579 | 115k | unsigned InputModifiers = MI->getOperand(OpNo).getImm(); |
580 | 115k | |
581 | 115k | // Use 'neg(...)' instead of '-' to avoid ambiguity. |
582 | 115k | // This is important for integer literals because |
583 | 115k | // -1 is not the same value as neg(1). |
584 | 115k | bool NegMnemo = false; |
585 | 115k | |
586 | 115k | if (InputModifiers & SISrcMods::NEG115k ) { |
587 | 6.04k | if (OpNo + 1 < MI->getNumOperands() && |
588 | 6.04k | (InputModifiers & SISrcMods::ABS) == 06.04k ) { |
589 | 5.79k | const MCOperand &Op = MI->getOperand(OpNo + 1); |
590 | 5.78k | NegMnemo = Op.isImm() || Op.isFPImm(); |
591 | 5.79k | } |
592 | 6.04k | if (NegMnemo6.04k ) { |
593 | 10 | O << "neg("; |
594 | 6.04k | } else { |
595 | 6.03k | O << '-'; |
596 | 6.03k | } |
597 | 6.04k | } |
598 | 115k | |
599 | 115k | if (InputModifiers & SISrcMods::ABS) |
600 | 3.15k | O << '|'; |
601 | 115k | printOperand(MI, OpNo + 1, STI, O); |
602 | 115k | if (InputModifiers & SISrcMods::ABS) |
603 | 3.15k | O << '|'; |
604 | 115k | |
605 | 115k | if (NegMnemo115k ) { |
606 | 10 | O << ')'; |
607 | 10 | } |
608 | 115k | } |
609 | | |
610 | | void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI, |
611 | | unsigned OpNo, |
612 | | const MCSubtargetInfo &STI, |
613 | 21.6k | raw_ostream &O) { |
614 | 21.6k | unsigned InputModifiers = MI->getOperand(OpNo).getImm(); |
615 | 21.6k | if (InputModifiers & SISrcMods::SEXT) |
616 | 1.00k | O << "sext("; |
617 | 21.6k | printOperand(MI, OpNo + 1, STI, O); |
618 | 21.6k | if (InputModifiers & SISrcMods::SEXT) |
619 | 1.00k | O << ')'; |
620 | 21.6k | } |
621 | | |
622 | | void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo, |
623 | | const MCSubtargetInfo &STI, |
624 | 11.3k | raw_ostream &O) { |
625 | 11.3k | unsigned Imm = MI->getOperand(OpNo).getImm(); |
626 | 11.3k | if (Imm <= 0x0ff11.3k ) { |
627 | 5.43k | O << " quad_perm:["; |
628 | 5.43k | O << formatDec(Imm & 0x3) << ','; |
629 | 5.43k | O << formatDec((Imm & 0xc) >> 2) << ','; |
630 | 5.43k | O << formatDec((Imm & 0x30) >> 4) << ','; |
631 | 5.43k | O << formatDec((Imm & 0xc0) >> 6) << ']'; |
632 | 11.3k | } else if (5.92k (Imm >= 0x101) && 5.92k (Imm <= 0x10f)5.92k ) { |
633 | 1.21k | O << " row_shl:"; |
634 | 1.21k | printU4ImmDecOperand(MI, OpNo, O); |
635 | 5.92k | } else if (4.71k (Imm >= 0x111) && 4.71k (Imm <= 0x11f)4.71k ) { |
636 | 785 | O << " row_shr:"; |
637 | 785 | printU4ImmDecOperand(MI, OpNo, O); |
638 | 4.71k | } else if (3.92k (Imm >= 0x121) && 3.92k (Imm <= 0x12f)3.92k ) { |
639 | 781 | O << " row_ror:"; |
640 | 781 | printU4ImmDecOperand(MI, OpNo, O); |
641 | 3.92k | } else if (3.14k Imm == 0x1303.14k ) { |
642 | 394 | O << " wave_shl:1"; |
643 | 3.14k | } else if (2.75k Imm == 0x1342.75k ) { |
644 | 394 | O << " wave_rol:1"; |
645 | 2.75k | } else if (2.35k Imm == 0x1382.35k ) { |
646 | 394 | O << " wave_shr:1"; |
647 | 2.35k | } else if (1.96k Imm == 0x13c1.96k ) { |
648 | 394 | O << " wave_ror:1"; |
649 | 1.96k | } else if (1.57k Imm == 0x1401.57k ) { |
650 | 392 | O << " row_mirror"; |
651 | 1.57k | } else if (1.17k Imm == 0x1411.17k ) { |
652 | 392 | O << " row_half_mirror"; |
653 | 1.17k | } else if (786 Imm == 0x142786 ) { |
654 | 394 | O << " row_bcast:15"; |
655 | 786 | } else if (392 Imm == 0x143392 ) { |
656 | 392 | O << " row_bcast:31"; |
657 | 392 | } else { |
658 | 0 | llvm_unreachable("Invalid dpp_ctrl value"); |
659 | 5.92k | } |
660 | 11.3k | } |
661 | | |
662 | | void AMDGPUInstPrinter::printRowMask(const MCInst *MI, unsigned OpNo, |
663 | | const MCSubtargetInfo &STI, |
664 | 11.3k | raw_ostream &O) { |
665 | 11.3k | O << " row_mask:"; |
666 | 11.3k | printU4ImmOperand(MI, OpNo, STI, O); |
667 | 11.3k | } |
668 | | |
669 | | void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo, |
670 | | const MCSubtargetInfo &STI, |
671 | 11.3k | raw_ostream &O) { |
672 | 11.3k | O << " bank_mask:"; |
673 | 11.3k | printU4ImmOperand(MI, OpNo, STI, O); |
674 | 11.3k | } |
675 | | |
676 | | void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo, |
677 | | const MCSubtargetInfo &STI, |
678 | 11.3k | raw_ostream &O) { |
679 | 11.3k | unsigned Imm = MI->getOperand(OpNo).getImm(); |
680 | 11.3k | if (Imm11.3k ) { |
681 | 854 | O << " bound_ctrl:0"; // XXX - this syntax is used in sp3 |
682 | 854 | } |
683 | 11.3k | } |
684 | | |
685 | | void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo, |
686 | 52.3k | raw_ostream &O) { |
687 | 52.3k | using namespace llvm::AMDGPU::SDWA; |
688 | 52.3k | |
689 | 52.3k | unsigned Imm = MI->getOperand(OpNo).getImm(); |
690 | 52.3k | switch (Imm) { |
691 | 1.92k | case SdwaSel::BYTE_0: O << "BYTE_0"; break; |
692 | 1.79k | case SdwaSel::BYTE_1: O << "BYTE_1"; break; |
693 | 2.17k | case SdwaSel::BYTE_2: O << "BYTE_2"; break; |
694 | 1.76k | case SdwaSel::BYTE_3: O << "BYTE_3"; break; |
695 | 2.22k | case SdwaSel::WORD_0: O << "WORD_0"; break; |
696 | 2.91k | case SdwaSel::WORD_1: O << "WORD_1"; break; |
697 | 39.5k | case SdwaSel::DWORD: O << "DWORD"; break; |
698 | 0 | default: 0 llvm_unreachable0 ("Invalid SDWA data select operand"); |
699 | 52.3k | } |
700 | 52.3k | } |
701 | | |
702 | | void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo, |
703 | | const MCSubtargetInfo &STI, |
704 | 13.1k | raw_ostream &O) { |
705 | 13.1k | O << "dst_sel:"; |
706 | 13.1k | printSDWASel(MI, OpNo, O); |
707 | 13.1k | } |
708 | | |
709 | | void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo, |
710 | | const MCSubtargetInfo &STI, |
711 | 22.7k | raw_ostream &O) { |
712 | 22.7k | O << "src0_sel:"; |
713 | 22.7k | printSDWASel(MI, OpNo, O); |
714 | 22.7k | } |
715 | | |
716 | | void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo, |
717 | | const MCSubtargetInfo &STI, |
718 | 16.4k | raw_ostream &O) { |
719 | 16.4k | O << "src1_sel:"; |
720 | 16.4k | printSDWASel(MI, OpNo, O); |
721 | 16.4k | } |
722 | | |
723 | | void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo, |
724 | | const MCSubtargetInfo &STI, |
725 | 13.1k | raw_ostream &O) { |
726 | 13.1k | using namespace llvm::AMDGPU::SDWA; |
727 | 13.1k | |
728 | 13.1k | O << "dst_unused:"; |
729 | 13.1k | unsigned Imm = MI->getOperand(OpNo).getImm(); |
730 | 13.1k | switch (Imm) { |
731 | 12.0k | case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break; |
732 | 401 | case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break; |
733 | 646 | case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break; |
734 | 0 | default: 0 llvm_unreachable0 ("Invalid SDWA dest_unused operand"); |
735 | 13.1k | } |
736 | 13.1k | } |
737 | | |
738 | | template <unsigned N> |
739 | | void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo, |
740 | | const MCSubtargetInfo &STI, |
741 | 2.46k | raw_ostream &O) { |
742 | 2.46k | unsigned Opc = MI->getOpcode(); |
743 | 2.46k | int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); |
744 | 2.46k | unsigned En = MI->getOperand(EnIdx).getImm(); |
745 | 2.46k | |
746 | 2.46k | int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); |
747 | 2.46k | |
748 | 2.46k | // If compr is set, print as src0, src0, src1, src1 |
749 | 2.46k | if (MI->getOperand(ComprIdx).getImm()2.46k ) { |
750 | 436 | if (N == 1 || 436 N == 20 ) |
751 | 218 | --OpNo; |
752 | 218 | else if (218 N == 3218 ) |
753 | 109 | OpNo -= 2; |
754 | 436 | } |
755 | 2.46k | |
756 | 2.46k | if (En & (1 << N)) |
757 | 1.99k | printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI); |
758 | 2.46k | else |
759 | 465 | O << "off"; |
760 | 2.46k | } void llvm::AMDGPUInstPrinter::printExpSrcN<0u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) Line | Count | Source | 741 | 615 | raw_ostream &O) { | 742 | 615 | unsigned Opc = MI->getOpcode(); | 743 | 615 | int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); | 744 | 615 | unsigned En = MI->getOperand(EnIdx).getImm(); | 745 | 615 | | 746 | 615 | int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); | 747 | 615 | | 748 | 615 | // If compr is set, print as src0, src0, src1, src1 | 749 | 615 | if (MI->getOperand(ComprIdx).getImm()615 ) { | 750 | 109 | if (N == 1 || 109 N == 20 ) | 751 | 0 | --OpNo; | 752 | 109 | else if (109 N == 3109 ) | 753 | 0 | OpNo -= 2; | 754 | 109 | } | 755 | 615 | | 756 | 615 | if (En & (1 << N)) | 757 | 509 | printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI); | 758 | 615 | else | 759 | 106 | O << "off"; | 760 | 615 | } |
void llvm::AMDGPUInstPrinter::printExpSrcN<1u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) Line | Count | Source | 741 | 615 | raw_ostream &O) { | 742 | 615 | unsigned Opc = MI->getOpcode(); | 743 | 615 | int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); | 744 | 615 | unsigned En = MI->getOperand(EnIdx).getImm(); | 745 | 615 | | 746 | 615 | int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); | 747 | 615 | | 748 | 615 | // If compr is set, print as src0, src0, src1, src1 | 749 | 615 | if (MI->getOperand(ComprIdx).getImm()615 ) { | 750 | 109 | if (N == 1 || 109 N == 20 ) | 751 | 109 | --OpNo; | 752 | 0 | else if (0 N == 30 ) | 753 | 0 | OpNo -= 2; | 754 | 109 | } | 755 | 615 | | 756 | 615 | if (En & (1 << N)) | 757 | 491 | printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI); | 758 | 615 | else | 759 | 124 | O << "off"; | 760 | 615 | } |
void llvm::AMDGPUInstPrinter::printExpSrcN<2u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) Line | Count | Source | 741 | 615 | raw_ostream &O) { | 742 | 615 | unsigned Opc = MI->getOpcode(); | 743 | 615 | int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); | 744 | 615 | unsigned En = MI->getOperand(EnIdx).getImm(); | 745 | 615 | | 746 | 615 | int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); | 747 | 615 | | 748 | 615 | // If compr is set, print as src0, src0, src1, src1 | 749 | 615 | if (MI->getOperand(ComprIdx).getImm()615 ) { | 750 | 109 | if (N == 1 || 109 N == 20 ) | 751 | 109 | --OpNo; | 752 | 0 | else if (0 N == 30 ) | 753 | 0 | OpNo -= 2; | 754 | 109 | } | 755 | 615 | | 756 | 615 | if (En & (1 << N)) | 757 | 493 | printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI); | 758 | 615 | else | 759 | 122 | O << "off"; | 760 | 615 | } |
void llvm::AMDGPUInstPrinter::printExpSrcN<3u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) Line | Count | Source | 741 | 615 | raw_ostream &O) { | 742 | 615 | unsigned Opc = MI->getOpcode(); | 743 | 615 | int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); | 744 | 615 | unsigned En = MI->getOperand(EnIdx).getImm(); | 745 | 615 | | 746 | 615 | int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); | 747 | 615 | | 748 | 615 | // If compr is set, print as src0, src0, src1, src1 | 749 | 615 | if (MI->getOperand(ComprIdx).getImm()615 ) { | 750 | 109 | if (N == 1 || 109 N == 20 ) | 751 | 0 | --OpNo; | 752 | 109 | else if (109 N == 3109 ) | 753 | 109 | OpNo -= 2; | 754 | 109 | } | 755 | 615 | | 756 | 615 | if (En & (1 << N)) | 757 | 502 | printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI); | 758 | 615 | else | 759 | 113 | O << "off"; | 760 | 615 | } |
|
761 | | |
762 | | void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo, |
763 | | const MCSubtargetInfo &STI, |
764 | 615 | raw_ostream &O) { |
765 | 615 | printExpSrcN<0>(MI, OpNo, STI, O); |
766 | 615 | } |
767 | | |
768 | | void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo, |
769 | | const MCSubtargetInfo &STI, |
770 | 615 | raw_ostream &O) { |
771 | 615 | printExpSrcN<1>(MI, OpNo, STI, O); |
772 | 615 | } |
773 | | |
774 | | void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo, |
775 | | const MCSubtargetInfo &STI, |
776 | 615 | raw_ostream &O) { |
777 | 615 | printExpSrcN<2>(MI, OpNo, STI, O); |
778 | 615 | } |
779 | | |
780 | | void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo, |
781 | | const MCSubtargetInfo &STI, |
782 | 615 | raw_ostream &O) { |
783 | 615 | printExpSrcN<3>(MI, OpNo, STI, O); |
784 | 615 | } |
785 | | |
786 | | void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo, |
787 | | const MCSubtargetInfo &STI, |
788 | 615 | raw_ostream &O) { |
789 | 615 | // This is really a 6 bit field. |
790 | 615 | uint32_t Tgt = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1); |
791 | 615 | |
792 | 615 | if (Tgt <= 7) |
793 | 361 | O << " mrt" << Tgt; |
794 | 254 | else if (254 Tgt == 8254 ) |
795 | 36 | O << " mrtz"; |
796 | 218 | else if (218 Tgt == 9218 ) |
797 | 21 | O << " null"; |
798 | 197 | else if (197 Tgt >= 12 && 197 Tgt <= 15181 ) |
799 | 47 | O << " pos" << Tgt - 12; |
800 | 150 | else if (150 Tgt >= 32 && 150 Tgt <= 63134 ) |
801 | 134 | O << " param" << Tgt - 32; |
802 | 16 | else { |
803 | 16 | // Reserved values 10, 11 |
804 | 16 | O << " invalid_target_" << Tgt; |
805 | 16 | } |
806 | 615 | } |
807 | | |
808 | | static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod, |
809 | 7.93k | bool HasDstSel) { |
810 | 7.93k | int DefaultValue = (Mod == SISrcMods::OP_SEL_1); |
811 | 7.93k | |
812 | 25.2k | for (int I = 0; I < NumOps25.2k ; ++I17.2k ) { |
813 | 17.8k | if (!!(Ops[I] & Mod) != DefaultValue) |
814 | 528 | return false; |
815 | 17.8k | } |
816 | 7.93k | |
817 | 7.40k | if (7.40k HasDstSel && 7.40k (Ops[0] & SISrcMods::DST_OP_SEL) != 01.50k ) |
818 | 38 | return false; |
819 | 7.36k | |
820 | 7.36k | return true; |
821 | 7.36k | } |
822 | | |
823 | | void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI, |
824 | | StringRef Name, |
825 | | unsigned Mod, |
826 | 7.93k | raw_ostream &O) { |
827 | 7.93k | unsigned Opc = MI->getOpcode(); |
828 | 7.93k | int NumOps = 0; |
829 | 7.93k | int Ops[3]; |
830 | 7.93k | |
831 | 7.93k | for (int OpName : { AMDGPU::OpName::src0_modifiers, |
832 | 7.93k | AMDGPU::OpName::src1_modifiers, |
833 | 23.7k | AMDGPU::OpName::src2_modifiers }) { |
834 | 23.7k | int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName); |
835 | 23.7k | if (Idx == -1) |
836 | 5.48k | break; |
837 | 18.3k | |
838 | 18.3k | Ops[NumOps++] = MI->getOperand(Idx).getImm(); |
839 | 18.3k | } |
840 | 7.93k | |
841 | 7.93k | const bool HasDstSel = |
842 | 7.93k | NumOps > 0 && |
843 | 7.93k | Mod == SISrcMods::OP_SEL_0 && |
844 | 3.26k | MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL; |
845 | 7.93k | |
846 | 7.93k | if (allOpsDefaultValue(Ops, NumOps, Mod, HasDstSel)) |
847 | 7.36k | return; |
848 | 566 | |
849 | 566 | O << Name; |
850 | 1.97k | for (int I = 0; I < NumOps1.97k ; ++I1.40k ) { |
851 | 1.40k | if (I != 0) |
852 | 840 | O << ','; |
853 | 1.40k | |
854 | 1.40k | O << !!(Ops[I] & Mod); |
855 | 1.40k | } |
856 | 566 | |
857 | 566 | if (HasDstSel566 ) { |
858 | 170 | O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL); |
859 | 170 | } |
860 | 7.93k | |
861 | 7.93k | O << ']'; |
862 | 7.93k | } |
863 | | |
864 | | void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned, |
865 | | const MCSubtargetInfo &STI, |
866 | 3.26k | raw_ostream &O) { |
867 | 3.26k | printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O); |
868 | 3.26k | } |
869 | | |
870 | | void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo, |
871 | | const MCSubtargetInfo &STI, |
872 | 1.62k | raw_ostream &O) { |
873 | 1.62k | printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O); |
874 | 1.62k | } |
875 | | |
876 | | void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo, |
877 | | const MCSubtargetInfo &STI, |
878 | 1.52k | raw_ostream &O) { |
879 | 1.52k | printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O); |
880 | 1.52k | } |
881 | | |
882 | | void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo, |
883 | | const MCSubtargetInfo &STI, |
884 | 1.52k | raw_ostream &O) { |
885 | 1.52k | printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O); |
886 | 1.52k | } |
887 | | |
888 | | void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum, |
889 | | const MCSubtargetInfo &STI, |
890 | 155 | raw_ostream &O) { |
891 | 155 | unsigned Imm = MI->getOperand(OpNum).getImm(); |
892 | 155 | switch (Imm) { |
893 | 90 | case 0: |
894 | 90 | O << "p10"; |
895 | 90 | break; |
896 | 14 | case 1: |
897 | 14 | O << "p20"; |
898 | 14 | break; |
899 | 33 | case 2: |
900 | 33 | O << "p0"; |
901 | 33 | break; |
902 | 18 | default: |
903 | 18 | O << "invalid_param_" << Imm; |
904 | 155 | } |
905 | 155 | } |
906 | | |
907 | | void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum, |
908 | | const MCSubtargetInfo &STI, |
909 | 762 | raw_ostream &O) { |
910 | 762 | unsigned Attr = MI->getOperand(OpNum).getImm(); |
911 | 762 | O << "attr" << Attr; |
912 | 762 | } |
913 | | |
914 | | void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum, |
915 | | const MCSubtargetInfo &STI, |
916 | 762 | raw_ostream &O) { |
917 | 762 | unsigned Chan = MI->getOperand(OpNum).getImm(); |
918 | 762 | O << '.' << "xyzw"[Chan & 0x3]; |
919 | 762 | } |
920 | | |
921 | | void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo, |
922 | | const MCSubtargetInfo &STI, |
923 | 105 | raw_ostream &O) { |
924 | 105 | unsigned Val = MI->getOperand(OpNo).getImm(); |
925 | 105 | if (Val == 0105 ) { |
926 | 35 | O << " 0"; |
927 | 35 | return; |
928 | 35 | } |
929 | 70 | |
930 | 70 | if (70 Val & VGPRIndexMode::DST_ENABLE70 ) |
931 | 36 | O << " dst"; |
932 | 70 | |
933 | 70 | if (Val & VGPRIndexMode::SRC0_ENABLE) |
934 | 40 | O << " src0"; |
935 | 70 | |
936 | 70 | if (Val & VGPRIndexMode::SRC1_ENABLE) |
937 | 7 | O << " src1"; |
938 | 70 | |
939 | 70 | if (Val & VGPRIndexMode::SRC2_ENABLE) |
940 | 6 | O << " src2"; |
941 | 105 | } |
942 | | |
943 | | void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, |
944 | | const MCSubtargetInfo &STI, |
945 | 1.48k | raw_ostream &O) { |
946 | 1.48k | if (!STI.getFeatureBits()[AMDGPU::FeatureGCN]1.48k ) { |
947 | 1.48k | static_cast<R600InstPrinter*>(this)->printMemOperand(MI, OpNo, O); |
948 | 1.48k | return; |
949 | 1.48k | } |
950 | 0 |
|
951 | 0 | printOperand(MI, OpNo, STI, O); |
952 | 0 | O << ", "; |
953 | 0 | printOperand(MI, OpNo + 1, STI, O); |
954 | 0 | } |
955 | | |
956 | | void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo, |
957 | | raw_ostream &O, StringRef Asm, |
958 | 150k | StringRef Default) { |
959 | 150k | const MCOperand &Op = MI->getOperand(OpNo); |
960 | 150k | assert(Op.isImm()); |
961 | 150k | if (Op.getImm() == 1150k ) { |
962 | 25.0k | O << Asm; |
963 | 150k | } else { |
964 | 125k | O << Default; |
965 | 125k | } |
966 | 150k | } |
967 | | |
968 | | void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo, |
969 | 358k | raw_ostream &O, char Asm) { |
970 | 358k | const MCOperand &Op = MI->getOperand(OpNo); |
971 | 358k | assert(Op.isImm()); |
972 | 358k | if (Op.getImm() == 1) |
973 | 604 | O << Asm; |
974 | 358k | } |
975 | | |
976 | | void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo, |
977 | 132k | const MCSubtargetInfo &STI, raw_ostream &O) { |
978 | 132k | static_cast<R600InstPrinter*>(this)->printAbs(MI, OpNo, O); |
979 | 132k | } |
980 | | |
981 | | void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo, |
982 | 44.7k | const MCSubtargetInfo &STI, raw_ostream &O) { |
983 | 44.7k | static_cast<R600InstPrinter*>(this)->printClamp(MI, OpNo, O); |
984 | 44.7k | } |
985 | | |
986 | | void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo, |
987 | | const MCSubtargetInfo &STI, |
988 | 77 | raw_ostream &O) { |
989 | 77 | if (MI->getOperand(OpNo).getImm()) |
990 | 9 | O << " high"; |
991 | 77 | } |
992 | | |
993 | | void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo, |
994 | | const MCSubtargetInfo &STI, |
995 | 68.5k | raw_ostream &O) { |
996 | 68.5k | if (MI->getOperand(OpNo).getImm()) |
997 | 1.87k | O << " clamp"; |
998 | 68.5k | } |
999 | | |
1000 | | void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo, |
1001 | | const MCSubtargetInfo &STI, |
1002 | 23.3k | raw_ostream &O) { |
1003 | 23.3k | int Imm = MI->getOperand(OpNo).getImm(); |
1004 | 23.3k | if (Imm == SIOutMods::MUL2) |
1005 | 454 | O << " mul:2"; |
1006 | 22.8k | else if (22.8k Imm == SIOutMods::MUL422.8k ) |
1007 | 456 | O << " mul:4"; |
1008 | 22.4k | else if (22.4k Imm == SIOutMods::DIV222.4k ) |
1009 | 449 | O << " div:2"; |
1010 | 23.3k | } |
1011 | | |
1012 | | void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo, |
1013 | | const MCSubtargetInfo &STI, |
1014 | 26.1k | raw_ostream &O) { |
1015 | 26.1k | static_cast<R600InstPrinter*>(this)->printLiteral(MI, OpNo, O); |
1016 | 26.1k | } |
1017 | | |
1018 | | void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo, |
1019 | 48.0k | const MCSubtargetInfo &STI, raw_ostream &O) { |
1020 | 48.0k | static_cast<R600InstPrinter*>(this)->printLast(MI, OpNo, O); |
1021 | 48.0k | } |
1022 | | |
1023 | | void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo, |
1024 | 87.6k | const MCSubtargetInfo &STI, raw_ostream &O) { |
1025 | 87.6k | static_cast<R600InstPrinter*>(this)->printNeg(MI, OpNo, O); |
1026 | 87.6k | } |
1027 | | |
1028 | | void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo, |
1029 | 37.5k | const MCSubtargetInfo &STI, raw_ostream &O) { |
1030 | 37.5k | static_cast<R600InstPrinter*>(this)->printOMOD(MI, OpNo, O); |
1031 | 37.5k | } |
1032 | | |
1033 | | void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo, |
1034 | 138k | const MCSubtargetInfo &STI, raw_ostream &O) { |
1035 | 138k | static_cast<R600InstPrinter*>(this)->printRel(MI, OpNo, O); |
1036 | 138k | } |
1037 | | |
1038 | | void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo, |
1039 | | const MCSubtargetInfo &STI, |
1040 | 28.6k | raw_ostream &O) { |
1041 | 28.6k | static_cast<R600InstPrinter*>(this)->printUpdateExecMask(MI, OpNo, O); |
1042 | 28.6k | } |
1043 | | |
1044 | | void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo, |
1045 | | const MCSubtargetInfo &STI, |
1046 | 28.6k | raw_ostream &O) { |
1047 | 28.6k | static_cast<R600InstPrinter*>(this)->printUpdatePred(MI, OpNo, O); |
1048 | 28.6k | } |
1049 | | |
1050 | | void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo, |
1051 | 37.5k | const MCSubtargetInfo &STI, raw_ostream &O) { |
1052 | 37.5k | static_cast<R600InstPrinter*>(this)->printWrite(MI, OpNo, O); |
1053 | 37.5k | } |
1054 | | |
1055 | | void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo, |
1056 | | const MCSubtargetInfo &STI, |
1057 | 44.7k | raw_ostream &O) { |
1058 | 44.7k | static_cast<R600InstPrinter*>(this)->printBankSwizzle(MI, OpNo, O); |
1059 | 44.7k | } |
1060 | | |
1061 | | void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo, |
1062 | 2.44k | const MCSubtargetInfo &STI, raw_ostream &O) { |
1063 | 2.44k | static_cast<R600InstPrinter*>(this)->printRSel(MI, OpNo, O); |
1064 | 2.44k | } |
1065 | | |
1066 | | void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo, |
1067 | 1.10k | const MCSubtargetInfo &STI, raw_ostream &O) { |
1068 | 1.10k | static_cast<R600InstPrinter*>(this)->printCT(MI, OpNo, O); |
1069 | 1.10k | } |
1070 | | |
1071 | | void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo, |
1072 | 7.00k | const MCSubtargetInfo &STI, raw_ostream &O) { |
1073 | 7.00k | static_cast<R600InstPrinter*>(this)->printKCache(MI, OpNo, O); |
1074 | 7.00k | } |
1075 | | |
1076 | | void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo, |
1077 | | const MCSubtargetInfo &STI, |
1078 | 120 | raw_ostream &O) { |
1079 | 120 | using namespace llvm::AMDGPU::SendMsg; |
1080 | 120 | |
1081 | 120 | const unsigned SImm16 = MI->getOperand(OpNo).getImm(); |
1082 | 120 | const unsigned Id = SImm16 & ID_MASK_; |
1083 | 120 | do { |
1084 | 120 | if (Id == ID_INTERRUPT120 ) { |
1085 | 28 | if ((SImm16 & ~ID_MASK_) != 0) // Unused/unknown bits must be 0. |
1086 | 12 | break; |
1087 | 16 | O << "sendmsg(" << IdSymbolic[Id] << ')'; |
1088 | 16 | return; |
1089 | 16 | } |
1090 | 92 | if (92 Id == ID_GS || 92 Id == ID_GS_DONE42 ) { |
1091 | 70 | if ((SImm16 & ~(ID_MASK_|OP_GS_MASK_|STREAM_ID_MASK_)) != 0) // Unused/unknown bits must be 0. |
1092 | 0 | break; |
1093 | 70 | const unsigned OpGs = (SImm16 & OP_GS_MASK_) >> OP_SHIFT_; |
1094 | 70 | const unsigned StreamId = (SImm16 & STREAM_ID_MASK_) >> STREAM_ID_SHIFT_; |
1095 | 70 | if (OpGs == OP_GS_NOP && 70 Id != ID_GS_DONE24 ) // NOP to be used for GS_DONE only. |
1096 | 4 | break; |
1097 | 66 | if (66 OpGs == OP_GS_NOP && 66 StreamId != 020 ) // NOP does not use/define stream id bits. |
1098 | 0 | break; |
1099 | 66 | O << "sendmsg(" << IdSymbolic[Id] << ", " << OpGsSymbolic[OpGs]; |
1100 | 66 | if (OpGs != OP_GS_NOP66 ) { O << ", " << StreamId; }46 |
1101 | 70 | O << ')'; |
1102 | 70 | return; |
1103 | 70 | } |
1104 | 22 | if (22 Id == ID_SYSMSG22 ) { |
1105 | 15 | if ((SImm16 & ~(ID_MASK_|OP_SYS_MASK_)) != 0) // Unused/unknown bits must be 0. |
1106 | 0 | break; |
1107 | 15 | const unsigned OpSys = (SImm16 & OP_SYS_MASK_) >> OP_SHIFT_; |
1108 | 15 | if (! (OP_SYS_FIRST_ <= OpSys && 15 OpSys < OP_SYS_LAST_15 )) // Unused/unknown. |
1109 | 5 | break; |
1110 | 10 | O << "sendmsg(" << IdSymbolic[Id] << ", " << OpSysSymbolic[OpSys] << ')'; |
1111 | 10 | return; |
1112 | 10 | } |
1113 | 7 | } while (false); |
1114 | 28 | O << SImm16; // Unknown simm16 code. |
1115 | 28 | } |
1116 | | |
1117 | | static void printSwizzleBitmask(const uint16_t AndMask, |
1118 | | const uint16_t OrMask, |
1119 | | const uint16_t XorMask, |
1120 | 54 | raw_ostream &O) { |
1121 | 54 | using namespace llvm::AMDGPU::Swizzle; |
1122 | 54 | |
1123 | 54 | uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask; |
1124 | 54 | uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask; |
1125 | 54 | |
1126 | 54 | O << "\""; |
1127 | 54 | |
1128 | 324 | for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0324 ; Mask >>= 1270 ) { |
1129 | 270 | uint16_t p0 = Probe0 & Mask; |
1130 | 270 | uint16_t p1 = Probe1 & Mask; |
1131 | 270 | |
1132 | 270 | if (p0 == p1270 ) { |
1133 | 230 | if (p0 == 0230 ) { |
1134 | 205 | O << "0"; |
1135 | 230 | } else { |
1136 | 25 | O << "1"; |
1137 | 25 | } |
1138 | 270 | } else { |
1139 | 40 | if (p0 == 040 ) { |
1140 | 26 | O << "p"; |
1141 | 40 | } else { |
1142 | 14 | O << "i"; |
1143 | 14 | } |
1144 | 40 | } |
1145 | 270 | } |
1146 | 54 | |
1147 | 54 | O << "\""; |
1148 | 54 | } |
1149 | | |
1150 | | void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo, |
1151 | | const MCSubtargetInfo &STI, |
1152 | 264 | raw_ostream &O) { |
1153 | 264 | using namespace llvm::AMDGPU::Swizzle; |
1154 | 264 | |
1155 | 264 | uint16_t Imm = MI->getOperand(OpNo).getImm(); |
1156 | 264 | if (Imm == 0264 ) { |
1157 | 23 | return; |
1158 | 23 | } |
1159 | 241 | |
1160 | 241 | O << " offset:"; |
1161 | 241 | |
1162 | 241 | if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC241 ) { |
1163 | 14 | |
1164 | 14 | O << "swizzle(" << IdSymbolic[ID_QUAD_PERM]; |
1165 | 70 | for (auto i = 0; i < LANE_NUM70 ; ++i56 ) { |
1166 | 56 | O << ","; |
1167 | 56 | O << formatDec(Imm & LANE_MASK); |
1168 | 56 | Imm >>= LANE_SHIFT; |
1169 | 56 | } |
1170 | 14 | O << ")"; |
1171 | 14 | |
1172 | 241 | } else if (227 (Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC227 ) { |
1173 | 208 | |
1174 | 208 | uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK; |
1175 | 208 | uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK; |
1176 | 208 | uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK; |
1177 | 208 | |
1178 | 208 | if (AndMask == BITMASK_MAX && |
1179 | 77 | OrMask == 0 && |
1180 | 208 | countPopulation(XorMask) == 177 ) { |
1181 | 42 | |
1182 | 42 | O << "swizzle(" << IdSymbolic[ID_SWAP]; |
1183 | 42 | O << ","; |
1184 | 42 | O << formatDec(XorMask); |
1185 | 42 | O << ")"; |
1186 | 42 | |
1187 | 208 | } else if (166 AndMask == BITMASK_MAX && |
1188 | 166 | OrMask == 035 && XorMask > 035 && |
1189 | 166 | isPowerOf2_64(XorMask + 1)35 ) { |
1190 | 35 | |
1191 | 35 | O << "swizzle(" << IdSymbolic[ID_REVERSE]; |
1192 | 35 | O << ","; |
1193 | 35 | O << formatDec(XorMask + 1); |
1194 | 35 | O << ")"; |
1195 | 35 | |
1196 | 166 | } else { |
1197 | 131 | |
1198 | 131 | uint16_t GroupSize = BITMASK_MAX - AndMask + 1; |
1199 | 131 | if (GroupSize > 1 && |
1200 | 131 | isPowerOf2_64(GroupSize) && |
1201 | 91 | OrMask < GroupSize && |
1202 | 131 | XorMask == 091 ) { |
1203 | 77 | |
1204 | 77 | O << "swizzle(" << IdSymbolic[ID_BROADCAST]; |
1205 | 77 | O << ","; |
1206 | 77 | O << formatDec(GroupSize); |
1207 | 77 | O << ","; |
1208 | 77 | O << formatDec(OrMask); |
1209 | 77 | O << ")"; |
1210 | 77 | |
1211 | 131 | } else { |
1212 | 54 | O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM]; |
1213 | 54 | O << ","; |
1214 | 54 | printSwizzleBitmask(AndMask, OrMask, XorMask, O); |
1215 | 54 | O << ")"; |
1216 | 54 | } |
1217 | 166 | } |
1218 | 227 | } else { |
1219 | 19 | printU16ImmDecOperand(MI, OpNo, O); |
1220 | 19 | } |
1221 | 264 | } |
1222 | | |
1223 | | void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo, |
1224 | | const MCSubtargetInfo &STI, |
1225 | 36.9k | raw_ostream &O) { |
1226 | 36.9k | AMDGPU::IsaInfo::IsaVersion ISA = |
1227 | 36.9k | AMDGPU::IsaInfo::getIsaVersion(STI.getFeatureBits()); |
1228 | 36.9k | |
1229 | 36.9k | unsigned SImm16 = MI->getOperand(OpNo).getImm(); |
1230 | 36.9k | unsigned Vmcnt, Expcnt, Lgkmcnt; |
1231 | 36.9k | decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt); |
1232 | 36.9k | |
1233 | 36.9k | bool NeedSpace = false; |
1234 | 36.9k | |
1235 | 36.9k | if (Vmcnt != getVmcntBitMask(ISA)36.9k ) { |
1236 | 16.7k | O << "vmcnt(" << Vmcnt << ')'; |
1237 | 16.7k | NeedSpace = true; |
1238 | 16.7k | } |
1239 | 36.9k | |
1240 | 36.9k | if (Expcnt != getExpcntBitMask(ISA)36.9k ) { |
1241 | 5.37k | if (NeedSpace) |
1242 | 1.29k | O << ' '; |
1243 | 5.37k | O << "expcnt(" << Expcnt << ')'; |
1244 | 5.37k | NeedSpace = true; |
1245 | 5.37k | } |
1246 | 36.9k | |
1247 | 36.9k | if (Lgkmcnt != getLgkmcntBitMask(ISA)36.9k ) { |
1248 | 19.5k | if (NeedSpace) |
1249 | 3.49k | O << ' '; |
1250 | 19.5k | O << "lgkmcnt(" << Lgkmcnt << ')'; |
1251 | 19.5k | } |
1252 | 36.9k | } |
1253 | | |
1254 | | void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo, |
1255 | 236 | const MCSubtargetInfo &STI, raw_ostream &O) { |
1256 | 236 | using namespace llvm::AMDGPU::Hwreg; |
1257 | 236 | |
1258 | 236 | unsigned SImm16 = MI->getOperand(OpNo).getImm(); |
1259 | 236 | const unsigned Id = (SImm16 & ID_MASK_) >> ID_SHIFT_; |
1260 | 236 | const unsigned Offset = (SImm16 & OFFSET_MASK_) >> OFFSET_SHIFT_; |
1261 | 236 | const unsigned Width = ((SImm16 & WIDTH_M1_MASK_) >> WIDTH_M1_SHIFT_) + 1; |
1262 | 236 | |
1263 | 236 | O << "hwreg("; |
1264 | 236 | if (ID_SYMBOLIC_FIRST_ <= Id && 236 Id < ID_SYMBOLIC_LAST_236 ) { |
1265 | 206 | O << IdSymbolic[Id]; |
1266 | 236 | } else { |
1267 | 30 | O << Id; |
1268 | 30 | } |
1269 | 236 | if (Width != WIDTH_M1_DEFAULT_ + 1 || 236 Offset != OFFSET_DEFAULT_11 ) { |
1270 | 225 | O << ", " << Offset << ", " << Width; |
1271 | 225 | } |
1272 | 236 | O << ')'; |
1273 | 236 | } |
1274 | | |
1275 | | #include "AMDGPUGenAsmWriter.inc" |
1276 | | |
1277 | | void R600InstPrinter::printAbs(const MCInst *MI, unsigned OpNo, |
1278 | 132k | raw_ostream &O) { |
1279 | 132k | AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '|'); |
1280 | 132k | } |
1281 | | |
1282 | | void R600InstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo, |
1283 | 44.7k | raw_ostream &O) { |
1284 | 44.7k | int BankSwizzle = MI->getOperand(OpNo).getImm(); |
1285 | 44.7k | switch (BankSwizzle) { |
1286 | 962 | case 1: |
1287 | 962 | O << "BS:VEC_021/SCL_122"; |
1288 | 962 | break; |
1289 | 696 | case 2: |
1290 | 696 | O << "BS:VEC_120/SCL_212"; |
1291 | 696 | break; |
1292 | 115 | case 3: |
1293 | 115 | O << "BS:VEC_102/SCL_221"; |
1294 | 115 | break; |
1295 | 167 | case 4: |
1296 | 167 | O << "BS:VEC_201"; |
1297 | 167 | break; |
1298 | 30 | case 5: |
1299 | 30 | O << "BS:VEC_210"; |
1300 | 30 | break; |
1301 | 42.7k | default: |
1302 | 42.7k | break; |
1303 | 44.7k | } |
1304 | 44.7k | } |
1305 | | |
1306 | | void R600InstPrinter::printClamp(const MCInst *MI, unsigned OpNo, |
1307 | 44.7k | raw_ostream &O) { |
1308 | 44.7k | AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "_SAT"); |
1309 | 44.7k | } |
1310 | | |
1311 | | void R600InstPrinter::printCT(const MCInst *MI, unsigned OpNo, |
1312 | 1.10k | raw_ostream &O) { |
1313 | 1.10k | unsigned CT = MI->getOperand(OpNo).getImm(); |
1314 | 1.10k | switch (CT) { |
1315 | 29 | case 0: |
1316 | 29 | O << 'U'; |
1317 | 29 | break; |
1318 | 1.07k | case 1: |
1319 | 1.07k | O << 'N'; |
1320 | 1.07k | break; |
1321 | 0 | default: |
1322 | 0 | break; |
1323 | 1.10k | } |
1324 | 1.10k | } |
1325 | | |
1326 | | void R600InstPrinter::printKCache(const MCInst *MI, unsigned OpNo, |
1327 | 7.00k | raw_ostream &O) { |
1328 | 7.00k | int KCacheMode = MI->getOperand(OpNo).getImm(); |
1329 | 7.00k | if (KCacheMode > 07.00k ) { |
1330 | 3.07k | int KCacheBank = MI->getOperand(OpNo - 2).getImm(); |
1331 | 3.07k | O << "CB" << KCacheBank << ':'; |
1332 | 3.07k | int KCacheAddr = MI->getOperand(OpNo + 2).getImm(); |
1333 | 3.07k | int LineSize = (KCacheMode == 1) ? 160 : 323.07k ; |
1334 | 3.07k | O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize; |
1335 | 3.07k | } |
1336 | 7.00k | } |
1337 | | |
1338 | | void R600InstPrinter::printLast(const MCInst *MI, unsigned OpNo, |
1339 | 48.0k | raw_ostream &O) { |
1340 | 48.0k | AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "*", " "); |
1341 | 48.0k | } |
1342 | | |
1343 | | void R600InstPrinter::printLiteral(const MCInst *MI, unsigned OpNo, |
1344 | 26.1k | raw_ostream &O) { |
1345 | 26.1k | const MCOperand &Op = MI->getOperand(OpNo); |
1346 | 26.1k | assert(Op.isImm() || Op.isExpr()); |
1347 | 26.1k | if (Op.isImm()26.1k ) { |
1348 | 26.1k | int64_t Imm = Op.getImm(); |
1349 | 26.1k | O << Imm << '(' << BitsToFloat(Imm) << ')'; |
1350 | 26.1k | } |
1351 | 26.1k | if (Op.isExpr()26.1k ) { |
1352 | 13 | Op.getExpr()->print(O << '@', &MAI); |
1353 | 13 | } |
1354 | 26.1k | } |
1355 | | |
1356 | | void R600InstPrinter::printNeg(const MCInst *MI, unsigned OpNo, |
1357 | 87.6k | raw_ostream &O) { |
1358 | 87.6k | AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '-'); |
1359 | 87.6k | } |
1360 | | |
1361 | | void R600InstPrinter::printOMOD(const MCInst *MI, unsigned OpNo, |
1362 | 37.5k | raw_ostream &O) { |
1363 | 37.5k | switch (MI->getOperand(OpNo).getImm()) { |
1364 | 37.5k | default: break; |
1365 | 0 | case 1: |
1366 | 0 | O << " * 2.0"; |
1367 | 0 | break; |
1368 | 0 | case 2: |
1369 | 0 | O << " * 4.0"; |
1370 | 0 | break; |
1371 | 0 | case 3: |
1372 | 0 | O << " / 2.0"; |
1373 | 0 | break; |
1374 | 37.5k | } |
1375 | 37.5k | } |
1376 | | |
1377 | | void R600InstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, |
1378 | 1.48k | raw_ostream &O) { |
1379 | 1.48k | printOperand(MI, OpNo, O); |
1380 | 1.48k | O << ", "; |
1381 | 1.48k | printOperand(MI, OpNo + 1, O); |
1382 | 1.48k | } |
1383 | | |
1384 | | void R600InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, |
1385 | 215k | raw_ostream &O) { |
1386 | 215k | if (OpNo >= MI->getNumOperands()215k ) { |
1387 | 0 | O << "/*Missing OP" << OpNo << "*/"; |
1388 | 0 | return; |
1389 | 0 | } |
1390 | 215k | |
1391 | 215k | const MCOperand &Op = MI->getOperand(OpNo); |
1392 | 215k | if (Op.isReg()215k ) { |
1393 | 195k | switch (Op.getReg()) { |
1394 | 195k | // This is the default predicate state, so we don't need to print it. |
1395 | 47.7k | case AMDGPU::PRED_SEL_OFF: |
1396 | 47.7k | break; |
1397 | 195k | |
1398 | 148k | default: |
1399 | 148k | O << getRegisterName(Op.getReg()); |
1400 | 148k | break; |
1401 | 215k | } |
1402 | 19.6k | } else if (19.6k Op.isImm()19.6k ) { |
1403 | 19.6k | O << Op.getImm(); |
1404 | 19.6k | } else if (2 Op.isFPImm()2 ) { |
1405 | 0 | // We special case 0.0 because otherwise it will be printed as an integer. |
1406 | 0 | if (Op.getFPImm() == 0.0) |
1407 | 0 | O << "0.0"; |
1408 | 0 | else { |
1409 | 0 | O << Op.getFPImm(); |
1410 | 0 | } |
1411 | 2 | } else if (2 Op.isExpr()2 ) { |
1412 | 2 | const MCExpr *Exp = Op.getExpr(); |
1413 | 2 | Exp->print(O, &MAI); |
1414 | 2 | } else { |
1415 | 0 | O << "/*INV_OP*/"; |
1416 | 0 | } |
1417 | 215k | } |
1418 | | |
1419 | | void R600InstPrinter::printRel(const MCInst *MI, unsigned OpNo, |
1420 | 138k | raw_ostream &O) { |
1421 | 138k | AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '+'); |
1422 | 138k | } |
1423 | | |
1424 | | void R600InstPrinter::printRSel(const MCInst *MI, unsigned OpNo, |
1425 | 2.44k | raw_ostream &O) { |
1426 | 2.44k | unsigned Sel = MI->getOperand(OpNo).getImm(); |
1427 | 2.44k | switch (Sel) { |
1428 | 616 | case 0: |
1429 | 616 | O << 'X'; |
1430 | 616 | break; |
1431 | 587 | case 1: |
1432 | 587 | O << 'Y'; |
1433 | 587 | break; |
1434 | 575 | case 2: |
1435 | 575 | O << 'Z'; |
1436 | 575 | break; |
1437 | 567 | case 3: |
1438 | 567 | O << 'W'; |
1439 | 567 | break; |
1440 | 27 | case 4: |
1441 | 27 | O << '0'; |
1442 | 27 | break; |
1443 | 1 | case 5: |
1444 | 1 | O << '1'; |
1445 | 1 | break; |
1446 | 75 | case 7: |
1447 | 75 | O << '_'; |
1448 | 75 | break; |
1449 | 0 | default: |
1450 | 0 | break; |
1451 | 2.44k | } |
1452 | 2.44k | } |
1453 | | |
1454 | | void R600InstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo, |
1455 | 28.6k | raw_ostream &O) { |
1456 | 28.6k | AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "ExecMask,"); |
1457 | 28.6k | } |
1458 | | |
1459 | | void R600InstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo, |
1460 | 28.6k | raw_ostream &O) { |
1461 | 28.6k | AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "Pred,"); |
1462 | 28.6k | } |
1463 | | |
1464 | | void R600InstPrinter::printWrite(const MCInst *MI, unsigned OpNo, |
1465 | 37.5k | raw_ostream &O) { |
1466 | 37.5k | const MCOperand &Op = MI->getOperand(OpNo); |
1467 | 37.5k | if (Op.getImm() == 037.5k ) { |
1468 | 523 | O << " (MASKED)"; |
1469 | 523 | } |
1470 | 37.5k | } |