/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp
Line | Count | Source (jump to first uncovered line) |
1 | | //===-- LanaiAsmPrinter.cpp - Lanai LLVM assembly writer ------------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file contains a printer that converts from our internal representation |
11 | | // of machine-dependent LLVM code to the Lanai assembly language. |
12 | | // |
13 | | //===----------------------------------------------------------------------===// |
14 | | |
15 | | #include "InstPrinter/LanaiInstPrinter.h" |
16 | | #include "Lanai.h" |
17 | | #include "LanaiInstrInfo.h" |
18 | | #include "LanaiMCInstLower.h" |
19 | | #include "LanaiTargetMachine.h" |
20 | | #include "llvm/CodeGen/AsmPrinter.h" |
21 | | #include "llvm/CodeGen/MachineConstantPool.h" |
22 | | #include "llvm/CodeGen/MachineFunctionPass.h" |
23 | | #include "llvm/CodeGen/MachineInstr.h" |
24 | | #include "llvm/CodeGen/MachineModuleInfo.h" |
25 | | #include "llvm/IR/Constants.h" |
26 | | #include "llvm/IR/DerivedTypes.h" |
27 | | #include "llvm/IR/Mangler.h" |
28 | | #include "llvm/IR/Module.h" |
29 | | #include "llvm/MC/MCAsmInfo.h" |
30 | | #include "llvm/MC/MCInst.h" |
31 | | #include "llvm/MC/MCInstBuilder.h" |
32 | | #include "llvm/MC/MCStreamer.h" |
33 | | #include "llvm/MC/MCSymbol.h" |
34 | | #include "llvm/Support/TargetRegistry.h" |
35 | | #include "llvm/Support/raw_ostream.h" |
36 | | |
37 | | #define DEBUG_TYPE "asm-printer" |
38 | | |
39 | | using namespace llvm; |
40 | | |
41 | | namespace { |
42 | | class LanaiAsmPrinter : public AsmPrinter { |
43 | | public: |
44 | | explicit LanaiAsmPrinter(TargetMachine &TM, |
45 | | std::unique_ptr<MCStreamer> Streamer) |
46 | 21 | : AsmPrinter(TM, std::move(Streamer)) {} |
47 | | |
48 | 0 | StringRef getPassName() const override { return "Lanai Assembly Printer"; } |
49 | | |
50 | | void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O); |
51 | | bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, |
52 | | unsigned AsmVariant, const char *ExtraCode, |
53 | | raw_ostream &O) override; |
54 | | void EmitInstruction(const MachineInstr *MI) override; |
55 | | bool isBlockOnlyReachableByFallthrough( |
56 | | const MachineBasicBlock *MBB) const override; |
57 | | |
58 | | private: |
59 | | void customEmitInstruction(const MachineInstr *MI); |
60 | | void emitCallInstruction(const MachineInstr *MI); |
61 | | }; |
62 | | } // end of anonymous namespace |
63 | | |
64 | | void LanaiAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, |
65 | 0 | raw_ostream &O) { |
66 | 0 | const MachineOperand &MO = MI->getOperand(OpNum); |
67 | 0 |
|
68 | 0 | switch (MO.getType()) { |
69 | 0 | case MachineOperand::MO_Register: |
70 | 0 | O << LanaiInstPrinter::getRegisterName(MO.getReg()); |
71 | 0 | break; |
72 | 0 |
|
73 | 0 | case MachineOperand::MO_Immediate: |
74 | 0 | O << MO.getImm(); |
75 | 0 | break; |
76 | 0 |
|
77 | 0 | case MachineOperand::MO_MachineBasicBlock: |
78 | 0 | O << *MO.getMBB()->getSymbol(); |
79 | 0 | break; |
80 | 0 |
|
81 | 0 | case MachineOperand::MO_GlobalAddress: |
82 | 0 | O << *getSymbol(MO.getGlobal()); |
83 | 0 | break; |
84 | 0 |
|
85 | 0 | case MachineOperand::MO_BlockAddress: { |
86 | 0 | MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress()); |
87 | 0 | O << BA->getName(); |
88 | 0 | break; |
89 | 0 | } |
90 | 0 |
|
91 | 0 | case MachineOperand::MO_ExternalSymbol: |
92 | 0 | O << *GetExternalSymbolSymbol(MO.getSymbolName()); |
93 | 0 | break; |
94 | 0 |
|
95 | 0 | case MachineOperand::MO_JumpTableIndex: |
96 | 0 | O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_' |
97 | 0 | << MO.getIndex(); |
98 | 0 | break; |
99 | 0 |
|
100 | 0 | case MachineOperand::MO_ConstantPoolIndex: |
101 | 0 | O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_' |
102 | 0 | << MO.getIndex(); |
103 | 0 | return; |
104 | 0 |
|
105 | 0 | default: |
106 | 0 | llvm_unreachable("<unknown operand type>"); |
107 | 0 | } |
108 | 0 | } |
109 | | |
110 | | // PrintAsmOperand - Print out an operand for an inline asm expression. |
111 | | bool LanaiAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, |
112 | | unsigned /*AsmVariant*/, |
113 | 0 | const char *ExtraCode, raw_ostream &O) { |
114 | 0 | // Does this asm operand have a single letter operand modifier? |
115 | 0 | if (ExtraCode && 0 ExtraCode[0]0 ) { |
116 | 0 | if (ExtraCode[1]) |
117 | 0 | return true; // Unknown modifier. |
118 | 0 |
|
119 | 0 | switch (ExtraCode[0]) { |
120 | 0 | // The highest-numbered register of a pair. |
121 | 0 | case 'H': { |
122 | 0 | if (OpNo == 0) |
123 | 0 | return true; |
124 | 0 | const MachineOperand &FlagsOP = MI->getOperand(OpNo - 1); |
125 | 0 | if (!FlagsOP.isImm()) |
126 | 0 | return true; |
127 | 0 | unsigned Flags = FlagsOP.getImm(); |
128 | 0 | unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); |
129 | 0 | if (NumVals != 2) |
130 | 0 | return true; |
131 | 0 | unsigned RegOp = OpNo + 1; |
132 | 0 | if (RegOp >= MI->getNumOperands()) |
133 | 0 | return true; |
134 | 0 | const MachineOperand &MO = MI->getOperand(RegOp); |
135 | 0 | if (!MO.isReg()) |
136 | 0 | return true; |
137 | 0 | unsigned Reg = MO.getReg(); |
138 | 0 | O << LanaiInstPrinter::getRegisterName(Reg); |
139 | 0 | return false; |
140 | 0 | } |
141 | 0 | default: |
142 | 0 | return true; // Unknown modifier. |
143 | 0 | } |
144 | 0 | } |
145 | 0 | printOperand(MI, OpNo, O); |
146 | 0 | return false; |
147 | 0 | } |
148 | | |
149 | | //===----------------------------------------------------------------------===// |
150 | 13 | void LanaiAsmPrinter::emitCallInstruction(const MachineInstr *MI) { |
151 | 13 | assert((MI->getOpcode() == Lanai::CALL || MI->getOpcode() == Lanai::CALLR) && |
152 | 13 | "Unsupported call function"); |
153 | 13 | |
154 | 13 | LanaiMCInstLower MCInstLowering(OutContext, *this); |
155 | 13 | MCSubtargetInfo STI = getSubtargetInfo(); |
156 | 13 | // Insert save rca instruction immediately before the call. |
157 | 13 | // TODO: We should generate a pc-relative mov instruction here instead |
158 | 13 | // of pc + 16 (should be mov .+16 %rca). |
159 | 13 | OutStreamer->EmitInstruction(MCInstBuilder(Lanai::ADD_I_LO) |
160 | 13 | .addReg(Lanai::RCA) |
161 | 13 | .addReg(Lanai::PC) |
162 | 13 | .addImm(16), |
163 | 13 | STI); |
164 | 13 | |
165 | 13 | // Push rca onto the stack. |
166 | 13 | // st %rca, [--%sp] |
167 | 13 | OutStreamer->EmitInstruction(MCInstBuilder(Lanai::SW_RI) |
168 | 13 | .addReg(Lanai::RCA) |
169 | 13 | .addReg(Lanai::SP) |
170 | 13 | .addImm(-4) |
171 | 13 | .addImm(LPAC::makePreOp(LPAC::ADD)), |
172 | 13 | STI); |
173 | 13 | |
174 | 13 | // Lower the call instruction. |
175 | 13 | if (MI->getOpcode() == Lanai::CALL13 ) { |
176 | 13 | MCInst TmpInst; |
177 | 13 | MCInstLowering.Lower(MI, TmpInst); |
178 | 13 | TmpInst.setOpcode(Lanai::BT); |
179 | 13 | OutStreamer->EmitInstruction(TmpInst, STI); |
180 | 13 | } else { |
181 | 0 | OutStreamer->EmitInstruction(MCInstBuilder(Lanai::ADD_R) |
182 | 0 | .addReg(Lanai::PC) |
183 | 0 | .addReg(MI->getOperand(0).getReg()) |
184 | 0 | .addReg(Lanai::R0) |
185 | 0 | .addImm(LPCC::ICC_T), |
186 | 0 | STI); |
187 | 0 | } |
188 | 13 | } |
189 | | |
190 | 858 | void LanaiAsmPrinter::customEmitInstruction(const MachineInstr *MI) { |
191 | 858 | LanaiMCInstLower MCInstLowering(OutContext, *this); |
192 | 858 | MCSubtargetInfo STI = getSubtargetInfo(); |
193 | 858 | MCInst TmpInst; |
194 | 858 | MCInstLowering.Lower(MI, TmpInst); |
195 | 858 | OutStreamer->EmitInstruction(TmpInst, STI); |
196 | 858 | } |
197 | | |
198 | 751 | void LanaiAsmPrinter::EmitInstruction(const MachineInstr *MI) { |
199 | 751 | MachineBasicBlock::const_instr_iterator I = MI->getIterator(); |
200 | 751 | MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); |
201 | 751 | |
202 | 871 | do { |
203 | 871 | if (I->isCall()871 ) { |
204 | 13 | emitCallInstruction(&*I); |
205 | 13 | continue; |
206 | 13 | } |
207 | 858 | |
208 | 858 | customEmitInstruction(&*I); |
209 | 871 | } while ((++I != E) && 871 I->isInsideBundle()755 ); |
210 | 751 | } |
211 | | |
212 | | // isBlockOnlyReachableByFallthough - Return true if the basic block has |
213 | | // exactly one predecessor and the control transfer mechanism between |
214 | | // the predecessor and this block is a fall-through. |
215 | | // FIXME: could the overridden cases be handled in AnalyzeBranch? |
216 | | bool LanaiAsmPrinter::isBlockOnlyReachableByFallthrough( |
217 | 27 | const MachineBasicBlock *MBB) const { |
218 | 27 | // The predecessor has to be immediately before this block. |
219 | 27 | const MachineBasicBlock *Pred = *MBB->pred_begin(); |
220 | 27 | |
221 | 27 | // If the predecessor is a switch statement, assume a jump table |
222 | 27 | // implementation, so it is not a fall through. |
223 | 27 | if (const BasicBlock *B = Pred->getBasicBlock()) |
224 | 26 | if (26 isa<SwitchInst>(B->getTerminator())26 ) |
225 | 0 | return false; |
226 | 27 | |
227 | 27 | // Check default implementation |
228 | 27 | if (27 !AsmPrinter::isBlockOnlyReachableByFallthrough(MBB)27 ) |
229 | 19 | return false; |
230 | 8 | |
231 | 8 | // Otherwise, check the last instruction. |
232 | 8 | // Check if the last terminator is an unconditional branch. |
233 | 8 | MachineBasicBlock::const_iterator I = Pred->end(); |
234 | 8 | while (I != Pred->begin() && 8 !(--I)->isTerminator()8 ) { |
235 | 0 | } |
236 | 27 | |
237 | 27 | return !I->isBarrier(); |
238 | 27 | } |
239 | | |
240 | | // Force static initialization. |
241 | 61.8k | extern "C" void LLVMInitializeLanaiAsmPrinter() { |
242 | 61.8k | RegisterAsmPrinter<LanaiAsmPrinter> X(getTheLanaiTarget()); |
243 | 61.8k | } |