/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
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1 | | //===- MipsMCCodeEmitter.h - Convert Mips Code to Machine Code --*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file defines the MipsMCCodeEmitter class. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H |
15 | | #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H |
16 | | |
17 | | #include "llvm/MC/MCCodeEmitter.h" |
18 | | #include <cstdint> |
19 | | |
20 | | namespace llvm { |
21 | | |
22 | | class MCContext; |
23 | | class MCExpr; |
24 | | class MCFixup; |
25 | | class MCInst; |
26 | | class MCInstrInfo; |
27 | | class MCOperand; |
28 | | class MCSubtargetInfo; |
29 | | class raw_ostream; |
30 | | |
31 | | class MipsMCCodeEmitter : public MCCodeEmitter { |
32 | | const MCInstrInfo &MCII; |
33 | | MCContext &Ctx; |
34 | | bool IsLittleEndian; |
35 | | |
36 | | bool isMicroMips(const MCSubtargetInfo &STI) const; |
37 | | bool isMips32r6(const MCSubtargetInfo &STI) const; |
38 | | |
39 | | public: |
40 | | MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) |
41 | 807 | : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {} |
42 | | MipsMCCodeEmitter(const MipsMCCodeEmitter &) = delete; |
43 | | MipsMCCodeEmitter &operator=(const MipsMCCodeEmitter &) = delete; |
44 | 807 | ~MipsMCCodeEmitter() override = default; |
45 | | |
46 | | void EmitByte(unsigned char C, raw_ostream &OS) const; |
47 | | |
48 | | void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, |
49 | | raw_ostream &OS) const; |
50 | | |
51 | | void encodeInstruction(const MCInst &MI, raw_ostream &OS, |
52 | | SmallVectorImpl<MCFixup> &Fixups, |
53 | | const MCSubtargetInfo &STI) const override; |
54 | | |
55 | | // getBinaryCodeForInstr - TableGen'erated function for getting the |
56 | | // binary encoding for an instruction. |
57 | | uint64_t getBinaryCodeForInstr(const MCInst &MI, |
58 | | SmallVectorImpl<MCFixup> &Fixups, |
59 | | const MCSubtargetInfo &STI) const; |
60 | | |
61 | | // getJumpTargetOpValue - Return binary encoding of the jump |
62 | | // target operand. If the machine operand requires relocation, |
63 | | // record the relocation and return zero. |
64 | | unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, |
65 | | SmallVectorImpl<MCFixup> &Fixups, |
66 | | const MCSubtargetInfo &STI) const; |
67 | | |
68 | | // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump |
69 | | // target operand. If the machine operand requires relocation, |
70 | | // record the relocation and return zero. |
71 | | unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, |
72 | | SmallVectorImpl<MCFixup> &Fixups, |
73 | | const MCSubtargetInfo &STI) const; |
74 | | |
75 | | // getUImm5Lsl2Encoding - Return binary encoding of the microMIPS jump |
76 | | // target operand. |
77 | | unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
78 | | SmallVectorImpl<MCFixup> &Fixups, |
79 | | const MCSubtargetInfo &STI) const; |
80 | | |
81 | | unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, |
82 | | SmallVectorImpl<MCFixup> &Fixups, |
83 | | const MCSubtargetInfo &STI) const; |
84 | | |
85 | | unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
86 | | SmallVectorImpl<MCFixup> &Fixups, |
87 | | const MCSubtargetInfo &STI) const; |
88 | | |
89 | | // getSImm9AddiuspValue - Return binary encoding of the microMIPS addiusp |
90 | | // instruction immediate operand. |
91 | | unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, |
92 | | SmallVectorImpl<MCFixup> &Fixups, |
93 | | const MCSubtargetInfo &STI) const; |
94 | | |
95 | | // getBranchTargetOpValue - Return binary encoding of the branch |
96 | | // target operand. If the machine operand requires relocation, |
97 | | // record the relocation and return zero. |
98 | | unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, |
99 | | SmallVectorImpl<MCFixup> &Fixups, |
100 | | const MCSubtargetInfo &STI) const; |
101 | | |
102 | | // getBranchTargetOpValue1SImm16 - Return binary encoding of the branch |
103 | | // target operand. If the machine operand requires relocation, |
104 | | // record the relocation and return zero. |
105 | | unsigned getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo, |
106 | | SmallVectorImpl<MCFixup> &Fixups, |
107 | | const MCSubtargetInfo &STI) const; |
108 | | |
109 | | // getBranchTargetOpValueMMR6 - Return binary encoding of the branch |
110 | | // target operand. If the machine operand requires relocation, |
111 | | // record the relocation and return zero. |
112 | | unsigned getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo, |
113 | | SmallVectorImpl<MCFixup> &Fixups, |
114 | | const MCSubtargetInfo &STI) const; |
115 | | |
116 | | // getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch |
117 | | // target operand. If the machine operand requires relocation, |
118 | | // record the relocation and return zero. |
119 | | unsigned getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo, |
120 | | SmallVectorImpl<MCFixup> &Fixups, |
121 | | const MCSubtargetInfo &STI) const; |
122 | | |
123 | | // getBranchTarget7OpValue - Return binary encoding of the microMIPS branch |
124 | | // target operand. If the machine operand requires relocation, |
125 | | // record the relocation and return zero. |
126 | | unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, |
127 | | SmallVectorImpl<MCFixup> &Fixups, |
128 | | const MCSubtargetInfo &STI) const; |
129 | | |
130 | | // getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS |
131 | | // 10-bit branch target operand. If the machine operand requires relocation, |
132 | | // record the relocation and return zero. |
133 | | unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, |
134 | | SmallVectorImpl<MCFixup> &Fixups, |
135 | | const MCSubtargetInfo &STI) const; |
136 | | |
137 | | // getBranchTargetOpValue - Return binary encoding of the microMIPS branch |
138 | | // target operand. If the machine operand requires relocation, |
139 | | // record the relocation and return zero. |
140 | | unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, |
141 | | SmallVectorImpl<MCFixup> &Fixups, |
142 | | const MCSubtargetInfo &STI) const; |
143 | | |
144 | | // getBranchTarget21OpValue - Return binary encoding of the branch |
145 | | // offset operand. If the machine operand requires relocation, |
146 | | // record the relocation and return zero. |
147 | | unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, |
148 | | SmallVectorImpl<MCFixup> &Fixups, |
149 | | const MCSubtargetInfo &STI) const; |
150 | | |
151 | | // getBranchTarget21OpValueMM - Return binary encoding of the branch |
152 | | // offset operand for microMIPS. If the machine operand requires |
153 | | // relocation,record the relocation and return zero. |
154 | | unsigned getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo, |
155 | | SmallVectorImpl<MCFixup> &Fixups, |
156 | | const MCSubtargetInfo &STI) const; |
157 | | |
158 | | // getBranchTarget26OpValue - Return binary encoding of the branch |
159 | | // offset operand. If the machine operand requires relocation, |
160 | | // record the relocation and return zero. |
161 | | unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, |
162 | | SmallVectorImpl<MCFixup> &Fixups, |
163 | | const MCSubtargetInfo &STI) const; |
164 | | |
165 | | // getBranchTarget26OpValueMM - Return binary encoding of the branch |
166 | | // offset operand. If the machine operand requires relocation, |
167 | | // record the relocation and return zero. |
168 | | unsigned getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo, |
169 | | SmallVectorImpl<MCFixup> &Fixups, |
170 | | const MCSubtargetInfo &STI) const; |
171 | | |
172 | | // getJumpOffset16OpValue - Return binary encoding of the jump |
173 | | // offset operand. If the machine operand requires relocation, |
174 | | // record the relocation and return zero. |
175 | | unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, |
176 | | SmallVectorImpl<MCFixup> &Fixups, |
177 | | const MCSubtargetInfo &STI) const; |
178 | | |
179 | | // getMachineOpValue - Return binary encoding of operand. If the machin |
180 | | // operand requires relocation, record the relocation and return zero. |
181 | | unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, |
182 | | SmallVectorImpl<MCFixup> &Fixups, |
183 | | const MCSubtargetInfo &STI) const; |
184 | | |
185 | | unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo, |
186 | | SmallVectorImpl<MCFixup> &Fixups, |
187 | | const MCSubtargetInfo &STI) const; |
188 | | |
189 | | template <unsigned ShiftAmount = 0> |
190 | | unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, |
191 | | SmallVectorImpl<MCFixup> &Fixups, |
192 | | const MCSubtargetInfo &STI) const; |
193 | | unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, |
194 | | SmallVectorImpl<MCFixup> &Fixups, |
195 | | const MCSubtargetInfo &STI) const; |
196 | | unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, |
197 | | SmallVectorImpl<MCFixup> &Fixups, |
198 | | const MCSubtargetInfo &STI) const; |
199 | | unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, |
200 | | SmallVectorImpl<MCFixup> &Fixups, |
201 | | const MCSubtargetInfo &STI) const; |
202 | | unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, |
203 | | SmallVectorImpl<MCFixup> &Fixups, |
204 | | const MCSubtargetInfo &STI) const; |
205 | | unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, |
206 | | SmallVectorImpl<MCFixup> &Fixups, |
207 | | const MCSubtargetInfo &STI) const; |
208 | | unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, |
209 | | SmallVectorImpl<MCFixup> &Fixups, |
210 | | const MCSubtargetInfo &STI) const; |
211 | | unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo, |
212 | | SmallVectorImpl<MCFixup> &Fixups, |
213 | | const MCSubtargetInfo &STI) const; |
214 | | unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, |
215 | | SmallVectorImpl<MCFixup> &Fixups, |
216 | | const MCSubtargetInfo &STI) const; |
217 | | unsigned getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo, |
218 | | SmallVectorImpl<MCFixup> &Fixups, |
219 | | const MCSubtargetInfo &STI) const; |
220 | | unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, |
221 | | SmallVectorImpl<MCFixup> &Fixups, |
222 | | const MCSubtargetInfo &STI) const; |
223 | | unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, |
224 | | SmallVectorImpl<MCFixup> &Fixups, |
225 | | const MCSubtargetInfo &STI) const; |
226 | | |
227 | | /// Subtract Offset then encode as a N-bit unsigned integer. |
228 | | template <unsigned Bits, int Offset> |
229 | | unsigned getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo, |
230 | | SmallVectorImpl<MCFixup> &Fixups, |
231 | | const MCSubtargetInfo &STI) const; |
232 | | |
233 | | unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
234 | | SmallVectorImpl<MCFixup> &Fixups, |
235 | | const MCSubtargetInfo &STI) const; |
236 | | |
237 | | unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, |
238 | | SmallVectorImpl<MCFixup> &Fixups, |
239 | | const MCSubtargetInfo &STI) const; |
240 | | |
241 | | unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, |
242 | | SmallVectorImpl<MCFixup> &Fixups, |
243 | | const MCSubtargetInfo &STI) const; |
244 | | unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo, |
245 | | SmallVectorImpl<MCFixup> &Fixups, |
246 | | const MCSubtargetInfo &STI) const; |
247 | | |
248 | | unsigned getRegisterPairOpValue(const MCInst &MI, unsigned OpNo, |
249 | | SmallVectorImpl<MCFixup> &Fixups, |
250 | | const MCSubtargetInfo &STI) const; |
251 | | |
252 | | unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, |
253 | | SmallVectorImpl<MCFixup> &Fixups, |
254 | | const MCSubtargetInfo &STI) const; |
255 | | |
256 | | unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
257 | | SmallVectorImpl<MCFixup> &Fixups, |
258 | | const MCSubtargetInfo &STI) const; |
259 | | |
260 | | unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, |
261 | | const MCSubtargetInfo &STI) const; |
262 | | |
263 | | unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo, |
264 | | SmallVectorImpl<MCFixup> &Fixups, |
265 | | const MCSubtargetInfo &STI) const; |
266 | | |
267 | | unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, |
268 | | SmallVectorImpl<MCFixup> &Fixups, |
269 | | const MCSubtargetInfo &STI) const; |
270 | | |
271 | | private: |
272 | | void LowerCompactBranch(MCInst& Inst) const; |
273 | | }; |
274 | | |
275 | | } // end namespace llvm |
276 | | |
277 | | #endif // LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H |