/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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1 | | //===-- Mips16RegisterInfo.cpp - MIPS16 Register Information --------------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file contains the MIPS16 implementation of the TargetRegisterInfo class. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #include "Mips16RegisterInfo.h" |
15 | | #include "Mips.h" |
16 | | #include "Mips16InstrInfo.h" |
17 | | #include "MipsInstrInfo.h" |
18 | | #include "MipsMachineFunction.h" |
19 | | #include "MipsSubtarget.h" |
20 | | #include "llvm/ADT/STLExtras.h" |
21 | | #include "llvm/CodeGen/MachineFrameInfo.h" |
22 | | #include "llvm/CodeGen/MachineFunction.h" |
23 | | #include "llvm/CodeGen/MachineInstrBuilder.h" |
24 | | #include "llvm/CodeGen/MachineRegisterInfo.h" |
25 | | #include "llvm/IR/Constants.h" |
26 | | #include "llvm/IR/DebugInfo.h" |
27 | | #include "llvm/IR/Function.h" |
28 | | #include "llvm/IR/Type.h" |
29 | | #include "llvm/Support/Debug.h" |
30 | | #include "llvm/Support/ErrorHandling.h" |
31 | | #include "llvm/Support/raw_ostream.h" |
32 | | #include "llvm/Target/TargetFrameLowering.h" |
33 | | #include "llvm/Target/TargetInstrInfo.h" |
34 | | #include "llvm/Target/TargetMachine.h" |
35 | | #include "llvm/Target/TargetOptions.h" |
36 | | |
37 | | using namespace llvm; |
38 | | |
39 | | #define DEBUG_TYPE "mips16-registerinfo" |
40 | | |
41 | 2.37k | Mips16RegisterInfo::Mips16RegisterInfo() : MipsRegisterInfo() {} |
42 | | |
43 | | bool Mips16RegisterInfo::requiresRegisterScavenging |
44 | 754 | (const MachineFunction &MF) const { |
45 | 754 | return false; |
46 | 754 | } |
47 | | bool Mips16RegisterInfo::requiresFrameIndexScavenging |
48 | 377 | (const MachineFunction &MF) const { |
49 | 377 | return false; |
50 | 377 | } |
51 | | |
52 | | bool Mips16RegisterInfo::useFPForScavengingIndex |
53 | 0 | (const MachineFunction &MF) const { |
54 | 0 | return false; |
55 | 0 | } |
56 | | |
57 | | bool Mips16RegisterInfo::saveScavengerRegister |
58 | | (MachineBasicBlock &MBB, |
59 | | MachineBasicBlock::iterator I, |
60 | | MachineBasicBlock::iterator &UseMI, |
61 | | const TargetRegisterClass *RC, |
62 | 0 | unsigned Reg) const { |
63 | 0 | DebugLoc DL; |
64 | 0 | const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo(); |
65 | 0 | TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true); |
66 | 0 | TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true); |
67 | 0 | return true; |
68 | 0 | } |
69 | | |
70 | | const TargetRegisterClass * |
71 | 0 | Mips16RegisterInfo::intRegClass(unsigned Size) const { |
72 | 0 | assert(Size == 4); |
73 | 0 | return &Mips::CPU16RegsRegClass; |
74 | 0 | } |
75 | | |
76 | | void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II, |
77 | | unsigned OpNo, int FrameIndex, |
78 | | uint64_t StackSize, |
79 | 1.12k | int64_t SPOffset) const { |
80 | 1.12k | MachineInstr &MI = *II; |
81 | 1.12k | MachineFunction &MF = *MI.getParent()->getParent(); |
82 | 1.12k | MachineFrameInfo &MFI = MF.getFrameInfo(); |
83 | 1.12k | |
84 | 1.12k | const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); |
85 | 1.12k | int MinCSFI = 0; |
86 | 1.12k | int MaxCSFI = -1; |
87 | 1.12k | |
88 | 1.12k | if (CSI.size()1.12k ) { |
89 | 1.09k | MinCSFI = CSI[0].getFrameIdx(); |
90 | 1.09k | MaxCSFI = CSI[CSI.size() - 1].getFrameIdx(); |
91 | 1.09k | } |
92 | 1.12k | |
93 | 1.12k | // The following stack frame objects are always |
94 | 1.12k | // referenced relative to $sp: |
95 | 1.12k | // 1. Outgoing arguments. |
96 | 1.12k | // 2. Pointer to dynamically allocated stack space. |
97 | 1.12k | // 3. Locations for callee-saved registers. |
98 | 1.12k | // Everything else is referenced relative to whatever register |
99 | 1.12k | // getFrameRegister() returns. |
100 | 1.12k | unsigned FrameReg; |
101 | 1.12k | |
102 | 1.12k | if (FrameIndex >= MinCSFI && 1.12k FrameIndex <= MaxCSFI30 ) |
103 | 0 | FrameReg = Mips::SP; |
104 | 1.12k | else { |
105 | 1.12k | const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); |
106 | 1.12k | if (TFI->hasFP(MF)1.12k ) { |
107 | 870 | FrameReg = Mips::S0; |
108 | 870 | } |
109 | 253 | else { |
110 | 253 | if ((MI.getNumOperands()> OpNo+2) && 253 MI.getOperand(OpNo+2).isReg()0 ) |
111 | 0 | FrameReg = MI.getOperand(OpNo+2).getReg(); |
112 | 253 | else |
113 | 253 | FrameReg = Mips::SP; |
114 | 253 | } |
115 | 1.12k | } |
116 | 1.12k | // Calculate final offset. |
117 | 1.12k | // - There is no need to change the offset if the frame object |
118 | 1.12k | // is one of the |
119 | 1.12k | // following: an outgoing argument, pointer to a dynamically allocated |
120 | 1.12k | // stack space or a $gp restore location, |
121 | 1.12k | // - If the frame object is any of the following, |
122 | 1.12k | // its offset must be adjusted |
123 | 1.12k | // by adding the size of the stack: |
124 | 1.12k | // incoming argument, callee-saved register location or local variable. |
125 | 1.12k | int64_t Offset; |
126 | 1.12k | bool IsKill = false; |
127 | 1.12k | Offset = SPOffset + (int64_t)StackSize; |
128 | 1.12k | Offset += MI.getOperand(OpNo + 1).getImm(); |
129 | 1.12k | |
130 | 1.12k | |
131 | 1.12k | DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); |
132 | 1.12k | |
133 | 1.12k | if (!MI.isDebugValue() && |
134 | 1.12k | !Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)1.12k ) { |
135 | 0 | MachineBasicBlock &MBB = *MI.getParent(); |
136 | 0 | DebugLoc DL = II->getDebugLoc(); |
137 | 0 | unsigned NewImm; |
138 | 0 | const Mips16InstrInfo &TII = |
139 | 0 | *static_cast<const Mips16InstrInfo *>(MF.getSubtarget().getInstrInfo()); |
140 | 0 | FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm); |
141 | 0 | Offset = SignExtend64<16>(NewImm); |
142 | 0 | IsKill = true; |
143 | 0 | } |
144 | 1.12k | MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); |
145 | 1.12k | MI.getOperand(OpNo + 1).ChangeToImmediate(Offset); |
146 | 1.12k | |
147 | 1.12k | |
148 | 1.12k | } |