Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
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//===-- Mips16RegisterInfo.cpp - MIPS16 Register Information --------------===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MIPS16 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips16RegisterInfo.h"
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#include "Mips.h"
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#include "Mips16InstrInfo.h"
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#include "MipsInstrInfo.h"
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#include "MipsMachineFunction.h"
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#include "MipsSubtarget.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DebugInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips16-registerinfo"
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Mips16RegisterInfo::Mips16RegisterInfo() : MipsRegisterInfo() {}
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bool Mips16RegisterInfo::requiresRegisterScavenging
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  (const MachineFunction &MF) const {
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  return false;
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}
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bool Mips16RegisterInfo::requiresFrameIndexScavenging
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  (const MachineFunction &MF) const {
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  return false;
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}
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bool Mips16RegisterInfo::useFPForScavengingIndex
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  (const MachineFunction &MF) const {
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  return false;
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0
}
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bool Mips16RegisterInfo::saveScavengerRegister
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  (MachineBasicBlock &MBB,
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   MachineBasicBlock::iterator I,
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   MachineBasicBlock::iterator &UseMI,
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   const TargetRegisterClass *RC,
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   unsigned Reg) const {
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  DebugLoc DL;
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  const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
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  TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
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  TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
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  return true;
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}
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const TargetRegisterClass *
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Mips16RegisterInfo::intRegClass(unsigned Size) const {
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  assert(Size == 4);
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  return &Mips::CPU16RegsRegClass;
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}
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void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
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                                     unsigned OpNo, int FrameIndex,
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                                     uint64_t StackSize,
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                                     int64_t SPOffset) const {
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  MachineInstr &MI = *II;
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  MachineFunction &MF = *MI.getParent()->getParent();
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  MachineFrameInfo &MFI = MF.getFrameInfo();
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  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
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  int MinCSFI = 0;
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  int MaxCSFI = -1;
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  if (
CSI.size()1.12k
) {
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    MinCSFI = CSI[0].getFrameIdx();
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    MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
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  }
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  // The following stack frame objects are always
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  // referenced relative to $sp:
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  //  1. Outgoing arguments.
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  //  2. Pointer to dynamically allocated stack space.
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  //  3. Locations for callee-saved registers.
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  // Everything else is referenced relative to whatever register
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  // getFrameRegister() returns.
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  unsigned FrameReg;
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  if (
FrameIndex >= MinCSFI && 1.12k
FrameIndex <= MaxCSFI30
)
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    FrameReg = Mips::SP;
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  else {
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    const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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    if (
TFI->hasFP(MF)1.12k
) {
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      FrameReg = Mips::S0;
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    }
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    else {
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      if (
(MI.getNumOperands()> OpNo+2) && 253
MI.getOperand(OpNo+2).isReg()0
)
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        FrameReg = MI.getOperand(OpNo+2).getReg();
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      else
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        FrameReg = Mips::SP;
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    }
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  }
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  // Calculate final offset.
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  // - There is no need to change the offset if the frame object
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  //   is one of the
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  //   following: an outgoing argument, pointer to a dynamically allocated
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  //   stack space or a $gp restore location,
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  // - If the frame object is any of the following,
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  //   its offset must be adjusted
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  //   by adding the size of the stack:
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  //   incoming argument, callee-saved register location or local variable.
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  int64_t Offset;
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  bool IsKill = false;
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  Offset = SPOffset + (int64_t)StackSize;
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  Offset += MI.getOperand(OpNo + 1).getImm();
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  DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
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  if (!MI.isDebugValue() &&
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!Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)1.12k
) {
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    MachineBasicBlock &MBB = *MI.getParent();
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    DebugLoc DL = II->getDebugLoc();
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    unsigned NewImm;
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    const Mips16InstrInfo &TII =
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        *static_cast<const Mips16InstrInfo *>(MF.getSubtarget().getInstrInfo());
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    FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
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    Offset = SignExtend64<16>(NewImm);
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    IsKill = true;
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  }
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  MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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  MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
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}