Coverage Report

Created: 2017-10-03 07:32

/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
Line
Count
Source (jump to first uncovered line)
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//===- MipsSEFrameLowering.cpp - Mips32/64 Frame Information --------------===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This file contains the Mips32/64 implementation of TargetFrameLowering class.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#include "MipsSEFrameLowering.h"
15
#include "MCTargetDesc/MipsABIInfo.h"
16
#include "MipsMachineFunction.h"
17
#include "MipsRegisterInfo.h"
18
#include "MipsSEInstrInfo.h"
19
#include "MipsSubtarget.h"
20
#include "llvm/ADT/BitVector.h"
21
#include "llvm/ADT/StringRef.h"
22
#include "llvm/ADT/StringSwitch.h"
23
#include "llvm/CodeGen/MachineBasicBlock.h"
24
#include "llvm/CodeGen/MachineFrameInfo.h"
25
#include "llvm/CodeGen/MachineFunction.h"
26
#include "llvm/CodeGen/MachineInstr.h"
27
#include "llvm/CodeGen/MachineInstrBuilder.h"
28
#include "llvm/CodeGen/MachineModuleInfo.h"
29
#include "llvm/CodeGen/MachineOperand.h"
30
#include "llvm/CodeGen/MachineRegisterInfo.h"
31
#include "llvm/CodeGen/RegisterScavenging.h"
32
#include "llvm/IR/DebugLoc.h"
33
#include "llvm/IR/Function.h"
34
#include "llvm/MC/MCDwarf.h"
35
#include "llvm/MC/MCRegisterInfo.h"
36
#include "llvm/MC/MachineLocation.h"
37
#include "llvm/Support/CodeGen.h"
38
#include "llvm/Support/ErrorHandling.h"
39
#include "llvm/Support/MathExtras.h"
40
#include "llvm/Target/TargetInstrInfo.h"
41
#include "llvm/Target/TargetRegisterInfo.h"
42
#include "llvm/Target/TargetSubtargetInfo.h"
43
#include <cassert>
44
#include <cstdint>
45
#include <utility>
46
#include <vector>
47
48
using namespace llvm;
49
50
3.36k
static std::pair<unsigned, unsigned> getMFHiLoOpc(unsigned Src) {
51
3.36k
  if (Mips::ACC64RegClass.contains(Src))
52
1
    return std::make_pair((unsigned)Mips::PseudoMFHI,
53
1
                          (unsigned)Mips::PseudoMFLO);
54
3.35k
55
3.35k
  
if (3.35k
Mips::ACC64DSPRegClass.contains(Src)3.35k
)
56
0
    return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);
57
3.35k
58
3.35k
  
if (3.35k
Mips::ACC128RegClass.contains(Src)3.35k
)
59
0
    return std::make_pair((unsigned)Mips::PseudoMFHI64,
60
0
                          (unsigned)Mips::PseudoMFLO64);
61
3.35k
62
3.35k
  return std::make_pair(0, 0);
63
3.35k
}
64
65
namespace {
66
67
/// Helper class to expand pseudos.
68
class ExpandPseudo {
69
public:
70
  ExpandPseudo(MachineFunction &MF);
71
  bool expand();
72
73
private:
74
  using Iter = MachineBasicBlock::iterator;
75
76
  bool expandInstr(MachineBasicBlock &MBB, Iter I);
77
  void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
78
  void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
79
  void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
80
  void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
81
                      unsigned MFLoOpc, unsigned RegSize);
82
  bool expandCopy(MachineBasicBlock &MBB, Iter I);
83
  bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
84
                     unsigned MFLoOpc);
85
  bool expandBuildPairF64(MachineBasicBlock &MBB,
86
                          MachineBasicBlock::iterator I, bool FP64) const;
87
  bool expandExtractElementF64(MachineBasicBlock &MBB,
88
                               MachineBasicBlock::iterator I, bool FP64) const;
89
90
  MachineFunction &MF;
91
  MachineRegisterInfo &MRI;
92
  const MipsSubtarget &Subtarget;
93
  const MipsSEInstrInfo &TII;
94
  const MipsRegisterInfo &RegInfo;
95
};
96
97
} // end anonymous namespace
98
99
ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
100
    : MF(MF_), MRI(MF.getRegInfo()),
101
      Subtarget(static_cast<const MipsSubtarget &>(MF.getSubtarget())),
102
      TII(*static_cast<const MipsSEInstrInfo *>(Subtarget.getInstrInfo())),
103
11.9k
      RegInfo(*Subtarget.getRegisterInfo()) {}
104
105
11.9k
bool ExpandPseudo::expand() {
106
11.9k
  bool Expanded = false;
107
11.9k
108
13.8k
  for (auto &MBB : MF) {
109
102k
    for (Iter I = MBB.begin(), End = MBB.end(); I != End;)
110
88.2k
      Expanded |= expandInstr(MBB, I++);
111
13.8k
  }
112
11.9k
113
11.9k
  return Expanded;
114
11.9k
}
115
116
88.2k
bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
117
88.2k
  switch(I->getOpcode()) {
118
1
  case Mips::LOAD_CCOND_DSP:
119
1
    expandLoadCCond(MBB, I);
120
1
    break;
121
1
  case Mips::STORE_CCOND_DSP:
122
1
    expandStoreCCond(MBB, I);
123
1
    break;
124
0
  case Mips::LOAD_ACC64:
125
0
  case Mips::LOAD_ACC64DSP:
126
0
    expandLoadACC(MBB, I, 4);
127
0
    break;
128
0
  case Mips::LOAD_ACC128:
129
0
    expandLoadACC(MBB, I, 8);
130
0
    break;
131
0
  case Mips::STORE_ACC64:
132
0
    expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);
133
0
    break;
134
0
  case Mips::STORE_ACC64DSP:
135
0
    expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);
136
0
    break;
137
0
  case Mips::STORE_ACC128:
138
0
    expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
139
0
    break;
140
122
  case Mips::BuildPairF64:
141
122
    if (expandBuildPairF64(MBB, I, false))
142
7
      MBB.erase(I);
143
122
    return false;
144
52
  case Mips::BuildPairF64_64:
145
52
    if (expandBuildPairF64(MBB, I, true))
146
12
      MBB.erase(I);
147
52
    return false;
148
112
  case Mips::ExtractElementF64:
149
112
    if (expandExtractElementF64(MBB, I, false))
150
18
      MBB.erase(I);
151
112
    return false;
152
50
  case Mips::ExtractElementF64_64:
153
50
    if (expandExtractElementF64(MBB, I, true))
154
12
      MBB.erase(I);
155
50
    return false;
156
3.36k
  case TargetOpcode::COPY:
157
3.36k
    if (!expandCopy(MBB, I))
158
3.35k
      return false;
159
1
    break;
160
84.5k
  default:
161
84.5k
    return false;
162
3
  }
163
3
164
3
  MBB.erase(I);
165
3
  return true;
166
3
}
167
168
1
void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
169
1
  //  load $vr, FI
170
1
  //  copy ccond, $vr
171
1
172
1
  assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
173
1
174
1
  const TargetRegisterClass *RC = RegInfo.intRegClass(4);
175
1
  unsigned VR = MRI.createVirtualRegister(RC);
176
1
  unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
177
1
178
1
  TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
179
1
  BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
180
1
    .addReg(VR, RegState::Kill);
181
1
}
182
183
1
void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
184
1
  //  copy $vr, ccond
185
1
  //  store $vr, FI
186
1
187
1
  assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
188
1
189
1
  const TargetRegisterClass *RC = RegInfo.intRegClass(4);
190
1
  unsigned VR = MRI.createVirtualRegister(RC);
191
1
  unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
192
1
193
1
  BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
194
1
    .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
195
1
  TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
196
1
}
197
198
void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
199
0
                                 unsigned RegSize) {
200
0
  //  load $vr0, FI
201
0
  //  copy lo, $vr0
202
0
  //  load $vr1, FI + 4
203
0
  //  copy hi, $vr1
204
0
205
0
  assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
206
0
207
0
  const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
208
0
  unsigned VR0 = MRI.createVirtualRegister(RC);
209
0
  unsigned VR1 = MRI.createVirtualRegister(RC);
210
0
  unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
211
0
  unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
212
0
  unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
213
0
  DebugLoc DL = I->getDebugLoc();
214
0
  const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
215
0
216
0
  TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
217
0
  BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
218
0
  TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
219
0
  BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
220
0
}
221
222
void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
223
                                  unsigned MFHiOpc, unsigned MFLoOpc,
224
0
                                  unsigned RegSize) {
225
0
  //  mflo $vr0, src
226
0
  //  store $vr0, FI
227
0
  //  mfhi $vr1, src
228
0
  //  store $vr1, FI + 4
229
0
230
0
  assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
231
0
232
0
  const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
233
0
  unsigned VR0 = MRI.createVirtualRegister(RC);
234
0
  unsigned VR1 = MRI.createVirtualRegister(RC);
235
0
  unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
236
0
  unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
237
0
  DebugLoc DL = I->getDebugLoc();
238
0
239
0
  BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
240
0
  TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
241
0
  BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
242
0
  TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
243
0
}
244
245
3.36k
bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
246
3.36k
  unsigned Src = I->getOperand(1).getReg();
247
3.36k
  std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src);
248
3.36k
249
3.36k
  if (!Opcodes.first)
250
3.35k
    return false;
251
1
252
1
  return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second);
253
1
}
254
255
bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
256
1
                                 unsigned MFHiOpc, unsigned MFLoOpc) {
257
1
  //  mflo $vr0, src
258
1
  //  copy dst_lo, $vr0
259
1
  //  mfhi $vr1, src
260
1
  //  copy dst_hi, $vr1
261
1
262
1
  unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
263
1
  const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst);
264
1
  unsigned VRegSize = RegInfo.getRegSizeInBits(*DstRC) / 16;
265
1
  const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
266
1
  unsigned VR0 = MRI.createVirtualRegister(RC);
267
1
  unsigned VR1 = MRI.createVirtualRegister(RC);
268
1
  unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
269
1
  unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
270
1
  unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
271
1
  DebugLoc DL = I->getDebugLoc();
272
1
273
1
  BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
274
1
  BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
275
1
    .addReg(VR0, RegState::Kill);
276
1
  BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
277
1
  BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
278
1
    .addReg(VR1, RegState::Kill);
279
1
  return true;
280
1
}
281
282
/// This method expands the same instruction that MipsSEInstrInfo::
283
/// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is not
284
/// available and the case where the ABI is FP64A. It is implemented here
285
/// because frame indexes are eliminated before MipsSEInstrInfo::
286
/// expandBuildPairF64 is called.
287
bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
288
                                      MachineBasicBlock::iterator I,
289
174
                                      bool FP64) const {
290
174
  // For fpxx and when mthc1 is not available, use:
291
174
  //   spill + reload via ldc1
292
174
  //
293
174
  // The case where dmtc1 is available doesn't need to be handled here
294
174
  // because it never creates a BuildPairF64 node.
295
174
  //
296
174
  // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
297
174
  // for odd-numbered double precision values (because the lower 32-bits is
298
174
  // transferred with mtc1 which is redirected to the upper half of the even
299
174
  // register). Unfortunately, we have to make this decision before register
300
174
  // allocation so for now we use a spill/reload sequence for all
301
174
  // double-precision values in regardless of being an odd/even register.
302
174
  if (
(Subtarget.isABI_FPXX() && 174
!Subtarget.hasMTHC1()14
) ||
303
174
      
(FP64 && 167
!Subtarget.useOddSPReg()52
)) {
304
19
    unsigned DstReg = I->getOperand(0).getReg();
305
19
    unsigned LoReg = I->getOperand(1).getReg();
306
19
    unsigned HiReg = I->getOperand(2).getReg();
307
19
308
19
    // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
309
19
    // the cases where mthc1 is not available). 64-bit architectures and
310
19
    // MIPS32r2 or later can use FGR64 though.
311
19
    assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
312
19
           !Subtarget.isFP64bit());
313
19
314
19
    const TargetRegisterClass *RC = &Mips::GPR32RegClass;
315
19
    const TargetRegisterClass *RC2 =
316
19
        FP64 ? 
&Mips::FGR64RegClass12
:
&Mips::AFGR64RegClass7
;
317
19
318
19
    // We re-use the same spill slot each time so that the stack frame doesn't
319
19
    // grow too much in functions with a large number of moves.
320
19
    int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2);
321
19
    if (!Subtarget.isLittle())
322
6
      std::swap(LoReg, HiReg);
323
19
    TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
324
19
                        &RegInfo, 0);
325
19
    TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC,
326
19
                        &RegInfo, 4);
327
19
    TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, 0);
328
19
    return true;
329
19
  }
330
155
331
155
  return false;
332
155
}
333
334
/// This method expands the same instruction that MipsSEInstrInfo::
335
/// expandExtractElementF64 does, for the case when ABI is fpxx and mfhc1 is not
336
/// available and the case where the ABI is FP64A. It is implemented here
337
/// because frame indexes are eliminated before MipsSEInstrInfo::
338
/// expandExtractElementF64 is called.
339
bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
340
                                           MachineBasicBlock::iterator I,
341
162
                                           bool FP64) const {
342
162
  const MachineOperand &Op1 = I->getOperand(1);
343
162
  const MachineOperand &Op2 = I->getOperand(2);
344
162
345
162
  if (
(Op1.isReg() && 162
Op1.isUndef()162
) ||
(Op2.isReg() && 138
Op2.isUndef()0
)) {
346
24
    unsigned DstReg = I->getOperand(0).getReg();
347
24
    BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);
348
24
    return true;
349
24
  }
350
138
351
138
  // For fpxx and when mfhc1 is not available, use:
352
138
  //   spill + reload via ldc1
353
138
  //
354
138
  // The case where dmfc1 is available doesn't need to be handled here
355
138
  // because it never creates a ExtractElementF64 node.
356
138
  //
357
138
  // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
358
138
  // for odd-numbered double precision values (because the lower 32-bits is
359
138
  // transferred with mfc1 which is redirected to the upper half of the even
360
138
  // register). Unfortunately, we have to make this decision before register
361
138
  // allocation so for now we use a spill/reload sequence for all
362
138
  // double-precision values in regardless of being an odd/even register.
363
138
364
138
  
if (138
(Subtarget.isABI_FPXX() && 138
!Subtarget.hasMTHC1()4
) ||
365
138
      
(FP64 && 136
!Subtarget.useOddSPReg()42
)) {
366
6
    unsigned DstReg = I->getOperand(0).getReg();
367
6
    unsigned SrcReg = Op1.getReg();
368
6
    unsigned N = Op2.getImm();
369
6
    int64_t Offset = 4 * (Subtarget.isLittle() ? 
N4
:
(1 - N)2
);
370
6
371
6
    // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
372
6
    // the cases where mfhc1 is not available). 64-bit architectures and
373
6
    // MIPS32r2 or later can use FGR64 though.
374
6
    assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
375
6
           !Subtarget.isFP64bit());
376
6
377
6
    const TargetRegisterClass *RC =
378
6
        FP64 ? 
&Mips::FGR64RegClass4
:
&Mips::AFGR64RegClass2
;
379
6
    const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;
380
6
381
6
    // We re-use the same spill slot each time so that the stack frame doesn't
382
6
    // grow too much in functions with a large number of moves.
383
6
    int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC);
384
6
    TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0);
385
6
    TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset);
386
6
    return true;
387
6
  }
388
132
389
132
  return false;
390
132
}
391
392
MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)
393
6.59k
    : MipsFrameLowering(STI, STI.getStackAlignment()) {}
394
395
void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
396
11.8k
                                       MachineBasicBlock &MBB) const {
397
11.8k
  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
398
11.8k
  MachineFrameInfo &MFI    = MF.getFrameInfo();
399
11.8k
  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
400
11.8k
401
11.8k
  const MipsSEInstrInfo &TII =
402
11.8k
      *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
403
11.8k
  const MipsRegisterInfo &RegInfo =
404
11.8k
      *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
405
11.8k
406
11.8k
  MachineBasicBlock::iterator MBBI = MBB.begin();
407
11.8k
  DebugLoc dl;
408
11.8k
  MipsABIInfo ABI = STI.getABI();
409
11.8k
  unsigned SP = ABI.GetStackPtr();
410
11.8k
  unsigned FP = ABI.GetFramePtr();
411
11.8k
  unsigned ZERO = ABI.GetNullPtr();
412
11.8k
  unsigned MOVE = ABI.GetGPRMoveOp();
413
11.8k
  unsigned ADDiu = ABI.GetPtrAddiuOp();
414
11.8k
  unsigned AND = ABI.IsN64() ? 
Mips::AND644.13k
:
Mips::AND7.73k
;
415
11.8k
416
11.8k
  const TargetRegisterClass *RC = ABI.ArePtrs64bit() ?
417
11.8k
        
&Mips::GPR64RegClass4.13k
:
&Mips::GPR32RegClass7.73k
;
418
11.8k
419
11.8k
  // First, compute final stack size.
420
11.8k
  uint64_t StackSize = MFI.getStackSize();
421
11.8k
422
11.8k
  // No need to allocate space on the stack.
423
11.8k
  if (
StackSize == 0 && 11.8k
!MFI.adjustsStack()9.65k
)
return9.65k
;
424
2.21k
425
2.21k
  MachineModuleInfo &MMI = MF.getMMI();
426
2.21k
  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
427
2.21k
  MachineLocation DstML, SrcML;
428
2.21k
429
2.21k
  // Adjust stack.
430
2.21k
  TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
431
2.21k
432
2.21k
  // emit ".cfi_def_cfa_offset StackSize"
433
2.21k
  unsigned CFIIndex = MF.addFrameInst(
434
2.21k
      MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
435
2.21k
  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
436
2.21k
      .addCFIIndex(CFIIndex);
437
2.21k
438
2.21k
  if (MF.getFunction()->hasFnAttribute("interrupt"))
439
11
    emitInterruptPrologueStub(MF, MBB);
440
2.21k
441
2.21k
  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
442
2.21k
443
2.21k
  if (
!CSI.empty()2.21k
) {
444
1.88k
    // Find the instruction past the last instruction that saves a callee-saved
445
1.88k
    // register to the stack.
446
5.45k
    for (unsigned i = 0; 
i < CSI.size()5.45k
;
++i3.56k
)
447
3.56k
      ++MBBI;
448
1.88k
449
1.88k
    // Iterate over list of callee-saved registers and emit .cfi_offset
450
1.88k
    // directives.
451
1.88k
    for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
452
5.45k
           E = CSI.end(); 
I != E5.45k
;
++I3.56k
) {
453
3.56k
      int64_t Offset = MFI.getObjectOffset(I->getFrameIdx());
454
3.56k
      unsigned Reg = I->getReg();
455
3.56k
456
3.56k
      // If Reg is a double precision register, emit two cfa_offsets,
457
3.56k
      // one for each of the paired single precision registers.
458
3.56k
      if (
Mips::AFGR64RegClass.contains(Reg)3.56k
) {
459
108
        unsigned Reg0 =
460
108
            MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
461
108
        unsigned Reg1 =
462
108
            MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
463
108
464
108
        if (!STI.isLittle())
465
30
          std::swap(Reg0, Reg1);
466
108
467
108
        unsigned CFIIndex = MF.addFrameInst(
468
108
            MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
469
108
        BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
470
108
            .addCFIIndex(CFIIndex);
471
108
472
108
        CFIIndex = MF.addFrameInst(
473
108
            MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
474
108
        BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
475
108
            .addCFIIndex(CFIIndex);
476
3.56k
      } else 
if (3.45k
Mips::FGR64RegClass.contains(Reg)3.45k
) {
477
210
        unsigned Reg0 = MRI->getDwarfRegNum(Reg, true);
478
210
        unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1;
479
210
480
210
        if (!STI.isLittle())
481
60
          std::swap(Reg0, Reg1);
482
210
483
210
        unsigned CFIIndex = MF.addFrameInst(
484
210
          MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
485
210
        BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
486
210
            .addCFIIndex(CFIIndex);
487
210
488
210
        CFIIndex = MF.addFrameInst(
489
210
          MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
490
210
        BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
491
210
            .addCFIIndex(CFIIndex);
492
3.45k
      } else {
493
3.24k
        // Reg is either in GPR32 or FGR32.
494
3.24k
        unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
495
3.24k
            nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
496
3.24k
        BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
497
3.24k
            .addCFIIndex(CFIIndex);
498
3.24k
      }
499
3.56k
    }
500
1.88k
  }
501
2.21k
502
2.21k
  if (
MipsFI->callsEhReturn()2.21k
) {
503
14
    // Insert instructions that spill eh data registers.
504
70
    for (int I = 0; 
I < 470
;
++I56
) {
505
56
      if (!MBB.isLiveIn(ABI.GetEhDataReg(I)))
506
28
        MBB.addLiveIn(ABI.GetEhDataReg(I));
507
56
      TII.storeRegToStackSlot(MBB, MBBI, ABI.GetEhDataReg(I), false,
508
56
                              MipsFI->getEhDataRegFI(I), RC, &RegInfo);
509
56
    }
510
14
511
14
    // Emit .cfi_offset directives for eh data registers.
512
70
    for (int I = 0; 
I < 470
;
++I56
) {
513
56
      int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I));
514
56
      unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true);
515
56
      unsigned CFIIndex = MF.addFrameInst(
516
56
          MCCFIInstruction::createOffset(nullptr, Reg, Offset));
517
56
      BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
518
56
          .addCFIIndex(CFIIndex);
519
56
    }
520
14
  }
521
2.21k
522
2.21k
  // if framepointer enabled, set it to point to the stack pointer.
523
2.21k
  if (
hasFP(MF)2.21k
) {
524
310
    // Insert instruction "move $fp, $sp" at this location.
525
310
    BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO)
526
310
      .setMIFlag(MachineInstr::FrameSetup);
527
310
528
310
    // emit ".cfi_def_cfa_register $fp"
529
310
    unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
530
310
        nullptr, MRI->getDwarfRegNum(FP, true)));
531
310
    BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
532
310
        .addCFIIndex(CFIIndex);
533
310
534
310
    if (
RegInfo.needsStackRealignment(MF)310
) {
535
183
      // addiu $Reg, $zero, -MaxAlignment
536
183
      // andi $sp, $sp, $Reg
537
183
      unsigned VR = MF.getRegInfo().createVirtualRegister(RC);
538
183
      assert(isInt<16>(MFI.getMaxAlignment()) &&
539
183
             "Function's alignment size requirement is not supported.");
540
183
      int MaxAlign = -(int)MFI.getMaxAlignment();
541
183
542
183
      BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
543
183
      BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);
544
183
545
183
      if (
hasBP(MF)183
) {
546
37
        // move $s7, $sp
547
37
        unsigned BP = STI.isABI_N64() ? 
Mips::S7_6412
:
Mips::S725
;
548
37
        BuildMI(MBB, MBBI, dl, TII.get(MOVE), BP)
549
37
          .addReg(SP)
550
37
          .addReg(ZERO);
551
37
      }
552
183
    }
553
310
  }
554
11.8k
}
555
556
void MipsSEFrameLowering::emitInterruptPrologueStub(
557
11
    MachineFunction &MF, MachineBasicBlock &MBB) const {
558
11
  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
559
11
  MachineBasicBlock::iterator MBBI = MBB.begin();
560
11
  DebugLoc DL = MBBI != MBB.end() ? 
MBBI->getDebugLoc()11
:
DebugLoc()0
;
561
11
562
11
  // Report an error the target doesn't support Mips32r2 or later.
563
11
  // The epilogue relies on the use of the "ehb" to clear execution
564
11
  // hazards. Pre R2 Mips relies on an implementation defined number
565
11
  // of "ssnop"s to clear the execution hazard. Support for ssnop hazard
566
11
  // clearing is not provided so reject that configuration.
567
11
  if (!STI.hasMips32r2())
568
1
    report_fatal_error(
569
1
        "\"interrupt\" attribute is not supported on pre-MIPS32R2 or "
570
1
        "MIPS16 targets.");
571
10
572
10
  // The GP register contains the "user" value, so we cannot perform
573
10
  // any gp relative loads until we restore the "kernel" or "system" gp
574
10
  // value. Until support is written we shall only accept the static
575
10
  // relocation model.
576
10
  
if (10
(STI.getRelocationModel() != Reloc::Static)10
)
577
0
    report_fatal_error("\"interrupt\" attribute is only supported for the "
578
0
                       "static relocation model on MIPS at the present time.");
579
10
580
10
  
if (10
!STI.isABI_O32() || 10
STI.hasMips64()9
)
581
1
    report_fatal_error("\"interrupt\" attribute is only supported for the "
582
1
                       "O32 ABI on MIPS32R2+ at the present time.");
583
9
584
9
  // Perform ISR handling like GCC
585
9
  StringRef IntKind =
586
9
      MF.getFunction()->getFnAttribute("interrupt").getValueAsString();
587
9
  const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
588
9
589
9
  // EIC interrupt handling needs to read the Cause register to disable
590
9
  // interrupts.
591
9
  if (
IntKind == "eic"9
) {
592
1
    // Coprocessor registers are always live per se.
593
1
    MBB.addLiveIn(Mips::COP013);
594
1
    BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0)
595
1
        .addReg(Mips::COP013)
596
1
        .addImm(0)
597
1
        .setMIFlag(MachineInstr::FrameSetup);
598
1
599
1
    BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0)
600
1
        .addReg(Mips::K0)
601
1
        .addImm(10)
602
1
        .addImm(6)
603
1
        .setMIFlag(MachineInstr::FrameSetup);
604
1
  }
605
9
606
9
  // Fetch and spill EPC
607
9
  MBB.addLiveIn(Mips::COP014);
608
9
  BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
609
9
      .addReg(Mips::COP014)
610
9
      .addImm(0)
611
9
      .setMIFlag(MachineInstr::FrameSetup);
612
9
613
9
  STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
614
9
                                      MipsFI->getISRRegFI(0), PtrRC,
615
9
                                      STI.getRegisterInfo(), 0);
616
9
617
9
  // Fetch and Spill Status
618
9
  MBB.addLiveIn(Mips::COP012);
619
9
  BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
620
9
      .addReg(Mips::COP012)
621
9
      .addImm(0)
622
9
      .setMIFlag(MachineInstr::FrameSetup);
623
9
624
9
  STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
625
9
                                      MipsFI->getISRRegFI(1), PtrRC,
626
9
                                      STI.getRegisterInfo(), 0);
627
9
628
9
  // Build the configuration for disabling lower priority interrupts. Non EIC
629
9
  // interrupts need to be masked off with zero, EIC from the Cause register.
630
9
  unsigned InsPosition = 8;
631
9
  unsigned InsSize = 0;
632
9
  unsigned SrcReg = Mips::ZERO;
633
9
634
9
  // If the interrupt we're tied to is the EIC, switch the source for the
635
9
  // masking off interrupts to the cause register.
636
9
  if (
IntKind == "eic"9
) {
637
1
    SrcReg = Mips::K0;
638
1
    InsPosition = 10;
639
1
    InsSize = 6;
640
1
  } else
641
8
    InsSize = StringSwitch<unsigned>(IntKind)
642
8
                  .Case("sw0", 1)
643
8
                  .Case("sw1", 2)
644
8
                  .Case("hw0", 3)
645
8
                  .Case("hw1", 4)
646
8
                  .Case("hw2", 5)
647
8
                  .Case("hw3", 6)
648
8
                  .Case("hw4", 7)
649
8
                  .Case("hw5", 8)
650
8
                  .Default(0);
651
9
  assert(InsSize != 0 && "Unknown interrupt type!");
652
9
653
9
  BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
654
9
      .addReg(SrcReg)
655
9
      .addImm(InsPosition)
656
9
      .addImm(InsSize)
657
9
      .addReg(Mips::K1)
658
9
      .setMIFlag(MachineInstr::FrameSetup);
659
9
660
9
  // Mask off KSU, ERL, EXL
661
9
  BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
662
9
      .addReg(Mips::ZERO)
663
9
      .addImm(1)
664
9
      .addImm(4)
665
9
      .addReg(Mips::K1)
666
9
      .setMIFlag(MachineInstr::FrameSetup);
667
9
668
9
  // Disable the FPU as we are not spilling those register sets.
669
9
  if (!STI.useSoftFloat())
670
9
    BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
671
9
        .addReg(Mips::ZERO)
672
9
        .addImm(29)
673
9
        .addImm(1)
674
9
        .addReg(Mips::K1)
675
9
        .setMIFlag(MachineInstr::FrameSetup);
676
11
677
11
  // Set the new status
678
11
  BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
679
11
      .addReg(Mips::K1)
680
11
      .addImm(0)
681
11
      .setMIFlag(MachineInstr::FrameSetup);
682
11
}
683
684
void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
685
11.9k
                                       MachineBasicBlock &MBB) const {
686
11.9k
  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
687
11.9k
  MachineFrameInfo &MFI            = MF.getFrameInfo();
688
11.9k
  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
689
11.9k
690
11.9k
  const MipsSEInstrInfo &TII =
691
11.9k
      *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
692
11.9k
  const MipsRegisterInfo &RegInfo =
693
11.9k
      *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
694
11.9k
695
11.9k
  DebugLoc DL = MBBI->getDebugLoc();
696
11.9k
  MipsABIInfo ABI = STI.getABI();
697
11.9k
  unsigned SP = ABI.GetStackPtr();
698
11.9k
  unsigned FP = ABI.GetFramePtr();
699
11.9k
  unsigned ZERO = ABI.GetNullPtr();
700
11.9k
  unsigned MOVE = ABI.GetGPRMoveOp();
701
11.9k
702
11.9k
  // if framepointer enabled, restore the stack pointer.
703
11.9k
  if (
hasFP(MF)11.9k
) {
704
309
    // Find the first instruction that restores a callee-saved register.
705
309
    MachineBasicBlock::iterator I = MBBI;
706
309
707
837
    for (unsigned i = 0; 
i < MFI.getCalleeSavedInfo().size()837
;
++i528
)
708
528
      --I;
709
309
710
309
    // Insert instruction "move $sp, $fp" at this location.
711
309
    BuildMI(MBB, I, DL, TII.get(MOVE), SP).addReg(FP).addReg(ZERO);
712
309
  }
713
11.9k
714
11.9k
  if (
MipsFI->callsEhReturn()11.9k
) {
715
14
    const TargetRegisterClass *RC =
716
14
        ABI.ArePtrs64bit() ? 
&Mips::GPR64RegClass8
:
&Mips::GPR32RegClass6
;
717
14
718
14
    // Find first instruction that restores a callee-saved register.
719
14
    MachineBasicBlock::iterator I = MBBI;
720
39
    for (unsigned i = 0; 
i < MFI.getCalleeSavedInfo().size()39
;
++i25
)
721
25
      --I;
722
14
723
14
    // Insert instructions that restore eh data registers.
724
70
    for (int J = 0; 
J < 470
;
++J56
) {
725
56
      TII.loadRegFromStackSlot(MBB, I, ABI.GetEhDataReg(J),
726
56
                               MipsFI->getEhDataRegFI(J), RC, &RegInfo);
727
56
    }
728
14
  }
729
11.9k
730
11.9k
  if (MF.getFunction()->hasFnAttribute("interrupt"))
731
9
    emitInterruptEpilogueStub(MF, MBB);
732
11.9k
733
11.9k
  // Get the number of bytes from FrameInfo
734
11.9k
  uint64_t StackSize = MFI.getStackSize();
735
11.9k
736
11.9k
  if (!StackSize)
737
9.73k
    return;
738
2.24k
739
2.24k
  // Adjust stack.
740
2.24k
  TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
741
2.24k
}
742
743
void MipsSEFrameLowering::emitInterruptEpilogueStub(
744
9
    MachineFunction &MF, MachineBasicBlock &MBB) const {
745
9
  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
746
9
  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
747
9
  DebugLoc DL = MBBI != MBB.end() ? 
MBBI->getDebugLoc()9
:
DebugLoc()0
;
748
9
749
9
  // Perform ISR handling like GCC
750
9
  const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
751
9
752
9
  // Disable Interrupts.
753
9
  BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO);
754
9
  BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB));
755
9
756
9
  // Restore EPC
757
9
  STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
758
9
                                           MipsFI->getISRRegFI(0), PtrRC,
759
9
                                           STI.getRegisterInfo());
760
9
  BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014)
761
9
      .addReg(Mips::K1)
762
9
      .addImm(0);
763
9
764
9
  // Restore Status
765
9
  STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
766
9
                                           MipsFI->getISRRegFI(1), PtrRC,
767
9
                                           STI.getRegisterInfo());
768
9
  BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
769
9
      .addReg(Mips::K1)
770
9
      .addImm(0);
771
9
}
772
773
int MipsSEFrameLowering::getFrameIndexReference(const MachineFunction &MF,
774
                                                int FI,
775
11
                                                unsigned &FrameReg) const {
776
11
  const MachineFrameInfo &MFI = MF.getFrameInfo();
777
11
  MipsABIInfo ABI = STI.getABI();
778
11
779
11
  if (MFI.isFixedObjectIndex(FI))
780
2
    
FrameReg = hasFP(MF) ? 2
ABI.GetFramePtr()1
:
ABI.GetStackPtr()1
;
781
11
  else
782
9
    
FrameReg = hasBP(MF) ? 9
ABI.GetBasePtr()4
:
ABI.GetStackPtr()5
;
783
11
784
11
  return MFI.getObjectOffset(FI) + MFI.getStackSize() -
785
11
         getOffsetOfLocalArea() + MFI.getOffsetAdjustment();
786
11
}
787
788
bool MipsSEFrameLowering::
789
spillCalleeSavedRegisters(MachineBasicBlock &MBB,
790
                          MachineBasicBlock::iterator MI,
791
                          const std::vector<CalleeSavedInfo> &CSI,
792
1.88k
                          const TargetRegisterInfo *TRI) const {
793
1.88k
  MachineFunction *MF = MBB.getParent();
794
1.88k
  MachineBasicBlock *EntryBlock = &MF->front();
795
1.88k
  const TargetInstrInfo &TII = *STI.getInstrInfo();
796
1.88k
797
5.45k
  for (unsigned i = 0, e = CSI.size(); 
i != e5.45k
;
++i3.56k
) {
798
3.56k
    // Add the callee-saved register as live-in. Do not add if the register is
799
3.56k
    // RA and return address is taken, because it has already been added in
800
3.56k
    // method MipsTargetLowering::lowerRETURNADDR.
801
3.56k
    // It's killed at the spill, unless the register is RA and return address
802
3.56k
    // is taken.
803
3.56k
    unsigned Reg = CSI[i].getReg();
804
2.71k
    bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
805
1.59k
        && MF->getFrameInfo().isReturnAddressTaken();
806
3.56k
    if (!IsRAAndRetAddrIsTaken)
807
3.56k
      EntryBlock->addLiveIn(Reg);
808
3.56k
809
3.56k
    // ISRs require HI/LO to be spilled into kernel registers to be then
810
3.56k
    // spilled to the stack frame.
811
3.56k
    bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 ||
812
3.56k
                   
Reg == Mips::HI03.56k
||
Reg == Mips::HI0_643.56k
);
813
3.56k
    const Function *Func = MBB.getParent()->getFunction();
814
3.56k
    if (
IsLOHI && 3.56k
Func->hasFnAttribute("interrupt")2
) {
815
2
      DebugLoc DL = MI->getDebugLoc();
816
2
817
2
      unsigned Op = 0;
818
2
      if (
!STI.getABI().ArePtrs64bit()2
) {
819
2
        Op = (Reg == Mips::HI0) ? 
Mips::MFHI1
:
Mips::MFLO1
;
820
2
        Reg = Mips::K0;
821
0
      } else {
822
0
        Op = (Reg == Mips::HI0) ? 
Mips::MFHI640
:
Mips::MFLO640
;
823
0
        Reg = Mips::K0_64;
824
0
      }
825
2
      BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0)
826
2
          .setMIFlag(MachineInstr::FrameSetup);
827
2
    }
828
3.56k
829
3.56k
    // Insert the spill to the stack frame.
830
3.56k
    bool IsKill = !IsRAAndRetAddrIsTaken;
831
3.56k
    const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
832
3.56k
    TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
833
3.56k
                            CSI[i].getFrameIdx(), RC, TRI);
834
3.56k
  }
835
1.88k
836
1.88k
  return true;
837
1.88k
}
838
839
bool
840
14.2k
MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
841
14.2k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
842
14.2k
  // Reserve call frame if the size of the maximum call frame fits into 16-bit
843
14.2k
  // immediate field and there are no variable sized objects on the stack.
844
14.2k
  // Make sure the second register scavenger spill slot can be accessed with one
845
14.2k
  // instruction.
846
14.2k
  return isInt<16>(MFI.getMaxCallFrameSize() + getStackAlignment()) &&
847
14.2k
    !MFI.hasVarSizedObjects();
848
14.2k
}
849
850
/// Mark \p Reg and all registers aliasing it in the bitset.
851
static void setAliasRegs(MachineFunction &MF, BitVector &SavedRegs,
852
348
                         unsigned Reg) {
853
348
  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
854
1.04k
  for (MCRegAliasIterator AI(Reg, TRI, true); 
AI.isValid()1.04k
;
++AI696
)
855
696
    SavedRegs.set(*AI);
856
348
}
857
858
void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF,
859
                                               BitVector &SavedRegs,
860
11.9k
                                               RegScavenger *RS) const {
861
11.9k
  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
862
11.9k
  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
863
11.9k
  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
864
11.9k
  MipsABIInfo ABI = STI.getABI();
865
11.9k
  unsigned FP = ABI.GetFramePtr();
866
11.9k
  unsigned BP = ABI.IsN64() ? 
Mips::S7_644.13k
:
Mips::S77.79k
;
867
11.9k
868
11.9k
  // Mark $fp as used if function has dedicated frame pointer.
869
11.9k
  if (hasFP(MF))
870
311
    setAliasRegs(MF, SavedRegs, FP);
871
11.9k
  // Mark $s7 as used if function has dedicated base pointer.
872
11.9k
  if (hasBP(MF))
873
37
    setAliasRegs(MF, SavedRegs, BP);
874
11.9k
875
11.9k
  // Create spill slots for eh data registers if function calls eh_return.
876
11.9k
  if (MipsFI->callsEhReturn())
877
14
    MipsFI->createEhDataRegsFI();
878
11.9k
879
11.9k
  // Create spill slots for Coprocessor 0 registers if function is an ISR.
880
11.9k
  if (MipsFI->isISR())
881
11
    MipsFI->createISRRegFI();
882
11.9k
883
11.9k
  // Expand pseudo instructions which load, store or copy accumulators.
884
11.9k
  // Add an emergency spill slot if a pseudo was expanded.
885
11.9k
  if (
ExpandPseudo(MF).expand()11.9k
) {
886
2
    // The spill slot should be half the size of the accumulator. If target is
887
2
    // mips64, it should be 64-bit, otherwise it should be 32-bt.
888
2
    const TargetRegisterClass &RC = STI.hasMips64() ?
889
2
      
Mips::GPR64RegClass0
:
Mips::GPR32RegClass2
;
890
2
    int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
891
2
                                                 TRI->getSpillAlignment(RC),
892
2
                                                 false);
893
2
    RS->addScavengingFrameIndex(FI);
894
2
  }
895
11.9k
896
11.9k
  // Set scavenging frame index if necessary.
897
11.9k
  uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
898
11.9k
    estimateStackSize(MF);
899
11.9k
900
11.9k
  if (isInt<16>(MaxSPOffset))
901
11.9k
    return;
902
27
903
27
  const TargetRegisterClass &RC =
904
27
      ABI.ArePtrs64bit() ? 
Mips::GPR64RegClass5
:
Mips::GPR32RegClass22
;
905
11.9k
  int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
906
11.9k
                                               TRI->getSpillAlignment(RC),
907
11.9k
                                               false);
908
11.9k
  RS->addScavengingFrameIndex(FI);
909
11.9k
}
910
911
const MipsFrameLowering *
912
6.59k
llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
913
6.59k
  return new MipsSEFrameLowering(ST);
914
6.59k
}