/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
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1 | | //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | |
10 | | #include "MCTargetDesc/X86BaseInfo.h" |
11 | | #include "X86AsmInstrumentation.h" |
12 | | #include "X86AsmParserCommon.h" |
13 | | #include "X86Operand.h" |
14 | | #include "InstPrinter/X86IntelInstPrinter.h" |
15 | | #include "llvm/ADT/STLExtras.h" |
16 | | #include "llvm/ADT/SmallString.h" |
17 | | #include "llvm/ADT/SmallVector.h" |
18 | | #include "llvm/ADT/StringSwitch.h" |
19 | | #include "llvm/ADT/Twine.h" |
20 | | #include "llvm/MC/MCContext.h" |
21 | | #include "llvm/MC/MCExpr.h" |
22 | | #include "llvm/MC/MCInst.h" |
23 | | #include "llvm/MC/MCInstrInfo.h" |
24 | | #include "llvm/MC/MCParser/MCAsmLexer.h" |
25 | | #include "llvm/MC/MCParser/MCAsmParser.h" |
26 | | #include "llvm/MC/MCParser/MCParsedAsmOperand.h" |
27 | | #include "llvm/MC/MCParser/MCTargetAsmParser.h" |
28 | | #include "llvm/MC/MCRegisterInfo.h" |
29 | | #include "llvm/MC/MCSection.h" |
30 | | #include "llvm/MC/MCStreamer.h" |
31 | | #include "llvm/MC/MCSubtargetInfo.h" |
32 | | #include "llvm/MC/MCSymbol.h" |
33 | | #include "llvm/Support/SourceMgr.h" |
34 | | #include "llvm/Support/TargetRegistry.h" |
35 | | #include "llvm/Support/raw_ostream.h" |
36 | | #include <algorithm> |
37 | | #include <memory> |
38 | | |
39 | | using namespace llvm; |
40 | | |
41 | 25.2k | static bool checkScale(unsigned Scale, StringRef &ErrMsg) { |
42 | 25.2k | if (Scale != 1 && 25.2k Scale != 25.11k && Scale != 45.03k && Scale != 84.58k ) { |
43 | 5 | ErrMsg = "scale factor in address must be 1, 2, 4 or 8"; |
44 | 5 | return true; |
45 | 5 | } |
46 | 25.2k | return false; |
47 | 25.2k | } |
48 | | |
49 | | namespace { |
50 | | |
51 | | static const char OpPrecedence[] = { |
52 | | 0, // IC_OR |
53 | | 1, // IC_XOR |
54 | | 2, // IC_AND |
55 | | 3, // IC_LSHIFT |
56 | | 3, // IC_RSHIFT |
57 | | 4, // IC_PLUS |
58 | | 4, // IC_MINUS |
59 | | 5, // IC_MULTIPLY |
60 | | 5, // IC_DIVIDE |
61 | | 5, // IC_MOD |
62 | | 6, // IC_NOT |
63 | | 7, // IC_NEG |
64 | | 8, // IC_RPAREN |
65 | | 9, // IC_LPAREN |
66 | | 0, // IC_IMM |
67 | | 0 // IC_REGISTER |
68 | | }; |
69 | | |
70 | | class X86AsmParser : public MCTargetAsmParser { |
71 | | const MCInstrInfo &MII; |
72 | | ParseInstructionInfo *InstInfo; |
73 | | std::unique_ptr<X86AsmInstrumentation> Instrumentation; |
74 | | bool Code16GCC; |
75 | | |
76 | | private: |
77 | 50.7k | SMLoc consumeToken() { |
78 | 50.7k | MCAsmParser &Parser = getParser(); |
79 | 50.7k | SMLoc Result = Parser.getTok().getLoc(); |
80 | 50.7k | Parser.Lex(); |
81 | 50.7k | return Result; |
82 | 50.7k | } |
83 | | |
84 | | unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst, |
85 | | uint64_t &ErrorInfo, bool matchingInlineAsm, |
86 | 75.9k | unsigned VariantID = 0) { |
87 | 75.9k | // In Code16GCC mode, match as 32-bit. |
88 | 75.9k | if (Code16GCC) |
89 | 30 | SwitchMode(X86::Mode32Bit); |
90 | 75.9k | unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo, |
91 | 75.9k | matchingInlineAsm, VariantID); |
92 | 75.9k | if (Code16GCC) |
93 | 30 | SwitchMode(X86::Mode16Bit); |
94 | 75.9k | return rv; |
95 | 75.9k | } |
96 | | |
97 | | enum InfixCalculatorTok { |
98 | | IC_OR = 0, |
99 | | IC_XOR, |
100 | | IC_AND, |
101 | | IC_LSHIFT, |
102 | | IC_RSHIFT, |
103 | | IC_PLUS, |
104 | | IC_MINUS, |
105 | | IC_MULTIPLY, |
106 | | IC_DIVIDE, |
107 | | IC_MOD, |
108 | | IC_NOT, |
109 | | IC_NEG, |
110 | | IC_RPAREN, |
111 | | IC_LPAREN, |
112 | | IC_IMM, |
113 | | IC_REGISTER |
114 | | }; |
115 | | |
116 | | enum IntelOperatorKind { |
117 | | IOK_INVALID = 0, |
118 | | IOK_LENGTH, |
119 | | IOK_SIZE, |
120 | | IOK_TYPE, |
121 | | IOK_OFFSET |
122 | | }; |
123 | | |
124 | | class InfixCalculator { |
125 | | typedef std::pair< InfixCalculatorTok, int64_t > ICToken; |
126 | | SmallVector<InfixCalculatorTok, 4> InfixOperatorStack; |
127 | | SmallVector<ICToken, 4> PostfixStack; |
128 | | |
129 | 7.38k | bool isUnaryOperator(const InfixCalculatorTok Op) { |
130 | 7.34k | return Op == IC_NEG || Op == IC_NOT; |
131 | 7.38k | } |
132 | | |
133 | | public: |
134 | 965 | int64_t popOperand() { |
135 | 965 | assert (!PostfixStack.empty() && "Poped an empty stack!"); |
136 | 965 | ICToken Op = PostfixStack.pop_back_val(); |
137 | 965 | if (!(Op.first == IC_IMM || 965 Op.first == IC_REGISTER1 )) |
138 | 1 | return -1; // The invalid Scale value will be caught later by checkScale |
139 | 964 | return Op.second; |
140 | 964 | } |
141 | 17.2k | void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) { |
142 | 17.2k | assert ((Op == IC_IMM || Op == IC_REGISTER) && |
143 | 17.2k | "Unexpected operand!"); |
144 | 17.2k | PostfixStack.push_back(std::make_pair(Op, Val)); |
145 | 17.2k | } |
146 | | |
147 | 1.14k | void popOperator() { InfixOperatorStack.pop_back(); } |
148 | 8.41k | void pushOperator(InfixCalculatorTok Op) { |
149 | 8.41k | // Push the new operator if the stack is empty. |
150 | 8.41k | if (InfixOperatorStack.empty()8.41k ) { |
151 | 5.84k | InfixOperatorStack.push_back(Op); |
152 | 5.84k | return; |
153 | 5.84k | } |
154 | 2.57k | |
155 | 2.57k | // Push the new operator if it has a higher precedence than the operator |
156 | 2.57k | // on the top of the stack or the operator on the top of the stack is a |
157 | 2.57k | // left parentheses. |
158 | 2.57k | unsigned Idx = InfixOperatorStack.size() - 1; |
159 | 2.57k | InfixCalculatorTok StackOp = InfixOperatorStack[Idx]; |
160 | 2.57k | if (OpPrecedence[Op] > OpPrecedence[StackOp] || 2.57k StackOp == IC_LPAREN1.34k ) { |
161 | 1.29k | InfixOperatorStack.push_back(Op); |
162 | 1.29k | return; |
163 | 1.29k | } |
164 | 1.28k | |
165 | 1.28k | // The operator on the top of the stack has higher precedence than the |
166 | 1.28k | // new operator. |
167 | 1.28k | unsigned ParenCount = 0; |
168 | 2.63k | while (12.63k ) { |
169 | 2.63k | // Nothing to process. |
170 | 2.63k | if (InfixOperatorStack.empty()) |
171 | 1.25k | break; |
172 | 1.38k | |
173 | 1.38k | Idx = InfixOperatorStack.size() - 1; |
174 | 1.38k | StackOp = InfixOperatorStack[Idx]; |
175 | 1.38k | if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || 1.38k ParenCount17 )) |
176 | 9 | break; |
177 | 1.37k | |
178 | 1.37k | // If we have an even parentheses count and we see a left parentheses, |
179 | 1.37k | // then stop processing. |
180 | 1.37k | if (1.37k !ParenCount && 1.37k StackOp == IC_LPAREN1.31k ) |
181 | 14 | break; |
182 | 1.35k | |
183 | 1.35k | if (1.35k StackOp == IC_RPAREN1.35k ) { |
184 | 29 | ++ParenCount; |
185 | 29 | InfixOperatorStack.pop_back(); |
186 | 1.35k | } else if (1.32k StackOp == IC_LPAREN1.32k ) { |
187 | 29 | --ParenCount; |
188 | 29 | InfixOperatorStack.pop_back(); |
189 | 1.32k | } else { |
190 | 1.29k | InfixOperatorStack.pop_back(); |
191 | 1.29k | PostfixStack.push_back(std::make_pair(StackOp, 0)); |
192 | 1.29k | } |
193 | 2.63k | } |
194 | 8.41k | // Push the new operator. |
195 | 8.41k | InfixOperatorStack.push_back(Op); |
196 | 8.41k | } |
197 | | |
198 | 9.51k | int64_t execute() { |
199 | 9.51k | // Push any remaining operators onto the postfix stack. |
200 | 15.4k | while (!InfixOperatorStack.empty()15.4k ) { |
201 | 5.89k | InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val(); |
202 | 5.89k | if (StackOp != IC_LPAREN && 5.89k StackOp != IC_RPAREN5.86k ) |
203 | 5.83k | PostfixStack.push_back(std::make_pair(StackOp, 0)); |
204 | 5.89k | } |
205 | 9.51k | |
206 | 9.51k | if (PostfixStack.empty()) |
207 | 0 | return 0; |
208 | 9.51k | |
209 | 9.51k | SmallVector<ICToken, 16> OperandStack; |
210 | 33.7k | for (unsigned i = 0, e = PostfixStack.size(); i != e33.7k ; ++i24.2k ) { |
211 | 24.2k | ICToken Op = PostfixStack[i]; |
212 | 24.2k | if (Op.first == IC_IMM || 24.2k Op.first == IC_REGISTER14.7k ) { |
213 | 16.8k | OperandStack.push_back(Op); |
214 | 24.2k | } else if (7.38k isUnaryOperator(Op.first)7.38k ) { |
215 | 58 | assert (OperandStack.size() > 0 && "Too few operands."); |
216 | 58 | ICToken Operand = OperandStack.pop_back_val(); |
217 | 58 | assert (Operand.first == IC_IMM && |
218 | 58 | "Unary operation with a register!"); |
219 | 58 | switch (Op.first) { |
220 | 0 | default: |
221 | 0 | report_fatal_error("Unexpected operator!"); |
222 | 0 | break; |
223 | 45 | case IC_NEG: |
224 | 45 | OperandStack.push_back(std::make_pair(IC_IMM, -Operand.second)); |
225 | 45 | break; |
226 | 13 | case IC_NOT: |
227 | 13 | OperandStack.push_back(std::make_pair(IC_IMM, ~Operand.second)); |
228 | 13 | break; |
229 | 7.38k | } |
230 | 7.33k | } else { |
231 | 7.33k | assert (OperandStack.size() > 1 && "Too few operands."); |
232 | 7.33k | int64_t Val; |
233 | 7.33k | ICToken Op2 = OperandStack.pop_back_val(); |
234 | 7.33k | ICToken Op1 = OperandStack.pop_back_val(); |
235 | 7.33k | switch (Op.first) { |
236 | 0 | default: |
237 | 0 | report_fatal_error("Unexpected operator!"); |
238 | 0 | break; |
239 | 4.86k | case IC_PLUS: |
240 | 4.86k | Val = Op1.second + Op2.second; |
241 | 4.86k | OperandStack.push_back(std::make_pair(IC_IMM, Val)); |
242 | 4.86k | break; |
243 | 2.31k | case IC_MINUS: |
244 | 2.31k | Val = Op1.second - Op2.second; |
245 | 2.31k | OperandStack.push_back(std::make_pair(IC_IMM, Val)); |
246 | 2.31k | break; |
247 | 102 | case IC_MULTIPLY: |
248 | 102 | assert (Op1.first == IC_IMM && Op2.first == IC_IMM && |
249 | 102 | "Multiply operation with an immediate and a register!"); |
250 | 102 | Val = Op1.second * Op2.second; |
251 | 102 | OperandStack.push_back(std::make_pair(IC_IMM, Val)); |
252 | 102 | break; |
253 | 10 | case IC_DIVIDE: |
254 | 10 | assert (Op1.first == IC_IMM && Op2.first == IC_IMM && |
255 | 10 | "Divide operation with an immediate and a register!"); |
256 | 10 | assert (Op2.second != 0 && "Division by zero!"); |
257 | 10 | Val = Op1.second / Op2.second; |
258 | 10 | OperandStack.push_back(std::make_pair(IC_IMM, Val)); |
259 | 10 | break; |
260 | 2 | case IC_MOD: |
261 | 2 | assert (Op1.first == IC_IMM && Op2.first == IC_IMM && |
262 | 2 | "Modulo operation with an immediate and a register!"); |
263 | 2 | Val = Op1.second % Op2.second; |
264 | 2 | OperandStack.push_back(std::make_pair(IC_IMM, Val)); |
265 | 2 | break; |
266 | 7 | case IC_OR: |
267 | 7 | assert (Op1.first == IC_IMM && Op2.first == IC_IMM && |
268 | 7 | "Or operation with an immediate and a register!"); |
269 | 7 | Val = Op1.second | Op2.second; |
270 | 7 | OperandStack.push_back(std::make_pair(IC_IMM, Val)); |
271 | 7 | break; |
272 | 7 | case IC_XOR: |
273 | 7 | assert(Op1.first == IC_IMM && Op2.first == IC_IMM && |
274 | 7 | "Xor operation with an immediate and a register!"); |
275 | 7 | Val = Op1.second ^ Op2.second; |
276 | 7 | OperandStack.push_back(std::make_pair(IC_IMM, Val)); |
277 | 7 | break; |
278 | 10 | case IC_AND: |
279 | 10 | assert (Op1.first == IC_IMM && Op2.first == IC_IMM && |
280 | 10 | "And operation with an immediate and a register!"); |
281 | 10 | Val = Op1.second & Op2.second; |
282 | 10 | OperandStack.push_back(std::make_pair(IC_IMM, Val)); |
283 | 10 | break; |
284 | 9 | case IC_LSHIFT: |
285 | 9 | assert (Op1.first == IC_IMM && Op2.first == IC_IMM && |
286 | 9 | "Left shift operation with an immediate and a register!"); |
287 | 9 | Val = Op1.second << Op2.second; |
288 | 9 | OperandStack.push_back(std::make_pair(IC_IMM, Val)); |
289 | 9 | break; |
290 | 5 | case IC_RSHIFT: |
291 | 5 | assert (Op1.first == IC_IMM && Op2.first == IC_IMM && |
292 | 5 | "Right shift operation with an immediate and a register!"); |
293 | 5 | Val = Op1.second >> Op2.second; |
294 | 5 | OperandStack.push_back(std::make_pair(IC_IMM, Val)); |
295 | 5 | break; |
296 | 7.38k | } |
297 | 7.38k | } |
298 | 24.2k | } |
299 | 9.51k | assert (OperandStack.size() == 1 && "Expected a single result."); |
300 | 9.51k | return OperandStack.pop_back_val().second; |
301 | 9.51k | } |
302 | | }; |
303 | | |
304 | | enum IntelExprState { |
305 | | IES_INIT, |
306 | | IES_OR, |
307 | | IES_XOR, |
308 | | IES_AND, |
309 | | IES_LSHIFT, |
310 | | IES_RSHIFT, |
311 | | IES_PLUS, |
312 | | IES_MINUS, |
313 | | IES_NOT, |
314 | | IES_MULTIPLY, |
315 | | IES_DIVIDE, |
316 | | IES_MOD, |
317 | | IES_LBRAC, |
318 | | IES_RBRAC, |
319 | | IES_LPAREN, |
320 | | IES_RPAREN, |
321 | | IES_REGISTER, |
322 | | IES_INTEGER, |
323 | | IES_IDENTIFIER, |
324 | | IES_ERROR |
325 | | }; |
326 | | |
327 | | class IntelExprStateMachine { |
328 | | IntelExprState State, PrevState; |
329 | | unsigned BaseReg, IndexReg, TmpReg, Scale; |
330 | | int64_t Imm; |
331 | | const MCExpr *Sym; |
332 | | StringRef SymName; |
333 | | InfixCalculator IC; |
334 | | InlineAsmIdentifierInfo Info; |
335 | | short BracCount; |
336 | | bool MemExpr; |
337 | | |
338 | | public: |
339 | | IntelExprStateMachine() |
340 | | : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), |
341 | | TmpReg(0), Scale(1), Imm(0), Sym(nullptr), BracCount(0), |
342 | 9.22k | MemExpr(false) { |
343 | 9.22k | Info.clear(); |
344 | 9.22k | } |
345 | | |
346 | 26 | void addImm(int64_t imm) { Imm += imm; } |
347 | 0 | short getBracCount() { return BracCount; } |
348 | 9.37k | bool isMemExpr() { return MemExpr; } |
349 | 7.64k | unsigned getBaseReg() { return BaseReg; } |
350 | 7.61k | unsigned getIndexReg() { return IndexReg; } |
351 | 7.47k | unsigned getScale() { return Scale; } |
352 | 9.48k | const MCExpr *getSym() { return Sym; } |
353 | 327 | StringRef getSymName() { return SymName; } |
354 | 9.51k | int64_t getImm() { return Imm + IC.execute(); } |
355 | 3.45k | bool isValidEndState() { |
356 | 24 | return State == IES_RBRAC || State == IES_INTEGER; |
357 | 3.45k | } |
358 | 49.5k | bool hadError() { return State == IES_ERROR; } |
359 | 335 | InlineAsmIdentifierInfo &getIdentifierInfo() { return Info; } |
360 | | |
361 | 7 | void onOr() { |
362 | 7 | IntelExprState CurrState = State; |
363 | 7 | switch (State) { |
364 | 0 | default: |
365 | 0 | State = IES_ERROR; |
366 | 0 | break; |
367 | 7 | case IES_INTEGER: |
368 | 7 | case IES_RPAREN: |
369 | 7 | case IES_REGISTER: |
370 | 7 | State = IES_OR; |
371 | 7 | IC.pushOperator(IC_OR); |
372 | 7 | break; |
373 | 7 | } |
374 | 7 | PrevState = CurrState; |
375 | 7 | } |
376 | 6 | void onXor() { |
377 | 6 | IntelExprState CurrState = State; |
378 | 6 | switch (State) { |
379 | 0 | default: |
380 | 0 | State = IES_ERROR; |
381 | 0 | break; |
382 | 6 | case IES_INTEGER: |
383 | 6 | case IES_RPAREN: |
384 | 6 | case IES_REGISTER: |
385 | 6 | State = IES_XOR; |
386 | 6 | IC.pushOperator(IC_XOR); |
387 | 6 | break; |
388 | 6 | } |
389 | 6 | PrevState = CurrState; |
390 | 6 | } |
391 | 10 | void onAnd() { |
392 | 10 | IntelExprState CurrState = State; |
393 | 10 | switch (State) { |
394 | 0 | default: |
395 | 0 | State = IES_ERROR; |
396 | 0 | break; |
397 | 10 | case IES_INTEGER: |
398 | 10 | case IES_RPAREN: |
399 | 10 | case IES_REGISTER: |
400 | 10 | State = IES_AND; |
401 | 10 | IC.pushOperator(IC_AND); |
402 | 10 | break; |
403 | 10 | } |
404 | 10 | PrevState = CurrState; |
405 | 10 | } |
406 | 7 | void onLShift() { |
407 | 7 | IntelExprState CurrState = State; |
408 | 7 | switch (State) { |
409 | 0 | default: |
410 | 0 | State = IES_ERROR; |
411 | 0 | break; |
412 | 7 | case IES_INTEGER: |
413 | 7 | case IES_RPAREN: |
414 | 7 | case IES_REGISTER: |
415 | 7 | State = IES_LSHIFT; |
416 | 7 | IC.pushOperator(IC_LSHIFT); |
417 | 7 | break; |
418 | 7 | } |
419 | 7 | PrevState = CurrState; |
420 | 7 | } |
421 | 5 | void onRShift() { |
422 | 5 | IntelExprState CurrState = State; |
423 | 5 | switch (State) { |
424 | 0 | default: |
425 | 0 | State = IES_ERROR; |
426 | 0 | break; |
427 | 5 | case IES_INTEGER: |
428 | 5 | case IES_RPAREN: |
429 | 5 | case IES_REGISTER: |
430 | 5 | State = IES_RSHIFT; |
431 | 5 | IC.pushOperator(IC_RSHIFT); |
432 | 5 | break; |
433 | 5 | } |
434 | 5 | PrevState = CurrState; |
435 | 5 | } |
436 | 4.56k | bool onPlus(StringRef &ErrMsg) { |
437 | 4.56k | IntelExprState CurrState = State; |
438 | 4.56k | switch (State) { |
439 | 1 | default: |
440 | 1 | State = IES_ERROR; |
441 | 1 | break; |
442 | 4.56k | case IES_INTEGER: |
443 | 4.56k | case IES_RPAREN: |
444 | 4.56k | case IES_REGISTER: |
445 | 4.56k | State = IES_PLUS; |
446 | 4.56k | IC.pushOperator(IC_PLUS); |
447 | 4.56k | if (CurrState == IES_REGISTER && 4.56k PrevState != IES_MULTIPLY4.32k ) { |
448 | 3.47k | // If we already have a BaseReg, then assume this is the IndexReg with |
449 | 3.47k | // a scale of 1. |
450 | 3.47k | if (!BaseReg3.47k ) { |
451 | 3.40k | BaseReg = TmpReg; |
452 | 3.47k | } else { |
453 | 66 | if (IndexReg66 ) { |
454 | 0 | ErrMsg = "BaseReg/IndexReg already set!"; |
455 | 0 | return true; |
456 | 0 | } |
457 | 66 | IndexReg = TmpReg; |
458 | 66 | Scale = 1; |
459 | 66 | } |
460 | 3.47k | } |
461 | 4.56k | break; |
462 | 4.56k | } |
463 | 4.56k | PrevState = CurrState; |
464 | 4.56k | return false; |
465 | 4.56k | } |
466 | 2.33k | bool onMinus(StringRef &ErrMsg) { |
467 | 2.33k | IntelExprState CurrState = State; |
468 | 2.33k | switch (State) { |
469 | 0 | default: |
470 | 0 | State = IES_ERROR; |
471 | 0 | break; |
472 | 2.33k | case IES_OR: |
473 | 2.33k | case IES_XOR: |
474 | 2.33k | case IES_AND: |
475 | 2.33k | case IES_LSHIFT: |
476 | 2.33k | case IES_RSHIFT: |
477 | 2.33k | case IES_PLUS: |
478 | 2.33k | case IES_NOT: |
479 | 2.33k | case IES_MULTIPLY: |
480 | 2.33k | case IES_DIVIDE: |
481 | 2.33k | case IES_MOD: |
482 | 2.33k | case IES_LPAREN: |
483 | 2.33k | case IES_RPAREN: |
484 | 2.33k | case IES_LBRAC: |
485 | 2.33k | case IES_RBRAC: |
486 | 2.33k | case IES_INTEGER: |
487 | 2.33k | case IES_REGISTER: |
488 | 2.33k | case IES_INIT: |
489 | 2.33k | State = IES_MINUS; |
490 | 2.33k | // push minus operator if it is not a negate operator |
491 | 2.33k | if (CurrState == IES_REGISTER || 2.33k CurrState == IES_RPAREN96 || |
492 | 2.33k | CurrState == IES_INTEGER89 || CurrState == IES_RBRAC42 ) |
493 | 2.29k | IC.pushOperator(IC_MINUS); |
494 | 42 | else if (42 PrevState == IES_REGISTER && 42 CurrState == IES_MULTIPLY2 ) { |
495 | 1 | // We have negate operator for Scale: it's illegal |
496 | 1 | ErrMsg = "Scale can't be negative"; |
497 | 1 | return true; |
498 | 1 | } else |
499 | 41 | IC.pushOperator(IC_NEG); |
500 | 2.33k | if (2.33k CurrState == IES_REGISTER && 2.33k PrevState != IES_MULTIPLY2.23k ) { |
501 | 2.18k | // If we already have a BaseReg, then assume this is the IndexReg with |
502 | 2.18k | // a scale of 1. |
503 | 2.18k | if (!BaseReg2.18k ) { |
504 | 2.18k | BaseReg = TmpReg; |
505 | 2.18k | } else { |
506 | 0 | if (IndexReg0 ) { |
507 | 0 | ErrMsg = "BaseReg/IndexReg already set!"; |
508 | 0 | return true; |
509 | 0 | } |
510 | 0 | IndexReg = TmpReg; |
511 | 0 | Scale = 1; |
512 | 0 | } |
513 | 2.18k | } |
514 | 2.33k | break; |
515 | 2.33k | } |
516 | 2.33k | PrevState = CurrState; |
517 | 2.33k | return false; |
518 | 2.33k | } |
519 | 10 | void onNot() { |
520 | 10 | IntelExprState CurrState = State; |
521 | 10 | switch (State) { |
522 | 0 | default: |
523 | 0 | State = IES_ERROR; |
524 | 0 | break; |
525 | 10 | case IES_OR: |
526 | 10 | case IES_XOR: |
527 | 10 | case IES_AND: |
528 | 10 | case IES_LSHIFT: |
529 | 10 | case IES_RSHIFT: |
530 | 10 | case IES_PLUS: |
531 | 10 | case IES_MINUS: |
532 | 10 | case IES_NOT: |
533 | 10 | case IES_MULTIPLY: |
534 | 10 | case IES_DIVIDE: |
535 | 10 | case IES_MOD: |
536 | 10 | case IES_LPAREN: |
537 | 10 | case IES_LBRAC: |
538 | 10 | case IES_INIT: |
539 | 10 | State = IES_NOT; |
540 | 10 | IC.pushOperator(IC_NOT); |
541 | 10 | break; |
542 | 10 | } |
543 | 10 | PrevState = CurrState; |
544 | 10 | } |
545 | | |
546 | 8.32k | bool onRegister(unsigned Reg, StringRef &ErrMsg) { |
547 | 8.32k | IntelExprState CurrState = State; |
548 | 8.32k | switch (State) { |
549 | 0 | default: |
550 | 0 | State = IES_ERROR; |
551 | 0 | break; |
552 | 7.35k | case IES_PLUS: |
553 | 7.35k | case IES_LPAREN: |
554 | 7.35k | case IES_LBRAC: |
555 | 7.35k | State = IES_REGISTER; |
556 | 7.35k | TmpReg = Reg; |
557 | 7.35k | IC.pushOperand(IC_REGISTER); |
558 | 7.35k | break; |
559 | 966 | case IES_MULTIPLY: |
560 | 966 | // Index Register - Scale * Register |
561 | 966 | if (PrevState == IES_INTEGER966 ) { |
562 | 966 | if (IndexReg966 ) { |
563 | 1 | ErrMsg = "BaseReg/IndexReg already set!"; |
564 | 1 | return true; |
565 | 1 | } |
566 | 965 | State = IES_REGISTER; |
567 | 965 | IndexReg = Reg; |
568 | 965 | // Get the scale and replace the 'Scale * Register' with '0'. |
569 | 965 | Scale = IC.popOperand(); |
570 | 965 | if (checkScale(Scale, ErrMsg)) |
571 | 2 | return true; |
572 | 963 | IC.pushOperand(IC_IMM); |
573 | 963 | IC.popOperator(); |
574 | 966 | } else { |
575 | 0 | State = IES_ERROR; |
576 | 0 | } |
577 | 963 | break; |
578 | 8.31k | } |
579 | 8.31k | PrevState = CurrState; |
580 | 8.31k | return false; |
581 | 8.31k | } |
582 | | bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName, |
583 | 190 | StringRef &ErrMsg) { |
584 | 190 | PrevState = State; |
585 | 190 | bool HasSymbol = Sym != nullptr; |
586 | 190 | switch (State) { |
587 | 2 | default: |
588 | 2 | State = IES_ERROR; |
589 | 2 | break; |
590 | 188 | case IES_PLUS: |
591 | 188 | case IES_MINUS: |
592 | 188 | case IES_NOT: |
593 | 188 | case IES_INIT: |
594 | 188 | case IES_LBRAC: |
595 | 188 | MemExpr = !(SymRef->getKind() == MCExpr::Constant); |
596 | 188 | State = IES_INTEGER; |
597 | 188 | Sym = SymRef; |
598 | 188 | SymName = SymRefName; |
599 | 188 | IC.pushOperand(IC_IMM); |
600 | 188 | break; |
601 | 190 | } |
602 | 190 | if (190 HasSymbol190 ) |
603 | 4 | ErrMsg = "cannot use more than one symbol in memory operand"; |
604 | 190 | return HasSymbol; |
605 | 190 | } |
606 | 8.95k | bool onInteger(int64_t TmpInt, StringRef &ErrMsg) { |
607 | 8.95k | IntelExprState CurrState = State; |
608 | 8.95k | switch (State) { |
609 | 0 | default: |
610 | 0 | State = IES_ERROR; |
611 | 0 | break; |
612 | 8.95k | case IES_PLUS: |
613 | 8.95k | case IES_MINUS: |
614 | 8.95k | case IES_NOT: |
615 | 8.95k | case IES_OR: |
616 | 8.95k | case IES_XOR: |
617 | 8.95k | case IES_AND: |
618 | 8.95k | case IES_LSHIFT: |
619 | 8.95k | case IES_RSHIFT: |
620 | 8.95k | case IES_DIVIDE: |
621 | 8.95k | case IES_MOD: |
622 | 8.95k | case IES_MULTIPLY: |
623 | 8.95k | case IES_LPAREN: |
624 | 8.95k | case IES_INIT: |
625 | 8.95k | case IES_LBRAC: |
626 | 8.95k | State = IES_INTEGER; |
627 | 8.95k | if (PrevState == IES_REGISTER && 8.95k CurrState == IES_MULTIPLY6.51k ) { |
628 | 183 | // Index Register - Register * Scale |
629 | 183 | if (IndexReg183 ) { |
630 | 0 | ErrMsg = "BaseReg/IndexReg already set!"; |
631 | 0 | return true; |
632 | 0 | } |
633 | 183 | IndexReg = TmpReg; |
634 | 183 | Scale = TmpInt; |
635 | 183 | if (checkScale(Scale, ErrMsg)) |
636 | 3 | return true; |
637 | 180 | // Get the scale and replace the 'Register * Scale' with '0'. |
638 | 180 | IC.popOperator(); |
639 | 8.95k | } else { |
640 | 8.77k | IC.pushOperand(IC_IMM, TmpInt); |
641 | 8.77k | } |
642 | 8.95k | break; |
643 | 8.95k | } |
644 | 8.95k | PrevState = CurrState; |
645 | 8.95k | return false; |
646 | 8.95k | } |
647 | 1.20k | void onStar() { |
648 | 1.20k | PrevState = State; |
649 | 1.20k | switch (State) { |
650 | 0 | default: |
651 | 0 | State = IES_ERROR; |
652 | 0 | break; |
653 | 1.20k | case IES_INTEGER: |
654 | 1.20k | case IES_REGISTER: |
655 | 1.20k | case IES_RPAREN: |
656 | 1.20k | State = IES_MULTIPLY; |
657 | 1.20k | IC.pushOperator(IC_MULTIPLY); |
658 | 1.20k | break; |
659 | 1.20k | } |
660 | 1.20k | } |
661 | 8 | void onDivide() { |
662 | 8 | PrevState = State; |
663 | 8 | switch (State) { |
664 | 0 | default: |
665 | 0 | State = IES_ERROR; |
666 | 0 | break; |
667 | 8 | case IES_INTEGER: |
668 | 8 | case IES_RPAREN: |
669 | 8 | State = IES_DIVIDE; |
670 | 8 | IC.pushOperator(IC_DIVIDE); |
671 | 8 | break; |
672 | 8 | } |
673 | 8 | } |
674 | 2 | void onMod() { |
675 | 2 | PrevState = State; |
676 | 2 | switch (State) { |
677 | 0 | default: |
678 | 0 | State = IES_ERROR; |
679 | 0 | break; |
680 | 2 | case IES_INTEGER: |
681 | 2 | case IES_RPAREN: |
682 | 2 | State = IES_MOD; |
683 | 2 | IC.pushOperator(IC_MOD); |
684 | 2 | break; |
685 | 2 | } |
686 | 2 | } |
687 | 7.32k | bool onLBrac() { |
688 | 7.32k | if (BracCount) |
689 | 2 | return true; |
690 | 7.31k | PrevState = State; |
691 | 7.31k | switch (State) { |
692 | 0 | default: |
693 | 0 | State = IES_ERROR; |
694 | 0 | break; |
695 | 145 | case IES_RBRAC: |
696 | 145 | case IES_INTEGER: |
697 | 145 | case IES_RPAREN: |
698 | 145 | State = IES_PLUS; |
699 | 145 | IC.pushOperator(IC_PLUS); |
700 | 145 | break; |
701 | 7.17k | case IES_INIT: |
702 | 7.17k | assert(!BracCount && "BracCount should be zero on parsing's start"); |
703 | 7.17k | State = IES_LBRAC; |
704 | 7.17k | break; |
705 | 7.31k | } |
706 | 7.31k | MemExpr = true; |
707 | 7.31k | BracCount++; |
708 | 7.31k | return false; |
709 | 7.31k | } |
710 | 7.30k | bool onRBrac() { |
711 | 7.30k | IntelExprState CurrState = State; |
712 | 7.30k | switch (State) { |
713 | 0 | default: |
714 | 0 | State = IES_ERROR; |
715 | 0 | break; |
716 | 7.30k | case IES_INTEGER: |
717 | 7.30k | case IES_REGISTER: |
718 | 7.30k | case IES_RPAREN: |
719 | 7.30k | if (BracCount-- != 1) |
720 | 0 | return true; |
721 | 7.30k | State = IES_RBRAC; |
722 | 7.30k | if (CurrState == IES_REGISTER && 7.30k PrevState != IES_MULTIPLY1.56k ) { |
723 | 1.51k | // If we already have a BaseReg, then assume this is the IndexReg with |
724 | 1.51k | // a scale of 1. |
725 | 1.51k | if (!BaseReg1.51k ) { |
726 | 1.51k | BaseReg = TmpReg; |
727 | 1.51k | } else { |
728 | 7 | assert (!IndexReg && "BaseReg/IndexReg already set!"); |
729 | 7 | IndexReg = TmpReg; |
730 | 7 | Scale = 1; |
731 | 7 | } |
732 | 1.51k | } |
733 | 7.30k | break; |
734 | 7.30k | } |
735 | 7.30k | PrevState = CurrState; |
736 | 7.30k | return false; |
737 | 7.30k | } |
738 | 57 | void onLParen() { |
739 | 57 | IntelExprState CurrState = State; |
740 | 57 | switch (State) { |
741 | 0 | default: |
742 | 0 | State = IES_ERROR; |
743 | 0 | break; |
744 | 57 | case IES_PLUS: |
745 | 57 | case IES_MINUS: |
746 | 57 | case IES_NOT: |
747 | 57 | case IES_OR: |
748 | 57 | case IES_XOR: |
749 | 57 | case IES_AND: |
750 | 57 | case IES_LSHIFT: |
751 | 57 | case IES_RSHIFT: |
752 | 57 | case IES_MULTIPLY: |
753 | 57 | case IES_DIVIDE: |
754 | 57 | case IES_MOD: |
755 | 57 | case IES_LPAREN: |
756 | 57 | case IES_INIT: |
757 | 57 | case IES_LBRAC: |
758 | 57 | State = IES_LPAREN; |
759 | 57 | IC.pushOperator(IC_LPAREN); |
760 | 57 | break; |
761 | 57 | } |
762 | 57 | PrevState = CurrState; |
763 | 57 | } |
764 | 57 | void onRParen() { |
765 | 57 | PrevState = State; |
766 | 57 | switch (State) { |
767 | 0 | default: |
768 | 0 | State = IES_ERROR; |
769 | 0 | break; |
770 | 57 | case IES_INTEGER: |
771 | 57 | case IES_REGISTER: |
772 | 57 | case IES_RPAREN: |
773 | 57 | State = IES_RPAREN; |
774 | 57 | IC.pushOperator(IC_RPAREN); |
775 | 57 | break; |
776 | 57 | } |
777 | 57 | } |
778 | | }; |
779 | | |
780 | | bool Error(SMLoc L, const Twine &Msg, SMRange Range = None, |
781 | 173 | bool MatchingInlineAsm = false) { |
782 | 173 | MCAsmParser &Parser = getParser(); |
783 | 173 | if (MatchingInlineAsm173 ) { |
784 | 7 | if (!getLexer().isAtStartOfStatement()) |
785 | 0 | Parser.eatToEndOfStatement(); |
786 | 7 | return false; |
787 | 7 | } |
788 | 166 | return Parser.Error(L, Msg, Range); |
789 | 166 | } |
790 | | |
791 | 8 | std::nullptr_t ErrorOperand(SMLoc Loc, StringRef Msg) { |
792 | 8 | Error(Loc, Msg); |
793 | 8 | return nullptr; |
794 | 8 | } |
795 | | |
796 | | std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc); |
797 | | std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc); |
798 | | bool IsSIReg(unsigned Reg); |
799 | | unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg); |
800 | | void |
801 | | AddDefaultSrcDestOperands(OperandVector &Operands, |
802 | | std::unique_ptr<llvm::MCParsedAsmOperand> &&Src, |
803 | | std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst); |
804 | | bool VerifyAndAdjustOperands(OperandVector &OrigOperands, |
805 | | OperandVector &FinalOperands); |
806 | | std::unique_ptr<X86Operand> ParseOperand(); |
807 | | std::unique_ptr<X86Operand> ParseATTOperand(); |
808 | | std::unique_ptr<X86Operand> ParseIntelOperand(); |
809 | | std::unique_ptr<X86Operand> ParseIntelOffsetOfOperator(); |
810 | | bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End); |
811 | | unsigned IdentifyIntelInlineAsmOperator(StringRef Name); |
812 | | unsigned ParseIntelInlineAsmOperator(unsigned OpKind); |
813 | | std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start, SMLoc End); |
814 | | bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM); |
815 | | void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start, |
816 | | SMLoc End); |
817 | | bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End); |
818 | | bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier, |
819 | | InlineAsmIdentifierInfo &Info, |
820 | | bool IsUnevaluatedOperand, SMLoc &End); |
821 | | |
822 | | std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg, SMLoc StartLoc); |
823 | | |
824 | | bool ParseIntelMemoryOperandSize(unsigned &Size); |
825 | | std::unique_ptr<X86Operand> |
826 | | CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, |
827 | | unsigned IndexReg, unsigned Scale, SMLoc Start, |
828 | | SMLoc End, unsigned Size, StringRef Identifier, |
829 | | const InlineAsmIdentifierInfo &Info); |
830 | | |
831 | | bool parseDirectiveEven(SMLoc L); |
832 | | bool ParseDirectiveWord(unsigned Size, SMLoc L); |
833 | | bool ParseDirectiveCode(StringRef IDVal, SMLoc L); |
834 | | |
835 | | bool processInstruction(MCInst &Inst, const OperandVector &Ops); |
836 | | |
837 | | /// Wrapper around MCStreamer::EmitInstruction(). Possibly adds |
838 | | /// instrumentation around Inst. |
839 | | void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out); |
840 | | |
841 | | bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, |
842 | | OperandVector &Operands, MCStreamer &Out, |
843 | | uint64_t &ErrorInfo, |
844 | | bool MatchingInlineAsm) override; |
845 | | |
846 | | void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands, |
847 | | MCStreamer &Out, bool MatchingInlineAsm); |
848 | | |
849 | | bool ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo, |
850 | | bool MatchingInlineAsm); |
851 | | |
852 | | bool MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, |
853 | | OperandVector &Operands, MCStreamer &Out, |
854 | | uint64_t &ErrorInfo, |
855 | | bool MatchingInlineAsm); |
856 | | |
857 | | bool MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode, |
858 | | OperandVector &Operands, MCStreamer &Out, |
859 | | uint64_t &ErrorInfo, |
860 | | bool MatchingInlineAsm); |
861 | | |
862 | | bool OmitRegisterFromClobberLists(unsigned RegNo) override; |
863 | | |
864 | | /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z}) |
865 | | /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required. |
866 | | /// return false if no parsing errors occurred, true otherwise. |
867 | | bool HandleAVX512Operand(OperandVector &Operands, |
868 | | const MCParsedAsmOperand &Op); |
869 | | |
870 | | bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc); |
871 | | |
872 | 134k | bool is64BitMode() const { |
873 | 134k | // FIXME: Can tablegen auto-generate this? |
874 | 134k | return getSTI().getFeatureBits()[X86::Mode64Bit]; |
875 | 134k | } |
876 | 29.7k | bool is32BitMode() const { |
877 | 29.7k | // FIXME: Can tablegen auto-generate this? |
878 | 29.7k | return getSTI().getFeatureBits()[X86::Mode32Bit]; |
879 | 29.7k | } |
880 | 29.5k | bool is16BitMode() const { |
881 | 29.5k | // FIXME: Can tablegen auto-generate this? |
882 | 29.5k | return getSTI().getFeatureBits()[X86::Mode16Bit]; |
883 | 29.5k | } |
884 | 72 | void SwitchMode(unsigned mode) { |
885 | 72 | MCSubtargetInfo &STI = copySTI(); |
886 | 72 | FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit}); |
887 | 72 | FeatureBitset OldMode = STI.getFeatureBits() & AllModes; |
888 | 72 | unsigned FB = ComputeAvailableFeatures( |
889 | 72 | STI.ToggleFeature(OldMode.flip(mode))); |
890 | 72 | setAvailableFeatures(FB); |
891 | 72 | |
892 | 72 | assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes)); |
893 | 72 | } |
894 | | |
895 | 29.4k | unsigned getPointerWidth() { |
896 | 29.4k | if (is16BitMode()29.4k ) return 16229 ; |
897 | 29.2k | if (29.2k is32BitMode()29.2k ) return 327.12k ; |
898 | 22.1k | if (22.1k is64BitMode()22.1k ) return 6422.1k ; |
899 | 0 | llvm_unreachable0 ("invalid mode"); |
900 | 0 | } |
901 | | |
902 | 458k | bool isParsingIntelSyntax() { |
903 | 458k | return getParser().getAssemblerDialect(); |
904 | 458k | } |
905 | | |
906 | | /// @name Auto-generated Matcher Functions |
907 | | /// { |
908 | | |
909 | | #define GET_ASSEMBLER_HEADER |
910 | | #include "X86GenAsmMatcher.inc" |
911 | | |
912 | | /// } |
913 | | |
914 | | public: |
915 | | |
916 | | X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser, |
917 | | const MCInstrInfo &mii, const MCTargetOptions &Options) |
918 | | : MCTargetAsmParser(Options, sti), MII(mii), InstInfo(nullptr), |
919 | 5.20k | Code16GCC(false) { |
920 | 5.20k | |
921 | 5.20k | // Initialize the set of available features. |
922 | 5.20k | setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); |
923 | 5.20k | Instrumentation.reset( |
924 | 5.20k | CreateX86AsmInstrumentation(Options, Parser.getContext(), STI)); |
925 | 5.20k | } |
926 | | |
927 | | bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; |
928 | | |
929 | | void SetFrameRegister(unsigned RegNo) override; |
930 | | |
931 | | bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, |
932 | | SMLoc NameLoc, OperandVector &Operands) override; |
933 | | |
934 | | bool ParseDirective(AsmToken DirectiveID) override; |
935 | | }; |
936 | | } // end anonymous namespace |
937 | | |
938 | | /// @name Auto-generated Match Functions |
939 | | /// { |
940 | | |
941 | | static unsigned MatchRegisterName(StringRef Name); |
942 | | |
943 | | /// } |
944 | | |
945 | | static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg, |
946 | 24.0k | unsigned Scale, StringRef &ErrMsg) { |
947 | 24.0k | // If we have both a base register and an index register make sure they are |
948 | 24.0k | // both 64-bit or 32-bit registers. |
949 | 24.0k | // To support VSIB, IndexReg can be 128-bit or 256-bit registers. |
950 | 24.0k | |
951 | 24.0k | if ((BaseReg == X86::RIP && 24.0k IndexReg != 0356 ) || (IndexReg == X86::RIP)24.0k ) { |
952 | 1 | ErrMsg = "invalid base+index expression"; |
953 | 1 | return true; |
954 | 1 | } |
955 | 24.0k | if (24.0k BaseReg != 0 && 24.0k IndexReg != 024.0k ) { |
956 | 4.25k | if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) && |
957 | 3.04k | (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) || |
958 | 3.04k | X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) && |
959 | 4.25k | IndexReg != X86::RIZ2 ) { |
960 | 2 | ErrMsg = "base register is 64-bit, but index register is not"; |
961 | 2 | return true; |
962 | 2 | } |
963 | 4.25k | if (4.25k X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) && |
964 | 1.20k | (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) || |
965 | 1.20k | X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) && |
966 | 4.25k | IndexReg != X86::EIZ0 ){ |
967 | 0 | ErrMsg = "base register is 32-bit, but index register is not"; |
968 | 0 | return true; |
969 | 0 | } |
970 | 4.25k | if (4.25k X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)4.25k ) { |
971 | 4 | if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) || |
972 | 4 | X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)4 ) { |
973 | 0 | ErrMsg = "base register is 16-bit, but index register is not"; |
974 | 0 | return true; |
975 | 0 | } |
976 | 4 | if (4 ((BaseReg == X86::BX || 4 BaseReg == X86::BP3 ) && |
977 | 4 | IndexReg != X86::SI3 && IndexReg != X86::DI1 ) || |
978 | 3 | ((BaseReg == X86::SI || 3 BaseReg == X86::DI3 ) && |
979 | 4 | IndexReg != X86::BX1 && IndexReg != X86::BP1 )) { |
980 | 1 | ErrMsg = "invalid 16-bit base/index register combination"; |
981 | 1 | return true; |
982 | 1 | } |
983 | 24.0k | } |
984 | 4.25k | } |
985 | 24.0k | return checkScale(Scale, ErrMsg); |
986 | 24.0k | } |
987 | | |
988 | | bool X86AsmParser::ParseRegister(unsigned &RegNo, |
989 | 111k | SMLoc &StartLoc, SMLoc &EndLoc) { |
990 | 111k | MCAsmParser &Parser = getParser(); |
991 | 111k | RegNo = 0; |
992 | 111k | const AsmToken &PercentTok = Parser.getTok(); |
993 | 111k | StartLoc = PercentTok.getLoc(); |
994 | 111k | |
995 | 111k | // If we encounter a %, ignore it. This code handles registers with and |
996 | 111k | // without the prefix, unprefixed registers can occur in cfi directives. |
997 | 111k | if (!isParsingIntelSyntax() && 111k PercentTok.is(AsmToken::Percent)80.8k ) |
998 | 80.8k | Parser.Lex(); // Eat percent token. |
999 | 111k | |
1000 | 111k | const AsmToken &Tok = Parser.getTok(); |
1001 | 111k | EndLoc = Tok.getEndLoc(); |
1002 | 111k | |
1003 | 111k | if (Tok.isNot(AsmToken::Identifier)111k ) { |
1004 | 2 | if (isParsingIntelSyntax()2 ) return true0 ; |
1005 | 2 | return Error(StartLoc, "invalid register name", |
1006 | 2 | SMRange(StartLoc, EndLoc)); |
1007 | 2 | } |
1008 | 111k | |
1009 | 111k | RegNo = MatchRegisterName(Tok.getString()); |
1010 | 111k | |
1011 | 111k | // If the match failed, try the register name as lowercase. |
1012 | 111k | if (RegNo == 0) |
1013 | 982 | RegNo = MatchRegisterName(Tok.getString().lower()); |
1014 | 111k | |
1015 | 111k | // The "flags" register cannot be referenced directly. |
1016 | 111k | // Treat it as an identifier instead. |
1017 | 111k | if (isParsingInlineAsm() && 111k isParsingIntelSyntax()708 && RegNo == X86::EFLAGS708 ) |
1018 | 2 | RegNo = 0; |
1019 | 111k | |
1020 | 111k | if (!is64BitMode()111k ) { |
1021 | 20.7k | // FIXME: This should be done using Requires<Not64BitMode> and |
1022 | 20.7k | // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also |
1023 | 20.7k | // checked. |
1024 | 20.7k | // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a |
1025 | 20.7k | // REX prefix. |
1026 | 20.7k | if (RegNo == X86::RIZ || |
1027 | 20.7k | X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) || |
1028 | 20.7k | X86II::isX86_64NonExtLowByteReg(RegNo) || |
1029 | 20.7k | X86II::isX86_64ExtendedReg(RegNo)) |
1030 | 19 | return Error(StartLoc, "register %" |
1031 | 19 | + Tok.getString() + " is only available in 64-bit mode", |
1032 | 19 | SMRange(StartLoc, EndLoc)); |
1033 | 90.8k | } else if (90.8k !getSTI().getFeatureBits()[X86::FeatureAVX512]90.8k ) { |
1034 | 9.94k | if (X86II::is32ExtendedReg(RegNo)) |
1035 | 1 | return Error(StartLoc, "register %" |
1036 | 1 | + Tok.getString() + " is only available with AVX512", |
1037 | 1 | SMRange(StartLoc, EndLoc)); |
1038 | 111k | } |
1039 | 111k | |
1040 | 111k | // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens. |
1041 | 111k | if (111k RegNo == 0 && 111k (Tok.getString() == "st" || 766 Tok.getString() == "ST"496 )) { |
1042 | 335 | RegNo = X86::ST0; |
1043 | 335 | Parser.Lex(); // Eat 'st' |
1044 | 335 | |
1045 | 335 | // Check to see if we have '(4)' after %st. |
1046 | 335 | if (getLexer().isNot(AsmToken::LParen)) |
1047 | 56 | return false; |
1048 | 279 | // Lex the paren. |
1049 | 279 | getParser().Lex(); |
1050 | 279 | |
1051 | 279 | const AsmToken &IntTok = Parser.getTok(); |
1052 | 279 | if (IntTok.isNot(AsmToken::Integer)) |
1053 | 0 | return Error(IntTok.getLoc(), "expected stack index"); |
1054 | 279 | switch (IntTok.getIntVal()) { |
1055 | 82 | case 0: RegNo = X86::ST0; break; |
1056 | 102 | case 1: RegNo = X86::ST1; break; |
1057 | 94 | case 2: RegNo = X86::ST2; break; |
1058 | 0 | case 3: RegNo = X86::ST3; break; |
1059 | 0 | case 4: RegNo = X86::ST4; break; |
1060 | 0 | case 5: RegNo = X86::ST5; break; |
1061 | 0 | case 6: RegNo = X86::ST6; break; |
1062 | 1 | case 7: RegNo = X86::ST7; break; |
1063 | 0 | default: return Error(IntTok.getLoc(), "invalid stack index"); |
1064 | 279 | } |
1065 | 279 | |
1066 | 279 | if (279 getParser().Lex().isNot(AsmToken::RParen)279 ) |
1067 | 0 | return Error(Parser.getTok().getLoc(), "expected ')'"); |
1068 | 279 | |
1069 | 279 | EndLoc = Parser.getTok().getEndLoc(); |
1070 | 279 | Parser.Lex(); // Eat ')' |
1071 | 279 | return false; |
1072 | 279 | } |
1073 | 111k | |
1074 | 111k | EndLoc = Parser.getTok().getEndLoc(); |
1075 | 111k | |
1076 | 111k | // If this is "db[0-7]", match it as an alias |
1077 | 111k | // for dr[0-7]. |
1078 | 111k | if (RegNo == 0 && 111k Tok.getString().size() == 3431 && |
1079 | 111k | Tok.getString().startswith("db")108 ) { |
1080 | 1 | switch (Tok.getString()[2]) { |
1081 | 0 | case '0': RegNo = X86::DR0; break; |
1082 | 0 | case '1': RegNo = X86::DR1; break; |
1083 | 0 | case '2': RegNo = X86::DR2; break; |
1084 | 0 | case '3': RegNo = X86::DR3; break; |
1085 | 0 | case '4': RegNo = X86::DR4; break; |
1086 | 0 | case '5': RegNo = X86::DR5; break; |
1087 | 1 | case '6': RegNo = X86::DR6; break; |
1088 | 0 | case '7': RegNo = X86::DR7; break; |
1089 | 1 | } |
1090 | 1 | |
1091 | 1 | if (1 RegNo != 01 ) { |
1092 | 1 | EndLoc = Parser.getTok().getEndLoc(); |
1093 | 1 | Parser.Lex(); // Eat it. |
1094 | 1 | return false; |
1095 | 1 | } |
1096 | 111k | } |
1097 | 111k | |
1098 | 111k | if (111k RegNo == 0111k ) { |
1099 | 430 | if (isParsingIntelSyntax()430 ) return true429 ; |
1100 | 1 | return Error(StartLoc, "invalid register name", |
1101 | 1 | SMRange(StartLoc, EndLoc)); |
1102 | 1 | } |
1103 | 110k | |
1104 | 110k | Parser.Lex(); // Eat identifier token. |
1105 | 110k | return false; |
1106 | 110k | } |
1107 | | |
1108 | 2.89k | void X86AsmParser::SetFrameRegister(unsigned RegNo) { |
1109 | 2.89k | Instrumentation->SetInitialFrameRegister(RegNo); |
1110 | 2.89k | } |
1111 | | |
1112 | 238 | std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) { |
1113 | 118 | bool Parse32 = is32BitMode() || Code16GCC; |
1114 | 238 | unsigned Basereg = is64BitMode() ? X86::RSI78 : (Parse32 ? 160 X86::ESI129 : X86::SI31 ); |
1115 | 238 | const MCExpr *Disp = MCConstantExpr::create(0, getContext()); |
1116 | 238 | return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp, |
1117 | 238 | /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1, |
1118 | 238 | Loc, Loc, 0); |
1119 | 238 | } |
1120 | | |
1121 | 243 | std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) { |
1122 | 122 | bool Parse32 = is32BitMode() || Code16GCC; |
1123 | 243 | unsigned Basereg = is64BitMode() ? X86::RDI85 : (Parse32 ? 158 X86::EDI128 : X86::DI30 ); |
1124 | 243 | const MCExpr *Disp = MCConstantExpr::create(0, getContext()); |
1125 | 243 | return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp, |
1126 | 243 | /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1, |
1127 | 243 | Loc, Loc, 0); |
1128 | 243 | } |
1129 | | |
1130 | 177 | bool X86AsmParser::IsSIReg(unsigned Reg) { |
1131 | 177 | switch (Reg) { |
1132 | 0 | default: 0 llvm_unreachable0 ("Only (R|E)SI and (R|E)DI are expected!"); |
1133 | 101 | case X86::RSI: |
1134 | 101 | case X86::ESI: |
1135 | 101 | case X86::SI: |
1136 | 101 | return true; |
1137 | 76 | case X86::RDI: |
1138 | 76 | case X86::EDI: |
1139 | 76 | case X86::DI: |
1140 | 76 | return false; |
1141 | 0 | } |
1142 | 0 | } |
1143 | | |
1144 | | unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, |
1145 | 177 | bool IsSIReg) { |
1146 | 177 | switch (RegClassID) { |
1147 | 0 | default: 0 llvm_unreachable0 ("Unexpected register class"); |
1148 | 43 | case X86::GR64RegClassID: |
1149 | 43 | return IsSIReg ? X86::RSI24 : X86::RDI19 ; |
1150 | 108 | case X86::GR32RegClassID: |
1151 | 108 | return IsSIReg ? X86::ESI65 : X86::EDI43 ; |
1152 | 26 | case X86::GR16RegClassID: |
1153 | 26 | return IsSIReg ? X86::SI12 : X86::DI14 ; |
1154 | 0 | } |
1155 | 0 | } |
1156 | | |
1157 | | void X86AsmParser::AddDefaultSrcDestOperands( |
1158 | | OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src, |
1159 | 259 | std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) { |
1160 | 259 | if (isParsingIntelSyntax()259 ) { |
1161 | 18 | Operands.push_back(std::move(Dst)); |
1162 | 18 | Operands.push_back(std::move(Src)); |
1163 | 18 | } |
1164 | 241 | else { |
1165 | 241 | Operands.push_back(std::move(Src)); |
1166 | 241 | Operands.push_back(std::move(Dst)); |
1167 | 241 | } |
1168 | 259 | } |
1169 | | |
1170 | | bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands, |
1171 | 311 | OperandVector &FinalOperands) { |
1172 | 311 | |
1173 | 311 | if (OrigOperands.size() > 1311 ) { |
1174 | 200 | // Check if sizes match, OrigOperands also contains the instruction name |
1175 | 200 | assert(OrigOperands.size() == FinalOperands.size() + 1 && |
1176 | 200 | "Operand size mismatch"); |
1177 | 200 | |
1178 | 200 | SmallVector<std::pair<SMLoc, std::string>, 2> Warnings; |
1179 | 200 | // Verify types match |
1180 | 200 | int RegClassID = -1; |
1181 | 436 | for (unsigned int i = 0; i < FinalOperands.size()436 ; ++i236 ) { |
1182 | 327 | X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]); |
1183 | 327 | X86Operand &FinalOp = static_cast<X86Operand &>(*FinalOperands[i]); |
1184 | 327 | |
1185 | 327 | if (FinalOp.isReg() && |
1186 | 59 | (!OrigOp.isReg() || 59 FinalOp.getReg() != OrigOp.getReg()59 )) |
1187 | 327 | // Return false and let a normal complaint about bogus operands happen |
1188 | 0 | return false; |
1189 | 327 | |
1190 | 327 | if (327 FinalOp.isMem()327 ) { |
1191 | 268 | |
1192 | 268 | if (!OrigOp.isMem()) |
1193 | 268 | // Return false and let a normal complaint about bogus operands happen |
1194 | 71 | return false; |
1195 | 197 | |
1196 | 197 | unsigned OrigReg = OrigOp.Mem.BaseReg; |
1197 | 197 | unsigned FinalReg = FinalOp.Mem.BaseReg; |
1198 | 197 | |
1199 | 197 | // If we've already encounterd a register class, make sure all register |
1200 | 197 | // bases are of the same register class |
1201 | 197 | if (RegClassID != -1 && |
1202 | 197 | !X86MCRegisterClasses[RegClassID].contains(OrigReg)42 ) { |
1203 | 2 | return Error(OrigOp.getStartLoc(), |
1204 | 2 | "mismatching source and destination index registers"); |
1205 | 2 | } |
1206 | 195 | |
1207 | 195 | if (195 X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg)195 ) |
1208 | 43 | RegClassID = X86::GR64RegClassID; |
1209 | 152 | else if (152 X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg)152 ) |
1210 | 108 | RegClassID = X86::GR32RegClassID; |
1211 | 44 | else if (44 X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg)44 ) |
1212 | 26 | RegClassID = X86::GR16RegClassID; |
1213 | 44 | else |
1214 | 44 | // Unexpected register class type |
1215 | 44 | // Return false and let a normal complaint about bogus operands happen |
1216 | 18 | return false; |
1217 | 177 | |
1218 | 177 | bool IsSI = IsSIReg(FinalReg); |
1219 | 177 | FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI); |
1220 | 177 | |
1221 | 177 | if (FinalReg != OrigReg177 ) { |
1222 | 41 | std::string RegName = IsSI ? "ES:(R|E)SI"29 : "ES:(R|E)DI"12 ; |
1223 | 41 | Warnings.push_back(std::make_pair( |
1224 | 41 | OrigOp.getStartLoc(), |
1225 | 41 | "memory operand is only for determining the size, " + RegName + |
1226 | 41 | " will be used for the location")); |
1227 | 41 | } |
1228 | 268 | |
1229 | 268 | FinalOp.Mem.Size = OrigOp.Mem.Size; |
1230 | 268 | FinalOp.Mem.SegReg = OrigOp.Mem.SegReg; |
1231 | 268 | FinalOp.Mem.BaseReg = FinalReg; |
1232 | 268 | } |
1233 | 327 | } |
1234 | 200 | |
1235 | 200 | // Produce warnings only if all the operands passed the adjustment - prevent |
1236 | 200 | // legal cases like "movsd (%rax), %xmm0" mistakenly produce warnings |
1237 | 109 | for (auto &WarningMsg : Warnings) 109 { |
1238 | 15 | Warning(WarningMsg.first, WarningMsg.second); |
1239 | 15 | } |
1240 | 109 | |
1241 | 109 | // Remove old operands |
1242 | 317 | for (unsigned int i = 0; i < FinalOperands.size()317 ; ++i208 ) |
1243 | 208 | OrigOperands.pop_back(); |
1244 | 200 | } |
1245 | 311 | // OrigOperands.append(FinalOperands.begin(), FinalOperands.end()); |
1246 | 608 | for (unsigned int i = 0; 220 i < FinalOperands.size()608 ; ++i388 ) |
1247 | 388 | OrigOperands.push_back(std::move(FinalOperands[i])); |
1248 | 220 | |
1249 | 220 | return false; |
1250 | 311 | } |
1251 | | |
1252 | 115k | std::unique_ptr<X86Operand> X86AsmParser::ParseOperand() { |
1253 | 115k | if (isParsingIntelSyntax()) |
1254 | 30.7k | return ParseIntelOperand(); |
1255 | 84.8k | return ParseATTOperand(); |
1256 | 84.8k | } |
1257 | | |
1258 | | std::unique_ptr<X86Operand> X86AsmParser::CreateMemForInlineAsm( |
1259 | | unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, |
1260 | | unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier, |
1261 | 185 | const InlineAsmIdentifierInfo &Info) { |
1262 | 185 | // If we found a decl other than a VarDecl, then assume it is a FuncDecl or |
1263 | 185 | // some other label reference. |
1264 | 185 | if (isa<MCSymbolRefExpr>(Disp) && 185 Info.OpDecl109 && !Info.IsVarDecl89 ) { |
1265 | 14 | // Insert an explicit size if the user didn't have one. |
1266 | 14 | if (!Size14 ) { |
1267 | 14 | Size = getPointerWidth(); |
1268 | 14 | InstInfo->AsmRewrites->emplace_back(AOK_SizeDirective, Start, |
1269 | 14 | /*Len=*/0, Size); |
1270 | 14 | } |
1271 | 14 | |
1272 | 14 | // Create an absolute memory reference in order to match against |
1273 | 14 | // instructions taking a PC relative operand. |
1274 | 14 | return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size, |
1275 | 14 | Identifier, Info.OpDecl); |
1276 | 14 | } |
1277 | 171 | |
1278 | 171 | |
1279 | 171 | // We either have a direct symbol reference, or an offset from a symbol. The |
1280 | 171 | // parser always puts the symbol on the LHS, so look there for size |
1281 | 171 | // calculation purposes. |
1282 | 171 | unsigned FrontendSize = 0; |
1283 | 171 | const MCBinaryExpr *BinOp = dyn_cast<MCBinaryExpr>(Disp); |
1284 | 171 | bool IsSymRef = |
1285 | 171 | isa<MCSymbolRefExpr>(BinOp ? BinOp->getLHS()33 : Disp138 ); |
1286 | 171 | if (IsSymRef && 171 !Size128 && Info.Type120 ) |
1287 | 100 | FrontendSize = Info.Type * 8; // Size is in terms of bits in this context. |
1288 | 171 | |
1289 | 171 | // When parsing inline assembly we set the base register to a non-zero value |
1290 | 171 | // if we don't know the actual value at this time. This is necessary to |
1291 | 171 | // get the matching correct in some cases. |
1292 | 171 | BaseReg = BaseReg ? BaseReg33 : 1138 ; |
1293 | 185 | return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg, |
1294 | 185 | IndexReg, Scale, Start, End, Size, Identifier, |
1295 | 185 | Info.OpDecl, FrontendSize); |
1296 | 185 | } |
1297 | | |
1298 | | // Some binary bitwise operators have a named synonymous |
1299 | | // Query a candidate string for being such a named operator |
1300 | | // and if so - invoke the appropriate handler |
1301 | 292 | bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM) { |
1302 | 292 | // A named operator should be either lower or upper case, but not a mix |
1303 | 292 | if (Name.compare(Name.lower()) && 292 Name.compare(Name.upper())85 ) |
1304 | 35 | return false; |
1305 | 257 | if (257 Name.equals_lower("not")257 ) |
1306 | 5 | SM.onNot(); |
1307 | 252 | else if (252 Name.equals_lower("or")252 ) |
1308 | 5 | SM.onOr(); |
1309 | 247 | else if (247 Name.equals_lower("shl")247 ) |
1310 | 4 | SM.onLShift(); |
1311 | 243 | else if (243 Name.equals_lower("shr")243 ) |
1312 | 4 | SM.onRShift(); |
1313 | 239 | else if (239 Name.equals_lower("xor")239 ) |
1314 | 4 | SM.onXor(); |
1315 | 235 | else if (235 Name.equals_lower("and")235 ) |
1316 | 7 | SM.onAnd(); |
1317 | 228 | else if (228 Name.equals_lower("mod")228 ) |
1318 | 2 | SM.onMod(); |
1319 | 228 | else |
1320 | 226 | return false; |
1321 | 31 | return true; |
1322 | 31 | } |
1323 | | |
1324 | 9.22k | bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) { |
1325 | 9.22k | MCAsmParser &Parser = getParser(); |
1326 | 9.22k | const AsmToken &Tok = Parser.getTok(); |
1327 | 9.22k | StringRef ErrMsg; |
1328 | 9.22k | |
1329 | 9.22k | AsmToken::TokenKind PrevTK = AsmToken::Error; |
1330 | 9.22k | bool Done = false; |
1331 | 58.8k | while (!Done58.8k ) { |
1332 | 49.6k | bool UpdateLocLex = true; |
1333 | 49.6k | AsmToken::TokenKind TK = getLexer().getKind(); |
1334 | 49.6k | |
1335 | 49.6k | switch (TK) { |
1336 | 3.45k | default: |
1337 | 3.45k | if ((Done = SM.isValidEndState())) |
1338 | 3.45k | break; |
1339 | 5 | return Error(Tok.getLoc(), "unknown token in expression"); |
1340 | 5.75k | case AsmToken::EndOfStatement: |
1341 | 5.75k | Done = true; |
1342 | 5.75k | break; |
1343 | 4 | case AsmToken::Real: |
1344 | 4 | // DotOperator: [ebx].0 |
1345 | 4 | UpdateLocLex = false; |
1346 | 4 | if (ParseIntelDotOperator(SM, End)) |
1347 | 0 | return true; |
1348 | 4 | break; |
1349 | 8.61k | case AsmToken::String: |
1350 | 8.61k | case AsmToken::Identifier: { |
1351 | 8.61k | // This could be a register or a symbolic displacement. |
1352 | 8.61k | unsigned TmpReg; |
1353 | 8.61k | const MCExpr *Val; |
1354 | 8.61k | SMLoc IdentLoc = Tok.getLoc(); |
1355 | 8.61k | StringRef Identifier = Tok.getString(); |
1356 | 8.61k | UpdateLocLex = false; |
1357 | 8.61k | if (TK != AsmToken::String && 8.61k !ParseRegister(TmpReg, IdentLoc, End)8.61k ) { |
1358 | 8.32k | if (SM.onRegister(TmpReg, ErrMsg)) |
1359 | 3 | return Error(Tok.getLoc(), ErrMsg); |
1360 | 292 | } else if (292 ParseIntelNamedOperator(Identifier, SM)292 ) { |
1361 | 31 | UpdateLocLex = true; |
1362 | 292 | } else if (261 !isParsingInlineAsm()261 ) { |
1363 | 53 | if (getParser().parsePrimaryExpr(Val, End)) |
1364 | 0 | return Error(Tok.getLoc(), "Unexpected identifier!"); |
1365 | 53 | if (auto *53 CE53 = dyn_cast<MCConstantExpr>(Val)) { |
1366 | 14 | if (SM.onInteger(CE->getValue(), ErrMsg)) |
1367 | 0 | return Error(IdentLoc, ErrMsg); |
1368 | 39 | } else if (39 SM.onIdentifierExpr(Val, Identifier, ErrMsg)39 ) |
1369 | 1 | return Error(IdentLoc, ErrMsg); |
1370 | 208 | } else if (unsigned 208 OpKind208 = IdentifyIntelInlineAsmOperator(Identifier)) { |
1371 | 33 | if (OpKind == IOK_OFFSET) |
1372 | 0 | return Error(IdentLoc, "Dealing OFFSET operator as part of" |
1373 | 0 | "a compound immediate expression is yet to be supported"); |
1374 | 33 | int64_t Val = ParseIntelInlineAsmOperator(OpKind); |
1375 | 33 | if (!Val) |
1376 | 3 | return true; |
1377 | 30 | if (30 SM.onInteger(Val, ErrMsg)30 ) |
1378 | 0 | return Error(IdentLoc, ErrMsg); |
1379 | 175 | } else if (175 Identifier.count('.') && 175 PrevTK == AsmToken::RBrac41 ) { |
1380 | 25 | if (ParseIntelDotOperator(SM, End)) |
1381 | 3 | return true; |
1382 | 150 | } else if (150 ParseIntelInlineAsmIdentifier(Val, Identifier, |
1383 | 150 | SM.getIdentifierInfo(), |
1384 | 150 | /*Unevaluated=*/false, End)) { |
1385 | 0 | return true; |
1386 | 150 | } else if (150 SM.onIdentifierExpr(Val, Identifier, ErrMsg)150 ) { |
1387 | 3 | return Error(IdentLoc, ErrMsg); |
1388 | 3 | } |
1389 | 8.60k | break; |
1390 | 8.60k | } |
1391 | 8.91k | case AsmToken::Integer: { |
1392 | 8.91k | // Look for 'b' or 'f' following an Integer as a directional label |
1393 | 8.91k | SMLoc Loc = getTok().getLoc(); |
1394 | 8.91k | int64_t IntVal = getTok().getIntVal(); |
1395 | 8.91k | End = consumeToken(); |
1396 | 8.91k | UpdateLocLex = false; |
1397 | 8.91k | if (getLexer().getKind() == AsmToken::Identifier8.91k ) { |
1398 | 25 | StringRef IDVal = getTok().getString(); |
1399 | 25 | if (IDVal == "f" || 25 IDVal == "b"24 ) { |
1400 | 1 | MCSymbol *Sym = |
1401 | 1 | getContext().getDirectionalLocalSymbol(IntVal, IDVal == "b"); |
1402 | 1 | MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; |
1403 | 1 | const MCExpr *Val = |
1404 | 1 | MCSymbolRefExpr::create(Sym, Variant, getContext()); |
1405 | 1 | if (IDVal == "b" && 1 Sym->isUndefined()0 ) |
1406 | 0 | return Error(Loc, "invalid reference to undefined symbol"); |
1407 | 1 | StringRef Identifier = Sym->getName(); |
1408 | 1 | if (SM.onIdentifierExpr(Val, Identifier, ErrMsg)) |
1409 | 0 | return Error(Loc, ErrMsg); |
1410 | 1 | End = consumeToken(); |
1411 | 25 | } else { |
1412 | 24 | if (SM.onInteger(IntVal, ErrMsg)) |
1413 | 0 | return Error(Loc, ErrMsg); |
1414 | 8.91k | } |
1415 | 0 | } else { |
1416 | 8.88k | if (SM.onInteger(IntVal, ErrMsg)) |
1417 | 3 | return Error(Loc, ErrMsg); |
1418 | 8.91k | } |
1419 | 8.91k | break; |
1420 | 8.91k | } |
1421 | 4.56k | case AsmToken::Plus: |
1422 | 4.56k | if (SM.onPlus(ErrMsg)) |
1423 | 0 | return Error(getTok().getLoc(), ErrMsg); |
1424 | 4.56k | break; |
1425 | 2.33k | case AsmToken::Minus: |
1426 | 2.33k | if (SM.onMinus(ErrMsg)) |
1427 | 1 | return Error(getTok().getLoc(), ErrMsg); |
1428 | 2.33k | break; |
1429 | 5 | case AsmToken::Tilde: SM.onNot(); break; |
1430 | 1.20k | case AsmToken::Star: SM.onStar(); break; |
1431 | 8 | case AsmToken::Slash: SM.onDivide(); break; |
1432 | 2 | case AsmToken::Pipe: SM.onOr(); break; |
1433 | 2 | case AsmToken::Caret: SM.onXor(); break; |
1434 | 3 | case AsmToken::Amp: SM.onAnd(); break; |
1435 | 3 | case AsmToken::LessLess: |
1436 | 3 | SM.onLShift(); break; |
1437 | 1 | case AsmToken::GreaterGreater: |
1438 | 1 | SM.onRShift(); break; |
1439 | 7.32k | case AsmToken::LBrac: |
1440 | 7.32k | if (SM.onLBrac()) |
1441 | 2 | return Error(Tok.getLoc(), "unexpected bracket encountered"); |
1442 | 7.31k | break; |
1443 | 7.30k | case AsmToken::RBrac: |
1444 | 7.30k | if (SM.onRBrac()) |
1445 | 0 | return Error(Tok.getLoc(), "unexpected bracket encountered"); |
1446 | 7.30k | break; |
1447 | 57 | case AsmToken::LParen: SM.onLParen(); break; |
1448 | 57 | case AsmToken::RParen: SM.onRParen(); break; |
1449 | 49.5k | } |
1450 | 49.5k | if (49.5k SM.hadError()49.5k ) |
1451 | 3 | return Error(Tok.getLoc(), "unknown token in expression"); |
1452 | 49.5k | |
1453 | 49.5k | if (49.5k !Done && 49.5k UpdateLocLex40.3k ) |
1454 | 22.8k | End = consumeToken(); |
1455 | 49.6k | |
1456 | 49.6k | PrevTK = TK; |
1457 | 49.6k | } |
1458 | 9.20k | return false; |
1459 | 9.22k | } |
1460 | | |
1461 | | void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM, |
1462 | 283 | SMLoc Start, SMLoc End) { |
1463 | 283 | SMLoc Loc = Start; |
1464 | 283 | unsigned ExprLen = End.getPointer() - Start.getPointer(); |
1465 | 283 | // Skip everything before a symbol displacement (if we have one) |
1466 | 283 | if (SM.getSym()283 ) { |
1467 | 142 | StringRef SymName = SM.getSymName(); |
1468 | 142 | if (unsigned Len = SymName.data() - Start.getPointer()) |
1469 | 51 | InstInfo->AsmRewrites->emplace_back(AOK_Skip, Start, Len); |
1470 | 142 | Loc = SMLoc::getFromPointer(SymName.data() + SymName.size()); |
1471 | 142 | ExprLen = End.getPointer() - (SymName.data() + SymName.size()); |
1472 | 142 | // If we have only a symbol than there's no need for complex rewrite, |
1473 | 142 | // simply skip everything after it |
1474 | 142 | if (!(SM.getBaseReg() || 142 SM.getIndexReg()142 || SM.getImm()142 )) { |
1475 | 109 | if (ExprLen) |
1476 | 22 | InstInfo->AsmRewrites->emplace_back(AOK_Skip, Loc, ExprLen); |
1477 | 109 | return; |
1478 | 109 | } |
1479 | 174 | } |
1480 | 174 | // Build an Intel Expression rewrite |
1481 | 174 | StringRef BaseRegStr; |
1482 | 174 | StringRef IndexRegStr; |
1483 | 174 | if (SM.getBaseReg()) |
1484 | 33 | BaseRegStr = X86IntelInstPrinter::getRegisterName(SM.getBaseReg()); |
1485 | 174 | if (SM.getIndexReg()) |
1486 | 1 | IndexRegStr = X86IntelInstPrinter::getRegisterName(SM.getIndexReg()); |
1487 | 283 | // Emit it |
1488 | 283 | IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), SM.getImm(), SM.isMemExpr()); |
1489 | 283 | InstInfo->AsmRewrites->emplace_back(Loc, ExprLen, Expr); |
1490 | 283 | } |
1491 | | |
1492 | | // Inline assembly may use variable names with namespace alias qualifiers. |
1493 | | bool X86AsmParser::ParseIntelInlineAsmIdentifier(const MCExpr *&Val, |
1494 | | StringRef &Identifier, |
1495 | | InlineAsmIdentifierInfo &Info, |
1496 | | bool IsUnevaluatedOperand, |
1497 | 190 | SMLoc &End) { |
1498 | 190 | MCAsmParser &Parser = getParser(); |
1499 | 190 | assert(isParsingInlineAsm() && "Expected to be parsing inline assembly."); |
1500 | 190 | Val = nullptr; |
1501 | 190 | |
1502 | 190 | StringRef LineBuf(Identifier.data()); |
1503 | 190 | void *Result = |
1504 | 190 | SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand); |
1505 | 190 | |
1506 | 190 | const AsmToken &Tok = Parser.getTok(); |
1507 | 190 | SMLoc Loc = Tok.getLoc(); |
1508 | 190 | |
1509 | 190 | // Advance the token stream until the end of the current token is |
1510 | 190 | // after the end of what the frontend claimed. |
1511 | 190 | const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size(); |
1512 | 314 | do { |
1513 | 314 | End = Tok.getEndLoc(); |
1514 | 314 | getLexer().Lex(); |
1515 | 314 | } while (End.getPointer() < EndPtr); |
1516 | 190 | Identifier = LineBuf; |
1517 | 190 | |
1518 | 190 | // The frontend should end parsing on an assembler token boundary, unless it |
1519 | 190 | // failed parsing. |
1520 | 190 | assert((End.getPointer() == EndPtr || !Result) && |
1521 | 190 | "frontend claimed part of a token?"); |
1522 | 190 | |
1523 | 190 | // If the identifier lookup was unsuccessful, assume that we are dealing with |
1524 | 190 | // a label. |
1525 | 190 | if (!Result190 ) { |
1526 | 25 | StringRef InternalName = |
1527 | 25 | SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(), |
1528 | 25 | Loc, false); |
1529 | 25 | assert(InternalName.size() && "We should have an internal name here."); |
1530 | 25 | // Push a rewrite for replacing the identifier name with the internal name. |
1531 | 25 | InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(), |
1532 | 25 | InternalName); |
1533 | 25 | } |
1534 | 190 | |
1535 | 190 | // Create the symbol reference. |
1536 | 190 | MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier); |
1537 | 190 | MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; |
1538 | 190 | Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext()); |
1539 | 190 | return false; |
1540 | 190 | } |
1541 | | |
1542 | | //ParseRoundingModeOp - Parse AVX-512 rounding mode operand |
1543 | | std::unique_ptr<X86Operand> |
1544 | 1.79k | X86AsmParser::ParseRoundingModeOp(SMLoc Start, SMLoc End) { |
1545 | 1.79k | MCAsmParser &Parser = getParser(); |
1546 | 1.79k | const AsmToken &Tok = Parser.getTok(); |
1547 | 1.79k | // Eat "{" and mark the current place. |
1548 | 1.79k | const SMLoc consumedToken = consumeToken(); |
1549 | 1.79k | if (Tok.getIdentifier().startswith("r")1.79k ){ |
1550 | 1.53k | int rndMode = StringSwitch<int>(Tok.getIdentifier()) |
1551 | 1.53k | .Case("rn", X86::STATIC_ROUNDING::TO_NEAREST_INT) |
1552 | 1.53k | .Case("rd", X86::STATIC_ROUNDING::TO_NEG_INF) |
1553 | 1.53k | .Case("ru", X86::STATIC_ROUNDING::TO_POS_INF) |
1554 | 1.53k | .Case("rz", X86::STATIC_ROUNDING::TO_ZERO) |
1555 | 1.53k | .Default(-1); |
1556 | 1.53k | if (-1 == rndMode) |
1557 | 0 | return ErrorOperand(Tok.getLoc(), "Invalid rounding mode."); |
1558 | 1.53k | Parser.Lex(); // Eat "r*" of r*-sae |
1559 | 1.53k | if (!getLexer().is(AsmToken::Minus)) |
1560 | 0 | return ErrorOperand(Tok.getLoc(), "Expected - at this point"); |
1561 | 1.53k | Parser.Lex(); // Eat "-" |
1562 | 1.53k | Parser.Lex(); // Eat the sae |
1563 | 1.53k | if (!getLexer().is(AsmToken::RCurly)) |
1564 | 0 | return ErrorOperand(Tok.getLoc(), "Expected } at this point"); |
1565 | 1.53k | Parser.Lex(); // Eat "}" |
1566 | 1.53k | const MCExpr *RndModeOp = |
1567 | 1.53k | MCConstantExpr::create(rndMode, Parser.getContext()); |
1568 | 1.53k | return X86Operand::CreateImm(RndModeOp, Start, End); |
1569 | 1.53k | } |
1570 | 259 | if(259 Tok.getIdentifier().equals("sae")259 ){ |
1571 | 259 | Parser.Lex(); // Eat the sae |
1572 | 259 | if (!getLexer().is(AsmToken::RCurly)) |
1573 | 0 | return ErrorOperand(Tok.getLoc(), "Expected } at this point"); |
1574 | 259 | Parser.Lex(); // Eat "}" |
1575 | 259 | return X86Operand::CreateToken("{sae}", consumedToken); |
1576 | 259 | } |
1577 | 0 | return ErrorOperand(Tok.getLoc(), "unknown token in expression"); |
1578 | 0 | } |
1579 | | |
1580 | | /// Parse the '.' operator. |
1581 | 29 | bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End) { |
1582 | 29 | const AsmToken &Tok = getTok(); |
1583 | 29 | unsigned Offset; |
1584 | 29 | |
1585 | 29 | // Drop the optional '.'. |
1586 | 29 | StringRef DotDispStr = Tok.getString(); |
1587 | 29 | if (DotDispStr.startswith(".")) |
1588 | 17 | DotDispStr = DotDispStr.drop_front(1); |
1589 | 29 | |
1590 | 29 | // .Imm gets lexed as a real. |
1591 | 29 | if (Tok.is(AsmToken::Real)29 ) { |
1592 | 4 | APInt DotDisp; |
1593 | 4 | DotDispStr.getAsInteger(10, DotDisp); |
1594 | 4 | Offset = DotDisp.getZExtValue(); |
1595 | 29 | } else if (25 isParsingInlineAsm() && 25 Tok.is(AsmToken::Identifier)25 ) { |
1596 | 25 | std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.'); |
1597 | 25 | if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second, |
1598 | 25 | Offset)) |
1599 | 3 | return Error(Tok.getLoc(), "Unable to lookup field reference!"); |
1600 | 25 | } else |
1601 | 0 | return Error(Tok.getLoc(), "Unexpected token type!"); |
1602 | 26 | |
1603 | 26 | // Eat the DotExpression and update End |
1604 | 26 | End = SMLoc::getFromPointer(DotDispStr.data()); |
1605 | 26 | const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size(); |
1606 | 52 | while (Tok.getLoc().getPointer() < DotExprEndLoc) |
1607 | 26 | Lex(); |
1608 | 29 | SM.addImm(Offset); |
1609 | 29 | return false; |
1610 | 29 | } |
1611 | | |
1612 | | /// Parse the 'offset' operator. This operator is used to specify the |
1613 | | /// location rather then the content of a variable. |
1614 | 7 | std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOffsetOfOperator() { |
1615 | 7 | MCAsmParser &Parser = getParser(); |
1616 | 7 | const AsmToken &Tok = Parser.getTok(); |
1617 | 7 | SMLoc OffsetOfLoc = Tok.getLoc(); |
1618 | 7 | Parser.Lex(); // Eat offset. |
1619 | 7 | |
1620 | 7 | const MCExpr *Val; |
1621 | 7 | InlineAsmIdentifierInfo Info; |
1622 | 7 | SMLoc Start = Tok.getLoc(), End; |
1623 | 7 | StringRef Identifier = Tok.getString(); |
1624 | 7 | if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, |
1625 | 7 | /*Unevaluated=*/false, End)) |
1626 | 0 | return nullptr; |
1627 | 7 | |
1628 | 7 | // Don't emit the offset operator. |
1629 | 7 | InstInfo->AsmRewrites->emplace_back(AOK_Skip, OffsetOfLoc, 7); |
1630 | 7 | |
1631 | 7 | // The offset operator will have an 'r' constraint, thus we need to create |
1632 | 7 | // register operand to ensure proper matching. Just pick a GPR based on |
1633 | 7 | // the size of a pointer. |
1634 | 2 | bool Parse32 = is32BitMode() || Code16GCC; |
1635 | 7 | unsigned RegNo = is64BitMode() ? X86::RBX2 : (Parse32 ? 5 X86::EBX5 : X86::BX0 ); |
1636 | 7 | |
1637 | 7 | return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true, |
1638 | 7 | OffsetOfLoc, Identifier, Info.OpDecl); |
1639 | 7 | } |
1640 | | |
1641 | | // Query a candidate string for being an Intel assembly operator |
1642 | | // Report back its kind, or IOK_INVALID if does not evaluated as a known one |
1643 | 844 | unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) { |
1644 | 844 | return StringSwitch<unsigned>(Name) |
1645 | 844 | .Cases("TYPE","type",IOK_TYPE) |
1646 | 844 | .Cases("SIZE","size",IOK_SIZE) |
1647 | 844 | .Cases("LENGTH","length",IOK_LENGTH) |
1648 | 844 | .Cases("OFFSET","offset",IOK_OFFSET) |
1649 | 844 | .Default(IOK_INVALID); |
1650 | 844 | } |
1651 | | |
1652 | | /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator |
1653 | | /// returns the number of elements in an array. It returns the value 1 for |
1654 | | /// non-array variables. The SIZE operator returns the size of a C or C++ |
1655 | | /// variable. A variable's size is the product of its LENGTH and TYPE. The |
1656 | | /// TYPE operator returns the size of a C or C++ type or variable. If the |
1657 | | /// variable is an array, TYPE returns the size of a single element. |
1658 | 33 | unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) { |
1659 | 33 | MCAsmParser &Parser = getParser(); |
1660 | 33 | const AsmToken &Tok = Parser.getTok(); |
1661 | 33 | Parser.Lex(); // Eat operator. |
1662 | 33 | |
1663 | 33 | const MCExpr *Val = nullptr; |
1664 | 33 | InlineAsmIdentifierInfo Info; |
1665 | 33 | SMLoc Start = Tok.getLoc(), End; |
1666 | 33 | StringRef Identifier = Tok.getString(); |
1667 | 33 | if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, |
1668 | 33 | /*Unevaluated=*/true, End)) |
1669 | 0 | return 0; |
1670 | 33 | |
1671 | 33 | if (33 !Info.OpDecl33 ) { |
1672 | 3 | Error(Start, "unable to lookup expression"); |
1673 | 3 | return 0; |
1674 | 3 | } |
1675 | 30 | |
1676 | 30 | unsigned CVal = 0; |
1677 | 30 | switch(OpKind) { |
1678 | 0 | default: 0 llvm_unreachable0 ("Unexpected operand kind!"); |
1679 | 10 | case IOK_LENGTH: CVal = Info.Length; break; |
1680 | 10 | case IOK_SIZE: CVal = Info.Size; break; |
1681 | 10 | case IOK_TYPE: CVal = Info.Type; break; |
1682 | 30 | } |
1683 | 30 | |
1684 | 30 | return CVal; |
1685 | 30 | } |
1686 | | |
1687 | 30.7k | bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) { |
1688 | 30.7k | Size = StringSwitch<unsigned>(getTok().getString()) |
1689 | 30.7k | .Cases("BYTE", "byte", 8) |
1690 | 30.7k | .Cases("WORD", "word", 16) |
1691 | 30.7k | .Cases("DWORD", "dword", 32) |
1692 | 30.7k | .Cases("FLOAT", "float", 32) |
1693 | 30.7k | .Cases("LONG", "long", 32) |
1694 | 30.7k | .Cases("FWORD", "fword", 48) |
1695 | 30.7k | .Cases("DOUBLE", "double", 64) |
1696 | 30.7k | .Cases("QWORD", "qword", 64) |
1697 | 30.7k | .Cases("MMWORD","mmword", 64) |
1698 | 30.7k | .Cases("XWORD", "xword", 80) |
1699 | 30.7k | .Cases("TBYTE", "tbyte", 80) |
1700 | 30.7k | .Cases("XMMWORD", "xmmword", 128) |
1701 | 30.7k | .Cases("YMMWORD", "ymmword", 256) |
1702 | 30.7k | .Cases("ZMMWORD", "zmmword", 512) |
1703 | 30.7k | .Cases("OPAQUE", "opaque", -1U) // needs to be non-zero, but doesn't matter |
1704 | 30.7k | .Default(0); |
1705 | 30.7k | if (Size30.7k ) { |
1706 | 6.89k | const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word). |
1707 | 6.89k | if (!(Tok.getString().equals("PTR") || 6.89k Tok.getString().equals("ptr")6.66k )) |
1708 | 1 | return Error(Tok.getLoc(), "Expected 'PTR' or 'ptr' token!"); |
1709 | 6.89k | Lex(); // Eat ptr. |
1710 | 6.89k | } |
1711 | 30.7k | return false; |
1712 | 30.7k | } |
1713 | | |
1714 | 30.7k | std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() { |
1715 | 30.7k | MCAsmParser &Parser = getParser(); |
1716 | 30.7k | const AsmToken &Tok = Parser.getTok(); |
1717 | 30.7k | SMLoc Start, End; |
1718 | 30.7k | |
1719 | 30.7k | // FIXME: Offset operator |
1720 | 30.7k | // Should be handled as part of immediate expression, as other operators |
1721 | 30.7k | // Currently, only supported as a stand-alone operand |
1722 | 30.7k | if (isParsingInlineAsm()) |
1723 | 636 | if (636 IdentifyIntelInlineAsmOperator(Tok.getString()) == IOK_OFFSET636 ) |
1724 | 7 | return ParseIntelOffsetOfOperator(); |
1725 | 30.7k | |
1726 | 30.7k | // Parse optional Size directive. |
1727 | 30.7k | unsigned Size; |
1728 | 30.7k | if (ParseIntelMemoryOperandSize(Size)) |
1729 | 1 | return nullptr; |
1730 | 30.7k | bool PtrInOperand = bool(Size); |
1731 | 30.7k | |
1732 | 30.7k | Start = Tok.getLoc(); |
1733 | 30.7k | |
1734 | 30.7k | // Rounding mode operand. |
1735 | 30.7k | if (getSTI().getFeatureBits()[X86::FeatureAVX512] && |
1736 | 28.9k | getLexer().is(AsmToken::LCurly)) |
1737 | 1.16k | return ParseRoundingModeOp(Start, End); |
1738 | 29.5k | |
1739 | 29.5k | // Register operand. |
1740 | 29.5k | unsigned RegNo = 0; |
1741 | 29.5k | if (Tok.is(AsmToken::Identifier) && 29.5k !ParseRegister(RegNo, Start, End)20.4k ) { |
1742 | 20.3k | if (RegNo == X86::RIP) |
1743 | 1 | return ErrorOperand(Start, "rip can only be used as a base register"); |
1744 | 20.3k | // A Register followed by ':' is considered a segment override |
1745 | 20.3k | if (20.3k Tok.isNot(AsmToken::Colon)20.3k ) |
1746 | 20.3k | return !PtrInOperand ? 20.3k X86Operand::CreateReg(RegNo, Start, End)20.3k : |
1747 | 3 | ErrorOperand(Start, "expected memory operand after 'ptr', " |
1748 | 3 | "found register operand instead"); |
1749 | 14 | // An alleged segment override. check if we have a valid segment register |
1750 | 14 | if (14 !X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo)14 ) |
1751 | 0 | return ErrorOperand(Start, "invalid segment register"); |
1752 | 14 | // Eat ':' and update Start location |
1753 | 14 | Start = Lex().getLoc(); |
1754 | 14 | } |
1755 | 29.5k | |
1756 | 29.5k | // Immediates and Memory |
1757 | 9.22k | IntelExprStateMachine SM; |
1758 | 9.22k | if (ParseIntelExpression(SM, End)) |
1759 | 27 | return nullptr; |
1760 | 9.20k | |
1761 | 9.20k | if (9.20k isParsingInlineAsm()9.20k ) |
1762 | 283 | RewriteIntelExpression(SM, Start, Tok.getLoc()); |
1763 | 9.20k | |
1764 | 9.20k | int64_t Imm = SM.getImm(); |
1765 | 9.20k | const MCExpr *Disp = SM.getSym(); |
1766 | 9.20k | const MCExpr *ImmDisp = MCConstantExpr::create(Imm, getContext()); |
1767 | 9.20k | if (Disp && 9.20k Imm178 ) |
1768 | 35 | Disp = MCBinaryExpr::createAdd(Disp, ImmDisp, getContext()); |
1769 | 9.20k | if (!Disp) |
1770 | 9.02k | Disp = ImmDisp; |
1771 | 9.20k | |
1772 | 9.20k | // RegNo != 0 specifies a valid segment register, |
1773 | 9.20k | // and we are parsing a segment override |
1774 | 9.20k | if (!SM.isMemExpr() && 9.20k !RegNo1.90k ) |
1775 | 1.90k | return X86Operand::CreateImm(Disp, Start, End); |
1776 | 7.29k | |
1777 | 7.29k | StringRef ErrMsg; |
1778 | 7.29k | unsigned BaseReg = SM.getBaseReg(); |
1779 | 7.29k | unsigned IndexReg = SM.getIndexReg(); |
1780 | 7.29k | unsigned Scale = SM.getScale(); |
1781 | 7.29k | |
1782 | 7.29k | if ((BaseReg || 7.29k IndexReg208 ) && |
1783 | 7.10k | CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, ErrMsg)) |
1784 | 2 | return ErrorOperand(Start, ErrMsg); |
1785 | 7.29k | if (7.29k isParsingInlineAsm()7.29k ) |
1786 | 185 | return CreateMemForInlineAsm(RegNo, Disp, BaseReg, IndexReg, |
1787 | 185 | Scale, Start, End, Size, SM.getSymName(), |
1788 | 185 | SM.getIdentifierInfo()); |
1789 | 7.11k | if (7.11k !(BaseReg || 7.11k IndexReg56 || RegNo39 )) |
1790 | 35 | return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size); |
1791 | 7.07k | return X86Operand::CreateMem(getPointerWidth(), RegNo, Disp, |
1792 | 7.07k | BaseReg, IndexReg, Scale, Start, End, Size); |
1793 | 7.07k | } |
1794 | | |
1795 | 84.8k | std::unique_ptr<X86Operand> X86AsmParser::ParseATTOperand() { |
1796 | 84.8k | MCAsmParser &Parser = getParser(); |
1797 | 84.8k | switch (getLexer().getKind()) { |
1798 | 21.4k | default: |
1799 | 21.4k | // Parse a memory operand with no segment register. |
1800 | 21.4k | return ParseMemOperand(0, Parser.getTok().getLoc()); |
1801 | 57.4k | case AsmToken::Percent: { |
1802 | 57.4k | // Read the register. |
1803 | 57.4k | unsigned RegNo; |
1804 | 57.4k | SMLoc Start, End; |
1805 | 57.4k | if (ParseRegister(RegNo, Start, End)57.4k ) return nullptr9 ; |
1806 | 57.4k | if (57.4k RegNo == X86::EIZ || 57.4k RegNo == X86::RIZ57.4k ) { |
1807 | 0 | Error(Start, "%eiz and %riz can only be used as index registers", |
1808 | 0 | SMRange(Start, End)); |
1809 | 0 | return nullptr; |
1810 | 0 | } |
1811 | 57.4k | if (57.4k RegNo == X86::RIP57.4k ) { |
1812 | 1 | Error(Start, "%rip can only be used as a base register", |
1813 | 1 | SMRange(Start, End)); |
1814 | 1 | return nullptr; |
1815 | 1 | } |
1816 | 57.4k | |
1817 | 57.4k | // If this is a segment register followed by a ':', then this is the start |
1818 | 57.4k | // of a memory reference, otherwise this is a normal register reference. |
1819 | 57.4k | if (57.4k getLexer().isNot(AsmToken::Colon)57.4k ) |
1820 | 57.2k | return X86Operand::CreateReg(RegNo, Start, End); |
1821 | 215 | |
1822 | 215 | if (215 !X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo)215 ) |
1823 | 2 | return ErrorOperand(Start, "invalid segment register"); |
1824 | 213 | |
1825 | 213 | getParser().Lex(); // Eat the colon. |
1826 | 213 | return ParseMemOperand(RegNo, Start); |
1827 | 213 | } |
1828 | 5.29k | case AsmToken::Dollar: { |
1829 | 5.29k | // $42 -> immediate. |
1830 | 5.29k | SMLoc Start = Parser.getTok().getLoc(), End; |
1831 | 5.29k | Parser.Lex(); |
1832 | 5.29k | const MCExpr *Val; |
1833 | 5.29k | if (getParser().parseExpression(Val, End)) |
1834 | 3 | return nullptr; |
1835 | 5.29k | return X86Operand::CreateImm(Val, Start, End); |
1836 | 5.29k | } |
1837 | 621 | case AsmToken::LCurly:{ |
1838 | 621 | SMLoc Start = Parser.getTok().getLoc(), End; |
1839 | 621 | if (getSTI().getFeatureBits()[X86::FeatureAVX512]) |
1840 | 621 | return ParseRoundingModeOp(Start, End); |
1841 | 0 | return ErrorOperand(Start, "Unexpected '{' in expression"); |
1842 | 0 | } |
1843 | 84.8k | } |
1844 | 84.8k | } |
1845 | | |
1846 | | // true on failure, false otherwise |
1847 | | // If no {z} mark was found - Parser doesn't advance |
1848 | | bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z, |
1849 | 6.93k | const SMLoc &StartLoc) { |
1850 | 6.93k | MCAsmParser &Parser = getParser(); |
1851 | 6.93k | // Assuming we are just pass the '{' mark, quering the next token |
1852 | 6.93k | // Searched for {z}, but none was found. Return false, as no parsing error was |
1853 | 6.93k | // encountered |
1854 | 6.93k | if (!(getLexer().is(AsmToken::Identifier) && |
1855 | 3.71k | (getLexer().getTok().getIdentifier() == "z"))) |
1856 | 4.91k | return false; |
1857 | 2.02k | Parser.Lex(); // Eat z |
1858 | 2.02k | // Query and eat the '}' mark |
1859 | 2.02k | if (!getLexer().is(AsmToken::RCurly)) |
1860 | 0 | return Error(getLexer().getLoc(), "Expected } at this point"); |
1861 | 2.02k | Parser.Lex(); // Eat '}' |
1862 | 2.02k | // Assign Z with the {z} mark opernad |
1863 | 2.02k | Z = X86Operand::CreateToken("{z}", StartLoc); |
1864 | 2.02k | return false; |
1865 | 2.02k | } |
1866 | | |
1867 | | // true on failure, false otherwise |
1868 | | bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands, |
1869 | 115k | const MCParsedAsmOperand &Op) { |
1870 | 115k | MCAsmParser &Parser = getParser(); |
1871 | 115k | if(getSTI().getFeatureBits()[X86::FeatureAVX512]115k ) { |
1872 | 79.7k | if (getLexer().is(AsmToken::LCurly)79.7k ) { |
1873 | 10.1k | // Eat "{" and mark the current place. |
1874 | 10.1k | const SMLoc consumedToken = consumeToken(); |
1875 | 10.1k | // Distinguish {1to<NUM>} from {%k<NUM>}. |
1876 | 10.1k | if(getLexer().is(AsmToken::Integer)10.1k ) { |
1877 | 5.19k | // Parse memory broadcasting ({1to<NUM>}). |
1878 | 5.19k | if (getLexer().getTok().getIntVal() != 1) |
1879 | 0 | return TokError("Expected 1to<NUM> at this point"); |
1880 | 5.19k | Parser.Lex(); // Eat "1" of 1to8 |
1881 | 5.19k | if (!getLexer().is(AsmToken::Identifier) || |
1882 | 5.19k | !getLexer().getTok().getIdentifier().startswith("to")) |
1883 | 0 | return TokError("Expected 1to<NUM> at this point"); |
1884 | 5.19k | // Recognize only reasonable suffixes. |
1885 | 5.19k | const char *BroadcastPrimitive = |
1886 | 5.19k | StringSwitch<const char*>(getLexer().getTok().getIdentifier()) |
1887 | 5.19k | .Case("to2", "{1to2}") |
1888 | 5.19k | .Case("to4", "{1to4}") |
1889 | 5.19k | .Case("to8", "{1to8}") |
1890 | 5.19k | .Case("to16", "{1to16}") |
1891 | 5.19k | .Default(nullptr); |
1892 | 5.19k | if (!BroadcastPrimitive) |
1893 | 0 | return TokError("Invalid memory broadcast primitive."); |
1894 | 5.19k | Parser.Lex(); // Eat "toN" of 1toN |
1895 | 5.19k | if (!getLexer().is(AsmToken::RCurly)) |
1896 | 0 | return TokError("Expected } at this point"); |
1897 | 5.19k | Parser.Lex(); // Eat "}" |
1898 | 5.19k | Operands.push_back(X86Operand::CreateToken(BroadcastPrimitive, |
1899 | 5.19k | consumedToken)); |
1900 | 5.19k | // No AVX512 specific primitives can pass |
1901 | 5.19k | // after memory broadcasting, so return. |
1902 | 5.19k | return false; |
1903 | 0 | } else { |
1904 | 4.91k | // Parse either {k}{z}, {z}{k}, {k} or {z} |
1905 | 4.91k | // last one have no meaning, but GCC accepts it |
1906 | 4.91k | // Currently, we're just pass a '{' mark |
1907 | 4.91k | std::unique_ptr<X86Operand> Z; |
1908 | 4.91k | if (ParseZ(Z, consumedToken)) |
1909 | 0 | return true; |
1910 | 4.91k | // Reaching here means that parsing of the allegadly '{z}' mark yielded |
1911 | 4.91k | // no errors. |
1912 | 4.91k | // Query for the need of further parsing for a {%k<NUM>} mark |
1913 | 4.91k | if (4.91k !Z || 4.91k getLexer().is(AsmToken::LCurly)2 ) { |
1914 | 4.91k | SMLoc StartLoc = Z ? consumeToken()2 : consumedToken4.91k ; |
1915 | 4.91k | // Parse an op-mask register mark ({%k<NUM>}), which is now to be |
1916 | 4.91k | // expected |
1917 | 4.91k | unsigned RegNo; |
1918 | 4.91k | SMLoc RegLoc; |
1919 | 4.91k | if (!ParseRegister(RegNo, RegLoc, StartLoc) && |
1920 | 4.91k | X86MCRegisterClasses[X86::VK1RegClassID].contains(RegNo)4.91k ) { |
1921 | 4.91k | if (RegNo == X86::K0) |
1922 | 2 | return Error(RegLoc, "Register k0 can't be used as write mask"); |
1923 | 4.91k | if (4.91k !getLexer().is(AsmToken::RCurly)4.91k ) |
1924 | 0 | return Error(getLexer().getLoc(), "Expected } at this point"); |
1925 | 4.91k | Operands.push_back(X86Operand::CreateToken("{", StartLoc)); |
1926 | 4.91k | Operands.push_back( |
1927 | 4.91k | X86Operand::CreateReg(RegNo, StartLoc, StartLoc)); |
1928 | 4.91k | Operands.push_back(X86Operand::CreateToken("}", consumeToken())); |
1929 | 4.91k | } else |
1930 | 3 | return Error(getLexer().getLoc(), |
1931 | 3 | "Expected an op-mask register at this point"); |
1932 | 4.91k | // {%k<NUM>} mark is found, inquire for {z} |
1933 | 4.91k | if (4.91k getLexer().is(AsmToken::LCurly) && 4.91k !Z2.02k ) { |
1934 | 2.02k | // Have we've found a parsing error, or found no (expected) {z} mark |
1935 | 2.02k | // - report an error |
1936 | 2.02k | if (ParseZ(Z, consumeToken()) || 2.02k !Z2.02k ) |
1937 | 2 | return Error(getLexer().getLoc(), |
1938 | 2 | "Expected a {z} mark at this point"); |
1939 | 4.91k | |
1940 | 4.91k | } |
1941 | 4.91k | // '{z}' on its own is meaningless, hence should be ignored. |
1942 | 4.91k | // on the contrary - have it been accompanied by a K register, |
1943 | 4.91k | // allow it. |
1944 | 4.91k | if (4.91k Z4.91k ) |
1945 | 2.02k | Operands.push_back(std::move(Z)); |
1946 | 4.91k | } |
1947 | 4.91k | } |
1948 | 10.1k | } |
1949 | 79.7k | } |
1950 | 110k | return false; |
1951 | 115k | } |
1952 | | |
1953 | | /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix |
1954 | | /// has already been parsed if present. |
1955 | | std::unique_ptr<X86Operand> X86AsmParser::ParseMemOperand(unsigned SegReg, |
1956 | 21.6k | SMLoc MemStart) { |
1957 | 21.6k | |
1958 | 21.6k | MCAsmParser &Parser = getParser(); |
1959 | 21.6k | // We have to disambiguate a parenthesized expression "(4+5)" from the start |
1960 | 21.6k | // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The |
1961 | 21.6k | // only way to do this without lookahead is to eat the '(' and see what is |
1962 | 21.6k | // after it. |
1963 | 21.6k | const MCExpr *Disp = MCConstantExpr::create(0, getParser().getContext()); |
1964 | 21.6k | if (getLexer().isNot(AsmToken::LParen)21.6k ) { |
1965 | 17.5k | SMLoc ExprEnd; |
1966 | 17.5k | if (getParser().parseExpression(Disp, ExprEnd)17.5k ) return nullptr9 ; |
1967 | 17.5k | |
1968 | 17.5k | // After parsing the base expression we could either have a parenthesized |
1969 | 17.5k | // memory address or not. If not, return now. If so, eat the (. |
1970 | 17.5k | if (17.5k getLexer().isNot(AsmToken::LParen)17.5k ) { |
1971 | 4.67k | // Unless we have a segment register, treat this as an immediate. |
1972 | 4.67k | if (SegReg == 0) |
1973 | 4.62k | return X86Operand::CreateMem(getPointerWidth(), Disp, MemStart, ExprEnd); |
1974 | 48 | return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1, |
1975 | 48 | MemStart, ExprEnd); |
1976 | 48 | } |
1977 | 12.8k | |
1978 | 12.8k | // Eat the '('. |
1979 | 12.8k | Parser.Lex(); |
1980 | 21.6k | } else { |
1981 | 4.17k | // Okay, we have a '('. We don't know if this is an expression or not, but |
1982 | 4.17k | // so we have to eat the ( to see beyond it. |
1983 | 4.17k | SMLoc LParenLoc = Parser.getTok().getLoc(); |
1984 | 4.17k | Parser.Lex(); // Eat the '('. |
1985 | 4.17k | |
1986 | 4.17k | if (getLexer().is(AsmToken::Percent) || 4.17k getLexer().is(AsmToken::Comma)96 ) { |
1987 | 4.07k | // Nothing to do here, fall into the code below with the '(' part of the |
1988 | 4.07k | // memory operand consumed. |
1989 | 4.17k | } else { |
1990 | 93 | SMLoc ExprEnd; |
1991 | 93 | getLexer().UnLex(AsmToken(AsmToken::LParen, "(")); |
1992 | 93 | |
1993 | 93 | // It must be either an parenthesized expression, or an expression that |
1994 | 93 | // begins from a parenthesized expression, parse it now. Example: (1+2) or |
1995 | 93 | // (1+2)+3 |
1996 | 93 | if (getParser().parseExpression(Disp, ExprEnd)) |
1997 | 0 | return nullptr; |
1998 | 93 | |
1999 | 93 | // After parsing the base expression we could either have a parenthesized |
2000 | 93 | // memory address or not. If not, return now. If so, eat the (. |
2001 | 93 | if (93 getLexer().isNot(AsmToken::LParen)93 ) { |
2002 | 7 | // Unless we have a segment register, treat this as an immediate. |
2003 | 7 | if (SegReg == 0) |
2004 | 7 | return X86Operand::CreateMem(getPointerWidth(), Disp, LParenLoc, |
2005 | 7 | ExprEnd); |
2006 | 0 | return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1, |
2007 | 0 | MemStart, ExprEnd); |
2008 | 0 | } |
2009 | 86 | |
2010 | 86 | // Eat the '('. |
2011 | 86 | Parser.Lex(); |
2012 | 86 | } |
2013 | 4.17k | } |
2014 | 21.6k | |
2015 | 21.6k | // If we reached here, then we just ate the ( of the memory operand. Process |
2016 | 21.6k | // the rest of the memory operand. |
2017 | 16.9k | unsigned BaseReg = 0, IndexReg = 0, Scale = 1; |
2018 | 16.9k | SMLoc IndexLoc, BaseLoc; |
2019 | 16.9k | |
2020 | 16.9k | if (getLexer().is(AsmToken::Percent)16.9k ) { |
2021 | 16.9k | SMLoc StartLoc, EndLoc; |
2022 | 16.9k | BaseLoc = Parser.getTok().getLoc(); |
2023 | 16.9k | if (ParseRegister(BaseReg, StartLoc, EndLoc)16.9k ) return nullptr11 ; |
2024 | 16.9k | if (16.9k BaseReg == X86::EIZ || 16.9k BaseReg == X86::RIZ16.9k ) { |
2025 | 0 | Error(StartLoc, "eiz and riz can only be used as index registers", |
2026 | 0 | SMRange(StartLoc, EndLoc)); |
2027 | 0 | return nullptr; |
2028 | 0 | } |
2029 | 16.9k | } |
2030 | 16.9k | |
2031 | 16.9k | if (16.9k getLexer().is(AsmToken::Comma)16.9k ) { |
2032 | 3.09k | Parser.Lex(); // Eat the comma. |
2033 | 3.09k | IndexLoc = Parser.getTok().getLoc(); |
2034 | 3.09k | |
2035 | 3.09k | // Following the comma we should have either an index register, or a scale |
2036 | 3.09k | // value. We don't support the later form, but we want to parse it |
2037 | 3.09k | // correctly. |
2038 | 3.09k | // |
2039 | 3.09k | // Not that even though it would be completely consistent to support syntax |
2040 | 3.09k | // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this. |
2041 | 3.09k | if (getLexer().is(AsmToken::Percent)3.09k ) { |
2042 | 3.09k | SMLoc L; |
2043 | 3.09k | if (ParseRegister(IndexReg, L, L)) |
2044 | 0 | return nullptr; |
2045 | 3.09k | if (3.09k BaseReg == X86::RIP3.09k ) { |
2046 | 0 | Error(IndexLoc, "%rip as base register can not have an index register"); |
2047 | 0 | return nullptr; |
2048 | 0 | } |
2049 | 3.09k | if (3.09k IndexReg == X86::RIP3.09k ) { |
2050 | 1 | Error(IndexLoc, "%rip is not allowed as an index register"); |
2051 | 1 | return nullptr; |
2052 | 1 | } |
2053 | 3.09k | |
2054 | 3.09k | if (3.09k getLexer().isNot(AsmToken::RParen)3.09k ) { |
2055 | 2.90k | // Parse the scale amount: |
2056 | 2.90k | // ::= ',' [scale-expression] |
2057 | 2.90k | if (getLexer().isNot(AsmToken::Comma)2.90k ) { |
2058 | 0 | Error(Parser.getTok().getLoc(), |
2059 | 0 | "expected comma in scale expression"); |
2060 | 0 | return nullptr; |
2061 | 0 | } |
2062 | 2.90k | Parser.Lex(); // Eat the comma. |
2063 | 2.90k | |
2064 | 2.90k | if (getLexer().isNot(AsmToken::RParen)2.90k ) { |
2065 | 2.90k | SMLoc Loc = Parser.getTok().getLoc(); |
2066 | 2.90k | |
2067 | 2.90k | int64_t ScaleVal; |
2068 | 2.90k | if (getParser().parseAbsoluteExpression(ScaleVal)2.90k ){ |
2069 | 1 | Error(Loc, "expected scale expression"); |
2070 | 1 | return nullptr; |
2071 | 1 | } |
2072 | 2.90k | |
2073 | 2.90k | // Validate the scale amount. |
2074 | 2.90k | if (2.90k X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) && |
2075 | 2.90k | ScaleVal != 14 ) { |
2076 | 2 | Error(Loc, "scale factor in 16-bit address must be 1"); |
2077 | 2 | return nullptr; |
2078 | 2 | } |
2079 | 2.90k | if (2.90k ScaleVal != 1 && 2.90k ScaleVal != 22.89k && ScaleVal != 42.86k && |
2080 | 2.90k | ScaleVal != 82.78k ) { |
2081 | 0 | Error(Loc, "scale factor in address must be 1, 2, 4 or 8"); |
2082 | 0 | return nullptr; |
2083 | 0 | } |
2084 | 2.90k | Scale = (unsigned)ScaleVal; |
2085 | 2.90k | } |
2086 | 2.90k | } |
2087 | 3.09k | } else if (4 getLexer().isNot(AsmToken::RParen)4 ) { |
2088 | 3 | // A scale amount without an index is ignored. |
2089 | 3 | // index. |
2090 | 3 | SMLoc Loc = Parser.getTok().getLoc(); |
2091 | 3 | |
2092 | 3 | int64_t Value; |
2093 | 3 | if (getParser().parseAbsoluteExpression(Value)) |
2094 | 0 | return nullptr; |
2095 | 3 | |
2096 | 3 | if (3 Value != 13 ) |
2097 | 3 | Warning(Loc, "scale factor without index register is ignored"); |
2098 | 4 | Scale = 1; |
2099 | 4 | } |
2100 | 3.09k | } |
2101 | 16.9k | |
2102 | 16.9k | // Ok, we've eaten the memory operand, verify we have a ')' and eat it too. |
2103 | 16.9k | if (16.9k getLexer().isNot(AsmToken::RParen)16.9k ) { |
2104 | 0 | Error(Parser.getTok().getLoc(), "unexpected token in memory operand"); |
2105 | 0 | return nullptr; |
2106 | 0 | } |
2107 | 16.9k | SMLoc MemEnd = Parser.getTok().getEndLoc(); |
2108 | 16.9k | Parser.Lex(); // Eat the ')'. |
2109 | 16.9k | |
2110 | 16.9k | // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed, |
2111 | 16.9k | // and then only in non-64-bit modes. Except for DX, which is a special case |
2112 | 16.9k | // because an unofficial form of in/out instructions uses it. |
2113 | 16.9k | if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) && |
2114 | 106 | (is64BitMode() || 106 (BaseReg != X86::BX && 79 BaseReg != X86::BP76 && |
2115 | 106 | BaseReg != X86::SI73 && BaseReg != X86::DI43 )) && |
2116 | 16.9k | BaseReg != X86::DX48 ) { |
2117 | 8 | Error(BaseLoc, "invalid 16-bit base register"); |
2118 | 8 | return nullptr; |
2119 | 8 | } |
2120 | 16.9k | if (16.9k BaseReg == 0 && |
2121 | 16.9k | X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)28 ) { |
2122 | 2 | Error(IndexLoc, "16-bit memory operand may not include only index register"); |
2123 | 2 | return nullptr; |
2124 | 2 | } |
2125 | 16.9k | |
2126 | 16.9k | StringRef ErrMsg; |
2127 | 16.9k | if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, ErrMsg)16.9k ) { |
2128 | 2 | Error(BaseLoc, ErrMsg); |
2129 | 2 | return nullptr; |
2130 | 2 | } |
2131 | 16.9k | |
2132 | 16.9k | if (16.9k SegReg || 16.9k BaseReg16.8k || IndexReg26 ) |
2133 | 16.9k | return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg, |
2134 | 16.9k | IndexReg, Scale, MemStart, MemEnd); |
2135 | 2 | return X86Operand::CreateMem(getPointerWidth(), Disp, MemStart, MemEnd); |
2136 | 2 | } |
2137 | | |
2138 | | bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, |
2139 | 52.7k | SMLoc NameLoc, OperandVector &Operands) { |
2140 | 52.7k | MCAsmParser &Parser = getParser(); |
2141 | 52.7k | InstInfo = &Info; |
2142 | 52.7k | StringRef PatchedName = Name; |
2143 | 52.7k | |
2144 | 52.7k | if ((Name.equals("jmp") || 52.7k Name.equals("jc")52.6k || Name.equals("jz")52.6k ) && |
2145 | 52.7k | isParsingIntelSyntax()183 && isParsingInlineAsm()20 ) { |
2146 | 13 | StringRef NextTok = Parser.getTok().getString(); |
2147 | 13 | if (NextTok == "short"13 ) { |
2148 | 3 | SMLoc NameEndLoc = |
2149 | 3 | NameLoc.getFromPointer(NameLoc.getPointer() + Name.size()); |
2150 | 3 | // Eat the short keyword |
2151 | 3 | Parser.Lex(); |
2152 | 3 | // MS ignores the short keyword, it determines the jmp type based |
2153 | 3 | // on the distance of the label |
2154 | 3 | InstInfo->AsmRewrites->emplace_back(AOK_Skip, NameEndLoc, |
2155 | 3 | NextTok.size() + 1); |
2156 | 3 | } |
2157 | 13 | } |
2158 | 52.7k | |
2159 | 52.7k | // FIXME: Hack to recognize setneb as setne. |
2160 | 52.7k | if (PatchedName.startswith("set") && 52.7k PatchedName.endswith("b")210 && |
2161 | 52.7k | PatchedName != "setb"19 && PatchedName != "setnb"9 ) |
2162 | 6 | PatchedName = PatchedName.substr(0, Name.size()-1); |
2163 | 52.7k | |
2164 | 52.7k | // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}. |
2165 | 52.7k | if ((PatchedName.startswith("cmp") || 52.7k PatchedName.startswith("vcmp")52.5k ) && |
2166 | 1.08k | (PatchedName.endswith("ss") || 1.08k PatchedName.endswith("sd")968 || |
2167 | 52.7k | PatchedName.endswith("ps")852 || PatchedName.endswith("pd")506 )) { |
2168 | 878 | bool IsVCMP = PatchedName[0] == 'v'; |
2169 | 878 | unsigned CCIdx = IsVCMP ? 4855 : 323 ; |
2170 | 878 | unsigned ComparisonCode = StringSwitch<unsigned>( |
2171 | 878 | PatchedName.slice(CCIdx, PatchedName.size() - 2)) |
2172 | 878 | .Case("eq", 0x00) |
2173 | 878 | .Case("eq_oq", 0x00) |
2174 | 878 | .Case("lt", 0x01) |
2175 | 878 | .Case("lt_os", 0x01) |
2176 | 878 | .Case("le", 0x02) |
2177 | 878 | .Case("le_os", 0x02) |
2178 | 878 | .Case("unord", 0x03) |
2179 | 878 | .Case("unord_q", 0x03) |
2180 | 878 | .Case("neq", 0x04) |
2181 | 878 | .Case("neq_uq", 0x04) |
2182 | 878 | .Case("nlt", 0x05) |
2183 | 878 | .Case("nlt_us", 0x05) |
2184 | 878 | .Case("nle", 0x06) |
2185 | 878 | .Case("nle_us", 0x06) |
2186 | 878 | .Case("ord", 0x07) |
2187 | 878 | .Case("ord_q", 0x07) |
2188 | 878 | /* AVX only from here */ |
2189 | 878 | .Case("eq_uq", 0x08) |
2190 | 878 | .Case("nge", 0x09) |
2191 | 878 | .Case("nge_us", 0x09) |
2192 | 878 | .Case("ngt", 0x0A) |
2193 | 878 | .Case("ngt_us", 0x0A) |
2194 | 878 | .Case("false", 0x0B) |
2195 | 878 | .Case("false_oq", 0x0B) |
2196 | 878 | .Case("neq_oq", 0x0C) |
2197 | 878 | .Case("ge", 0x0D) |
2198 | 878 | .Case("ge_os", 0x0D) |
2199 | 878 | .Case("gt", 0x0E) |
2200 | 878 | .Case("gt_os", 0x0E) |
2201 | 878 | .Case("true", 0x0F) |
2202 | 878 | .Case("true_uq", 0x0F) |
2203 | 878 | .Case("eq_os", 0x10) |
2204 | 878 | .Case("lt_oq", 0x11) |
2205 | 878 | .Case("le_oq", 0x12) |
2206 | 878 | .Case("unord_s", 0x13) |
2207 | 878 | .Case("neq_us", 0x14) |
2208 | 878 | .Case("nlt_uq", 0x15) |
2209 | 878 | .Case("nle_uq", 0x16) |
2210 | 878 | .Case("ord_s", 0x17) |
2211 | 878 | .Case("eq_us", 0x18) |
2212 | 878 | .Case("nge_uq", 0x19) |
2213 | 878 | .Case("ngt_uq", 0x1A) |
2214 | 878 | .Case("false_os", 0x1B) |
2215 | 878 | .Case("neq_os", 0x1C) |
2216 | 878 | .Case("ge_oq", 0x1D) |
2217 | 878 | .Case("gt_oq", 0x1E) |
2218 | 878 | .Case("true_us", 0x1F) |
2219 | 878 | .Default(~0U); |
2220 | 878 | if (ComparisonCode != ~0U && 878 (IsVCMP || 544 ComparisonCode < 810 )) { |
2221 | 544 | |
2222 | 544 | Operands.push_back(X86Operand::CreateToken(PatchedName.slice(0, CCIdx), |
2223 | 544 | NameLoc)); |
2224 | 544 | |
2225 | 544 | const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode, |
2226 | 544 | getParser().getContext()); |
2227 | 544 | Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc)); |
2228 | 544 | |
2229 | 544 | PatchedName = PatchedName.substr(PatchedName.size() - 2); |
2230 | 544 | } |
2231 | 878 | } |
2232 | 52.7k | |
2233 | 52.7k | // FIXME: Hack to recognize vpcmp<comparison code>{ub,uw,ud,uq,b,w,d,q}. |
2234 | 52.7k | if (PatchedName.startswith("vpcmp") && |
2235 | 1.26k | (PatchedName.endswith("b") || 1.26k PatchedName.endswith("w")1.06k || |
2236 | 52.7k | PatchedName.endswith("d")862 || PatchedName.endswith("q")438 )) { |
2237 | 1.24k | unsigned CCIdx = PatchedName.drop_back().back() == 'u' ? 2453 : 1795 ; |
2238 | 1.24k | unsigned ComparisonCode = StringSwitch<unsigned>( |
2239 | 1.24k | PatchedName.slice(5, PatchedName.size() - CCIdx)) |
2240 | 1.24k | .Case("eq", 0x0) // Only allowed on unsigned. Checked below. |
2241 | 1.24k | .Case("lt", 0x1) |
2242 | 1.24k | .Case("le", 0x2) |
2243 | 1.24k | //.Case("false", 0x3) // Not a documented alias. |
2244 | 1.24k | .Case("neq", 0x4) |
2245 | 1.24k | .Case("nlt", 0x5) |
2246 | 1.24k | .Case("nle", 0x6) |
2247 | 1.24k | //.Case("true", 0x7) // Not a documented alias. |
2248 | 1.24k | .Default(~0U); |
2249 | 1.24k | if (ComparisonCode != ~0U && 1.24k (ComparisonCode != 0 || 663 CCIdx == 2237 )) { |
2250 | 469 | Operands.push_back(X86Operand::CreateToken("vpcmp", NameLoc)); |
2251 | 469 | |
2252 | 469 | const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode, |
2253 | 469 | getParser().getContext()); |
2254 | 469 | Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc)); |
2255 | 469 | |
2256 | 469 | PatchedName = PatchedName.substr(PatchedName.size() - CCIdx); |
2257 | 469 | } |
2258 | 1.24k | } |
2259 | 52.7k | |
2260 | 52.7k | // FIXME: Hack to recognize vpcom<comparison code>{ub,uw,ud,uq,b,w,d,q}. |
2261 | 52.7k | if (PatchedName.startswith("vpcom") && |
2262 | 72 | (PatchedName.endswith("b") || 72 PatchedName.endswith("w")68 || |
2263 | 52.7k | PatchedName.endswith("d")48 || PatchedName.endswith("q")24 )) { |
2264 | 72 | unsigned CCIdx = PatchedName.drop_back().back() == 'u' ? 216 : 156 ; |
2265 | 72 | unsigned ComparisonCode = StringSwitch<unsigned>( |
2266 | 72 | PatchedName.slice(5, PatchedName.size() - CCIdx)) |
2267 | 72 | .Case("lt", 0x0) |
2268 | 72 | .Case("le", 0x1) |
2269 | 72 | .Case("gt", 0x2) |
2270 | 72 | .Case("ge", 0x3) |
2271 | 72 | .Case("eq", 0x4) |
2272 | 72 | .Case("neq", 0x5) |
2273 | 72 | .Case("false", 0x6) |
2274 | 72 | .Case("true", 0x7) |
2275 | 72 | .Default(~0U); |
2276 | 72 | if (ComparisonCode != ~0U72 ) { |
2277 | 16 | Operands.push_back(X86Operand::CreateToken("vpcom", NameLoc)); |
2278 | 16 | |
2279 | 16 | const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode, |
2280 | 16 | getParser().getContext()); |
2281 | 16 | Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc)); |
2282 | 16 | |
2283 | 16 | PatchedName = PatchedName.substr(PatchedName.size() - CCIdx); |
2284 | 16 | } |
2285 | 72 | } |
2286 | 52.7k | |
2287 | 52.7k | Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc)); |
2288 | 52.7k | |
2289 | 52.7k | // Determine whether this is an instruction prefix. |
2290 | 52.7k | // FIXME: |
2291 | 52.7k | // Enhance prefixes integrity robustness. for example, following forms |
2292 | 52.7k | // are currently tolerated: |
2293 | 52.7k | // repz repnz <insn> ; GAS errors for the use of two similar prefixes |
2294 | 52.7k | // lock addq %rax, %rbx ; Destination operand must be of memory type |
2295 | 52.7k | // xacquire <insn> ; xacquire must be accompanied by 'lock' |
2296 | 52.7k | bool isPrefix = StringSwitch<bool>(Name) |
2297 | 52.7k | .Cases("lock", |
2298 | 52.7k | "rep", "repe", |
2299 | 52.7k | "repz", "repne", |
2300 | 52.7k | "repnz", "rex64", |
2301 | 52.7k | "data32", "data16", true) |
2302 | 52.7k | .Cases("xacquire", "xrelease", true) |
2303 | 52.7k | .Cases("acquire", "release", isParsingIntelSyntax()) |
2304 | 52.7k | .Default(false); |
2305 | 52.7k | |
2306 | 52.7k | bool CurlyAsEndOfStatement = false; |
2307 | 52.7k | // This does the actual operand parsing. Don't parse any more if we have a |
2308 | 52.7k | // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we |
2309 | 52.7k | // just want to parse the "lock" as the first instruction and the "incl" as |
2310 | 52.7k | // the next one. |
2311 | 52.7k | if (getLexer().isNot(AsmToken::EndOfStatement) && 52.7k !isPrefix48.4k ) { |
2312 | 48.3k | |
2313 | 48.3k | // Parse '*' modifier. |
2314 | 48.3k | if (getLexer().is(AsmToken::Star)) |
2315 | 106 | Operands.push_back(X86Operand::CreateToken("*", consumeToken())); |
2316 | 48.3k | |
2317 | 48.3k | // Read the operands. |
2318 | 115k | while(1115k ) { |
2319 | 115k | if (std::unique_ptr<X86Operand> Op115k = ParseOperand()) { |
2320 | 115k | Operands.push_back(std::move(Op)); |
2321 | 115k | if (HandleAVX512Operand(Operands, *Operands.back())) |
2322 | 7 | return true; |
2323 | 85 | } else { |
2324 | 85 | return true; |
2325 | 85 | } |
2326 | 115k | // check for comma and eat it |
2327 | 115k | if (115k getLexer().is(AsmToken::Comma)115k ) |
2328 | 67.1k | Parser.Lex(); |
2329 | 115k | else |
2330 | 48.2k | break; |
2331 | 115k | } |
2332 | 48.3k | |
2333 | 48.3k | // In MS inline asm curly braces mark the beginning/end of a block, |
2334 | 48.3k | // therefore they should be interepreted as end of statement |
2335 | 48.2k | CurlyAsEndOfStatement = |
2336 | 10.9k | isParsingIntelSyntax() && isParsingInlineAsm() && |
2337 | 334 | (getLexer().is(AsmToken::LCurly) || 334 getLexer().is(AsmToken::RCurly)334 ); |
2338 | 48.2k | if (getLexer().isNot(AsmToken::EndOfStatement) && 48.2k !CurlyAsEndOfStatement10 ) |
2339 | 5 | return TokError("unexpected token in argument list"); |
2340 | 52.6k | } |
2341 | 52.6k | |
2342 | 52.6k | // Consume the EndOfStatement or the prefix separator Slash |
2343 | 52.6k | if (52.6k getLexer().is(AsmToken::EndOfStatement) || |
2344 | 53 | (isPrefix && 53 getLexer().is(AsmToken::Slash)48 )) |
2345 | 52.6k | Parser.Lex(); |
2346 | 52 | else if (52 CurlyAsEndOfStatement52 ) |
2347 | 52 | // Add an actual EndOfStatement before the curly brace |
2348 | 5 | Info.AsmRewrites->emplace_back(AOK_EndOfStatement, |
2349 | 5 | getLexer().getTok().getLoc(), 0); |
2350 | 52.6k | |
2351 | 52.6k | // This is for gas compatibility and cannot be done in td. |
2352 | 52.6k | // Adding "p" for some floating point with no argument. |
2353 | 52.6k | // For example: fsub --> fsubp |
2354 | 52.6k | bool IsFp = |
2355 | 52.6k | Name == "fsub" || Name == "fdiv"52.6k || Name == "fsubr"52.6k || Name == "fdivr"52.6k ; |
2356 | 52.6k | if (IsFp && 52.6k Operands.size() == 149 ) { |
2357 | 8 | const char *Repl = StringSwitch<const char *>(Name) |
2358 | 8 | .Case("fsub", "fsubp") |
2359 | 8 | .Case("fdiv", "fdivp") |
2360 | 8 | .Case("fsubr", "fsubrp") |
2361 | 8 | .Case("fdivr", "fdivrp"); |
2362 | 8 | static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl); |
2363 | 8 | } |
2364 | 52.6k | |
2365 | 52.6k | // Moving a 32 or 16 bit value into a segment register has the same |
2366 | 52.6k | // behavior. Modify such instructions to always take shorter form. |
2367 | 52.6k | if ((Name == "mov" || 52.6k Name == "movw"52.0k || Name == "movl"52.0k ) && |
2368 | 52.6k | (Operands.size() == 3)1.92k ) { |
2369 | 1.92k | X86Operand &Op1 = (X86Operand &)*Operands[1]; |
2370 | 1.92k | X86Operand &Op2 = (X86Operand &)*Operands[2]; |
2371 | 1.92k | SMLoc Loc = Op1.getEndLoc(); |
2372 | 1.92k | if (Op1.isReg() && 1.92k Op2.isReg()743 && |
2373 | 373 | X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains( |
2374 | 373 | Op2.getReg()) && |
2375 | 8 | (X86MCRegisterClasses[X86::GR16RegClassID].contains(Op1.getReg()) || |
2376 | 1.92k | X86MCRegisterClasses[X86::GR32RegClassID].contains(Op1.getReg())4 )) { |
2377 | 8 | // Change instruction name to match new instruction. |
2378 | 8 | if (Name != "mov" && 8 Name[3] == (is16BitMode() ? 4 'l'2 : 'w'2 )) { |
2379 | 2 | Name = is16BitMode() ? "movw"1 : "movl"1 ; |
2380 | 2 | Operands[0] = X86Operand::CreateToken(Name, NameLoc); |
2381 | 2 | } |
2382 | 8 | // Select the correct equivalent 16-/32-bit source register. |
2383 | 8 | unsigned Reg = |
2384 | 8 | getX86SubSuperRegisterOrZero(Op1.getReg(), is16BitMode() ? 164 : 324 ); |
2385 | 8 | Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc); |
2386 | 8 | } |
2387 | 1.92k | } |
2388 | 52.6k | |
2389 | 52.6k | // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" -> |
2390 | 52.6k | // "outb %al, %dx". Out doesn't take a memory form, but this is a widely |
2391 | 52.6k | // documented form in various unofficial manuals, so a lot of code uses it. |
2392 | 52.6k | if ((Name == "outb" || 52.6k Name == "outsb"52.6k || Name == "outw"52.6k || Name == "outsw"52.6k || |
2393 | 52.6k | Name == "outl"52.6k || Name == "outsl"52.6k || Name == "out"52.6k || Name == "outs"52.5k ) && |
2394 | 52.6k | Operands.size() == 370 ) { |
2395 | 49 | X86Operand &Op = (X86Operand &)*Operands.back(); |
2396 | 49 | if (Op.isMem() && 49 Op.Mem.SegReg == 023 && |
2397 | 23 | isa<MCConstantExpr>(Op.Mem.Disp) && |
2398 | 23 | cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 && |
2399 | 49 | Op.Mem.BaseReg == MatchRegisterName("dx")21 && Op.Mem.IndexReg == 020 ) { |
2400 | 20 | SMLoc Loc = Op.getEndLoc(); |
2401 | 20 | Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); |
2402 | 20 | } |
2403 | 49 | } |
2404 | 52.6k | // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al". |
2405 | 52.6k | if ((Name == "inb" || 52.6k Name == "insb"52.6k || Name == "inw"52.6k || Name == "insw"52.6k || |
2406 | 52.6k | Name == "inl"52.6k || Name == "insl"52.6k || Name == "in"52.6k || Name == "ins"52.6k ) && |
2407 | 52.6k | Operands.size() == 362 ) { |
2408 | 44 | X86Operand &Op = (X86Operand &)*Operands[1]; |
2409 | 44 | if (Op.isMem() && 44 Op.Mem.SegReg == 021 && |
2410 | 21 | isa<MCConstantExpr>(Op.Mem.Disp) && |
2411 | 21 | cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 && |
2412 | 44 | Op.Mem.BaseReg == MatchRegisterName("dx")21 && Op.Mem.IndexReg == 020 ) { |
2413 | 20 | SMLoc Loc = Op.getEndLoc(); |
2414 | 20 | Operands[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); |
2415 | 20 | } |
2416 | 44 | } |
2417 | 52.6k | |
2418 | 52.6k | SmallVector<std::unique_ptr<MCParsedAsmOperand>, 2> TmpOperands; |
2419 | 52.6k | bool HadVerifyError = false; |
2420 | 52.6k | |
2421 | 52.6k | // Append default arguments to "ins[bwld]" |
2422 | 52.6k | if (Name.startswith("ins") && |
2423 | 47 | (Operands.size() == 1 || 47 Operands.size() == 334 ) && |
2424 | 42 | (Name == "insb" || 42 Name == "insw"32 || Name == "insl"13 || Name == "insd"5 || |
2425 | 52.6k | Name == "ins"4 )) { |
2426 | 41 | |
2427 | 41 | AddDefaultSrcDestOperands(TmpOperands, |
2428 | 41 | X86Operand::CreateReg(X86::DX, NameLoc, NameLoc), |
2429 | 41 | DefaultMemDIOperand(NameLoc)); |
2430 | 41 | HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); |
2431 | 41 | } |
2432 | 52.6k | |
2433 | 52.6k | // Append default arguments to "outs[bwld]" |
2434 | 52.6k | if (Name.startswith("outs") && |
2435 | 48 | (Operands.size() == 1 || 48 Operands.size() == 331 ) && |
2436 | 48 | (Name == "outsb" || 48 Name == "outsw"31 || Name == "outsl"15 || |
2437 | 52.6k | Name == "outsd"4 || Name == "outs"3 )) { |
2438 | 48 | AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc), |
2439 | 48 | X86Operand::CreateReg(X86::DX, NameLoc, NameLoc)); |
2440 | 48 | HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); |
2441 | 48 | } |
2442 | 52.6k | |
2443 | 52.6k | // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate |
2444 | 52.6k | // values of $SIREG according to the mode. It would be nice if this |
2445 | 52.6k | // could be achieved with InstAlias in the tables. |
2446 | 52.6k | if (Name.startswith("lods") && |
2447 | 78 | (Operands.size() == 1 || 78 Operands.size() == 263 ) && |
2448 | 20 | (Name == "lods" || 20 Name == "lodsb"19 || Name == "lodsw"11 || |
2449 | 52.6k | Name == "lodsl"8 || Name == "lodsd"1 || Name == "lodsq"1 )) { |
2450 | 20 | TmpOperands.push_back(DefaultMemSIOperand(NameLoc)); |
2451 | 20 | HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); |
2452 | 20 | } |
2453 | 52.6k | |
2454 | 52.6k | // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate |
2455 | 52.6k | // values of $DIREG according to the mode. It would be nice if this |
2456 | 52.6k | // could be achieved with InstAlias in the tables. |
2457 | 52.6k | if (Name.startswith("stos") && |
2458 | 58 | (Operands.size() == 1 || 58 Operands.size() == 233 ) && |
2459 | 26 | (Name == "stos" || 26 Name == "stosb"25 || Name == "stosw"21 || |
2460 | 52.6k | Name == "stosl"12 || Name == "stosd"6 || Name == "stosq"6 )) { |
2461 | 26 | TmpOperands.push_back(DefaultMemDIOperand(NameLoc)); |
2462 | 26 | HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); |
2463 | 26 | } |
2464 | 52.6k | |
2465 | 52.6k | // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate |
2466 | 52.6k | // values of $DIREG according to the mode. It would be nice if this |
2467 | 52.6k | // could be achieved with InstAlias in the tables. |
2468 | 52.6k | if (Name.startswith("scas") && |
2469 | 16 | (Operands.size() == 1 || 16 Operands.size() == 214 ) && |
2470 | 6 | (Name == "scas" || 6 Name == "scasb"5 || Name == "scasw"3 || |
2471 | 52.6k | Name == "scasl"3 || Name == "scasd"3 || Name == "scasq"3 )) { |
2472 | 6 | TmpOperands.push_back(DefaultMemDIOperand(NameLoc)); |
2473 | 6 | HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); |
2474 | 6 | } |
2475 | 52.6k | |
2476 | 52.6k | // Add default SI and DI operands to "cmps[bwlq]". |
2477 | 52.6k | if (Name.startswith("cmps") && |
2478 | 26 | (Operands.size() == 1 || 26 Operands.size() == 316 ) && |
2479 | 22 | (Name == "cmps" || 22 Name == "cmpsb"21 || Name == "cmpsw"9 || |
2480 | 52.6k | Name == "cmpsl"5 || Name == "cmpsd"1 || Name == "cmpsq"1 )) { |
2481 | 22 | AddDefaultSrcDestOperands(TmpOperands, DefaultMemDIOperand(NameLoc), |
2482 | 22 | DefaultMemSIOperand(NameLoc)); |
2483 | 22 | HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); |
2484 | 22 | } |
2485 | 52.6k | |
2486 | 52.6k | // Add default SI and DI operands to "movs[bwlq]". |
2487 | 52.6k | if (((Name.startswith("movs") && |
2488 | 259 | (Name == "movs" || 259 Name == "movsb"258 || Name == "movsw"241 || |
2489 | 259 | Name == "movsl"230 || Name == "movsd"212 || Name == "movsq"121 )) || |
2490 | 52.5k | (Name.startswith("smov") && |
2491 | 4 | (Name == "smov" || 4 Name == "smovb"4 || Name == "smovw"3 || |
2492 | 52.5k | Name == "smovl"2 || Name == "smovd"1 || Name == "smovq"1 ))) && |
2493 | 52.6k | (Operands.size() == 1 || 148 Operands.size() == 3119 )) { |
2494 | 148 | if (Name == "movsd" && 148 Operands.size() == 191 && !isParsingIntelSyntax()2 ) |
2495 | 1 | Operands.back() = X86Operand::CreateToken("movsl", NameLoc); |
2496 | 148 | AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc), |
2497 | 148 | DefaultMemDIOperand(NameLoc)); |
2498 | 148 | HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); |
2499 | 148 | } |
2500 | 52.6k | |
2501 | 52.6k | // Check if we encountered an error for one the string insturctions |
2502 | 52.6k | if (HadVerifyError52.6k ) { |
2503 | 2 | return HadVerifyError; |
2504 | 2 | } |
2505 | 52.6k | |
2506 | 52.6k | // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to |
2507 | 52.6k | // "shift <op>". |
2508 | 52.6k | if (52.6k (Name.startswith("shr") || 52.6k Name.startswith("sar")52.4k || |
2509 | 52.6k | Name.startswith("shl")52.4k || Name.startswith("sal")52.3k || |
2510 | 52.6k | Name.startswith("rcl")52.2k || Name.startswith("rcr")52.2k || |
2511 | 52.6k | Name.startswith("rol")52.2k || Name.startswith("ror")52.2k ) && |
2512 | 52.6k | Operands.size() == 3480 ) { |
2513 | 315 | if (isParsingIntelSyntax()315 ) { |
2514 | 7 | // Intel syntax |
2515 | 7 | X86Operand &Op1 = static_cast<X86Operand &>(*Operands[2]); |
2516 | 7 | if (Op1.isImm() && 7 isa<MCConstantExpr>(Op1.getImm())3 && |
2517 | 3 | cast<MCConstantExpr>(Op1.getImm())->getValue() == 1) |
2518 | 1 | Operands.pop_back(); |
2519 | 315 | } else { |
2520 | 308 | X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]); |
2521 | 308 | if (Op1.isImm() && 308 isa<MCConstantExpr>(Op1.getImm())212 && |
2522 | 210 | cast<MCConstantExpr>(Op1.getImm())->getValue() == 1) |
2523 | 9 | Operands.erase(Operands.begin() + 1); |
2524 | 308 | } |
2525 | 315 | } |
2526 | 52.6k | |
2527 | 52.6k | // Transforms "int $3" into "int3" as a size optimization. We can't write an |
2528 | 52.6k | // instalias with an immediate operand yet. |
2529 | 52.6k | if (Name == "int" && 52.6k Operands.size() == 239 ) { |
2530 | 39 | X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]); |
2531 | 39 | if (Op1.isImm()) |
2532 | 39 | if (auto *39 CE39 = dyn_cast<MCConstantExpr>(Op1.getImm())) |
2533 | 39 | if (39 CE->getValue() == 339 ) { |
2534 | 4 | Operands.erase(Operands.begin() + 1); |
2535 | 4 | static_cast<X86Operand &>(*Operands[0]).setTokenValue("int3"); |
2536 | 4 | } |
2537 | 39 | } |
2538 | 52.6k | |
2539 | 52.6k | // Transforms "xlat mem8" into "xlatb" |
2540 | 52.6k | if ((Name == "xlat" || 52.6k Name == "xlatb"52.6k ) && Operands.size() == 21 ) { |
2541 | 1 | X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]); |
2542 | 1 | if (Op1.isMem8()1 ) { |
2543 | 1 | Warning(Op1.getStartLoc(), "memory operand is only for determining the " |
2544 | 1 | "size, (R|E)BX will be used for the location"); |
2545 | 1 | Operands.pop_back(); |
2546 | 1 | static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb"); |
2547 | 1 | } |
2548 | 1 | } |
2549 | 52.7k | |
2550 | 52.7k | return false; |
2551 | 52.7k | } |
2552 | | |
2553 | 47.1k | bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) { |
2554 | 47.1k | return false; |
2555 | 47.1k | } |
2556 | | |
2557 | | static const char *getSubtargetFeatureName(uint64_t Val); |
2558 | | |
2559 | | void X86AsmParser::EmitInstruction(MCInst &Inst, OperandVector &Operands, |
2560 | 52.2k | MCStreamer &Out) { |
2561 | 52.2k | Instrumentation->InstrumentAndEmitInstruction(Inst, Operands, getContext(), |
2562 | 52.2k | MII, Out); |
2563 | 52.2k | } |
2564 | | |
2565 | | bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, |
2566 | | OperandVector &Operands, |
2567 | | MCStreamer &Out, uint64_t &ErrorInfo, |
2568 | 52.6k | bool MatchingInlineAsm) { |
2569 | 52.6k | if (isParsingIntelSyntax()) |
2570 | 11.0k | return MatchAndEmitIntelInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo, |
2571 | 11.0k | MatchingInlineAsm); |
2572 | 41.6k | return MatchAndEmitATTInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo, |
2573 | 41.6k | MatchingInlineAsm); |
2574 | 41.6k | } |
2575 | | |
2576 | | void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, |
2577 | | OperandVector &Operands, MCStreamer &Out, |
2578 | 52.6k | bool MatchingInlineAsm) { |
2579 | 52.6k | // FIXME: This should be replaced with a real .td file alias mechanism. |
2580 | 52.6k | // Also, MatchInstructionImpl should actually *do* the EmitInstruction |
2581 | 52.6k | // call. |
2582 | 52.6k | const char *Repl = StringSwitch<const char *>(Op.getToken()) |
2583 | 52.6k | .Case("finit", "fninit") |
2584 | 52.6k | .Case("fsave", "fnsave") |
2585 | 52.6k | .Case("fstcw", "fnstcw") |
2586 | 52.6k | .Case("fstcww", "fnstcw") |
2587 | 52.6k | .Case("fstenv", "fnstenv") |
2588 | 52.6k | .Case("fstsw", "fnstsw") |
2589 | 52.6k | .Case("fstsww", "fnstsw") |
2590 | 52.6k | .Case("fclex", "fnclex") |
2591 | 52.6k | .Default(nullptr); |
2592 | 52.6k | if (Repl52.6k ) { |
2593 | 18 | MCInst Inst; |
2594 | 18 | Inst.setOpcode(X86::WAIT); |
2595 | 18 | Inst.setLoc(IDLoc); |
2596 | 18 | if (!MatchingInlineAsm) |
2597 | 18 | EmitInstruction(Inst, Operands, Out); |
2598 | 18 | Operands[0] = X86Operand::CreateToken(Repl, IDLoc); |
2599 | 18 | } |
2600 | 52.6k | } |
2601 | | |
2602 | | bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo, |
2603 | 21 | bool MatchingInlineAsm) { |
2604 | 21 | assert(ErrorInfo && "Unknown missing feature!"); |
2605 | 21 | SmallString<126> Msg; |
2606 | 21 | raw_svector_ostream OS(Msg); |
2607 | 21 | OS << "instruction requires:"; |
2608 | 21 | uint64_t Mask = 1; |
2609 | 1.34k | for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1)1.34k ; ++i1.32k ) { |
2610 | 1.32k | if (ErrorInfo & Mask) |
2611 | 21 | OS << ' ' << getSubtargetFeatureName(ErrorInfo & Mask); |
2612 | 1.32k | Mask <<= 1; |
2613 | 1.32k | } |
2614 | 21 | return Error(IDLoc, OS.str(), SMRange(), MatchingInlineAsm); |
2615 | 21 | } |
2616 | | |
2617 | | bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, |
2618 | | OperandVector &Operands, |
2619 | | MCStreamer &Out, |
2620 | | uint64_t &ErrorInfo, |
2621 | 41.6k | bool MatchingInlineAsm) { |
2622 | 41.6k | assert(!Operands.empty() && "Unexpect empty operand list!"); |
2623 | 41.6k | X86Operand &Op = static_cast<X86Operand &>(*Operands[0]); |
2624 | 41.6k | assert(Op.isToken() && "Leading operand should always be a mnemonic!"); |
2625 | 41.6k | SMRange EmptyRange = None; |
2626 | 41.6k | |
2627 | 41.6k | // First, handle aliases that expand to multiple instructions. |
2628 | 41.6k | MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm); |
2629 | 41.6k | |
2630 | 41.6k | bool WasOriginallyInvalidOperand = false; |
2631 | 41.6k | MCInst Inst; |
2632 | 41.6k | |
2633 | 41.6k | // First, try a direct match. |
2634 | 41.6k | switch (MatchInstruction(Operands, Inst, ErrorInfo, MatchingInlineAsm, |
2635 | 41.6k | isParsingIntelSyntax())) { |
2636 | 0 | default: 0 llvm_unreachable0 ("Unexpected match result!"); |
2637 | 36.4k | case Match_Success: |
2638 | 36.4k | // Some instructions need post-processing to, for example, tweak which |
2639 | 36.4k | // encoding is selected. Loop on it while changes happen so the |
2640 | 36.4k | // individual transformations can chain off each other. |
2641 | 36.4k | if (!MatchingInlineAsm) |
2642 | 36.4k | while (36.4k processInstruction(Inst, Operands)36.4k ) |
2643 | 0 | ; |
2644 | 36.4k | |
2645 | 36.4k | Inst.setLoc(IDLoc); |
2646 | 36.4k | if (!MatchingInlineAsm) |
2647 | 36.4k | EmitInstruction(Inst, Operands, Out); |
2648 | 36.4k | Opcode = Inst.getOpcode(); |
2649 | 36.4k | return false; |
2650 | 21 | case Match_MissingFeature: |
2651 | 21 | return ErrorMissingFeature(IDLoc, ErrorInfo, MatchingInlineAsm); |
2652 | 327 | case Match_InvalidOperand: |
2653 | 327 | WasOriginallyInvalidOperand = true; |
2654 | 327 | break; |
2655 | 4.82k | case Match_MnemonicFail: |
2656 | 4.82k | break; |
2657 | 5.15k | } |
2658 | 5.15k | |
2659 | 5.15k | // FIXME: Ideally, we would only attempt suffix matches for things which are |
2660 | 5.15k | // valid prefixes, and we could just infer the right unambiguous |
2661 | 5.15k | // type. However, that requires substantially more matcher support than the |
2662 | 5.15k | // following hack. |
2663 | 5.15k | |
2664 | 5.15k | // Change the operand to point to a temporary token. |
2665 | 5.15k | StringRef Base = Op.getToken(); |
2666 | 5.15k | SmallString<16> Tmp; |
2667 | 5.15k | Tmp += Base; |
2668 | 5.15k | Tmp += ' '; |
2669 | 5.15k | Op.setTokenValue(Tmp); |
2670 | 5.15k | |
2671 | 5.15k | // If this instruction starts with an 'f', then it is a floating point stack |
2672 | 5.15k | // instruction. These come in up to three forms for 32-bit, 64-bit, and |
2673 | 5.15k | // 80-bit floating point, which use the suffixes s,l,t respectively. |
2674 | 5.15k | // |
2675 | 5.15k | // Otherwise, we assume that this may be an integer instruction, which comes |
2676 | 5.15k | // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively. |
2677 | 5.15k | const char *Suffixes = Base[0] != 'f' ? "bwlq"5.15k : "slt\0"1 ; |
2678 | 5.15k | |
2679 | 5.15k | // Check for the various suffix matches. |
2680 | 5.15k | uint64_t ErrorInfoIgnore; |
2681 | 5.15k | uint64_t ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings. |
2682 | 5.15k | unsigned Match[4]; |
2683 | 5.15k | |
2684 | 25.7k | for (unsigned I = 0, E = array_lengthof(Match); I != E25.7k ; ++I20.6k ) { |
2685 | 20.6k | Tmp.back() = Suffixes[I]; |
2686 | 20.6k | Match[I] = MatchInstruction(Operands, Inst, ErrorInfoIgnore, |
2687 | 20.6k | MatchingInlineAsm, isParsingIntelSyntax()); |
2688 | 20.6k | // If this returned as a missing feature failure, remember that. |
2689 | 20.6k | if (Match[I] == Match_MissingFeature) |
2690 | 0 | ErrorInfoMissingFeature = ErrorInfoIgnore; |
2691 | 20.6k | } |
2692 | 5.15k | |
2693 | 5.15k | // Restore the old token. |
2694 | 5.15k | Op.setTokenValue(Base); |
2695 | 5.15k | |
2696 | 5.15k | // If exactly one matched, then we treat that as a successful match (and the |
2697 | 5.15k | // instruction will already have been filled in correctly, since the failing |
2698 | 5.15k | // matches won't have modified it). |
2699 | 5.15k | unsigned NumSuccessfulMatches = |
2700 | 5.15k | std::count(std::begin(Match), std::end(Match), Match_Success); |
2701 | 5.15k | if (NumSuccessfulMatches == 15.15k ) { |
2702 | 5.11k | Inst.setLoc(IDLoc); |
2703 | 5.11k | if (!MatchingInlineAsm) |
2704 | 5.11k | EmitInstruction(Inst, Operands, Out); |
2705 | 5.11k | Opcode = Inst.getOpcode(); |
2706 | 5.11k | return false; |
2707 | 5.11k | } |
2708 | 44 | |
2709 | 44 | // Otherwise, the match failed, try to produce a decent error message. |
2710 | 44 | |
2711 | 44 | // If we had multiple suffix matches, then identify this as an ambiguous |
2712 | 44 | // match. |
2713 | 44 | if (44 NumSuccessfulMatches > 144 ) { |
2714 | 2 | char MatchChars[4]; |
2715 | 2 | unsigned NumMatches = 0; |
2716 | 10 | for (unsigned I = 0, E = array_lengthof(Match); I != E10 ; ++I8 ) |
2717 | 8 | if (8 Match[I] == Match_Success8 ) |
2718 | 8 | MatchChars[NumMatches++] = Suffixes[I]; |
2719 | 2 | |
2720 | 2 | SmallString<126> Msg; |
2721 | 2 | raw_svector_ostream OS(Msg); |
2722 | 2 | OS << "ambiguous instructions require an explicit suffix (could be "; |
2723 | 10 | for (unsigned i = 0; i != NumMatches10 ; ++i8 ) { |
2724 | 8 | if (i != 0) |
2725 | 6 | OS << ", "; |
2726 | 8 | if (i + 1 == NumMatches) |
2727 | 2 | OS << "or "; |
2728 | 8 | OS << "'" << Base << MatchChars[i] << "'"; |
2729 | 8 | } |
2730 | 2 | OS << ")"; |
2731 | 2 | Error(IDLoc, OS.str(), EmptyRange, MatchingInlineAsm); |
2732 | 2 | return true; |
2733 | 2 | } |
2734 | 42 | |
2735 | 42 | // Okay, we know that none of the variants matched successfully. |
2736 | 42 | |
2737 | 42 | // If all of the instructions reported an invalid mnemonic, then the original |
2738 | 42 | // mnemonic was invalid. |
2739 | 42 | if (42 std::count(std::begin(Match), std::end(Match), Match_MnemonicFail) == 442 ) { |
2740 | 39 | if (!WasOriginallyInvalidOperand39 ) { |
2741 | 15 | return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'", |
2742 | 15 | Op.getLocRange(), MatchingInlineAsm); |
2743 | 15 | } |
2744 | 24 | |
2745 | 24 | // Recover location info for the operand if we know which was the problem. |
2746 | 24 | if (24 ErrorInfo != ~0ULL24 ) { |
2747 | 24 | if (ErrorInfo >= Operands.size()) |
2748 | 0 | return Error(IDLoc, "too few operands for instruction", EmptyRange, |
2749 | 0 | MatchingInlineAsm); |
2750 | 24 | |
2751 | 24 | X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo]; |
2752 | 24 | if (Operand.getStartLoc().isValid()24 ) { |
2753 | 24 | SMRange OperandRange = Operand.getLocRange(); |
2754 | 24 | return Error(Operand.getStartLoc(), "invalid operand for instruction", |
2755 | 24 | OperandRange, MatchingInlineAsm); |
2756 | 24 | } |
2757 | 0 | } |
2758 | 0 |
|
2759 | 0 | return Error(IDLoc, "invalid operand for instruction", EmptyRange, |
2760 | 0 | MatchingInlineAsm); |
2761 | 0 | } |
2762 | 3 | |
2763 | 3 | // If one instruction matched with a missing feature, report this as a |
2764 | 3 | // missing feature. |
2765 | 3 | if (3 std::count(std::begin(Match), std::end(Match), |
2766 | 3 | Match_MissingFeature) == 1) { |
2767 | 0 | ErrorInfo = ErrorInfoMissingFeature; |
2768 | 0 | return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature, |
2769 | 0 | MatchingInlineAsm); |
2770 | 0 | } |
2771 | 3 | |
2772 | 3 | // If one instruction matched with an invalid operand, report this as an |
2773 | 3 | // operand failure. |
2774 | 3 | if (3 std::count(std::begin(Match), std::end(Match), |
2775 | 3 | Match_InvalidOperand) == 1) { |
2776 | 0 | return Error(IDLoc, "invalid operand for instruction", EmptyRange, |
2777 | 0 | MatchingInlineAsm); |
2778 | 0 | } |
2779 | 3 | |
2780 | 3 | // If all of these were an outright failure, report it in a useless way. |
2781 | 3 | Error(IDLoc, "unknown use of instruction mnemonic without a size suffix", |
2782 | 3 | EmptyRange, MatchingInlineAsm); |
2783 | 3 | return true; |
2784 | 3 | } |
2785 | | |
2786 | | bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode, |
2787 | | OperandVector &Operands, |
2788 | | MCStreamer &Out, |
2789 | | uint64_t &ErrorInfo, |
2790 | 11.0k | bool MatchingInlineAsm) { |
2791 | 11.0k | assert(!Operands.empty() && "Unexpect empty operand list!"); |
2792 | 11.0k | X86Operand &Op = static_cast<X86Operand &>(*Operands[0]); |
2793 | 11.0k | assert(Op.isToken() && "Leading operand should always be a mnemonic!"); |
2794 | 11.0k | StringRef Mnemonic = Op.getToken(); |
2795 | 11.0k | SMRange EmptyRange = None; |
2796 | 11.0k | StringRef Base = Op.getToken(); |
2797 | 11.0k | |
2798 | 11.0k | // First, handle aliases that expand to multiple instructions. |
2799 | 11.0k | MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm); |
2800 | 11.0k | |
2801 | 11.0k | MCInst Inst; |
2802 | 11.0k | |
2803 | 11.0k | // Find one unsized memory operand, if present. |
2804 | 11.0k | X86Operand *UnsizedMemOp = nullptr; |
2805 | 49.0k | for (const auto &Op : Operands) { |
2806 | 49.0k | X86Operand *X86Op = static_cast<X86Operand *>(Op.get()); |
2807 | 49.0k | if (X86Op->isMemUnsized()49.0k ) { |
2808 | 399 | UnsizedMemOp = X86Op; |
2809 | 399 | // Have we found an unqualified memory operand, |
2810 | 399 | // break. IA allows only one memory operand. |
2811 | 399 | break; |
2812 | 399 | } |
2813 | 11.0k | } |
2814 | 11.0k | |
2815 | 11.0k | // Allow some instructions to have implicitly pointer-sized operands. This is |
2816 | 11.0k | // compatible with gas. |
2817 | 11.0k | if (UnsizedMemOp11.0k ) { |
2818 | 399 | static const char *const PtrSizedInstrs[] = {"call", "jmp", "push"}; |
2819 | 1.16k | for (const char *Instr : PtrSizedInstrs) { |
2820 | 1.16k | if (Mnemonic == Instr1.16k ) { |
2821 | 27 | UnsizedMemOp->Mem.Size = getPointerWidth(); |
2822 | 27 | break; |
2823 | 27 | } |
2824 | 11.0k | } |
2825 | 399 | } |
2826 | 11.0k | |
2827 | 11.0k | SmallVector<unsigned, 8> Match; |
2828 | 11.0k | uint64_t ErrorInfoMissingFeature = 0; |
2829 | 11.0k | |
2830 | 11.0k | // If unsized push has immediate operand we should default the default pointer |
2831 | 11.0k | // size for the size. |
2832 | 11.0k | if (Mnemonic == "push" && 11.0k Operands.size() == 228 ) { |
2833 | 28 | auto *X86Op = static_cast<X86Operand *>(Operands[1].get()); |
2834 | 28 | if (X86Op->isImm()28 ) { |
2835 | 15 | // If it's not a constant fall through and let remainder take care of it. |
2836 | 15 | const auto *CE = dyn_cast<MCConstantExpr>(X86Op->getImm()); |
2837 | 15 | unsigned Size = getPointerWidth(); |
2838 | 15 | if (CE && |
2839 | 15 | (isIntN(Size, CE->getValue()) || 15 isUIntN(Size, CE->getValue())1 )) { |
2840 | 14 | SmallString<16> Tmp; |
2841 | 14 | Tmp += Base; |
2842 | 14 | Tmp += (is64BitMode()) |
2843 | 0 | ? "q" |
2844 | 14 | : (is32BitMode()) ? 14 "l"10 : (is16BitMode()) ? 4 "w"4 : " "0 ; |
2845 | 14 | Op.setTokenValue(Tmp); |
2846 | 14 | // Do match in ATT mode to allow explicit suffix usage. |
2847 | 14 | Match.push_back(MatchInstruction(Operands, Inst, ErrorInfo, |
2848 | 14 | MatchingInlineAsm, |
2849 | 14 | false /*isParsingIntelSyntax()*/)); |
2850 | 14 | Op.setTokenValue(Base); |
2851 | 14 | } |
2852 | 15 | } |
2853 | 28 | } |
2854 | 11.0k | |
2855 | 11.0k | // If an unsized memory operand is present, try to match with each memory |
2856 | 11.0k | // operand size. In Intel assembly, the size is not part of the instruction |
2857 | 11.0k | // mnemonic. |
2858 | 11.0k | if (UnsizedMemOp && 11.0k UnsizedMemOp->isMemUnsized()399 ) { |
2859 | 372 | static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512}; |
2860 | 2.97k | for (unsigned Size : MopSizes) { |
2861 | 2.97k | UnsizedMemOp->Mem.Size = Size; |
2862 | 2.97k | uint64_t ErrorInfoIgnore; |
2863 | 2.97k | unsigned LastOpcode = Inst.getOpcode(); |
2864 | 2.97k | unsigned M = MatchInstruction(Operands, Inst, ErrorInfoIgnore, |
2865 | 2.97k | MatchingInlineAsm, isParsingIntelSyntax()); |
2866 | 2.97k | if (Match.empty() || 2.97k LastOpcode != Inst.getOpcode()2.60k ) |
2867 | 725 | Match.push_back(M); |
2868 | 2.97k | |
2869 | 2.97k | // If this returned as a missing feature failure, remember that. |
2870 | 2.97k | if (Match.back() == Match_MissingFeature) |
2871 | 0 | ErrorInfoMissingFeature = ErrorInfoIgnore; |
2872 | 2.97k | } |
2873 | 372 | |
2874 | 372 | // Restore the size of the unsized memory operand if we modified it. |
2875 | 372 | UnsizedMemOp->Mem.Size = 0; |
2876 | 372 | } |
2877 | 11.0k | |
2878 | 11.0k | // If we haven't matched anything yet, this is not a basic integer or FPU |
2879 | 11.0k | // operation. There shouldn't be any ambiguity in our mnemonic table, so try |
2880 | 11.0k | // matching with the unsized operand. |
2881 | 11.0k | if (Match.empty()11.0k ) { |
2882 | 10.6k | Match.push_back(MatchInstruction( |
2883 | 10.6k | Operands, Inst, ErrorInfo, MatchingInlineAsm, isParsingIntelSyntax())); |
2884 | 10.6k | // If this returned as a missing feature failure, remember that. |
2885 | 10.6k | if (Match.back() == Match_MissingFeature) |
2886 | 0 | ErrorInfoMissingFeature = ErrorInfo; |
2887 | 10.6k | } |
2888 | 11.0k | |
2889 | 11.0k | // Restore the size of the unsized memory operand if we modified it. |
2890 | 11.0k | if (UnsizedMemOp) |
2891 | 399 | UnsizedMemOp->Mem.Size = 0; |
2892 | 11.0k | |
2893 | 11.0k | // If it's a bad mnemonic, all results will be the same. |
2894 | 11.0k | if (Match.back() == Match_MnemonicFail11.0k ) { |
2895 | 3 | return Error(IDLoc, "invalid instruction mnemonic '" + Mnemonic + "'", |
2896 | 3 | Op.getLocRange(), MatchingInlineAsm); |
2897 | 3 | } |
2898 | 11.0k | |
2899 | 11.0k | unsigned NumSuccessfulMatches = |
2900 | 11.0k | std::count(std::begin(Match), std::end(Match), Match_Success); |
2901 | 11.0k | |
2902 | 11.0k | // If matching was ambiguous and we had size information from the frontend, |
2903 | 11.0k | // try again with that. This handles cases like "movxz eax, m8/m16". |
2904 | 11.0k | if (UnsizedMemOp && 11.0k NumSuccessfulMatches > 1398 && |
2905 | 11.0k | UnsizedMemOp->getMemFrontendSize()23 ) { |
2906 | 15 | UnsizedMemOp->Mem.Size = UnsizedMemOp->getMemFrontendSize(); |
2907 | 15 | unsigned M = MatchInstruction( |
2908 | 15 | Operands, Inst, ErrorInfo, MatchingInlineAsm, isParsingIntelSyntax()); |
2909 | 15 | if (M == Match_Success) |
2910 | 15 | NumSuccessfulMatches = 1; |
2911 | 15 | |
2912 | 15 | // Add a rewrite that encodes the size information we used from the |
2913 | 15 | // frontend. |
2914 | 15 | InstInfo->AsmRewrites->emplace_back( |
2915 | 15 | AOK_SizeDirective, UnsizedMemOp->getStartLoc(), |
2916 | 15 | /*Len=*/0, UnsizedMemOp->getMemFrontendSize()); |
2917 | 15 | } |
2918 | 11.0k | |
2919 | 11.0k | // If exactly one matched, then we treat that as a successful match (and the |
2920 | 11.0k | // instruction will already have been filled in correctly, since the failing |
2921 | 11.0k | // matches won't have modified it). |
2922 | 11.0k | if (NumSuccessfulMatches == 111.0k ) { |
2923 | 10.9k | // Some instructions need post-processing to, for example, tweak which |
2924 | 10.9k | // encoding is selected. Loop on it while changes happen so the individual |
2925 | 10.9k | // transformations can chain off each other. |
2926 | 10.9k | if (!MatchingInlineAsm) |
2927 | 10.6k | while (10.6k processInstruction(Inst, Operands)10.6k ) |
2928 | 0 | ; |
2929 | 10.9k | Inst.setLoc(IDLoc); |
2930 | 10.9k | if (!MatchingInlineAsm) |
2931 | 10.6k | EmitInstruction(Inst, Operands, Out); |
2932 | 10.9k | Opcode = Inst.getOpcode(); |
2933 | 10.9k | return false; |
2934 | 16 | } else if (16 NumSuccessfulMatches > 116 ) { |
2935 | 8 | assert(UnsizedMemOp && |
2936 | 8 | "multiple matches only possible with unsized memory operands"); |
2937 | 8 | return Error(UnsizedMemOp->getStartLoc(), |
2938 | 8 | "ambiguous operand size for instruction '" + Mnemonic + "\'", |
2939 | 8 | UnsizedMemOp->getLocRange()); |
2940 | 8 | } |
2941 | 8 | |
2942 | 8 | // If one instruction matched with a missing feature, report this as a |
2943 | 8 | // missing feature. |
2944 | 8 | if (8 std::count(std::begin(Match), std::end(Match), |
2945 | 8 | Match_MissingFeature) == 1) { |
2946 | 0 | ErrorInfo = ErrorInfoMissingFeature; |
2947 | 0 | return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature, |
2948 | 0 | MatchingInlineAsm); |
2949 | 0 | } |
2950 | 8 | |
2951 | 8 | // If one instruction matched with an invalid operand, report this as an |
2952 | 8 | // operand failure. |
2953 | 8 | if (8 std::count(std::begin(Match), std::end(Match), |
2954 | 8 | Match_InvalidOperand) == 1) { |
2955 | 8 | return Error(IDLoc, "invalid operand for instruction", EmptyRange, |
2956 | 8 | MatchingInlineAsm); |
2957 | 8 | } |
2958 | 0 |
|
2959 | 0 | // If all of these were an outright failure, report it in a useless way. |
2960 | 0 | return Error(IDLoc, "unknown instruction mnemonic", EmptyRange, |
2961 | 0 | MatchingInlineAsm); |
2962 | 0 | } |
2963 | | |
2964 | 316 | bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) { |
2965 | 316 | return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo); |
2966 | 316 | } |
2967 | | |
2968 | 509k | bool X86AsmParser::ParseDirective(AsmToken DirectiveID) { |
2969 | 509k | MCAsmParser &Parser = getParser(); |
2970 | 509k | StringRef IDVal = DirectiveID.getIdentifier(); |
2971 | 509k | if (IDVal == ".word") |
2972 | 24 | return ParseDirectiveWord(2, DirectiveID.getLoc()); |
2973 | 509k | else if (509k IDVal.startswith(".code")509k ) |
2974 | 14 | return ParseDirectiveCode(IDVal, DirectiveID.getLoc()); |
2975 | 509k | else if (509k IDVal.startswith(".att_syntax")509k ) { |
2976 | 20 | getParser().setParsingInlineAsm(false); |
2977 | 20 | if (getLexer().isNot(AsmToken::EndOfStatement)20 ) { |
2978 | 2 | if (Parser.getTok().getString() == "prefix") |
2979 | 1 | Parser.Lex(); |
2980 | 1 | else if (1 Parser.getTok().getString() == "noprefix"1 ) |
2981 | 1 | return Error(DirectiveID.getLoc(), "'.att_syntax noprefix' is not " |
2982 | 1 | "supported: registers must have a " |
2983 | 1 | "'%' prefix in .att_syntax"); |
2984 | 19 | } |
2985 | 19 | getParser().setAssemblerDialect(0); |
2986 | 19 | return false; |
2987 | 509k | } else if (509k IDVal.startswith(".intel_syntax")509k ) { |
2988 | 32 | getParser().setAssemblerDialect(1); |
2989 | 32 | getParser().setParsingInlineAsm(true); |
2990 | 32 | if (getLexer().isNot(AsmToken::EndOfStatement)32 ) { |
2991 | 3 | if (Parser.getTok().getString() == "noprefix") |
2992 | 2 | Parser.Lex(); |
2993 | 1 | else if (1 Parser.getTok().getString() == "prefix"1 ) |
2994 | 1 | return Error(DirectiveID.getLoc(), "'.intel_syntax prefix' is not " |
2995 | 1 | "supported: registers must not have " |
2996 | 1 | "a '%' prefix in .intel_syntax"); |
2997 | 31 | } |
2998 | 31 | return false; |
2999 | 509k | } else if (509k IDVal == ".even"509k ) |
3000 | 3 | return parseDirectiveEven(DirectiveID.getLoc()); |
3001 | 509k | return true; |
3002 | 509k | } |
3003 | | |
3004 | | /// parseDirectiveEven |
3005 | | /// ::= .even |
3006 | 3 | bool X86AsmParser::parseDirectiveEven(SMLoc L) { |
3007 | 3 | if (getLexer().isNot(AsmToken::EndOfStatement)3 ) { |
3008 | 0 | TokError("unexpected token in directive"); |
3009 | 0 | return false; |
3010 | 0 | } |
3011 | 3 | const MCSection *Section = getStreamer().getCurrentSectionOnly(); |
3012 | 3 | if (!Section3 ) { |
3013 | 0 | getStreamer().InitSections(false); |
3014 | 0 | Section = getStreamer().getCurrentSectionOnly(); |
3015 | 0 | } |
3016 | 3 | if (Section->UseCodeAlign()) |
3017 | 3 | getStreamer().EmitCodeAlignment(2, 0); |
3018 | 3 | else |
3019 | 0 | getStreamer().EmitValueToAlignment(2, 0, 1, 0); |
3020 | 3 | return false; |
3021 | 3 | } |
3022 | | /// ParseDirectiveWord |
3023 | | /// ::= .word [ expression (, expression)* ] |
3024 | 24 | bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { |
3025 | 24 | MCAsmParser &Parser = getParser(); |
3026 | 24 | if (getLexer().isNot(AsmToken::EndOfStatement)24 ) { |
3027 | 24 | for (;;) { |
3028 | 24 | const MCExpr *Value; |
3029 | 24 | SMLoc ExprLoc = getLexer().getLoc(); |
3030 | 24 | if (getParser().parseExpression(Value)) |
3031 | 0 | return false; |
3032 | 24 | |
3033 | 24 | if (const auto *24 MCE24 = dyn_cast<MCConstantExpr>(Value)) { |
3034 | 18 | assert(Size <= 8 && "Invalid size"); |
3035 | 18 | uint64_t IntValue = MCE->getValue(); |
3036 | 18 | if (!isUIntN(8 * Size, IntValue) && 18 !isIntN(8 * Size, IntValue)1 ) |
3037 | 1 | return Error(ExprLoc, "literal value out of range for directive"); |
3038 | 17 | getStreamer().EmitIntValue(IntValue, Size); |
3039 | 24 | } else { |
3040 | 6 | getStreamer().EmitValue(Value, Size, ExprLoc); |
3041 | 6 | } |
3042 | 24 | |
3043 | 23 | if (23 getLexer().is(AsmToken::EndOfStatement)23 ) |
3044 | 23 | break; |
3045 | 0 |
|
3046 | 0 | // FIXME: Improve diagnostic. |
3047 | 0 | if (0 getLexer().isNot(AsmToken::Comma)0 ) { |
3048 | 0 | Error(L, "unexpected token in directive"); |
3049 | 0 | return false; |
3050 | 0 | } |
3051 | 0 | Parser.Lex(); |
3052 | 0 | } |
3053 | 24 | } |
3054 | 24 | |
3055 | 23 | Parser.Lex(); |
3056 | 23 | return false; |
3057 | 24 | } |
3058 | | |
3059 | | /// ParseDirectiveCode |
3060 | | /// ::= .code16 | .code32 | .code64 |
3061 | 14 | bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) { |
3062 | 14 | MCAsmParser &Parser = getParser(); |
3063 | 14 | Code16GCC = false; |
3064 | 14 | if (IDVal == ".code16"14 ) { |
3065 | 4 | Parser.Lex(); |
3066 | 4 | if (!is16BitMode()4 ) { |
3067 | 4 | SwitchMode(X86::Mode16Bit); |
3068 | 4 | getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); |
3069 | 4 | } |
3070 | 14 | } else if (10 IDVal == ".code16gcc"10 ) { |
3071 | 1 | // .code16gcc parses as if in 32-bit mode, but emits code in 16-bit mode. |
3072 | 1 | Parser.Lex(); |
3073 | 1 | Code16GCC = true; |
3074 | 1 | if (!is16BitMode()1 ) { |
3075 | 1 | SwitchMode(X86::Mode16Bit); |
3076 | 1 | getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); |
3077 | 1 | } |
3078 | 10 | } else if (9 IDVal == ".code32"9 ) { |
3079 | 3 | Parser.Lex(); |
3080 | 3 | if (!is32BitMode()3 ) { |
3081 | 3 | SwitchMode(X86::Mode32Bit); |
3082 | 3 | getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); |
3083 | 3 | } |
3084 | 9 | } else if (6 IDVal == ".code64"6 ) { |
3085 | 5 | Parser.Lex(); |
3086 | 5 | if (!is64BitMode()5 ) { |
3087 | 4 | SwitchMode(X86::Mode64Bit); |
3088 | 4 | getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64); |
3089 | 4 | } |
3090 | 6 | } else { |
3091 | 1 | Error(L, "unknown directive " + IDVal); |
3092 | 1 | return false; |
3093 | 1 | } |
3094 | 13 | |
3095 | 13 | return false; |
3096 | 13 | } |
3097 | | |
3098 | | // Force static initialization. |
3099 | 68.1k | extern "C" void LLVMInitializeX86AsmParser() { |
3100 | 68.1k | RegisterMCAsmParser<X86AsmParser> X(getTheX86_32Target()); |
3101 | 68.1k | RegisterMCAsmParser<X86AsmParser> Y(getTheX86_64Target()); |
3102 | 68.1k | } |
3103 | | |
3104 | | #define GET_REGISTER_MATCHER |
3105 | | #define GET_MATCHER_IMPLEMENTATION |
3106 | | #define GET_SUBTARGET_FEATURE_NAME |
3107 | | #include "X86GenAsmMatcher.inc" |