/Users/buildslave/jenkins/sharedspace/clang-stage2-coverage-R@2/llvm/lib/Target/XCore/XCoreISelLowering.h
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1 | | //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file defines the interfaces that XCore uses to lower LLVM code into a |
11 | | // selection DAG. |
12 | | // |
13 | | //===----------------------------------------------------------------------===// |
14 | | |
15 | | #ifndef LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H |
16 | | #define LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H |
17 | | |
18 | | #include "XCore.h" |
19 | | #include "llvm/CodeGen/SelectionDAG.h" |
20 | | #include "llvm/Target/TargetLowering.h" |
21 | | |
22 | | namespace llvm { |
23 | | |
24 | | // Forward delcarations |
25 | | class XCoreSubtarget; |
26 | | class XCoreTargetMachine; |
27 | | |
28 | | namespace XCoreISD { |
29 | | enum NodeType : unsigned { |
30 | | // Start the numbering where the builtin ops and target ops leave off. |
31 | | FIRST_NUMBER = ISD::BUILTIN_OP_END, |
32 | | |
33 | | // Branch and link (call) |
34 | | BL, |
35 | | |
36 | | // pc relative address |
37 | | PCRelativeWrapper, |
38 | | |
39 | | // dp relative address |
40 | | DPRelativeWrapper, |
41 | | |
42 | | // cp relative address |
43 | | CPRelativeWrapper, |
44 | | |
45 | | // Load word from stack |
46 | | LDWSP, |
47 | | |
48 | | // Store word to stack |
49 | | STWSP, |
50 | | |
51 | | // Corresponds to retsp instruction |
52 | | RETSP, |
53 | | |
54 | | // Corresponds to LADD instruction |
55 | | LADD, |
56 | | |
57 | | // Corresponds to LSUB instruction |
58 | | LSUB, |
59 | | |
60 | | // Corresponds to LMUL instruction |
61 | | LMUL, |
62 | | |
63 | | // Corresponds to MACCU instruction |
64 | | MACCU, |
65 | | |
66 | | // Corresponds to MACCS instruction |
67 | | MACCS, |
68 | | |
69 | | // Corresponds to CRC8 instruction |
70 | | CRC8, |
71 | | |
72 | | // Jumptable branch. |
73 | | BR_JT, |
74 | | |
75 | | // Jumptable branch using long branches for each entry. |
76 | | BR_JT32, |
77 | | |
78 | | // Offset from frame pointer to the first (possible) on-stack argument |
79 | | FRAME_TO_ARGS_OFFSET, |
80 | | |
81 | | // Exception handler return. The stack is restored to the first |
82 | | // followed by a jump to the second argument. |
83 | | EH_RETURN, |
84 | | |
85 | | // Memory barrier. |
86 | | MEMBARRIER |
87 | | }; |
88 | | } |
89 | | |
90 | | //===--------------------------------------------------------------------===// |
91 | | // TargetLowering Implementation |
92 | | //===--------------------------------------------------------------------===// |
93 | | class XCoreTargetLowering : public TargetLowering |
94 | | { |
95 | | public: |
96 | | explicit XCoreTargetLowering(const TargetMachine &TM, |
97 | | const XCoreSubtarget &Subtarget); |
98 | | |
99 | | using TargetLowering::isZExtFree; |
100 | | bool isZExtFree(SDValue Val, EVT VT2) const override; |
101 | | |
102 | | |
103 | | unsigned getJumpTableEncoding() const override; |
104 | 77 | MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override { |
105 | 77 | return MVT::i32; |
106 | 77 | } |
107 | | |
108 | | /// LowerOperation - Provide custom lowering hooks for some operations. |
109 | | SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; |
110 | | |
111 | | /// ReplaceNodeResults - Replace the results of node with an illegal result |
112 | | /// type with new values built out of custom code. |
113 | | /// |
114 | | void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, |
115 | | SelectionDAG &DAG) const override; |
116 | | |
117 | | /// getTargetNodeName - This method returns the name of a target specific |
118 | | // DAG node. |
119 | | const char *getTargetNodeName(unsigned Opcode) const override; |
120 | | |
121 | | MachineBasicBlock * |
122 | | EmitInstrWithCustomInserter(MachineInstr &MI, |
123 | | MachineBasicBlock *MBB) const override; |
124 | | |
125 | | bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, |
126 | | Type *Ty, unsigned AS, |
127 | | Instruction *I = nullptr) const override; |
128 | | |
129 | | /// If a physical register, this returns the register that receives the |
130 | | /// exception address on entry to an EH pad. |
131 | | unsigned |
132 | 22 | getExceptionPointerRegister(const Constant *PersonalityFn) const override { |
133 | 22 | return XCore::R0; |
134 | 22 | } |
135 | | |
136 | | /// If a physical register, this returns the register that receives the |
137 | | /// exception typeid on entry to a landing pad. |
138 | | unsigned |
139 | 21 | getExceptionSelectorRegister(const Constant *PersonalityFn) const override { |
140 | 21 | return XCore::R1; |
141 | 21 | } |
142 | | |
143 | | private: |
144 | | const TargetMachine &TM; |
145 | | const XCoreSubtarget &Subtarget; |
146 | | |
147 | | // Lower Operand helpers |
148 | | SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, |
149 | | bool isVarArg, |
150 | | const SmallVectorImpl<ISD::InputArg> &Ins, |
151 | | const SDLoc &dl, SelectionDAG &DAG, |
152 | | SmallVectorImpl<SDValue> &InVals) const; |
153 | | SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee, |
154 | | CallingConv::ID CallConv, bool isVarArg, |
155 | | bool isTailCall, |
156 | | const SmallVectorImpl<ISD::OutputArg> &Outs, |
157 | | const SmallVectorImpl<SDValue> &OutVals, |
158 | | const SmallVectorImpl<ISD::InputArg> &Ins, |
159 | | const SDLoc &dl, SelectionDAG &DAG, |
160 | | SmallVectorImpl<SDValue> &InVals) const; |
161 | | SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; |
162 | | SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV, |
163 | | SelectionDAG &DAG) const; |
164 | | SDValue lowerLoadWordFromAlignedBasePlusOffset(const SDLoc &DL, |
165 | | SDValue Chain, SDValue Base, |
166 | | int64_t Offset, |
167 | | SelectionDAG &DAG) const; |
168 | | |
169 | | // Lower Operand specifics |
170 | | SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; |
171 | | SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; |
172 | | SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; |
173 | | SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; |
174 | | SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; |
175 | | SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; |
176 | | SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; |
177 | | SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; |
178 | | SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; |
179 | | SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; |
180 | | SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; |
181 | | SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; |
182 | | SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; |
183 | | SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const; |
184 | | SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; |
185 | | SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; |
186 | | SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; |
187 | | SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; |
188 | | SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; |
189 | | SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const; |
190 | | SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; |
191 | | |
192 | | // Inline asm support |
193 | | std::pair<unsigned, const TargetRegisterClass *> |
194 | | getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, |
195 | | StringRef Constraint, MVT VT) const override; |
196 | | |
197 | | // Expand specifics |
198 | | SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const; |
199 | | SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const; |
200 | | |
201 | | SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; |
202 | | |
203 | | void computeKnownBitsForTargetNode(const SDValue Op, |
204 | | KnownBits &Known, |
205 | | const APInt &DemandedElts, |
206 | | const SelectionDAG &DAG, |
207 | | unsigned Depth = 0) const override; |
208 | | |
209 | | SDValue |
210 | | LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, |
211 | | const SmallVectorImpl<ISD::InputArg> &Ins, |
212 | | const SDLoc &dl, SelectionDAG &DAG, |
213 | | SmallVectorImpl<SDValue> &InVals) const override; |
214 | | |
215 | | SDValue |
216 | | LowerCall(TargetLowering::CallLoweringInfo &CLI, |
217 | | SmallVectorImpl<SDValue> &InVals) const override; |
218 | | |
219 | | SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, |
220 | | const SmallVectorImpl<ISD::OutputArg> &Outs, |
221 | | const SmallVectorImpl<SDValue> &OutVals, |
222 | | const SDLoc &dl, SelectionDAG &DAG) const override; |
223 | | |
224 | | bool |
225 | | CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, |
226 | | bool isVarArg, |
227 | | const SmallVectorImpl<ISD::OutputArg> &ArgsFlags, |
228 | | LLVMContext &Context) const override; |
229 | 18 | bool shouldInsertFencesForAtomic(const Instruction *I) const override { |
230 | 18 | return true; |
231 | 18 | } |
232 | | }; |
233 | | } |
234 | | |
235 | | #endif |