Coverage Report

Created: 2018-07-19 03:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/CallingConvLower.h
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//===- llvm/CallingConvLower.h - Calling Conventions ------------*- C++ -*-===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This file declares the CCState and CCValAssign classes, used for lowering
11
// and implementing calling conventions.
12
//
13
//===----------------------------------------------------------------------===//
14
15
#ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
16
#define LLVM_CODEGEN_CALLINGCONVLOWER_H
17
18
#include "llvm/ADT/SmallVector.h"
19
#include "llvm/CodeGen/MachineFrameInfo.h"
20
#include "llvm/CodeGen/MachineFunction.h"
21
#include "llvm/CodeGen/TargetCallingConv.h"
22
#include "llvm/IR/CallingConv.h"
23
#include "llvm/MC/MCRegisterInfo.h"
24
25
namespace llvm {
26
27
class CCState;
28
class MVT;
29
class TargetMachine;
30
class TargetRegisterInfo;
31
32
/// CCValAssign - Represent assignment of one arg/retval to a location.
33
0
class CCValAssign {
34
public:
35
  enum LocInfo {
36
    Full,      // The value fills the full location.
37
    SExt,      // The value is sign extended in the location.
38
    ZExt,      // The value is zero extended in the location.
39
    AExt,      // The value is extended with undefined upper bits.
40
    SExtUpper, // The value is in the upper bits of the location and should be
41
               // sign extended when retrieved.
42
    ZExtUpper, // The value is in the upper bits of the location and should be
43
               // zero extended when retrieved.
44
    AExtUpper, // The value is in the upper bits of the location and should be
45
               // extended with undefined upper bits when retrieved.
46
    BCvt,      // The value is bit-converted in the location.
47
    VExt,      // The value is vector-widened in the location.
48
               // FIXME: Not implemented yet. Code that uses AExt to mean
49
               // vector-widen should be fixed to use VExt instead.
50
    FPExt,     // The floating-point value is fp-extended in the location.
51
    Indirect   // The location contains pointer to the value.
52
    // TODO: a subset of the value is in the location.
53
  };
54
55
private:
56
  /// ValNo - This is the value number begin assigned (e.g. an argument number).
57
  unsigned ValNo;
58
59
  /// Loc is either a stack offset or a register number.
60
  unsigned Loc;
61
62
  /// isMem - True if this is a memory loc, false if it is a register loc.
63
  unsigned isMem : 1;
64
65
  /// isCustom - True if this arg/retval requires special handling.
66
  unsigned isCustom : 1;
67
68
  /// Information about how the value is assigned.
69
  LocInfo HTP : 6;
70
71
  /// ValVT - The type of the value being assigned.
72
  MVT ValVT;
73
74
  /// LocVT - The type of the location being assigned to.
75
  MVT LocVT;
76
public:
77
78
  static CCValAssign getReg(unsigned ValNo, MVT ValVT,
79
                            unsigned RegNo, MVT LocVT,
80
8.00M
                            LocInfo HTP) {
81
8.00M
    CCValAssign Ret;
82
8.00M
    Ret.ValNo = ValNo;
83
8.00M
    Ret.Loc = RegNo;
84
8.00M
    Ret.isMem = false;
85
8.00M
    Ret.isCustom = false;
86
8.00M
    Ret.HTP = HTP;
87
8.00M
    Ret.ValVT = ValVT;
88
8.00M
    Ret.LocVT = LocVT;
89
8.00M
    return Ret;
90
8.00M
  }
91
92
  static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
93
                                  unsigned RegNo, MVT LocVT,
94
16.1k
                                  LocInfo HTP) {
95
16.1k
    CCValAssign Ret;
96
16.1k
    Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
97
16.1k
    Ret.isCustom = true;
98
16.1k
    return Ret;
99
16.1k
  }
100
101
  static CCValAssign getMem(unsigned ValNo, MVT ValVT,
102
                            unsigned Offset, MVT LocVT,
103
383k
                            LocInfo HTP) {
104
383k
    CCValAssign Ret;
105
383k
    Ret.ValNo = ValNo;
106
383k
    Ret.Loc = Offset;
107
383k
    Ret.isMem = true;
108
383k
    Ret.isCustom = false;
109
383k
    Ret.HTP = HTP;
110
383k
    Ret.ValVT = ValVT;
111
383k
    Ret.LocVT = LocVT;
112
383k
    return Ret;
113
383k
  }
114
115
  static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
116
                                  unsigned Offset, MVT LocVT,
117
45.0k
                                  LocInfo HTP) {
118
45.0k
    CCValAssign Ret;
119
45.0k
    Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP);
120
45.0k
    Ret.isCustom = true;
121
45.0k
    return Ret;
122
45.0k
  }
123
124
  // There is no need to differentiate between a pending CCValAssign and other
125
  // kinds, as they are stored in a different list.
126
  static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT,
127
6.19k
                                LocInfo HTP, unsigned ExtraInfo = 0) {
128
6.19k
    return getReg(ValNo, ValVT, ExtraInfo, LocVT, HTP);
129
6.19k
  }
130
131
5.94k
  void convertToReg(unsigned RegNo) {
132
5.94k
    Loc = RegNo;
133
5.94k
    isMem = false;
134
5.94k
  }
135
136
417
  void convertToMem(unsigned Offset) {
137
417
    Loc = Offset;
138
417
    isMem = true;
139
417
  }
140
141
142k
  unsigned getValNo() const { return ValNo; }
142
486k
  MVT getValVT() const { return ValVT; }
143
144
7.04M
  bool isRegLoc() const { return !isMem; }
145
129k
  bool isMemLoc() const { return isMem; }
146
147
5.46M
  bool needsCustom() const { return isCustom; }
148
149
7.89M
  unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
150
385k
  unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
151
4.09k
  unsigned getExtraInfo() const { return Loc; }
152
4.52M
  MVT getLocVT() const { return LocVT; }
153
154
8.35M
  LocInfo getLocInfo() const { return HTP; }
155
341k
  bool isExtInLoc() const {
156
341k
    return (HTP == AExt || 
HTP == SExt327k
||
HTP == ZExt327k
);
157
341k
  }
158
159
2.37k
  bool isUpperBitsInLoc() const {
160
2.37k
    return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper;
161
2.37k
  }
162
};
163
164
/// Describes a register that needs to be forwarded from the prologue to a
165
/// musttail call.
166
struct ForwardedRegister {
167
  ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
168
225
      : VReg(VReg), PReg(PReg), VT(VT) {}
169
  unsigned VReg;
170
  MCPhysReg PReg;
171
  MVT VT;
172
};
173
174
/// CCAssignFn - This function assigns a location for Val, updating State to
175
/// reflect the change.  It returns 'true' if it failed to handle Val.
176
typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
177
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
178
                        ISD::ArgFlagsTy ArgFlags, CCState &State);
179
180
/// CCCustomFn - This function assigns a location for Val, possibly updating
181
/// all args to reflect changes and indicates if it handled it. It must set
182
/// isCustom if it handles the arg and returns true.
183
typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
184
                        MVT &LocVT, CCValAssign::LocInfo &LocInfo,
185
                        ISD::ArgFlagsTy &ArgFlags, CCState &State);
186
187
/// CCState - This class holds information needed while lowering arguments and
188
/// return values.  It captures which registers are already assigned and which
189
/// stack slots are used.  It provides accessors to allocate these values.
190
class CCState {
191
private:
192
  CallingConv::ID CallingConv;
193
  bool IsVarArg;
194
  bool AnalyzingMustTailForwardedRegs = false;
195
  MachineFunction &MF;
196
  const TargetRegisterInfo &TRI;
197
  SmallVectorImpl<CCValAssign> &Locs;
198
  LLVMContext &Context;
199
200
  unsigned StackOffset;
201
  unsigned MaxStackArgAlign;
202
  SmallVector<uint32_t, 16> UsedRegs;
203
  SmallVector<CCValAssign, 4> PendingLocs;
204
  SmallVector<ISD::ArgFlagsTy, 4> PendingArgFlags;
205
206
  // ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:
207
  //
208
  // Vector of ByValInfo instances (ByValRegs) is introduced for byval registers
209
  // tracking.
210
  // Or, in another words it tracks byval parameters that are stored in
211
  // general purpose registers.
212
  //
213
  // For 4 byte stack alignment,
214
  // instance index means byval parameter number in formal
215
  // arguments set. Assume, we have some "struct_type" with size = 4 bytes,
216
  // then, for function "foo":
217
  //
218
  // i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t)
219
  //
220
  // ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2)
221
  // ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4).
222
  //
223
  // In case of 8 bytes stack alignment,
224
  // ByValRegs may also contain information about wasted registers.
225
  // In function shown above, r3 would be wasted according to AAPCS rules.
226
  // And in that case ByValRegs[1].Waste would be "true".
227
  // ByValRegs vector size still would be 2,
228
  // while "%t" goes to the stack: it wouldn't be described in ByValRegs.
229
  //
230
  // Supposed use-case for this collection:
231
  // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0.
232
  // 2. HandleByVal fillups ByValRegs.
233
  // 3. Argument analysis (LowerFormatArguments, for example). After
234
  // some byval argument was analyzed, InRegsParamsProcessed is increased.
235
  struct ByValInfo {
236
    ByValInfo(unsigned B, unsigned E, bool IsWaste = false) :
237
470
      Begin(B), End(E), Waste(IsWaste) {}
238
    // First register allocated for current parameter.
239
    unsigned Begin;
240
241
    // First after last register allocated for current parameter.
242
    unsigned End;
243
244
    // Means that current range of registers doesn't belong to any
245
    // parameters. It was wasted due to stack alignment rules.
246
    // For more information see:
247
    // AAPCS, 5.5 Parameter Passing, Stage C, C.3.
248
    bool Waste;
249
  };
250
  SmallVector<ByValInfo, 4 > ByValRegs;
251
252
  // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed
253
  // during argument analysis.
254
  unsigned InRegsParamsProcessed;
255
256
public:
257
  CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
258
          SmallVectorImpl<CCValAssign> &locs, LLVMContext &C);
259
260
8.38M
  void addLoc(const CCValAssign &V) {
261
8.38M
    Locs.push_back(V);
262
8.38M
  }
263
264
47.2k
  LLVMContext &getContext() const { return Context; }
265
6.12M
  MachineFunction &getMachineFunction() const { return MF; }
266
11.6M
  CallingConv::ID getCallingConv() const { return CallingConv; }
267
640k
  bool isVarArg() const { return IsVarArg; }
268
269
  /// getNextStackOffset - Return the next stack offset such that all stack
270
  /// slots satisfy their alignment requirements.
271
3.97M
  unsigned getNextStackOffset() const {
272
3.97M
    return StackOffset;
273
3.97M
  }
274
275
  /// getAlignedCallFrameSize - Return the size of the call frame needed to
276
  /// be able to store all arguments and such that the alignment requirement
277
  /// of each of the arguments is satisfied.
278
162k
  unsigned getAlignedCallFrameSize() const {
279
162k
    return alignTo(StackOffset, MaxStackArgAlign);
280
162k
  }
281
282
  /// isAllocated - Return true if the specified register (or an alias) is
283
  /// allocated.
284
15.1M
  bool isAllocated(unsigned Reg) const {
285
15.1M
    return UsedRegs[Reg/32] & (1 << (Reg&31));
286
15.1M
  }
287
288
  /// AnalyzeFormalArguments - Analyze an array of argument values,
289
  /// incorporating info about the formals into this state.
290
  void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
291
                              CCAssignFn Fn);
292
293
  /// The function will invoke AnalyzeFormalArguments.
294
  void AnalyzeArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
295
121k
                        CCAssignFn Fn) {
296
121k
    AnalyzeFormalArguments(Ins, Fn);
297
121k
  }
298
299
  /// AnalyzeReturn - Analyze the returned values of a return,
300
  /// incorporating info about the result values into this state.
301
  void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
302
                     CCAssignFn Fn);
303
304
  /// CheckReturn - Analyze the return values of a function, returning
305
  /// true if the return can be performed without sret-demotion, and
306
  /// false otherwise.
307
  bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
308
                   CCAssignFn Fn);
309
310
  /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
311
  /// incorporating info about the passed values into this state.
312
  void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
313
                           CCAssignFn Fn);
314
315
  /// AnalyzeCallOperands - Same as above except it takes vectors of types
316
  /// and argument flags.
317
  void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
318
                           SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
319
                           CCAssignFn Fn);
320
321
  /// The function will invoke AnalyzeCallOperands.
322
  void AnalyzeArguments(const SmallVectorImpl<ISD::OutputArg> &Outs,
323
161k
                        CCAssignFn Fn) {
324
161k
    AnalyzeCallOperands(Outs, Fn);
325
161k
  }
326
327
  /// AnalyzeCallResult - Analyze the return values of a call,
328
  /// incorporating info about the passed values into this state.
329
  void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
330
                         CCAssignFn Fn);
331
332
  /// A shadow allocated register is a register that was allocated
333
  /// but wasn't added to the location list (Locs).
334
  /// \returns true if the register was allocated as shadow or false otherwise.
335
  bool IsShadowAllocatedReg(unsigned Reg) const;
336
337
  /// AnalyzeCallResult - Same as above except it's specialized for calls which
338
  /// produce a single value.
339
  void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
340
341
  /// getFirstUnallocated - Return the index of the first unallocated register
342
  /// in the set, or Regs.size() if they are all allocated.
343
8.11M
  unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
344
15.1M
    for (unsigned i = 0; i < Regs.size(); 
++i7.01M
)
345
15.0M
      if (!isAllocated(Regs[i]))
346
7.99M
        return i;
347
8.11M
    
return Regs.size()116k
;
348
8.11M
  }
349
350
  /// AllocateReg - Attempt to allocate one register.  If it is not available,
351
  /// return zero.  Otherwise, return the register, marking it and any aliases
352
  /// as allocated.
353
77.4k
  unsigned AllocateReg(unsigned Reg) {
354
77.4k
    if (isAllocated(Reg)) 
return 01.87k
;
355
75.5k
    MarkAllocated(Reg);
356
75.5k
    return Reg;
357
75.5k
  }
358
359
  /// Version of AllocateReg with extra register to be shadowed.
360
9.82k
  unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
361
9.82k
    if (isAllocated(Reg)) 
return 0109
;
362
9.71k
    MarkAllocated(Reg);
363
9.71k
    MarkAllocated(ShadowReg);
364
9.71k
    return Reg;
365
9.71k
  }
366
367
  /// AllocateReg - Attempt to allocate one of the specified registers.  If none
368
  /// are available, return zero.  Otherwise, return the first one available,
369
  /// marking it and any aliases as allocated.
370
1.30M
  unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) {
371
1.30M
    unsigned FirstUnalloc = getFirstUnallocated(Regs);
372
1.30M
    if (FirstUnalloc == Regs.size())
373
62.2k
      return 0;    // Didn't find the reg.
374
1.24M
375
1.24M
    // Mark the register and any aliases as allocated.
376
1.24M
    unsigned Reg = Regs[FirstUnalloc];
377
1.24M
    MarkAllocated(Reg);
378
1.24M
    return Reg;
379
1.24M
  }
380
381
  /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
382
  /// registers. If this is not possible, return zero. Otherwise, return the first
383
  /// register of the block that were allocated, marking the entire block as allocated.
384
4.66k
  unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
385
4.66k
    if (RegsRequired > Regs.size())
386
1
      return 0;
387
4.66k
388
9.20k
    
for (unsigned StartIdx = 0; 4.66k
StartIdx <= Regs.size() - RegsRequired;
389
8.99k
         
++StartIdx4.54k
) {
390
8.99k
      bool BlockAvailable = true;
391
8.99k
      // Check for already-allocated regs in this block
392
14.5k
      for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; 
++BlockIdx5.57k
) {
393
10.1k
        if (isAllocated(Regs[StartIdx + BlockIdx])) {
394
4.54k
          BlockAvailable = false;
395
4.54k
          break;
396
4.54k
        }
397
10.1k
      }
398
8.99k
      if (BlockAvailable) {
399
4.45k
        // Mark the entire block as allocated
400
10.0k
        for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; 
++BlockIdx5.57k
) {
401
5.57k
          MarkAllocated(Regs[StartIdx + BlockIdx]);
402
5.57k
        }
403
4.45k
        return Regs[StartIdx];
404
4.45k
      }
405
8.99k
    }
406
4.66k
    // No block was available
407
4.66k
    
return 0217
;
408
4.66k
  }
409
410
  /// Version of AllocateReg with list of registers to be shadowed.
411
6.78M
  unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
412
6.78M
    unsigned FirstUnalloc = getFirstUnallocated(Regs);
413
6.78M
    if (FirstUnalloc == Regs.size())
414
54.2k
      return 0;    // Didn't find the reg.
415
6.73M
416
6.73M
    // Mark the register and any aliases as allocated.
417
6.73M
    unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
418
6.73M
    MarkAllocated(Reg);
419
6.73M
    MarkAllocated(ShadowReg);
420
6.73M
    return Reg;
421
6.73M
  }
422
423
  /// AllocateStack - Allocate a chunk of stack space with the specified size
424
  /// and alignment.
425
361k
  unsigned AllocateStack(unsigned Size, unsigned Align) {
426
361k
    assert(Align && ((Align - 1) & Align) == 0); // Align is power of 2.
427
361k
    StackOffset = alignTo(StackOffset, Align);
428
361k
    unsigned Result = StackOffset;
429
361k
    StackOffset += Size;
430
361k
    MaxStackArgAlign = std::max(Align, MaxStackArgAlign);
431
361k
    ensureMaxAlignment(Align);
432
361k
    return Result;
433
361k
  }
434
435
362k
  void ensureMaxAlignment(unsigned Align) {
436
362k
    if (!AnalyzingMustTailForwardedRegs)
437
362k
      MF.getFrameInfo().ensureMaxAlignment(Align);
438
362k
  }
439
440
  /// Version of AllocateStack with extra register to be shadowed.
441
0
  unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) {
442
0
    MarkAllocated(ShadowReg);
443
0
    return AllocateStack(Size, Align);
444
0
  }
445
446
  /// Version of AllocateStack with list of extra registers to be shadowed.
447
  /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
448
  unsigned AllocateStack(unsigned Size, unsigned Align,
449
16.0k
                         ArrayRef<MCPhysReg> ShadowRegs) {
450
79.8k
    for (unsigned i = 0; i < ShadowRegs.size(); 
++i63.8k
)
451
63.8k
      MarkAllocated(ShadowRegs[i]);
452
16.0k
    return AllocateStack(Size, Align);
453
16.0k
  }
454
455
  // HandleByVal - Allocate a stack slot large enough to pass an argument by
456
  // value. The size and alignment information of the argument is encoded in its
457
  // parameter attribute.
458
  void HandleByVal(unsigned ValNo, MVT ValVT,
459
                   MVT LocVT, CCValAssign::LocInfo LocInfo,
460
                   int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
461
462
  // Returns count of byval arguments that are to be stored (even partly)
463
  // in registers.
464
31.8k
  unsigned getInRegsParamsCount() const { return ByValRegs.size(); }
465
466
  // Returns count of byval in-regs arguments proceed.
467
19.1k
  unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; }
468
469
  // Get information about N-th byval parameter that is stored in registers.
470
  // Here "ByValParamIndex" is N.
471
  void getInRegsParamInfo(unsigned InRegsParamRecordIndex,
472
504
                          unsigned& BeginReg, unsigned& EndReg) const {
473
504
    assert(InRegsParamRecordIndex < ByValRegs.size() &&
474
504
           "Wrong ByVal parameter index");
475
504
476
504
    const ByValInfo& info = ByValRegs[InRegsParamRecordIndex];
477
504
    BeginReg = info.Begin;
478
504
    EndReg = info.End;
479
504
  }
480
481
  // Add information about parameter that is kept in registers.
482
470
  void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) {
483
470
    ByValRegs.push_back(ByValInfo(RegBegin, RegEnd));
484
470
  }
485
486
  // Goes either to next byval parameter (excluding "waste" record), or
487
  // to the end of collection.
488
  // Returns false, if end is reached.
489
517
  bool nextInRegsParam() {
490
517
    unsigned e = ByValRegs.size();
491
517
    if (InRegsParamsProcessed < e)
492
504
      ++InRegsParamsProcessed;
493
517
    return InRegsParamsProcessed < e;
494
517
  }
495
496
  // Clear byval registers tracking info.
497
5.57M
  void clearByValRegsInfo() {
498
5.57M
    InRegsParamsProcessed = 0;
499
5.57M
    ByValRegs.clear();
500
5.57M
  }
501
502
  // Rewind byval registers tracking info.
503
37.5k
  void rewindByValRegsInfo() {
504
37.5k
    InRegsParamsProcessed = 0;
505
37.5k
  }
506
507
  // Get list of pending assignments
508
13.6k
  SmallVectorImpl<CCValAssign> &getPendingLocs() {
509
13.6k
    return PendingLocs;
510
13.6k
  }
511
512
  // Get a list of argflags for pending assignments.
513
0
  SmallVectorImpl<ISD::ArgFlagsTy> &getPendingArgFlags() {
514
0
    return PendingArgFlags;
515
0
  }
516
517
  /// Compute the remaining unused register parameters that would be used for
518
  /// the given value type. This is useful when varargs are passed in the
519
  /// registers that normal prototyped parameters would be passed in, or for
520
  /// implementing perfect forwarding.
521
  void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
522
                                   CCAssignFn Fn);
523
524
  /// Compute the set of registers that need to be preserved and forwarded to
525
  /// any musttail calls.
526
  void analyzeMustTailForwardedRegisters(
527
      SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
528
      CCAssignFn Fn);
529
530
  /// Returns true if the results of the two calling conventions are compatible.
531
  /// This is usually part of the check for tailcall eligibility.
532
  static bool resultsCompatible(CallingConv::ID CalleeCC,
533
                                CallingConv::ID CallerCC, MachineFunction &MF,
534
                                LLVMContext &C,
535
                                const SmallVectorImpl<ISD::InputArg> &Ins,
536
                                CCAssignFn CalleeFn, CCAssignFn CallerFn);
537
538
  /// The function runs an additional analysis pass over function arguments.
539
  /// It will mark each argument with the attribute flag SecArgPass.
540
  /// After running, it will sort the locs list.
541
  template <class T>
542
  void AnalyzeArgumentsSecondPass(const SmallVectorImpl<T> &Args,
543
61
                                  CCAssignFn Fn) {
544
61
    unsigned NumFirstPassLocs = Locs.size();
545
61
546
61
    /// Creates similar argument list to \p Args in which each argument is
547
61
    /// marked using SecArgPass flag.
548
61
    SmallVector<T, 16> SecPassArg;
549
61
    // SmallVector<ISD::InputArg, 16> SecPassArg;
550
183
    for (auto Arg : Args) {
551
183
      Arg.Flags.setSecArgPass();
552
183
      SecPassArg.push_back(Arg);
553
183
    }
554
61
555
61
    // Run the second argument pass
556
61
    AnalyzeArguments(SecPassArg, Fn);
557
61
558
61
    // Sort the locations of the arguments according to their original position.
559
61
    SmallVector<CCValAssign, 16> TmpArgLocs;
560
61
    std::swap(TmpArgLocs, Locs);
561
61
    auto B = TmpArgLocs.begin(), E = TmpArgLocs.end();
562
61
    std::merge(B, B + NumFirstPassLocs, B + NumFirstPassLocs, E,
563
61
               std::back_inserter(Locs),
564
61
               [](const CCValAssign &A, const CCValAssign &B) -> bool {
565
52
                 return A.getValNo() < B.getValNo();
566
52
               });
void llvm::CCState::AnalyzeArgumentsSecondPass<llvm::ISD::InputArg>(llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, bool (*)(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&))::'lambda'(llvm::CCValAssign const&, llvm::CCValAssign const&)::operator()(llvm::CCValAssign const&, llvm::CCValAssign const&) const
Line
Count
Source
564
44
               [](const CCValAssign &A, const CCValAssign &B) -> bool {
565
44
                 return A.getValNo() < B.getValNo();
566
44
               });
void llvm::CCState::AnalyzeArgumentsSecondPass<llvm::ISD::OutputArg>(llvm::SmallVectorImpl<llvm::ISD::OutputArg> const&, bool (*)(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&))::'lambda'(llvm::CCValAssign const&, llvm::CCValAssign const&)::operator()(llvm::CCValAssign const&, llvm::CCValAssign const&) const
Line
Count
Source
564
8
               [](const CCValAssign &A, const CCValAssign &B) -> bool {
565
8
                 return A.getValNo() < B.getValNo();
566
8
               });
567
61
  }
void llvm::CCState::AnalyzeArgumentsSecondPass<llvm::ISD::InputArg>(llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, bool (*)(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&))
Line
Count
Source
543
53
                                  CCAssignFn Fn) {
544
53
    unsigned NumFirstPassLocs = Locs.size();
545
53
546
53
    /// Creates similar argument list to \p Args in which each argument is
547
53
    /// marked using SecArgPass flag.
548
53
    SmallVector<T, 16> SecPassArg;
549
53
    // SmallVector<ISD::InputArg, 16> SecPassArg;
550
164
    for (auto Arg : Args) {
551
164
      Arg.Flags.setSecArgPass();
552
164
      SecPassArg.push_back(Arg);
553
164
    }
554
53
555
53
    // Run the second argument pass
556
53
    AnalyzeArguments(SecPassArg, Fn);
557
53
558
53
    // Sort the locations of the arguments according to their original position.
559
53
    SmallVector<CCValAssign, 16> TmpArgLocs;
560
53
    std::swap(TmpArgLocs, Locs);
561
53
    auto B = TmpArgLocs.begin(), E = TmpArgLocs.end();
562
53
    std::merge(B, B + NumFirstPassLocs, B + NumFirstPassLocs, E,
563
53
               std::back_inserter(Locs),
564
53
               [](const CCValAssign &A, const CCValAssign &B) -> bool {
565
53
                 return A.getValNo() < B.getValNo();
566
53
               });
567
53
  }
void llvm::CCState::AnalyzeArgumentsSecondPass<llvm::ISD::OutputArg>(llvm::SmallVectorImpl<llvm::ISD::OutputArg> const&, bool (*)(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&))
Line
Count
Source
543
8
                                  CCAssignFn Fn) {
544
8
    unsigned NumFirstPassLocs = Locs.size();
545
8
546
8
    /// Creates similar argument list to \p Args in which each argument is
547
8
    /// marked using SecArgPass flag.
548
8
    SmallVector<T, 16> SecPassArg;
549
8
    // SmallVector<ISD::InputArg, 16> SecPassArg;
550
19
    for (auto Arg : Args) {
551
19
      Arg.Flags.setSecArgPass();
552
19
      SecPassArg.push_back(Arg);
553
19
    }
554
8
555
8
    // Run the second argument pass
556
8
    AnalyzeArguments(SecPassArg, Fn);
557
8
558
8
    // Sort the locations of the arguments according to their original position.
559
8
    SmallVector<CCValAssign, 16> TmpArgLocs;
560
8
    std::swap(TmpArgLocs, Locs);
561
8
    auto B = TmpArgLocs.begin(), E = TmpArgLocs.end();
562
8
    std::merge(B, B + NumFirstPassLocs, B + NumFirstPassLocs, E,
563
8
               std::back_inserter(Locs),
564
8
               [](const CCValAssign &A, const CCValAssign &B) -> bool {
565
8
                 return A.getValNo() < B.getValNo();
566
8
               });
567
8
  }
568
569
private:
570
  /// MarkAllocated - Mark a register and all of its aliases as allocated.
571
  void MarkAllocated(unsigned Reg);
572
};
573
574
} // end namespace llvm
575
576
#endif // LLVM_CODEGEN_CALLINGCONVLOWER_H