Coverage Report

Created: 2019-02-21 13:17

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/CallingConvLower.h
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Source (jump to first uncovered line)
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//===- llvm/CallingConvLower.h - Calling Conventions ------------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file declares the CCState and CCValAssign classes, used for lowering
10
// and implementing calling conventions.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
15
#define LLVM_CODEGEN_CALLINGCONVLOWER_H
16
17
#include "llvm/ADT/SmallVector.h"
18
#include "llvm/CodeGen/MachineFrameInfo.h"
19
#include "llvm/CodeGen/MachineFunction.h"
20
#include "llvm/CodeGen/TargetCallingConv.h"
21
#include "llvm/IR/CallingConv.h"
22
#include "llvm/MC/MCRegisterInfo.h"
23
24
namespace llvm {
25
26
class CCState;
27
class MVT;
28
class TargetMachine;
29
class TargetRegisterInfo;
30
31
/// CCValAssign - Represent assignment of one arg/retval to a location.
32
0
class CCValAssign {
33
public:
34
  enum LocInfo {
35
    Full,      // The value fills the full location.
36
    SExt,      // The value is sign extended in the location.
37
    ZExt,      // The value is zero extended in the location.
38
    AExt,      // The value is extended with undefined upper bits.
39
    SExtUpper, // The value is in the upper bits of the location and should be
40
               // sign extended when retrieved.
41
    ZExtUpper, // The value is in the upper bits of the location and should be
42
               // zero extended when retrieved.
43
    AExtUpper, // The value is in the upper bits of the location and should be
44
               // extended with undefined upper bits when retrieved.
45
    BCvt,      // The value is bit-converted in the location.
46
    VExt,      // The value is vector-widened in the location.
47
               // FIXME: Not implemented yet. Code that uses AExt to mean
48
               // vector-widen should be fixed to use VExt instead.
49
    FPExt,     // The floating-point value is fp-extended in the location.
50
    Indirect   // The location contains pointer to the value.
51
    // TODO: a subset of the value is in the location.
52
  };
53
54
private:
55
  /// ValNo - This is the value number begin assigned (e.g. an argument number).
56
  unsigned ValNo;
57
58
  /// Loc is either a stack offset or a register number.
59
  unsigned Loc;
60
61
  /// isMem - True if this is a memory loc, false if it is a register loc.
62
  unsigned isMem : 1;
63
64
  /// isCustom - True if this arg/retval requires special handling.
65
  unsigned isCustom : 1;
66
67
  /// Information about how the value is assigned.
68
  LocInfo HTP : 6;
69
70
  /// ValVT - The type of the value being assigned.
71
  MVT ValVT;
72
73
  /// LocVT - The type of the location being assigned to.
74
  MVT LocVT;
75
public:
76
77
  static CCValAssign getReg(unsigned ValNo, MVT ValVT,
78
                            unsigned RegNo, MVT LocVT,
79
7.23M
                            LocInfo HTP) {
80
7.23M
    CCValAssign Ret;
81
7.23M
    Ret.ValNo = ValNo;
82
7.23M
    Ret.Loc = RegNo;
83
7.23M
    Ret.isMem = false;
84
7.23M
    Ret.isCustom = false;
85
7.23M
    Ret.HTP = HTP;
86
7.23M
    Ret.ValVT = ValVT;
87
7.23M
    Ret.LocVT = LocVT;
88
7.23M
    return Ret;
89
7.23M
  }
90
91
  static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
92
                                  unsigned RegNo, MVT LocVT,
93
17.0k
                                  LocInfo HTP) {
94
17.0k
    CCValAssign Ret;
95
17.0k
    Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
96
17.0k
    Ret.isCustom = true;
97
17.0k
    return Ret;
98
17.0k
  }
99
100
  static CCValAssign getMem(unsigned ValNo, MVT ValVT,
101
                            unsigned Offset, MVT LocVT,
102
330k
                            LocInfo HTP) {
103
330k
    CCValAssign Ret;
104
330k
    Ret.ValNo = ValNo;
105
330k
    Ret.Loc = Offset;
106
330k
    Ret.isMem = true;
107
330k
    Ret.isCustom = false;
108
330k
    Ret.HTP = HTP;
109
330k
    Ret.ValVT = ValVT;
110
330k
    Ret.LocVT = LocVT;
111
330k
    return Ret;
112
330k
  }
113
114
  static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
115
                                  unsigned Offset, MVT LocVT,
116
49.5k
                                  LocInfo HTP) {
117
49.5k
    CCValAssign Ret;
118
49.5k
    Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP);
119
49.5k
    Ret.isCustom = true;
120
49.5k
    return Ret;
121
49.5k
  }
122
123
  // There is no need to differentiate between a pending CCValAssign and other
124
  // kinds, as they are stored in a different list.
125
  static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT,
126
7.68k
                                LocInfo HTP, unsigned ExtraInfo = 0) {
127
7.68k
    return getReg(ValNo, ValVT, ExtraInfo, LocVT, HTP);
128
7.68k
  }
129
130
7.39k
  void convertToReg(unsigned RegNo) {
131
7.39k
    Loc = RegNo;
132
7.39k
    isMem = false;
133
7.39k
  }
134
135
455
  void convertToMem(unsigned Offset) {
136
455
    Loc = Offset;
137
455
    isMem = true;
138
455
  }
139
140
152k
  unsigned getValNo() const { return ValNo; }
141
460k
  MVT getValVT() const { return ValVT; }
142
143
6.52M
  bool isRegLoc() const { return !isMem; }
144
151k
  bool isMemLoc() const { return isMem; }
145
146
5.52M
  bool needsCustom() const { return isCustom; }
147
148
7.30M
  unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
149
329k
  unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
150
4.61k
  unsigned getExtraInfo() const { return Loc; }
151
4.36M
  MVT getLocVT() const { return LocVT; }
152
153
7.73M
  LocInfo getLocInfo() const { return HTP; }
154
337k
  bool isExtInLoc() const {
155
337k
    return (HTP == AExt || 
HTP == SExt322k
||
HTP == ZExt322k
);
156
337k
  }
157
158
2.41k
  bool isUpperBitsInLoc() const {
159
2.41k
    return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper;
160
2.41k
  }
161
};
162
163
/// Describes a register that needs to be forwarded from the prologue to a
164
/// musttail call.
165
struct ForwardedRegister {
166
  ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
167
345
      : VReg(VReg), PReg(PReg), VT(VT) {}
168
  unsigned VReg;
169
  MCPhysReg PReg;
170
  MVT VT;
171
};
172
173
/// CCAssignFn - This function assigns a location for Val, updating State to
174
/// reflect the change.  It returns 'true' if it failed to handle Val.
175
typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
176
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
177
                        ISD::ArgFlagsTy ArgFlags, CCState &State);
178
179
/// CCCustomFn - This function assigns a location for Val, possibly updating
180
/// all args to reflect changes and indicates if it handled it. It must set
181
/// isCustom if it handles the arg and returns true.
182
typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
183
                        MVT &LocVT, CCValAssign::LocInfo &LocInfo,
184
                        ISD::ArgFlagsTy &ArgFlags, CCState &State);
185
186
/// CCState - This class holds information needed while lowering arguments and
187
/// return values.  It captures which registers are already assigned and which
188
/// stack slots are used.  It provides accessors to allocate these values.
189
class CCState {
190
private:
191
  CallingConv::ID CallingConv;
192
  bool IsVarArg;
193
  bool AnalyzingMustTailForwardedRegs = false;
194
  MachineFunction &MF;
195
  const TargetRegisterInfo &TRI;
196
  SmallVectorImpl<CCValAssign> &Locs;
197
  LLVMContext &Context;
198
199
  unsigned StackOffset;
200
  unsigned MaxStackArgAlign;
201
  SmallVector<uint32_t, 16> UsedRegs;
202
  SmallVector<CCValAssign, 4> PendingLocs;
203
  SmallVector<ISD::ArgFlagsTy, 4> PendingArgFlags;
204
205
  // ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:
206
  //
207
  // Vector of ByValInfo instances (ByValRegs) is introduced for byval registers
208
  // tracking.
209
  // Or, in another words it tracks byval parameters that are stored in
210
  // general purpose registers.
211
  //
212
  // For 4 byte stack alignment,
213
  // instance index means byval parameter number in formal
214
  // arguments set. Assume, we have some "struct_type" with size = 4 bytes,
215
  // then, for function "foo":
216
  //
217
  // i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t)
218
  //
219
  // ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2)
220
  // ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4).
221
  //
222
  // In case of 8 bytes stack alignment,
223
  // ByValRegs may also contain information about wasted registers.
224
  // In function shown above, r3 would be wasted according to AAPCS rules.
225
  // And in that case ByValRegs[1].Waste would be "true".
226
  // ByValRegs vector size still would be 2,
227
  // while "%t" goes to the stack: it wouldn't be described in ByValRegs.
228
  //
229
  // Supposed use-case for this collection:
230
  // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0.
231
  // 2. HandleByVal fillups ByValRegs.
232
  // 3. Argument analysis (LowerFormatArguments, for example). After
233
  // some byval argument was analyzed, InRegsParamsProcessed is increased.
234
  struct ByValInfo {
235
    ByValInfo(unsigned B, unsigned E, bool IsWaste = false) :
236
474
      Begin(B), End(E), Waste(IsWaste) {}
237
    // First register allocated for current parameter.
238
    unsigned Begin;
239
240
    // First after last register allocated for current parameter.
241
    unsigned End;
242
243
    // Means that current range of registers doesn't belong to any
244
    // parameters. It was wasted due to stack alignment rules.
245
    // For more information see:
246
    // AAPCS, 5.5 Parameter Passing, Stage C, C.3.
247
    bool Waste;
248
  };
249
  SmallVector<ByValInfo, 4 > ByValRegs;
250
251
  // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed
252
  // during argument analysis.
253
  unsigned InRegsParamsProcessed;
254
255
public:
256
  CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
257
          SmallVectorImpl<CCValAssign> &locs, LLVMContext &C);
258
259
7.56M
  void addLoc(const CCValAssign &V) {
260
7.56M
    Locs.push_back(V);
261
7.56M
  }
262
263
1.94k
  LLVMContext &getContext() const { return Context; }
264
5.45M
  MachineFunction &getMachineFunction() const { return MF; }
265
11.6M
  CallingConv::ID getCallingConv() const { return CallingConv; }
266
502k
  bool isVarArg() const { return IsVarArg; }
267
268
  /// getNextStackOffset - Return the next stack offset such that all stack
269
  /// slots satisfy their alignment requirements.
270
3.81M
  unsigned getNextStackOffset() const {
271
3.81M
    return StackOffset;
272
3.81M
  }
273
274
  /// getAlignedCallFrameSize - Return the size of the call frame needed to
275
  /// be able to store all arguments and such that the alignment requirement
276
  /// of each of the arguments is satisfied.
277
152k
  unsigned getAlignedCallFrameSize() const {
278
152k
    return alignTo(StackOffset, MaxStackArgAlign);
279
152k
  }
280
281
  /// isAllocated - Return true if the specified register (or an alias) is
282
  /// allocated.
283
14.0M
  bool isAllocated(unsigned Reg) const {
284
14.0M
    return UsedRegs[Reg/32] & (1 << (Reg&31));
285
14.0M
  }
286
287
  /// AnalyzeFormalArguments - Analyze an array of argument values,
288
  /// incorporating info about the formals into this state.
289
  void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
290
                              CCAssignFn Fn);
291
292
  /// The function will invoke AnalyzeFormalArguments.
293
  void AnalyzeArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
294
125k
                        CCAssignFn Fn) {
295
125k
    AnalyzeFormalArguments(Ins, Fn);
296
125k
  }
297
298
  /// AnalyzeReturn - Analyze the returned values of a return,
299
  /// incorporating info about the result values into this state.
300
  void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
301
                     CCAssignFn Fn);
302
303
  /// CheckReturn - Analyze the return values of a function, returning
304
  /// true if the return can be performed without sret-demotion, and
305
  /// false otherwise.
306
  bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
307
                   CCAssignFn Fn);
308
309
  /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
310
  /// incorporating info about the passed values into this state.
311
  void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
312
                           CCAssignFn Fn);
313
314
  /// AnalyzeCallOperands - Same as above except it takes vectors of types
315
  /// and argument flags.
316
  void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
317
                           SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
318
                           CCAssignFn Fn);
319
320
  /// The function will invoke AnalyzeCallOperands.
321
  void AnalyzeArguments(const SmallVectorImpl<ISD::OutputArg> &Outs,
322
150k
                        CCAssignFn Fn) {
323
150k
    AnalyzeCallOperands(Outs, Fn);
324
150k
  }
325
326
  /// AnalyzeCallResult - Analyze the return values of a call,
327
  /// incorporating info about the passed values into this state.
328
  void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
329
                         CCAssignFn Fn);
330
331
  /// A shadow allocated register is a register that was allocated
332
  /// but wasn't added to the location list (Locs).
333
  /// \returns true if the register was allocated as shadow or false otherwise.
334
  bool IsShadowAllocatedReg(unsigned Reg) const;
335
336
  /// AnalyzeCallResult - Same as above except it's specialized for calls which
337
  /// produce a single value.
338
  void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
339
340
  /// getFirstUnallocated - Return the index of the first unallocated register
341
  /// in the set, or Regs.size() if they are all allocated.
342
7.35M
  unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
343
14.0M
    for (unsigned i = 0; i < Regs.size(); 
++i6.66M
)
344
13.9M
      if (!isAllocated(Regs[i]))
345
7.23M
        return i;
346
7.35M
    
return Regs.size()120k
;
347
7.35M
  }
348
349
  /// AllocateReg - Attempt to allocate one register.  If it is not available,
350
  /// return zero.  Otherwise, return the register, marking it and any aliases
351
  /// as allocated.
352
89.6k
  unsigned AllocateReg(unsigned Reg) {
353
89.6k
    if (isAllocated(Reg)) 
return 01.97k
;
354
87.6k
    MarkAllocated(Reg);
355
87.6k
    return Reg;
356
87.6k
  }
357
358
  /// Version of AllocateReg with extra register to be shadowed.
359
6.67k
  unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
360
6.67k
    if (isAllocated(Reg)) 
return 0109
;
361
6.56k
    MarkAllocated(Reg);
362
6.56k
    MarkAllocated(ShadowReg);
363
6.56k
    return Reg;
364
6.56k
  }
365
366
  /// AllocateReg - Attempt to allocate one of the specified registers.  If none
367
  /// are available, return zero.  Otherwise, return the first one available,
368
  /// marking it and any aliases as allocated.
369
1.36M
  unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) {
370
1.36M
    unsigned FirstUnalloc = getFirstUnallocated(Regs);
371
1.36M
    if (FirstUnalloc == Regs.size())
372
67.4k
      return 0;    // Didn't find the reg.
373
1.30M
374
1.30M
    // Mark the register and any aliases as allocated.
375
1.30M
    unsigned Reg = Regs[FirstUnalloc];
376
1.30M
    MarkAllocated(Reg);
377
1.30M
    return Reg;
378
1.30M
  }
379
380
  /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
381
  /// registers. If this is not possible, return zero. Otherwise, return the first
382
  /// register of the block that were allocated, marking the entire block as allocated.
383
5.62k
  unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
384
5.62k
    if (RegsRequired > Regs.size())
385
1
      return 0;
386
5.61k
387
11.4k
    
for (unsigned StartIdx = 0; 5.61k
StartIdx <= Regs.size() - RegsRequired;
388
11.2k
         
++StartIdx5.83k
) {
389
11.2k
      bool BlockAvailable = true;
390
11.2k
      // Check for already-allocated regs in this block
391
18.2k
      for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; 
++BlockIdx7.02k
) {
392
12.8k
        if (isAllocated(Regs[StartIdx + BlockIdx])) {
393
5.83k
          BlockAvailable = false;
394
5.83k
          break;
395
5.83k
        }
396
12.8k
      }
397
11.2k
      if (BlockAvailable) {
398
5.38k
        // Mark the entire block as allocated
399
12.4k
        for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; 
++BlockIdx7.02k
) {
400
7.02k
          MarkAllocated(Regs[StartIdx + BlockIdx]);
401
7.02k
        }
402
5.38k
        return Regs[StartIdx];
403
5.38k
      }
404
11.2k
    }
405
5.61k
    // No block was available
406
5.61k
    
return 0233
;
407
5.61k
  }
408
409
  /// Version of AllocateReg with list of registers to be shadowed.
410
5.96M
  unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
411
5.96M
    unsigned FirstUnalloc = getFirstUnallocated(Regs);
412
5.96M
    if (FirstUnalloc == Regs.size())
413
52.9k
      return 0;    // Didn't find the reg.
414
5.91M
415
5.91M
    // Mark the register and any aliases as allocated.
416
5.91M
    unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
417
5.91M
    MarkAllocated(Reg);
418
5.91M
    MarkAllocated(ShadowReg);
419
5.91M
    return Reg;
420
5.91M
  }
421
422
  /// AllocateStack - Allocate a chunk of stack space with the specified size
423
  /// and alignment.
424
306k
  unsigned AllocateStack(unsigned Size, unsigned Align) {
425
306k
    assert(Align && ((Align - 1) & Align) == 0); // Align is power of 2.
426
306k
    StackOffset = alignTo(StackOffset, Align);
427
306k
    unsigned Result = StackOffset;
428
306k
    StackOffset += Size;
429
306k
    MaxStackArgAlign = std::max(Align, MaxStackArgAlign);
430
306k
    ensureMaxAlignment(Align);
431
306k
    return Result;
432
306k
  }
433
434
308k
  void ensureMaxAlignment(unsigned Align) {
435
308k
    if (!AnalyzingMustTailForwardedRegs)
436
308k
      MF.getFrameInfo().ensureMaxAlignment(Align);
437
308k
  }
438
439
  /// Version of AllocateStack with extra register to be shadowed.
440
0
  unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) {
441
0
    MarkAllocated(ShadowReg);
442
0
    return AllocateStack(Size, Align);
443
0
  }
444
445
  /// Version of AllocateStack with list of extra registers to be shadowed.
446
  /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
447
  unsigned AllocateStack(unsigned Size, unsigned Align,
448
17.2k
                         ArrayRef<MCPhysReg> ShadowRegs) {
449
86.1k
    for (unsigned i = 0; i < ShadowRegs.size(); 
++i68.8k
)
450
68.8k
      MarkAllocated(ShadowRegs[i]);
451
17.2k
    return AllocateStack(Size, Align);
452
17.2k
  }
453
454
  // HandleByVal - Allocate a stack slot large enough to pass an argument by
455
  // value. The size and alignment information of the argument is encoded in its
456
  // parameter attribute.
457
  void HandleByVal(unsigned ValNo, MVT ValVT,
458
                   MVT LocVT, CCValAssign::LocInfo LocInfo,
459
                   int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
460
461
  // Returns count of byval arguments that are to be stored (even partly)
462
  // in registers.
463
33.3k
  unsigned getInRegsParamsCount() const { return ByValRegs.size(); }
464
465
  // Returns count of byval in-regs arguments proceed.
466
20.5k
  unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; }
467
468
  // Get information about N-th byval parameter that is stored in registers.
469
  // Here "ByValParamIndex" is N.
470
  void getInRegsParamInfo(unsigned InRegsParamRecordIndex,
471
506
                          unsigned& BeginReg, unsigned& EndReg) const {
472
506
    assert(InRegsParamRecordIndex < ByValRegs.size() &&
473
506
           "Wrong ByVal parameter index");
474
506
475
506
    const ByValInfo& info = ByValRegs[InRegsParamRecordIndex];
476
506
    BeginReg = info.Begin;
477
506
    EndReg = info.End;
478
506
  }
479
480
  // Add information about parameter that is kept in registers.
481
474
  void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) {
482
474
    ByValRegs.push_back(ByValInfo(RegBegin, RegEnd));
483
474
  }
484
485
  // Goes either to next byval parameter (excluding "waste" record), or
486
  // to the end of collection.
487
  // Returns false, if end is reached.
488
519
  bool nextInRegsParam() {
489
519
    unsigned e = ByValRegs.size();
490
519
    if (InRegsParamsProcessed < e)
491
506
      ++InRegsParamsProcessed;
492
519
    return InRegsParamsProcessed < e;
493
519
  }
494
495
  // Clear byval registers tracking info.
496
4.93M
  void clearByValRegsInfo() {
497
4.93M
    InRegsParamsProcessed = 0;
498
4.93M
    ByValRegs.clear();
499
4.93M
  }
500
501
  // Rewind byval registers tracking info.
502
39.2k
  void rewindByValRegsInfo() {
503
39.2k
    InRegsParamsProcessed = 0;
504
39.2k
  }
505
506
  // Get list of pending assignments
507
15.1k
  SmallVectorImpl<CCValAssign> &getPendingLocs() {
508
15.1k
    return PendingLocs;
509
15.1k
  }
510
511
  // Get a list of argflags for pending assignments.
512
0
  SmallVectorImpl<ISD::ArgFlagsTy> &getPendingArgFlags() {
513
0
    return PendingArgFlags;
514
0
  }
515
516
  /// Compute the remaining unused register parameters that would be used for
517
  /// the given value type. This is useful when varargs are passed in the
518
  /// registers that normal prototyped parameters would be passed in, or for
519
  /// implementing perfect forwarding.
520
  void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
521
                                   CCAssignFn Fn);
522
523
  /// Compute the set of registers that need to be preserved and forwarded to
524
  /// any musttail calls.
525
  void analyzeMustTailForwardedRegisters(
526
      SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
527
      CCAssignFn Fn);
528
529
  /// Returns true if the results of the two calling conventions are compatible.
530
  /// This is usually part of the check for tailcall eligibility.
531
  static bool resultsCompatible(CallingConv::ID CalleeCC,
532
                                CallingConv::ID CallerCC, MachineFunction &MF,
533
                                LLVMContext &C,
534
                                const SmallVectorImpl<ISD::InputArg> &Ins,
535
                                CCAssignFn CalleeFn, CCAssignFn CallerFn);
536
537
  /// The function runs an additional analysis pass over function arguments.
538
  /// It will mark each argument with the attribute flag SecArgPass.
539
  /// After running, it will sort the locs list.
540
  template <class T>
541
  void AnalyzeArgumentsSecondPass(const SmallVectorImpl<T> &Args,
542
61
                                  CCAssignFn Fn) {
543
61
    unsigned NumFirstPassLocs = Locs.size();
544
61
545
61
    /// Creates similar argument list to \p Args in which each argument is
546
61
    /// marked using SecArgPass flag.
547
61
    SmallVector<T, 16> SecPassArg;
548
61
    // SmallVector<ISD::InputArg, 16> SecPassArg;
549
183
    for (auto Arg : Args) {
550
183
      Arg.Flags.setSecArgPass();
551
183
      SecPassArg.push_back(Arg);
552
183
    }
553
61
554
61
    // Run the second argument pass
555
61
    AnalyzeArguments(SecPassArg, Fn);
556
61
557
61
    // Sort the locations of the arguments according to their original position.
558
61
    SmallVector<CCValAssign, 16> TmpArgLocs;
559
61
    std::swap(TmpArgLocs, Locs);
560
61
    auto B = TmpArgLocs.begin(), E = TmpArgLocs.end();
561
61
    std::merge(B, B + NumFirstPassLocs, B + NumFirstPassLocs, E,
562
61
               std::back_inserter(Locs),
563
61
               [](const CCValAssign &A, const CCValAssign &B) -> bool {
564
52
                 return A.getValNo() < B.getValNo();
565
52
               });
void llvm::CCState::AnalyzeArgumentsSecondPass<llvm::ISD::InputArg>(llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, bool (*)(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&))::'lambda'(llvm::CCValAssign const&, llvm::CCValAssign const&)::operator()(llvm::CCValAssign const&, llvm::CCValAssign const&) const
Line
Count
Source
563
44
               [](const CCValAssign &A, const CCValAssign &B) -> bool {
564
44
                 return A.getValNo() < B.getValNo();
565
44
               });
void llvm::CCState::AnalyzeArgumentsSecondPass<llvm::ISD::OutputArg>(llvm::SmallVectorImpl<llvm::ISD::OutputArg> const&, bool (*)(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&))::'lambda'(llvm::CCValAssign const&, llvm::CCValAssign const&)::operator()(llvm::CCValAssign const&, llvm::CCValAssign const&) const
Line
Count
Source
563
8
               [](const CCValAssign &A, const CCValAssign &B) -> bool {
564
8
                 return A.getValNo() < B.getValNo();
565
8
               });
566
61
  }
void llvm::CCState::AnalyzeArgumentsSecondPass<llvm::ISD::InputArg>(llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, bool (*)(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&))
Line
Count
Source
542
53
                                  CCAssignFn Fn) {
543
53
    unsigned NumFirstPassLocs = Locs.size();
544
53
545
53
    /// Creates similar argument list to \p Args in which each argument is
546
53
    /// marked using SecArgPass flag.
547
53
    SmallVector<T, 16> SecPassArg;
548
53
    // SmallVector<ISD::InputArg, 16> SecPassArg;
549
164
    for (auto Arg : Args) {
550
164
      Arg.Flags.setSecArgPass();
551
164
      SecPassArg.push_back(Arg);
552
164
    }
553
53
554
53
    // Run the second argument pass
555
53
    AnalyzeArguments(SecPassArg, Fn);
556
53
557
53
    // Sort the locations of the arguments according to their original position.
558
53
    SmallVector<CCValAssign, 16> TmpArgLocs;
559
53
    std::swap(TmpArgLocs, Locs);
560
53
    auto B = TmpArgLocs.begin(), E = TmpArgLocs.end();
561
53
    std::merge(B, B + NumFirstPassLocs, B + NumFirstPassLocs, E,
562
53
               std::back_inserter(Locs),
563
53
               [](const CCValAssign &A, const CCValAssign &B) -> bool {
564
53
                 return A.getValNo() < B.getValNo();
565
53
               });
566
53
  }
void llvm::CCState::AnalyzeArgumentsSecondPass<llvm::ISD::OutputArg>(llvm::SmallVectorImpl<llvm::ISD::OutputArg> const&, bool (*)(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&))
Line
Count
Source
542
8
                                  CCAssignFn Fn) {
543
8
    unsigned NumFirstPassLocs = Locs.size();
544
8
545
8
    /// Creates similar argument list to \p Args in which each argument is
546
8
    /// marked using SecArgPass flag.
547
8
    SmallVector<T, 16> SecPassArg;
548
8
    // SmallVector<ISD::InputArg, 16> SecPassArg;
549
19
    for (auto Arg : Args) {
550
19
      Arg.Flags.setSecArgPass();
551
19
      SecPassArg.push_back(Arg);
552
19
    }
553
8
554
8
    // Run the second argument pass
555
8
    AnalyzeArguments(SecPassArg, Fn);
556
8
557
8
    // Sort the locations of the arguments according to their original position.
558
8
    SmallVector<CCValAssign, 16> TmpArgLocs;
559
8
    std::swap(TmpArgLocs, Locs);
560
8
    auto B = TmpArgLocs.begin(), E = TmpArgLocs.end();
561
8
    std::merge(B, B + NumFirstPassLocs, B + NumFirstPassLocs, E,
562
8
               std::back_inserter(Locs),
563
8
               [](const CCValAssign &A, const CCValAssign &B) -> bool {
564
8
                 return A.getValNo() < B.getValNo();
565
8
               });
566
8
  }
567
568
private:
569
  /// MarkAllocated - Mark a register and all of its aliases as allocated.
570
  void MarkAllocated(unsigned Reg);
571
};
572
573
} // end namespace llvm
574
575
#endif // LLVM_CODEGEN_CALLINGCONVLOWER_H