Coverage Report

Created: 2019-02-21 13:17

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/ExecutionDomainFix.h
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//==-- llvm/CodeGen/ExecutionDomainFix.h - Execution Domain Fix -*- C++ -*--==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file Execution Domain Fix pass.
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///
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/// Some X86 SSE instructions like mov, and, or, xor are available in different
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/// variants for different operand types. These variant instructions are
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/// equivalent, but on Nehalem and newer cpus there is extra latency
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/// transferring data between integer and floating point domains.  ARM cores
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/// have similar issues when they are configured with both VFP and NEON
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/// pipelines.
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///
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/// This pass changes the variant instructions to minimize domain crossings.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_EXECUTIONDOMAINFIX_H
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#define LLVM_CODEGEN_EXECUTIONDOMAINFIX_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/LoopTraversal.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/ReachingDefAnalysis.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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namespace llvm {
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class MachineBasicBlock;
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class MachineInstr;
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class TargetInstrInfo;
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/// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
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/// of execution domains.
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///
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/// An open DomainValue represents a set of instructions that can still switch
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/// execution domain. Multiple registers may refer to the same open
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/// DomainValue - they will eventually be collapsed to the same execution
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/// domain.
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///
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/// A collapsed DomainValue represents a single register that has been forced
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/// into one of more execution domains. There is a separate collapsed
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/// DomainValue for each register, but it may contain multiple execution
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/// domains. A register value is initially created in a single execution
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/// domain, but if we were forced to pay the penalty of a domain crossing, we
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/// keep track of the fact that the register is now available in multiple
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/// domains.
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struct DomainValue {
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  /// Basic reference counting.
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  unsigned Refs = 0;
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  /// Bitmask of available domains. For an open DomainValue, it is the still
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  /// possible domains for collapsing. For a collapsed DomainValue it is the
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  /// domains where the register is available for free.
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  unsigned AvailableDomains;
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  /// Pointer to the next DomainValue in a chain.  When two DomainValues are
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  /// merged, Victim.Next is set to point to Victor, so old DomainValue
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  /// references can be updated by following the chain.
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  DomainValue *Next;
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  /// Twiddleable instructions using or defining these registers.
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  SmallVector<MachineInstr *, 8> Instrs;
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  DomainValue() { clear(); }
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  /// A collapsed DomainValue has no instructions to twiddle - it simply keeps
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  /// track of the domains where the registers are already available.
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  bool isCollapsed() const { return Instrs.empty(); }
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  /// Is domain available?
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  bool hasDomain(unsigned domain) const {
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    assert(domain <
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               static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
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           "undefined behavior");
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    return AvailableDomains & (1u << domain);
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  }
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  /// Mark domain as available.
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  void addDomain(unsigned domain) { AvailableDomains |= 1u << domain; }
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  // Restrict to a single domain available.
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  void setSingleDomain(unsigned domain) { AvailableDomains = 1u << domain; }
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  /// Return bitmask of domains that are available and in mask.
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  unsigned getCommonDomains(unsigned mask) const {
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    return AvailableDomains & mask;
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  }
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  /// First domain available.
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  unsigned getFirstDomain() const {
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    return countTrailingZeros(AvailableDomains);
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  }
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  /// Clear this DomainValue and point to next which has all its data.
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  void clear() {
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    AvailableDomains = 0;
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    Next = nullptr;
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    Instrs.clear();
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  }
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};
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class ExecutionDomainFix : public MachineFunctionPass {
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  SpecificBumpPtrAllocator<DomainValue> Allocator;
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  SmallVector<DomainValue *, 16> Avail;
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  const TargetRegisterClass *const RC;
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  MachineFunction *MF;
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  const TargetInstrInfo *TII;
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  const TargetRegisterInfo *TRI;
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  std::vector<SmallVector<int, 1>> AliasMap;
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  const unsigned NumRegs;
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  /// Value currently in each register, or NULL when no value is being tracked.
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  /// This counts as a DomainValue reference.
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  using LiveRegsDVInfo = std::vector<DomainValue *>;
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  LiveRegsDVInfo LiveRegs;
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  /// Keeps domain information for all registers. Note that this
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  /// is different from the usual definition notion of liveness. The CPU
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  /// doesn't care whether or not we consider a register killed.
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  using OutRegsInfoMap = SmallVector<LiveRegsDVInfo, 4>;
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  OutRegsInfoMap MBBOutRegsInfos;
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  ReachingDefAnalysis *RDA;
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public:
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  ExecutionDomainFix(char &PassID, const TargetRegisterClass &RC)
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      : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
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  void getAnalysisUsage(AnalysisUsage &AU) const override {
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    AU.setPreservesAll();
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    AU.addRequired<ReachingDefAnalysis>();
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    MachineFunctionPass::getAnalysisUsage(AU);
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  }
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  bool runOnMachineFunction(MachineFunction &MF) override;
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  MachineFunctionProperties getRequiredProperties() const override {
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    return MachineFunctionProperties().set(
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        MachineFunctionProperties::Property::NoVRegs);
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  }
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private:
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  /// Translate TRI register number to a list of indices into our smaller tables
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  /// of interesting registers.
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  iterator_range<SmallVectorImpl<int>::const_iterator>
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  regIndices(unsigned Reg) const;
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  /// DomainValue allocation.
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  DomainValue *alloc(int domain = -1);
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  /// Add reference to DV.
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  DomainValue *retain(DomainValue *DV) {
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    if (DV)
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      ++DV->Refs;
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    return DV;
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  }
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  /// Release a reference to DV.  When the last reference is released,
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  /// collapse if needed.
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  void release(DomainValue *);
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  /// Follow the chain of dead DomainValues until a live DomainValue is reached.
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  /// Update the referenced pointer when necessary.
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  DomainValue *resolve(DomainValue *&);
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  /// Set LiveRegs[rx] = dv, updating reference counts.
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  void setLiveReg(int rx, DomainValue *DV);
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  /// Kill register rx, recycle or collapse any DomainValue.
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  void kill(int rx);
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  /// Force register rx into domain.
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  void force(int rx, unsigned domain);
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  /// Collapse open DomainValue into given domain. If there are multiple
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  /// registers using dv, they each get a unique collapsed DomainValue.
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  void collapse(DomainValue *dv, unsigned domain);
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  /// All instructions and registers in B are moved to A, and B is released.
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  bool merge(DomainValue *A, DomainValue *B);
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  /// Set up LiveRegs by merging predecessor live-out values.
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  void enterBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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  /// Update live-out values.
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  void leaveBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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  /// Process he given basic block.
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  void processBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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  /// Visit given insturcion.
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  bool visitInstr(MachineInstr *);
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  /// Update def-ages for registers defined by MI.
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  /// If Kill is set, also kill off DomainValues clobbered by the defs.
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  void processDefs(MachineInstr *, bool Kill);
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  /// A soft instruction can be changed to work in other domains given by mask.
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  void visitSoftInstr(MachineInstr *, unsigned mask);
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  /// A hard instruction only works in one domain. All input registers will be
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  /// forced into that domain.
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  void visitHardInstr(MachineInstr *, unsigned domain);
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};
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} // namespace llvm
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#endif // LLVM_CODEGEN_EXECUTIONDOMAINFIX_H