Coverage Report

Created: 2018-11-12 17:33

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/FastISel.h
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//===- FastISel.h - Definition of the FastISel class ------------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines the FastISel class.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_FASTISEL_H
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#define LLVM_CODEGEN_FASTISEL_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/CallSite.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/Support/MachineValueType.h"
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#include <algorithm>
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#include <cstdint>
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#include <utility>
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namespace llvm {
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class AllocaInst;
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class BasicBlock;
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class CallInst;
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class Constant;
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class ConstantFP;
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class DataLayout;
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class FunctionLoweringInfo;
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class LoadInst;
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class MachineConstantPool;
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class MachineFrameInfo;
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class MachineFunction;
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class MachineInstr;
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class MachineMemOperand;
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class MachineOperand;
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class MachineRegisterInfo;
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class MCContext;
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class MCInstrDesc;
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class MCSymbol;
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class TargetInstrInfo;
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class TargetLibraryInfo;
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class TargetMachine;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class Type;
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class User;
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class Value;
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/// This is a fast-path instruction selection class that generates poor
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/// code and doesn't support illegal types or non-trivial lowering, but runs
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/// quickly.
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class FastISel {
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public:
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  using ArgListEntry = TargetLoweringBase::ArgListEntry;
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  using ArgListTy = TargetLoweringBase::ArgListTy;
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  struct CallLoweringInfo {
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    Type *RetTy = nullptr;
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    bool RetSExt : 1;
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    bool RetZExt : 1;
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    bool IsVarArg : 1;
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    bool IsInReg : 1;
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    bool DoesNotReturn : 1;
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    bool IsReturnValueUsed : 1;
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    bool IsPatchPoint : 1;
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    // IsTailCall Should be modified by implementations of FastLowerCall
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    // that perform tail call conversions.
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    bool IsTailCall = false;
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    unsigned NumFixedArgs = -1;
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    CallingConv::ID CallConv = CallingConv::C;
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    const Value *Callee = nullptr;
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    MCSymbol *Symbol = nullptr;
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    ArgListTy Args;
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    ImmutableCallSite *CS = nullptr;
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    MachineInstr *Call = nullptr;
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    unsigned ResultReg = 0;
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    unsigned NumResultRegs = 0;
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    SmallVector<Value *, 16> OutVals;
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    SmallVector<ISD::ArgFlagsTy, 16> OutFlags;
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    SmallVector<unsigned, 16> OutRegs;
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    SmallVector<ISD::InputArg, 4> Ins;
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    SmallVector<unsigned, 4> InRegs;
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    CallLoweringInfo()
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        : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
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2.00k
          DoesNotReturn(false), IsReturnValueUsed(true), IsPatchPoint(false) {}
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    CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
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                                const Value *Target, ArgListTy &&ArgsList,
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1.91k
                                ImmutableCallSite &Call) {
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1.91k
      RetTy = ResultTy;
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1.91k
      Callee = Target;
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1.91k
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1.91k
      IsInReg = Call.hasRetAttr(Attribute::InReg);
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1.91k
      DoesNotReturn = Call.doesNotReturn();
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      IsVarArg = FuncTy->isVarArg();
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1.91k
      IsReturnValueUsed = !Call.getInstruction()->use_empty();
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      RetSExt = Call.hasRetAttr(Attribute::SExt);
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      RetZExt = Call.hasRetAttr(Attribute::ZExt);
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1.91k
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1.91k
      CallConv = Call.getCallingConv();
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      Args = std::move(ArgsList);
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1.91k
      NumFixedArgs = FuncTy->getNumParams();
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1.91k
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1.91k
      CS = &Call;
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1.91k
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1.91k
      return *this;
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1.91k
    }
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    CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
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                                MCSymbol *Target, ArgListTy &&ArgsList,
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                                ImmutableCallSite &Call,
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34
                                unsigned FixedArgs = ~0U) {
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      RetTy = ResultTy;
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      Callee = Call.getCalledValue();
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      Symbol = Target;
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34
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      IsInReg = Call.hasRetAttr(Attribute::InReg);
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      DoesNotReturn = Call.doesNotReturn();
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      IsVarArg = FuncTy->isVarArg();
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34
      IsReturnValueUsed = !Call.getInstruction()->use_empty();
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      RetSExt = Call.hasRetAttr(Attribute::SExt);
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      RetZExt = Call.hasRetAttr(Attribute::ZExt);
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34
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      CallConv = Call.getCallingConv();
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      Args = std::move(ArgsList);
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34
      NumFixedArgs = (FixedArgs == ~0U) ? 
FuncTy->getNumParams()0
: FixedArgs;
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      CS = &Call;
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      return *this;
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34
    }
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    CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
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                                const Value *Target, ArgListTy &&ArgsList,
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39
                                unsigned FixedArgs = ~0U) {
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      RetTy = ResultTy;
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      Callee = Target;
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      CallConv = CC;
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      Args = std::move(ArgsList);
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39
      NumFixedArgs = (FixedArgs == ~0U) ? 
Args.size()0
: FixedArgs;
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      return *this;
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39
    }
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    CallLoweringInfo &setCallee(const DataLayout &DL, MCContext &Ctx,
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                                CallingConv::ID CC, Type *ResultTy,
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                                StringRef Target, ArgListTy &&ArgsList,
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                                unsigned FixedArgs = ~0U);
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    CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
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                                MCSymbol *Target, ArgListTy &&ArgsList,
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16
                                unsigned FixedArgs = ~0U) {
170
16
      RetTy = ResultTy;
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16
      Symbol = Target;
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16
      CallConv = CC;
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16
      Args = std::move(ArgsList);
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16
      NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : 
FixedArgs0
;
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16
      return *this;
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16
    }
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1.91k
    CallLoweringInfo &setTailCall(bool Value = true) {
179
1.91k
      IsTailCall = Value;
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      return *this;
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1.91k
    }
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39
    CallLoweringInfo &setIsPatchPoint(bool Value = true) {
184
39
      IsPatchPoint = Value;
185
39
      return *this;
186
39
    }
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2.00k
    ArgListTy &getArgs() { return Args; }
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2.00k
    void clearOuts() {
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2.00k
      OutVals.clear();
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2.00k
      OutFlags.clear();
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2.00k
      OutRegs.clear();
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2.00k
    }
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2.00k
    void clearIns() {
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2.00k
      Ins.clear();
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2.00k
      InRegs.clear();
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2.00k
    }
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  };
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protected:
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  DenseMap<const Value *, unsigned> LocalValueMap;
204
  FunctionLoweringInfo &FuncInfo;
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  MachineFunction *MF;
206
  MachineRegisterInfo &MRI;
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  MachineFrameInfo &MFI;
208
  MachineConstantPool &MCP;
209
  DebugLoc DbgLoc;
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  const TargetMachine &TM;
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  const DataLayout &DL;
212
  const TargetInstrInfo &TII;
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  const TargetLowering &TLI;
214
  const TargetRegisterInfo &TRI;
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  const TargetLibraryInfo *LibInfo;
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  bool SkipTargetIndependentISel;
217
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  /// The position of the last instruction for materializing constants
219
  /// for use in the current block. It resets to EmitStartPt when it makes sense
220
  /// (for example, it's usually profitable to avoid function calls between the
221
  /// definition and the use)
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  MachineInstr *LastLocalValue;
223
224
  /// The top most instruction in the current block that is allowed for
225
  /// emitting local variables. LastLocalValue resets to EmitStartPt when it
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  /// makes sense (for example, on function calls)
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  MachineInstr *EmitStartPt;
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  /// Last local value flush point. On a subsequent flush, no local value will
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  /// sink past this point.
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  MachineBasicBlock::iterator LastFlushPoint;
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public:
234
  virtual ~FastISel();
235
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  /// Return the position of the last instruction emitted for
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  /// materializing constants for use in the current block.
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245k
  MachineInstr *getLastLocalValue() { return LastLocalValue; }
239
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  /// Update the position of the last instruction emitted for
241
  /// materializing constants for use in the current block.
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12.8k
  void setLastLocalValue(MachineInstr *I) {
243
12.8k
    EmitStartPt = I;
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12.8k
    LastLocalValue = I;
245
12.8k
  }
246
247
  /// Set the current block to which generated machine instructions will
248
  /// be appended.
249
  void startNewBlock();
250
251
  /// Flush the local value map and sink local values if possible.
252
  void finishBasicBlock();
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  /// Return current debug location information.
255
0
  DebugLoc getCurDebugLoc() const { return DbgLoc; }
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257
  /// Do "fast" instruction selection for function arguments and append
258
  /// the machine instructions to the current block. Returns true when
259
  /// successful.
260
  bool lowerArguments();
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262
  /// Do "fast" instruction selection for the given LLVM IR instruction
263
  /// and append the generated machine instructions to the current block.
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  /// Returns true if selection was successful.
265
  bool selectInstruction(const Instruction *I);
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  /// Do "fast" instruction selection for the given LLVM IR operator
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  /// (Instruction or ConstantExpr), and append generated machine instructions
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  /// to the current block. Return true if selection was successful.
270
  bool selectOperator(const User *I, unsigned Opcode);
271
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  /// Create a virtual register and arrange for it to be assigned the
273
  /// value for the given LLVM value.
274
  unsigned getRegForValue(const Value *V);
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  /// Look up the value to see if its value is already cached in a
277
  /// register. It may be defined by instructions across blocks or defined
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  /// locally.
279
  unsigned lookUpRegForValue(const Value *V);
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  /// This is a wrapper around getRegForValue that also takes care of
282
  /// truncating or sign-extending the given getelementptr index value.
283
  std::pair<unsigned, bool> getRegForGEPIndex(const Value *Idx);
284
285
  /// We're checking to see if we can fold \p LI into \p FoldInst. Note
286
  /// that we could have a sequence where multiple LLVM IR instructions are
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  /// folded into the same machineinstr.  For example we could have:
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  ///
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  ///   A: x = load i32 *P
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  ///   B: y = icmp A, 42
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  ///   C: br y, ...
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  ///
293
  /// In this scenario, \p LI is "A", and \p FoldInst is "C".  We know about "B"
294
  /// (and any other folded instructions) because it is between A and C.
295
  ///
296
  /// If we succeed folding, return true.
297
  bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst);
298
299
  /// The specified machine instr operand is a vreg, and that vreg is
300
  /// being provided by the specified load instruction.  If possible, try to
301
  /// fold the load as an operand to the instruction, returning true if
302
  /// possible.
303
  ///
304
  /// This method should be implemented by targets.
305
  virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/,
306
464
                                   const LoadInst * /*LI*/) {
307
464
    return false;
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464
  }
309
310
  /// Reset InsertPt to prepare for inserting instructions into the
311
  /// current block.
312
  void recomputeInsertPt();
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  /// Remove all dead instructions between the I and E.
315
  void removeDeadCode(MachineBasicBlock::iterator I,
316
                      MachineBasicBlock::iterator E);
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318
  struct SavePoint {
319
    MachineBasicBlock::iterator InsertPt;
320
    DebugLoc DL;
321
  };
322
323
  /// Prepare InsertPt to begin inserting instructions into the local
324
  /// value area and return the old insert position.
325
  SavePoint enterLocalValueArea();
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327
  /// Reset InsertPt to the given old insert position.
328
  void leaveLocalValueArea(SavePoint Old);
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330
protected:
331
  explicit FastISel(FunctionLoweringInfo &FuncInfo,
332
                    const TargetLibraryInfo *LibInfo,
333
                    bool SkipTargetIndependentISel = false);
334
335
  /// This method is called by target-independent code when the normal
336
  /// FastISel process fails to select an instruction. This gives targets a
337
  /// chance to emit code for anything that doesn't fit into FastISel's
338
  /// framework. It returns true if it was successful.
339
  virtual bool fastSelectInstruction(const Instruction *I) = 0;
340
341
  /// This method is called by target-independent code to do target-
342
  /// specific argument lowering. It returns true if it was successful.
343
  virtual bool fastLowerArguments();
344
345
  /// This method is called by target-independent code to do target-
346
  /// specific call lowering. It returns true if it was successful.
347
  virtual bool fastLowerCall(CallLoweringInfo &CLI);
348
349
  /// This method is called by target-independent code to do target-
350
  /// specific intrinsic lowering. It returns true if it was successful.
351
  virtual bool fastLowerIntrinsicCall(const IntrinsicInst *II);
352
353
  /// This method is called by target-independent code to request that an
354
  /// instruction with the given type and opcode be emitted.
355
  virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
356
357
  /// This method is called by target-independent code to request that an
358
  /// instruction with the given type, opcode, and register operand be emitted.
359
  virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
360
                              bool Op0IsKill);
361
362
  /// This method is called by target-independent code to request that an
363
  /// instruction with the given type, opcode, and register operands be emitted.
364
  virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
365
                               bool Op0IsKill, unsigned Op1, bool Op1IsKill);
366
367
  /// This method is called by target-independent code to request that an
368
  /// instruction with the given type, opcode, and register and immediate
369
  /// operands be emitted.
370
  virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
371
                               bool Op0IsKill, uint64_t Imm);
372
373
  /// This method is a wrapper of fastEmit_ri.
374
  ///
375
  /// It first tries to emit an instruction with an immediate operand using
376
  /// fastEmit_ri.  If that fails, it materializes the immediate into a register
377
  /// and try fastEmit_rr instead.
378
  unsigned fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill,
379
                        uint64_t Imm, MVT ImmType);
380
381
  /// This method is called by target-independent code to request that an
382
  /// instruction with the given type, opcode, and immediate operand be emitted.
383
  virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
384
385
  /// This method is called by target-independent code to request that an
386
  /// instruction with the given type, opcode, and floating-point immediate
387
  /// operand be emitted.
388
  virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
389
                              const ConstantFP *FPImm);
390
391
  /// Emit a MachineInstr with no operands and a result register in the
392
  /// given register class.
393
  unsigned fastEmitInst_(unsigned MachineInstOpcode,
394
                         const TargetRegisterClass *RC);
395
396
  /// Emit a MachineInstr with one register operand and a result register
397
  /// in the given register class.
398
  unsigned fastEmitInst_r(unsigned MachineInstOpcode,
399
                          const TargetRegisterClass *RC, unsigned Op0,
400
                          bool Op0IsKill);
401
402
  /// Emit a MachineInstr with two register operands and a result
403
  /// register in the given register class.
404
  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
405
                           const TargetRegisterClass *RC, unsigned Op0,
406
                           bool Op0IsKill, unsigned Op1, bool Op1IsKill);
407
408
  /// Emit a MachineInstr with three register operands and a result
409
  /// register in the given register class.
410
  unsigned fastEmitInst_rrr(unsigned MachineInstOpcode,
411
                            const TargetRegisterClass *RC, unsigned Op0,
412
                            bool Op0IsKill, unsigned Op1, bool Op1IsKill,
413
                            unsigned Op2, bool Op2IsKill);
414
415
  /// Emit a MachineInstr with a register operand, an immediate, and a
416
  /// result register in the given register class.
417
  unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
418
                           const TargetRegisterClass *RC, unsigned Op0,
419
                           bool Op0IsKill, uint64_t Imm);
420
421
  /// Emit a MachineInstr with one register operand and two immediate
422
  /// operands.
423
  unsigned fastEmitInst_rii(unsigned MachineInstOpcode,
424
                            const TargetRegisterClass *RC, unsigned Op0,
425
                            bool Op0IsKill, uint64_t Imm1, uint64_t Imm2);
426
427
  /// Emit a MachineInstr with a floating point immediate, and a result
428
  /// register in the given register class.
429
  unsigned fastEmitInst_f(unsigned MachineInstOpcode,
430
                          const TargetRegisterClass *RC,
431
                          const ConstantFP *FPImm);
432
433
  /// Emit a MachineInstr with two register operands, an immediate, and a
434
  /// result register in the given register class.
435
  unsigned fastEmitInst_rri(unsigned MachineInstOpcode,
436
                            const TargetRegisterClass *RC, unsigned Op0,
437
                            bool Op0IsKill, unsigned Op1, bool Op1IsKill,
438
                            uint64_t Imm);
439
440
  /// Emit a MachineInstr with a single immediate operand, and a result
441
  /// register in the given register class.
442
  unsigned fastEmitInst_i(unsigned MachineInstOpcode,
443
                          const TargetRegisterClass *RC, uint64_t Imm);
444
445
  /// Emit a MachineInstr for an extract_subreg from a specified index of
446
  /// a superregister to a specified type.
447
  unsigned fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill,
448
                                      uint32_t Idx);
449
450
  /// Emit MachineInstrs to compute the value of Op with all but the
451
  /// least significant bit set to zero.
452
  unsigned fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill);
453
454
  /// Emit an unconditional branch to the given block, unless it is the
455
  /// immediate (fall-through) successor, and update the CFG.
456
  void fastEmitBranch(MachineBasicBlock *MSucc, const DebugLoc &DbgLoc);
457
458
  /// Emit an unconditional branch to \p FalseMBB, obtains the branch weight
459
  /// and adds TrueMBB and FalseMBB to the successor list.
460
  void finishCondBranch(const BasicBlock *BranchBB, MachineBasicBlock *TrueMBB,
461
                        MachineBasicBlock *FalseMBB);
462
463
  /// Update the value map to include the new mapping for this
464
  /// instruction, or insert an extra copy to get the result in a previous
465
  /// determined register.
466
  ///
467
  /// NOTE: This is only necessary because we might select a block that uses a
468
  /// value before we select the block that defines the value. It might be
469
  /// possible to fix this by selecting blocks in reverse postorder.
470
  void updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs = 1);
471
472
  unsigned createResultReg(const TargetRegisterClass *RC);
473
474
  /// Try to constrain Op so that it is usable by argument OpNum of the
475
  /// provided MCInstrDesc. If this fails, create a new virtual register in the
476
  /// correct class and COPY the value there.
477
  unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
478
                                    unsigned OpNum);
479
480
  /// Emit a constant in a register using target-specific logic, such as
481
  /// constant pool loads.
482
0
  virtual unsigned fastMaterializeConstant(const Constant *C) { return 0; }
483
484
  /// Emit an alloca address in a register using target-specific logic.
485
0
  virtual unsigned fastMaterializeAlloca(const AllocaInst *C) { return 0; }
486
487
  /// Emit the floating-point constant +0.0 in a register using target-
488
  /// specific logic.
489
0
  virtual unsigned fastMaterializeFloatZero(const ConstantFP *CF) {
490
0
    return 0;
491
0
  }
492
493
  /// Check if \c Add is an add that can be safely folded into \c GEP.
494
  ///
495
  /// \c Add can be folded into \c GEP if:
496
  /// - \c Add is an add,
497
  /// - \c Add's size matches \c GEP's,
498
  /// - \c Add is in the same basic block as \c GEP, and
499
  /// - \c Add has a constant operand.
500
  bool canFoldAddIntoGEP(const User *GEP, const Value *Add);
501
502
  /// Test whether the given value has exactly one use.
503
  bool hasTrivialKill(const Value *V);
504
505
  /// Create a machine mem operand from the given instruction.
506
  MachineMemOperand *createMachineMemOperandFor(const Instruction *I) const;
507
508
  CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const;
509
510
  bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs);
511
  bool lowerCallTo(const CallInst *CI, const char *SymName,
512
                   unsigned NumArgs);
513
  bool lowerCallTo(CallLoweringInfo &CLI);
514
515
1
  bool isCommutativeIntrinsic(IntrinsicInst const *II) {
516
1
    switch (II->getIntrinsicID()) {
517
1
    case Intrinsic::sadd_with_overflow:
518
1
    case Intrinsic::uadd_with_overflow:
519
1
    case Intrinsic::smul_with_overflow:
520
1
    case Intrinsic::umul_with_overflow:
521
1
      return true;
522
1
    default:
523
0
      return false;
524
1
    }
525
1
  }
526
527
  bool lowerCall(const CallInst *I);
528
  /// Select and emit code for a binary operator instruction, which has
529
  /// an opcode which directly corresponds to the given ISD opcode.
530
  bool selectBinaryOp(const User *I, unsigned ISDOpcode);
531
  bool selectFNeg(const User *I);
532
  bool selectGetElementPtr(const User *I);
533
  bool selectStackmap(const CallInst *I);
534
  bool selectPatchpoint(const CallInst *I);
535
  bool selectCall(const User *I);
536
  bool selectIntrinsicCall(const IntrinsicInst *II);
537
  bool selectBitCast(const User *I);
538
  bool selectCast(const User *I, unsigned Opcode);
539
  bool selectExtractValue(const User *U);
540
  bool selectInsertValue(const User *I);
541
  bool selectXRayCustomEvent(const CallInst *II);
542
  bool selectXRayTypedEvent(const CallInst *II);
543
544
private:
545
  /// Handle PHI nodes in successor blocks.
546
  ///
547
  /// Emit code to ensure constants are copied into registers when needed.
548
  /// Remember the virtual registers that need to be added to the Machine PHI
549
  /// nodes as input.  We cannot just directly add them, because expansion might
550
  /// result in multiple MBB's for one BB.  As such, the start of the BB might
551
  /// correspond to a different MBB than the end.
552
  bool handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
553
554
  /// Helper for materializeRegForValue to materialize a constant in a
555
  /// target-independent way.
556
  unsigned materializeConstant(const Value *V, MVT VT);
557
558
  /// Helper for getRegForVale. This function is called when the value
559
  /// isn't already available in a register and must be materialized with new
560
  /// instructions.
561
  unsigned materializeRegForValue(const Value *V, MVT VT);
562
563
  /// Clears LocalValueMap and moves the area for the new local variables
564
  /// to the beginning of the block. It helps to avoid spilling cached variables
565
  /// across heavy instructions like calls.
566
  void flushLocalValueMap();
567
568
  /// Removes dead local value instructions after SavedLastLocalvalue.
569
  void removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue);
570
571
  struct InstOrderMap {
572
    DenseMap<MachineInstr *, unsigned> Orders;
573
    MachineInstr *FirstTerminator = nullptr;
574
    unsigned FirstTerminatorOrder = std::numeric_limits<unsigned>::max();
575
576
    void initialize(MachineBasicBlock *MBB,
577
                    MachineBasicBlock::iterator LastFlushPoint);
578
  };
579
580
  /// Sinks the local value materialization instruction LocalMI to its first use
581
  /// in the basic block, or deletes it if it is not used.
582
  void sinkLocalValueMaterialization(MachineInstr &LocalMI, unsigned DefReg,
583
                                     InstOrderMap &OrderMap);
584
585
  /// Insertion point before trying to select the current instruction.
586
  MachineBasicBlock::iterator SavedInsertPt;
587
588
  /// Add a stackmap or patchpoint intrinsic call's live variable
589
  /// operands to a stackmap or patchpoint machine instruction.
590
  bool addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
591
                           const CallInst *CI, unsigned StartIdx);
592
  bool lowerCallOperands(const CallInst *CI, unsigned ArgIdx, unsigned NumArgs,
593
                         const Value *Callee, bool ForceRetVoidTy,
594
                         CallLoweringInfo &CLI);
595
};
596
597
} // end namespace llvm
598
599
#endif // LLVM_CODEGEN_FASTISEL_H