Coverage Report

Created: 2019-02-20 07:29

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
Line
Count
Source
1
//===- FunctionLoweringInfo.h - Lower functions from LLVM IR ---*- C++ -*--===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This implements routines for translating functions from LLVM IR into
10
// Machine IR.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
15
#define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
16
17
#include "llvm/ADT/APInt.h"
18
#include "llvm/ADT/BitVector.h"
19
#include "llvm/ADT/DenseMap.h"
20
#include "llvm/ADT/IndexedMap.h"
21
#include "llvm/ADT/Optional.h"
22
#include "llvm/ADT/SmallPtrSet.h"
23
#include "llvm/ADT/SmallVector.h"
24
#include "llvm/CodeGen/ISDOpcodes.h"
25
#include "llvm/CodeGen/MachineBasicBlock.h"
26
#include "llvm/CodeGen/TargetRegisterInfo.h"
27
#include "llvm/IR/Instructions.h"
28
#include "llvm/IR/Type.h"
29
#include "llvm/IR/Value.h"
30
#include "llvm/Support/KnownBits.h"
31
#include <cassert>
32
#include <utility>
33
#include <vector>
34
35
namespace llvm {
36
37
class Argument;
38
class BasicBlock;
39
class BranchProbabilityInfo;
40
class Function;
41
class Instruction;
42
class MachineFunction;
43
class MachineInstr;
44
class MachineRegisterInfo;
45
class MVT;
46
class SelectionDAG;
47
class TargetLowering;
48
49
//===--------------------------------------------------------------------===//
50
/// FunctionLoweringInfo - This contains information that is global to a
51
/// function that is used when lowering a region of the function.
52
///
53
class FunctionLoweringInfo {
54
public:
55
  const Function *Fn;
56
  MachineFunction *MF;
57
  const TargetLowering *TLI;
58
  MachineRegisterInfo *RegInfo;
59
  BranchProbabilityInfo *BPI;
60
  /// CanLowerReturn - true iff the function's return value can be lowered to
61
  /// registers.
62
  bool CanLowerReturn;
63
64
  /// True if part of the CSRs will be handled via explicit copies.
65
  bool SplitCSR;
66
67
  /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
68
  /// allocated to hold a pointer to the hidden sret parameter.
69
  unsigned DemoteRegister;
70
71
  /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
72
  DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
73
74
  /// A map from swifterror value in a basic block to the virtual register it is
75
  /// currently represented by.
76
  DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned>
77
      SwiftErrorVRegDefMap;
78
79
  /// A list of upward exposed vreg uses that need to be satisfied by either a
80
  /// copy def or a phi node at the beginning of the basic block representing
81
  /// the predecessor(s) swifterror value.
82
  DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned>
83
      SwiftErrorVRegUpwardsUse;
84
85
  /// A map from instructions that define/use a swifterror value to the virtual
86
  /// register that represents that def/use.
87
  llvm::DenseMap<PointerIntPair<const Instruction *, 1, bool>, unsigned>
88
      SwiftErrorVRegDefUses;
89
90
  /// The swifterror argument of the current function.
91
  const Value *SwiftErrorArg;
92
93
  using SwiftErrorValues = SmallVector<const Value*, 1>;
94
  /// A function can only have a single swifterror argument. And if it does
95
  /// have a swifterror argument, it must be the first entry in
96
  /// SwiftErrorVals.
97
  SwiftErrorValues SwiftErrorVals;
98
99
  /// Get or create the swifterror value virtual register in
100
  /// SwiftErrorVRegDefMap for this basic block.
101
  unsigned getOrCreateSwiftErrorVReg(const MachineBasicBlock *,
102
                                     const Value *);
103
104
  /// Set the swifterror virtual register in the SwiftErrorVRegDefMap for this
105
  /// basic block.
106
  void setCurrentSwiftErrorVReg(const MachineBasicBlock *MBB, const Value *,
107
                                unsigned);
108
109
  /// Get or create the swifterror value virtual register for a def of a
110
  /// swifterror by an instruction.
111
  std::pair<unsigned, bool> getOrCreateSwiftErrorVRegDefAt(const Instruction *);
112
  std::pair<unsigned, bool>
113
  getOrCreateSwiftErrorVRegUseAt(const Instruction *, const MachineBasicBlock *,
114
                                 const Value *);
115
116
  /// ValueMap - Since we emit code for the function a basic block at a time,
117
  /// we must remember which virtual registers hold the values for
118
  /// cross-basic-block values.
119
  DenseMap<const Value *, unsigned> ValueMap;
120
121
  /// VirtReg2Value map is needed by the Divergence Analysis driven
122
  /// instruction selection. It is reverted ValueMap. It is computed
123
  /// in lazy style - on demand. It is used to get the Value corresponding
124
  /// to the live in virtual register and is called from the
125
  /// TargetLowerinInfo::isSDNodeSourceOfDivergence.
126
  DenseMap<unsigned, const Value*> VirtReg2Value;
127
128
  /// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence
129
  /// to get the Value corresponding to the live-in virtual register.
130
  const Value * getValueFromVirtualReg(unsigned Vreg);
131
132
  /// Track virtual registers created for exception pointers.
133
  DenseMap<const Value *, unsigned> CatchPadExceptionPointers;
134
135
  /// Keep track of frame indices allocated for statepoints as they could be
136
  /// used across basic block boundaries.  This struct is more complex than a
137
  /// simple map because the stateopint lowering code de-duplicates gc pointers
138
  /// based on their SDValue (so %p and (bitcast %p to T) will get the same
139
  /// slot), and we track that here.
140
141
  struct StatepointSpillMap {
142
    using SlotMapTy = DenseMap<const Value *, Optional<int>>;
143
144
    /// Maps uniqued llvm IR values to the slots they were spilled in.  If a
145
    /// value is mapped to None it means we visited the value but didn't spill
146
    /// it (because it was a constant, for instance).
147
    SlotMapTy SlotMap;
148
149
    /// Maps llvm IR values to the values they were de-duplicated to.
150
    DenseMap<const Value *, const Value *> DuplicateMap;
151
152
77
    SlotMapTy::const_iterator find(const Value *V) const {
153
77
      auto DuplIt = DuplicateMap.find(V);
154
77
      if (DuplIt != DuplicateMap.end())
155
15
        V = DuplIt->second;
156
77
      return SlotMap.find(V);
157
77
    }
158
159
9
    SlotMapTy::const_iterator end() const { return SlotMap.end(); }
160
  };
161
162
  /// Maps gc.statepoint instructions to their corresponding StatepointSpillMap
163
  /// instances.
164
  DenseMap<const Instruction *, StatepointSpillMap> StatepointSpillMaps;
165
166
  /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
167
  /// the entry block.  This allows the allocas to be efficiently referenced
168
  /// anywhere in the function.
169
  DenseMap<const AllocaInst*, int> StaticAllocaMap;
170
171
  /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
172
  DenseMap<const Argument*, int> ByValArgFrameIndexMap;
173
174
  /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
175
  /// function arguments that are inserted after scheduling is completed.
176
  SmallVector<MachineInstr*, 8> ArgDbgValues;
177
178
  /// Bitvector with a bit set if corresponding argument is described in
179
  /// ArgDbgValues. Using arg numbers according to Argument numbering.
180
  BitVector DescribedArgs;
181
182
  /// RegFixups - Registers which need to be replaced after isel is done.
183
  DenseMap<unsigned, unsigned> RegFixups;
184
185
  DenseSet<unsigned> RegsWithFixups;
186
187
  /// StatepointStackSlots - A list of temporary stack slots (frame indices)
188
  /// used to spill values at a statepoint.  We store them here to enable
189
  /// reuse of the same stack slots across different statepoints in different
190
  /// basic blocks.
191
  SmallVector<unsigned, 50> StatepointStackSlots;
192
193
  /// MBB - The current block.
194
  MachineBasicBlock *MBB;
195
196
  /// MBB - The current insert position inside the current block.
197
  MachineBasicBlock::iterator InsertPt;
198
199
  struct LiveOutInfo {
200
    unsigned NumSignBits : 31;
201
    unsigned IsValid : 1;
202
    KnownBits Known = 1;
203
204
36.0k
    LiveOutInfo() : NumSignBits(0), IsValid(true) {}
205
  };
206
207
  /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
208
  /// for a value.
209
  DenseMap<const Value *, ISD::NodeType> PreferredExtendType;
210
211
  /// VisitedBBs - The set of basic blocks visited thus far by instruction
212
  /// selection.
213
  SmallPtrSet<const BasicBlock*, 4> VisitedBBs;
214
215
  /// PHINodesToUpdate - A list of phi instructions whose operand list will
216
  /// be updated after processing the current basic block.
217
  /// TODO: This isn't per-function state, it's per-basic-block state. But
218
  /// there's no other convenient place for it to live right now.
219
  std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
220
  unsigned OrigNumPHINodesToUpdate;
221
222
  /// If the current MBB is a landing pad, the exception pointer and exception
223
  /// selector registers are copied into these virtual registers by
224
  /// SelectionDAGISel::PrepareEHLandingPad().
225
  unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
226
227
  /// set - Initialize this FunctionLoweringInfo with the given Function
228
  /// and its associated MachineFunction.
229
  ///
230
  void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
231
232
  /// clear - Clear out all the function-specific state. This returns this
233
  /// FunctionLoweringInfo to an empty state, ready to be used for a
234
  /// different function.
235
  void clear();
236
237
  /// isExportedInst - Return true if the specified value is an instruction
238
  /// exported from its block.
239
110k
  bool isExportedInst(const Value *V) {
240
110k
    return ValueMap.count(V);
241
110k
  }
242
243
  unsigned CreateReg(MVT VT);
244
245
  unsigned CreateRegs(Type *Ty);
246
247
1.08M
  unsigned InitializeRegForValue(const Value *V) {
248
1.08M
    // Tokens never live in vregs.
249
1.08M
    if (V->getType()->isTokenTy())
250
180
      return 0;
251
1.08M
    unsigned &R = ValueMap[V];
252
1.08M
    assert(R == 0 && "Already initialized this value register!");
253
1.08M
    assert(VirtReg2Value.empty());
254
1.08M
    return R = CreateRegs(V->getType());
255
1.08M
  }
256
257
  /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
258
  /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
259
2.11M
  const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
260
2.11M
    if (!LiveOutRegInfo.inBounds(Reg))
261
438k
      return nullptr;
262
1.68M
263
1.68M
    const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
264
1.68M
    if (!LOI->IsValid)
265
372k
      return nullptr;
266
1.30M
267
1.30M
    return LOI;
268
1.30M
  }
269
270
  /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
271
  /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
272
  /// the register's LiveOutInfo is for a smaller bit width, it is extended to
273
  /// the larger bit width by zero extension. The bit width must be no smaller
274
  /// than the LiveOutInfo's existing bit width.
275
  const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
276
277
  /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
278
  void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
279
966k
                         const KnownBits &Known) {
280
966k
    // Only install this information if it tells us something.
281
966k
    if (NumSignBits == 1 && 
Known.isUnknown()674k
)
282
642k
      return;
283
323k
284
323k
    LiveOutRegInfo.grow(Reg);
285
323k
    LiveOutInfo &LOI = LiveOutRegInfo[Reg];
286
323k
    LOI.NumSignBits = NumSignBits;
287
323k
    LOI.Known.One = Known.One;
288
323k
    LOI.Known.Zero = Known.Zero;
289
323k
  }
290
291
  /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
292
  /// register based on the LiveOutInfo of its operands.
293
  void ComputePHILiveOutRegInfo(const PHINode*);
294
295
  /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
296
  /// called when a block is visited before all of its predecessors.
297
152k
  void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
298
152k
    // PHIs with no uses have no ValueMap entry.
299
152k
    DenseMap<const Value*, unsigned>::const_iterator It = ValueMap.find(PN);
300
152k
    if (It == ValueMap.end())
301
4
      return;
302
152k
303
152k
    unsigned Reg = It->second;
304
152k
    if (Reg == 0)
305
1
      return;
306
152k
307
152k
    LiveOutRegInfo.grow(Reg);
308
152k
    LiveOutRegInfo[Reg].IsValid = false;
309
152k
  }
310
311
  /// setArgumentFrameIndex - Record frame index for the byval
312
  /// argument.
313
  void setArgumentFrameIndex(const Argument *A, int FI);
314
315
  /// getArgumentFrameIndex - Get frame index for the byval argument.
316
  int getArgumentFrameIndex(const Argument *A);
317
318
  unsigned getCatchPadExceptionPointerVReg(const Value *CPI,
319
                                           const TargetRegisterClass *RC);
320
321
private:
322
  void addSEHHandlersForLPads(ArrayRef<const LandingPadInst *> LPads);
323
324
  /// LiveOutRegInfo - Information about live out vregs.
325
  IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
326
};
327
328
} // end namespace llvm
329
330
#endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H