Coverage Report

Created: 2018-07-18 22:01

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
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//===- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ----*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the IRTranslator pass.
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/// This pass is responsible for translating LLVM IR into MachineInstr.
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/// It uses target hooks to lower the ABI but aside from that, the pass
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/// generated code is generic. This is the default translator used for
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/// GlobalISel.
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///
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/// \todo Replace the comments with actual doxygen comments.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
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#define LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
25
#include "llvm/CodeGen/GlobalISel/Types.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/Support/Allocator.h"
28
#include "llvm/IR/Intrinsics.h"
29
#include <memory>
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#include <utility>
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32
namespace llvm {
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34
class AllocaInst;
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class BasicBlock;
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class CallInst;
37
class CallLowering;
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class Constant;
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class DataLayout;
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class Instruction;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class MachineRegisterInfo;
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class OptimizationRemarkEmitter;
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class PHINode;
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class TargetPassConfig;
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class User;
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class Value;
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// Technically the pass should run on an hypothetical MachineModule,
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// since it should translate Global into some sort of MachineGlobal.
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// The MachineGlobal should ultimately just be a transfer of ownership of
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// the interesting bits that are relevant to represent a global value.
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// That being said, we could investigate what would it cost to just duplicate
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// the information from the LLVM IR.
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// The idea is that ultimately we would be able to free up the memory used
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// by the LLVM IR as soon as the translation is over.
59
class IRTranslator : public MachineFunctionPass {
60
public:
61
  static char ID;
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63
private:
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  /// Interface used to lower the everything related to calls.
65
  const CallLowering *CLI;
66
67
  /// This class contains the mapping between the Values to vreg related data.
68
  class ValueToVRegInfo {
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  public:
70
6.75k
    ValueToVRegInfo() = default;
71
72
    using VRegListT = SmallVector<unsigned, 1>;
73
    using OffsetListT = SmallVector<uint64_t, 1>;
74
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    using const_vreg_iterator =
76
        DenseMap<const Value *, VRegListT *>::const_iterator;
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    using const_offset_iterator =
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        DenseMap<const Value *, OffsetListT *>::const_iterator;
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80
26.4M
    inline const_vreg_iterator vregs_end() const { return ValToVRegs.end(); }
81
82
11.7M
    VRegListT *getVRegs(const Value &V) {
83
11.7M
      auto It = ValToVRegs.find(&V);
84
11.7M
      if (It != ValToVRegs.end())
85
42.9k
        return It->second;
86
11.7M
87
11.7M
      return insertVRegs(V);
88
11.7M
    }
89
90
16.7M
    OffsetListT *getOffsets(const Value &V) {
91
16.7M
      auto It = TypeToOffsets.find(V.getType());
92
16.7M
      if (It != TypeToOffsets.end())
93
14.9M
        return It->second;
94
1.75M
95
1.75M
      return insertOffsets(V);
96
1.75M
    }
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98
26.4M
    const_vreg_iterator findVRegs(const Value &V) const {
99
26.4M
      return ValToVRegs.find(&V);
100
26.4M
    }
101
102
0
    bool contains(const Value &V) const {
103
0
      return ValToVRegs.find(&V) != ValToVRegs.end();
104
0
    }
105
106
233k
    void reset() {
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233k
      ValToVRegs.clear();
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233k
      TypeToOffsets.clear();
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233k
      VRegAlloc.DestroyAll();
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233k
      OffsetAlloc.DestroyAll();
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233k
    }
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  private:
114
11.7M
    VRegListT *insertVRegs(const Value &V) {
115
11.7M
      assert(ValToVRegs.find(&V) == ValToVRegs.end() && "Value already exists");
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11.7M
117
11.7M
      // We placement new using our fast allocator since we never try to free
118
11.7M
      // the vectors until translation is finished.
119
11.7M
      auto *VRegList = new (VRegAlloc.Allocate()) VRegListT();
120
11.7M
      ValToVRegs[&V] = VRegList;
121
11.7M
      return VRegList;
122
11.7M
    }
123
124
1.75M
    OffsetListT *insertOffsets(const Value &V) {
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1.75M
      assert(TypeToOffsets.find(V.getType()) == TypeToOffsets.end() &&
126
1.75M
             "Type already exists");
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1.75M
128
1.75M
      auto *OffsetList = new (OffsetAlloc.Allocate()) OffsetListT();
129
1.75M
      TypeToOffsets[V.getType()] = OffsetList;
130
1.75M
      return OffsetList;
131
1.75M
    }
132
    SpecificBumpPtrAllocator<VRegListT> VRegAlloc;
133
    SpecificBumpPtrAllocator<OffsetListT> OffsetAlloc;
134
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    // We store pointers to vectors here since references may be invalidated
136
    // while we hold them if we stored the vectors directly.
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    DenseMap<const Value *, VRegListT*> ValToVRegs;
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    DenseMap<const Type *, OffsetListT*> TypeToOffsets;
139
  };
140
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  /// Mapping of the values of the current LLVM IR function to the related
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  /// virtual registers and offsets.
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  ValueToVRegInfo VMap;
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  // N.b. it's not completely obvious that this will be sufficient for every
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  // LLVM IR construct (with "invoke" being the obvious candidate to mess up our
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  // lives.
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  DenseMap<const BasicBlock *, MachineBasicBlock *> BBToMBB;
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  // One BasicBlock can be translated to multiple MachineBasicBlocks.  For such
151
  // BasicBlocks translated to multiple MachineBasicBlocks, MachinePreds retains
152
  // a mapping between the edges arriving at the BasicBlock to the corresponding
153
  // created MachineBasicBlocks. Some BasicBlocks that get translated to a
154
  // single MachineBasicBlock may also end up in this Map.
155
  using CFGEdge = std::pair<const BasicBlock *, const BasicBlock *>;
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  DenseMap<CFGEdge, SmallVector<MachineBasicBlock *, 1>> MachinePreds;
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  // List of stubbed PHI instructions, for values and basic blocks to be filled
159
  // in once all MachineBasicBlocks have been created.
160
  SmallVector<std::pair<const PHINode *, SmallVector<MachineInstr *, 1>>, 4>
161
      PendingPHIs;
162
163
  /// Record of what frame index has been allocated to specified allocas for
164
  /// this function.
165
  DenseMap<const AllocaInst *, int> FrameIndices;
166
167
  /// \name Methods for translating form LLVM IR to MachineInstr.
168
  /// \see ::translate for general information on the translate methods.
169
  /// @{
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  /// Translate \p Inst into its corresponding MachineInstr instruction(s).
172
  /// Insert the newly translated instruction(s) right where the CurBuilder
173
  /// is set.
174
  ///
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  /// The general algorithm is:
176
  /// 1. Look for a virtual register for each operand or
177
  ///    create one.
178
  /// 2 Update the VMap accordingly.
179
  /// 2.alt. For constant arguments, if they are compile time constants,
180
  ///   produce an immediate in the right operand and do not touch
181
  ///   ValToReg. Actually we will go with a virtual register for each
182
  ///   constants because it may be expensive to actually materialize the
183
  ///   constant. Moreover, if the constant spans on several instructions,
184
  ///   CSE may not catch them.
185
  ///   => Update ValToVReg and remember that we saw a constant in Constants.
186
  ///   We will materialize all the constants in finalize.
187
  /// Note: we would need to do something so that we can recognize such operand
188
  ///       as constants.
189
  /// 3. Create the generic instruction.
190
  ///
191
  /// \return true if the translation succeeded.
192
  bool translate(const Instruction &Inst);
193
194
  /// Materialize \p C into virtual-register \p Reg. The generic instructions
195
  /// performing this materialization will be inserted into the entry block of
196
  /// the function.
197
  ///
198
  /// \return true if the materialization succeeded.
199
  bool translate(const Constant &C, unsigned Reg);
200
201
  /// Translate an LLVM bitcast into generic IR. Either a COPY or a G_BITCAST is
202
  /// emitted.
203
  bool translateBitCast(const User &U, MachineIRBuilder &MIRBuilder);
204
205
  /// Translate an LLVM load instruction into generic IR.
206
  bool translateLoad(const User &U, MachineIRBuilder &MIRBuilder);
207
208
  /// Translate an LLVM store instruction into generic IR.
209
  bool translateStore(const User &U, MachineIRBuilder &MIRBuilder);
210
211
  /// Translate an LLVM string intrinsic (memcpy, memset, ...).
212
  bool translateMemfunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
213
                        unsigned ID);
214
215
  void getStackGuard(unsigned DstReg, MachineIRBuilder &MIRBuilder);
216
217
  bool translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
218
                                  MachineIRBuilder &MIRBuilder);
219
220
  bool translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
221
                               MachineIRBuilder &MIRBuilder);
222
223
  bool translateInlineAsm(const CallInst &CI, MachineIRBuilder &MIRBuilder);
224
225
  // FIXME: temporary function to expose previous interface to call lowering
226
  // until it is refactored.
227
  /// Combines all component registers of \p V into a single scalar with size
228
  /// "max(Offsets) + last size".
229
  unsigned packRegs(const Value &V, MachineIRBuilder &MIRBuilder);
230
231
  void unpackRegs(const Value &V, unsigned Src, MachineIRBuilder &MIRBuilder);
232
233
  /// Returns true if the value should be split into multiple LLTs.
234
  /// If \p Offsets is given then the split type's offsets will be stored in it.
235
  bool valueIsSplit(const Value &V,
236
                    SmallVectorImpl<uint64_t> *Offsets = nullptr);
237
238
  /// Translate call instruction.
239
  /// \pre \p U is a call instruction.
240
  bool translateCall(const User &U, MachineIRBuilder &MIRBuilder);
241
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  bool translateInvoke(const User &U, MachineIRBuilder &MIRBuilder);
243
244
  bool translateLandingPad(const User &U, MachineIRBuilder &MIRBuilder);
245
246
  /// Translate one of LLVM's cast instructions into MachineInstrs, with the
247
  /// given generic Opcode.
248
  bool translateCast(unsigned Opcode, const User &U,
249
                     MachineIRBuilder &MIRBuilder);
250
251
  /// Translate a phi instruction.
252
  bool translatePHI(const User &U, MachineIRBuilder &MIRBuilder);
253
254
  /// Translate a comparison (icmp or fcmp) instruction or constant.
255
  bool translateCompare(const User &U, MachineIRBuilder &MIRBuilder);
256
257
  /// Translate an integer compare instruction (or constant).
258
1.01M
  bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) {
259
1.01M
    return translateCompare(U, MIRBuilder);
260
1.01M
  }
261
262
  /// Translate a floating-point compare instruction (or constant).
263
16.8k
  bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) {
264
16.8k
    return translateCompare(U, MIRBuilder);
265
16.8k
  }
266
267
  /// Add remaining operands onto phis we've translated. Executed after all
268
  /// MachineBasicBlocks for the function have been created.
269
  void finishPendingPhis();
270
271
  /// Translate \p Inst into a binary operation \p Opcode.
272
  /// \pre \p U is a binary operation.
273
  bool translateBinaryOp(unsigned Opcode, const User &U,
274
                         MachineIRBuilder &MIRBuilder);
275
276
  /// Translate branch (br) instruction.
277
  /// \pre \p U is a branch instruction.
278
  bool translateBr(const User &U, MachineIRBuilder &MIRBuilder);
279
280
  bool translateSwitch(const User &U, MachineIRBuilder &MIRBuilder);
281
282
  bool translateIndirectBr(const User &U, MachineIRBuilder &MIRBuilder);
283
284
  bool translateExtractValue(const User &U, MachineIRBuilder &MIRBuilder);
285
286
  bool translateInsertValue(const User &U, MachineIRBuilder &MIRBuilder);
287
288
  bool translateSelect(const User &U, MachineIRBuilder &MIRBuilder);
289
290
  bool translateGetElementPtr(const User &U, MachineIRBuilder &MIRBuilder);
291
292
  bool translateAlloca(const User &U, MachineIRBuilder &MIRBuilder);
293
294
  /// Translate return (ret) instruction.
295
  /// The target needs to implement CallLowering::lowerReturn for
296
  /// this to succeed.
297
  /// \pre \p U is a return instruction.
298
  bool translateRet(const User &U, MachineIRBuilder &MIRBuilder);
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300
  bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder);
301
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359k
  bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) {
303
359k
    return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder);
304
359k
  }
305
84.5k
  bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) {
306
84.5k
    return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder);
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84.5k
  }
308
104k
  bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) {
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104k
    return translateBinaryOp(TargetOpcode::G_AND, U, MIRBuilder);
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104k
  }
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79.5k
  bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) {
312
79.5k
    return translateBinaryOp(TargetOpcode::G_MUL, U, MIRBuilder);
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79.5k
  }
314
38.2k
  bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) {
315
38.2k
    return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder);
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38.2k
  }
317
10.3k
  bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) {
318
10.3k
    return translateBinaryOp(TargetOpcode::G_XOR, U, MIRBuilder);
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10.3k
  }
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321
6.51k
  bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) {
322
6.51k
    return translateBinaryOp(TargetOpcode::G_UDIV, U, MIRBuilder);
323
6.51k
  }
324
8.66k
  bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) {
325
8.66k
    return translateBinaryOp(TargetOpcode::G_SDIV, U, MIRBuilder);
326
8.66k
  }
327
847
  bool translateURem(const User &U, MachineIRBuilder &MIRBuilder) {
328
847
    return translateBinaryOp(TargetOpcode::G_UREM, U, MIRBuilder);
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847
  }
330
2.29k
  bool translateSRem(const User &U, MachineIRBuilder &MIRBuilder) {
331
2.29k
    return translateBinaryOp(TargetOpcode::G_SREM, U, MIRBuilder);
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2.29k
  }
333
30.7k
  bool translateIntToPtr(const User &U, MachineIRBuilder &MIRBuilder) {
334
30.7k
    return translateCast(TargetOpcode::G_INTTOPTR, U, MIRBuilder);
335
30.7k
  }
336
61.2k
  bool translatePtrToInt(const User &U, MachineIRBuilder &MIRBuilder) {
337
61.2k
    return translateCast(TargetOpcode::G_PTRTOINT, U, MIRBuilder);
338
61.2k
  }
339
166k
  bool translateTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
340
166k
    return translateCast(TargetOpcode::G_TRUNC, U, MIRBuilder);
341
166k
  }
342
4.03k
  bool translateFPTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
343
4.03k
    return translateCast(TargetOpcode::G_FPTRUNC, U, MIRBuilder);
344
4.03k
  }
345
12.7k
  bool translateFPExt(const User &U, MachineIRBuilder &MIRBuilder) {
346
12.7k
    return translateCast(TargetOpcode::G_FPEXT, U, MIRBuilder);
347
12.7k
  }
348
3.27k
  bool translateFPToUI(const User &U, MachineIRBuilder &MIRBuilder) {
349
3.27k
    return translateCast(TargetOpcode::G_FPTOUI, U, MIRBuilder);
350
3.27k
  }
351
2.55k
  bool translateFPToSI(const User &U, MachineIRBuilder &MIRBuilder) {
352
2.55k
    return translateCast(TargetOpcode::G_FPTOSI, U, MIRBuilder);
353
2.55k
  }
354
14.8k
  bool translateUIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
355
14.8k
    return translateCast(TargetOpcode::G_UITOFP, U, MIRBuilder);
356
14.8k
  }
357
29.4k
  bool translateSIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
358
29.4k
    return translateCast(TargetOpcode::G_SITOFP, U, MIRBuilder);
359
29.4k
  }
360
10.8k
  bool translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder) {
361
10.8k
    return true;
362
10.8k
  }
363
160k
  bool translateSExt(const User &U, MachineIRBuilder &MIRBuilder) {
364
160k
    return translateCast(TargetOpcode::G_SEXT, U, MIRBuilder);
365
160k
  }
366
367
104k
  bool translateZExt(const User &U, MachineIRBuilder &MIRBuilder) {
368
104k
    return translateCast(TargetOpcode::G_ZEXT, U, MIRBuilder);
369
104k
  }
370
371
63.3k
  bool translateShl(const User &U, MachineIRBuilder &MIRBuilder) {
372
63.3k
    return translateBinaryOp(TargetOpcode::G_SHL, U, MIRBuilder);
373
63.3k
  }
374
37.3k
  bool translateLShr(const User &U, MachineIRBuilder &MIRBuilder) {
375
37.3k
    return translateBinaryOp(TargetOpcode::G_LSHR, U, MIRBuilder);
376
37.3k
  }
377
13.1k
  bool translateAShr(const User &U, MachineIRBuilder &MIRBuilder) {
378
13.1k
    return translateBinaryOp(TargetOpcode::G_ASHR, U, MIRBuilder);
379
13.1k
  }
380
381
51.0k
  bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) {
382
51.0k
    return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder);
383
51.0k
  }
384
47.2k
  bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) {
385
47.2k
    return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder);
386
47.2k
  }
387
36.7k
  bool translateFDiv(const User &U, MachineIRBuilder &MIRBuilder) {
388
36.7k
    return translateBinaryOp(TargetOpcode::G_FDIV, U, MIRBuilder);
389
36.7k
  }
390
35
  bool translateFRem(const User &U, MachineIRBuilder &MIRBuilder) {
391
35
    return translateBinaryOp(TargetOpcode::G_FREM, U, MIRBuilder);
392
35
  }
393
394
  bool translateVAArg(const User &U, MachineIRBuilder &MIRBuilder);
395
396
  bool translateInsertElement(const User &U, MachineIRBuilder &MIRBuilder);
397
398
  bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder);
399
400
  bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder);
401
402
  bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder);
403
  bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder);
404
405
  // Stubs to keep the compiler happy while we implement the rest of the
406
  // translation.
407
0
  bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) {
408
0
    return false;
409
0
  }
410
0
  bool translateCleanupRet(const User &U, MachineIRBuilder &MIRBuilder) {
411
0
    return false;
412
0
  }
413
0
  bool translateCatchRet(const User &U, MachineIRBuilder &MIRBuilder) {
414
0
    return false;
415
0
  }
416
0
  bool translateCatchSwitch(const User &U, MachineIRBuilder &MIRBuilder) {
417
0
    return false;
418
0
  }
419
1.39k
  bool translateFence(const User &U, MachineIRBuilder &MIRBuilder) {
420
1.39k
    return false;
421
1.39k
  }
422
2
  bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) {
423
2
    return translateCast(TargetOpcode::G_ADDRSPACE_CAST, U, MIRBuilder);
424
2
  }
425
0
  bool translateCleanupPad(const User &U, MachineIRBuilder &MIRBuilder) {
426
0
    return false;
427
0
  }
428
0
  bool translateCatchPad(const User &U, MachineIRBuilder &MIRBuilder) {
429
0
    return false;
430
0
  }
431
0
  bool translateUserOp1(const User &U, MachineIRBuilder &MIRBuilder) {
432
0
    return false;
433
0
  }
434
0
  bool translateUserOp2(const User &U, MachineIRBuilder &MIRBuilder) {
435
0
    return false;
436
0
  }
437
438
  /// @}
439
440
  // Builder for machine instruction a la IRBuilder.
441
  // I.e., compared to regular MIBuilder, this one also inserts the instruction
442
  // in the current block, it can creates block, etc., basically a kind of
443
  // IRBuilder, but for Machine IR.
444
  MachineIRBuilder CurBuilder;
445
446
  // Builder set to the entry block (just after ABI lowering instructions). Used
447
  // as a convenient location for Constants.
448
  MachineIRBuilder EntryBuilder;
449
450
  // The MachineFunction currently being translated.
451
  MachineFunction *MF;
452
453
  /// MachineRegisterInfo used to create virtual registers.
454
  MachineRegisterInfo *MRI = nullptr;
455
456
  const DataLayout *DL;
457
458
  /// Current target configuration. Controls how the pass handles errors.
459
  const TargetPassConfig *TPC;
460
461
  /// Current optimization remark emitter. Used to report failures.
462
  std::unique_ptr<OptimizationRemarkEmitter> ORE;
463
464
  // * Insert all the code needed to materialize the constants
465
  // at the proper place. E.g., Entry block or dominator block
466
  // of each constant depending on how fancy we want to be.
467
  // * Clear the different maps.
468
  void finalizeFunction();
469
470
  /// Get the VRegs that represent \p Val.
471
  /// Non-aggregate types have just one corresponding VReg and the list can be
472
  /// used as a single "unsigned". Aggregates get flattened. If such VRegs do
473
  /// not exist, they are created.
474
  ArrayRef<unsigned> getOrCreateVRegs(const Value &Val);
475
476
19.1M
  unsigned getOrCreateVReg(const Value &Val) {
477
19.1M
    auto Regs = getOrCreateVRegs(Val);
478
19.1M
    if (Regs.empty())
479
354k
      return 0;
480
18.7M
    assert(Regs.size() == 1 &&
481
18.7M
           "attempt to get single VReg for aggregate or void");
482
18.7M
    return Regs[0];
483
18.7M
  }
484
485
  /// Allocate some vregs and offsets in the VMap. Then populate just the
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  /// offsets while leaving the vregs empty.
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  ValueToVRegInfo::VRegListT &allocateVRegs(const Value &Val);
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  /// Get the frame index that represents \p Val.
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  /// If such VReg does not exist, it is created.
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  int getOrCreateFrameIndex(const AllocaInst &AI);
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  /// Get the alignment of the given memory operation instruction. This will
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  /// either be the explicitly specified value or the ABI-required alignment for
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  /// the type being accessed (according to the Module's DataLayout).
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  unsigned getMemOpAlignment(const Instruction &I);
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498
  /// Get the MachineBasicBlock that represents \p BB. Specifically, the block
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  /// returned will be the head of the translated block (suitable for branch
500
  /// destinations).
501
  MachineBasicBlock &getMBB(const BasicBlock &BB);
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503
  /// Record \p NewPred as a Machine predecessor to `Edge.second`, corresponding
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  /// to `Edge.first` at the IR level. This is used when IRTranslation creates
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  /// multiple MachineBasicBlocks for a given IR block and the CFG is no longer
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  /// represented simply by the IR-level CFG.
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  void addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred);
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  /// Returns the Machine IR predecessors for the given IR CFG edge. Usually
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  /// this is just the single MachineBasicBlock corresponding to the predecessor
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  /// in the IR. More complex lowering can result in multiple MachineBasicBlocks
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  /// preceding the original though (e.g. switch instructions).
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1.21M
  SmallVector<MachineBasicBlock *, 1> getMachinePredBBs(CFGEdge Edge) {
514
1.21M
    auto RemappedEdge = MachinePreds.find(Edge);
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1.21M
    if (RemappedEdge != MachinePreds.end())
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11.0k
      return RemappedEdge->second;
517
1.20M
    return SmallVector<MachineBasicBlock *, 4>(1, &getMBB(*Edge.first));
518
1.20M
  }
519
520
public:
521
  // Ctor, nothing fancy.
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  IRTranslator();
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7
  StringRef getPassName() const override { return "IRTranslator"; }
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  void getAnalysisUsage(AnalysisUsage &AU) const override;
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  // Algo:
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  //   CallLowering = MF.subtarget.getCallLowering()
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  //   F = MF.getParent()
531
  //   MIRBuilder.reset(MF)
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  //   getMBB(F.getEntryBB())
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  //   CallLowering->translateArguments(MIRBuilder, F, ValToVReg)
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  //   for each bb in F
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  //     getMBB(bb)
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  //     for each inst in bb
537
  //       if (!translate(MIRBuilder, inst, ValToVReg, ConstantToSequence))
538
  //         report_fatal_error("Don't know how to translate input");
539
  //   finalize()
540
  bool runOnMachineFunction(MachineFunction &MF) override;
541
};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H