Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
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//===- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ----*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the IRTranslator pass.
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/// This pass is responsible for translating LLVM IR into MachineInstr.
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/// It uses target hooks to lower the ABI but aside from that, the pass
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/// generated code is generic. This is the default translator used for
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/// GlobalISel.
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///
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/// \todo Replace the comments with actual doxygen comments.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
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#define LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
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#include "llvm/ADT/DenseMap.h"
23
#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
25
#include "llvm/CodeGen/GlobalISel/Types.h"
26
#include "llvm/CodeGen/MachineFunctionPass.h"
27
#include "llvm/Support/Allocator.h"
28
#include "llvm/IR/Intrinsics.h"
29
#include <memory>
30
#include <utility>
31
32
namespace llvm {
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34
class AllocaInst;
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class BasicBlock;
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class CallInst;
37
class CallLowering;
38
class Constant;
39
class DataLayout;
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class Instruction;
41
class MachineBasicBlock;
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class MachineFunction;
43
class MachineInstr;
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class MachineRegisterInfo;
45
class OptimizationRemarkEmitter;
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class PHINode;
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class TargetPassConfig;
48
class User;
49
class Value;
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51
// Technically the pass should run on an hypothetical MachineModule,
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// since it should translate Global into some sort of MachineGlobal.
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// The MachineGlobal should ultimately just be a transfer of ownership of
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// the interesting bits that are relevant to represent a global value.
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// That being said, we could investigate what would it cost to just duplicate
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// the information from the LLVM IR.
57
// The idea is that ultimately we would be able to free up the memory used
58
// by the LLVM IR as soon as the translation is over.
59
class IRTranslator : public MachineFunctionPass {
60
public:
61
  static char ID;
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63
private:
64
  /// Interface used to lower the everything related to calls.
65
  const CallLowering *CLI;
66
67
  /// This class contains the mapping between the Values to vreg related data.
68
  class ValueToVRegInfo {
69
  public:
70
6.83k
    ValueToVRegInfo() = default;
71
72
    using VRegListT = SmallVector<unsigned, 1>;
73
    using OffsetListT = SmallVector<uint64_t, 1>;
74
75
    using const_vreg_iterator =
76
        DenseMap<const Value *, VRegListT *>::const_iterator;
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    using const_offset_iterator =
78
        DenseMap<const Value *, OffsetListT *>::const_iterator;
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80
27.3M
    inline const_vreg_iterator vregs_end() const { return ValToVRegs.end(); }
81
82
12.1M
    VRegListT *getVRegs(const Value &V) {
83
12.1M
      auto It = ValToVRegs.find(&V);
84
12.1M
      if (It != ValToVRegs.end())
85
42.8k
        return It->second;
86
12.1M
87
12.1M
      return insertVRegs(V);
88
12.1M
    }
89
90
16.9M
    OffsetListT *getOffsets(const Value &V) {
91
16.9M
      auto It = TypeToOffsets.find(V.getType());
92
16.9M
      if (It != TypeToOffsets.end())
93
15.2M
        return It->second;
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1.78M
95
1.78M
      return insertOffsets(V);
96
1.78M
    }
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98
27.3M
    const_vreg_iterator findVRegs(const Value &V) const {
99
27.3M
      return ValToVRegs.find(&V);
100
27.3M
    }
101
102
0
    bool contains(const Value &V) const {
103
0
      return ValToVRegs.find(&V) != ValToVRegs.end();
104
0
    }
105
106
235k
    void reset() {
107
235k
      ValToVRegs.clear();
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235k
      TypeToOffsets.clear();
109
235k
      VRegAlloc.DestroyAll();
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235k
      OffsetAlloc.DestroyAll();
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235k
    }
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113
  private:
114
12.1M
    VRegListT *insertVRegs(const Value &V) {
115
12.1M
      assert(ValToVRegs.find(&V) == ValToVRegs.end() && "Value already exists");
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12.1M
117
12.1M
      // We placement new using our fast allocator since we never try to free
118
12.1M
      // the vectors until translation is finished.
119
12.1M
      auto *VRegList = new (VRegAlloc.Allocate()) VRegListT();
120
12.1M
      ValToVRegs[&V] = VRegList;
121
12.1M
      return VRegList;
122
12.1M
    }
123
124
1.78M
    OffsetListT *insertOffsets(const Value &V) {
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1.78M
      assert(TypeToOffsets.find(V.getType()) == TypeToOffsets.end() &&
126
1.78M
             "Type already exists");
127
1.78M
128
1.78M
      auto *OffsetList = new (OffsetAlloc.Allocate()) OffsetListT();
129
1.78M
      TypeToOffsets[V.getType()] = OffsetList;
130
1.78M
      return OffsetList;
131
1.78M
    }
132
    SpecificBumpPtrAllocator<VRegListT> VRegAlloc;
133
    SpecificBumpPtrAllocator<OffsetListT> OffsetAlloc;
134
135
    // We store pointers to vectors here since references may be invalidated
136
    // while we hold them if we stored the vectors directly.
137
    DenseMap<const Value *, VRegListT*> ValToVRegs;
138
    DenseMap<const Type *, OffsetListT*> TypeToOffsets;
139
  };
140
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  /// Mapping of the values of the current LLVM IR function to the related
142
  /// virtual registers and offsets.
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  ValueToVRegInfo VMap;
144
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  // N.b. it's not completely obvious that this will be sufficient for every
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  // LLVM IR construct (with "invoke" being the obvious candidate to mess up our
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  // lives.
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  DenseMap<const BasicBlock *, MachineBasicBlock *> BBToMBB;
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  // One BasicBlock can be translated to multiple MachineBasicBlocks.  For such
151
  // BasicBlocks translated to multiple MachineBasicBlocks, MachinePreds retains
152
  // a mapping between the edges arriving at the BasicBlock to the corresponding
153
  // created MachineBasicBlocks. Some BasicBlocks that get translated to a
154
  // single MachineBasicBlock may also end up in this Map.
155
  using CFGEdge = std::pair<const BasicBlock *, const BasicBlock *>;
156
  DenseMap<CFGEdge, SmallVector<MachineBasicBlock *, 1>> MachinePreds;
157
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  // List of stubbed PHI instructions, for values and basic blocks to be filled
159
  // in once all MachineBasicBlocks have been created.
160
  SmallVector<std::pair<const PHINode *, SmallVector<MachineInstr *, 1>>, 4>
161
      PendingPHIs;
162
163
  /// Record of what frame index has been allocated to specified allocas for
164
  /// this function.
165
  DenseMap<const AllocaInst *, int> FrameIndices;
166
167
  /// \name Methods for translating form LLVM IR to MachineInstr.
168
  /// \see ::translate for general information on the translate methods.
169
  /// @{
170
171
  /// Translate \p Inst into its corresponding MachineInstr instruction(s).
172
  /// Insert the newly translated instruction(s) right where the CurBuilder
173
  /// is set.
174
  ///
175
  /// The general algorithm is:
176
  /// 1. Look for a virtual register for each operand or
177
  ///    create one.
178
  /// 2 Update the VMap accordingly.
179
  /// 2.alt. For constant arguments, if they are compile time constants,
180
  ///   produce an immediate in the right operand and do not touch
181
  ///   ValToReg. Actually we will go with a virtual register for each
182
  ///   constants because it may be expensive to actually materialize the
183
  ///   constant. Moreover, if the constant spans on several instructions,
184
  ///   CSE may not catch them.
185
  ///   => Update ValToVReg and remember that we saw a constant in Constants.
186
  ///   We will materialize all the constants in finalize.
187
  /// Note: we would need to do something so that we can recognize such operand
188
  ///       as constants.
189
  /// 3. Create the generic instruction.
190
  ///
191
  /// \return true if the translation succeeded.
192
  bool translate(const Instruction &Inst);
193
194
  /// Materialize \p C into virtual-register \p Reg. The generic instructions
195
  /// performing this materialization will be inserted into the entry block of
196
  /// the function.
197
  ///
198
  /// \return true if the materialization succeeded.
199
  bool translate(const Constant &C, unsigned Reg);
200
201
  /// Translate an LLVM bitcast into generic IR. Either a COPY or a G_BITCAST is
202
  /// emitted.
203
  bool translateBitCast(const User &U, MachineIRBuilder &MIRBuilder);
204
205
  /// Translate an LLVM load instruction into generic IR.
206
  bool translateLoad(const User &U, MachineIRBuilder &MIRBuilder);
207
208
  /// Translate an LLVM store instruction into generic IR.
209
  bool translateStore(const User &U, MachineIRBuilder &MIRBuilder);
210
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  /// Translate an LLVM string intrinsic (memcpy, memset, ...).
212
  bool translateMemfunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
213
                        unsigned ID);
214
215
  void getStackGuard(unsigned DstReg, MachineIRBuilder &MIRBuilder);
216
217
  bool translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
218
                                  MachineIRBuilder &MIRBuilder);
219
220
  bool translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
221
                               MachineIRBuilder &MIRBuilder);
222
223
  bool translateInlineAsm(const CallInst &CI, MachineIRBuilder &MIRBuilder);
224
225
  // FIXME: temporary function to expose previous interface to call lowering
226
  // until it is refactored.
227
  /// Combines all component registers of \p V into a single scalar with size
228
  /// "max(Offsets) + last size".
229
  unsigned packRegs(const Value &V, MachineIRBuilder &MIRBuilder);
230
231
  void unpackRegs(const Value &V, unsigned Src, MachineIRBuilder &MIRBuilder);
232
233
  /// Returns true if the value should be split into multiple LLTs.
234
  /// If \p Offsets is given then the split type's offsets will be stored in it.
235
  /// If \p Offsets is not empty it will be cleared first.
236
  bool valueIsSplit(const Value &V,
237
                    SmallVectorImpl<uint64_t> *Offsets = nullptr);
238
239
  /// Translate call instruction.
240
  /// \pre \p U is a call instruction.
241
  bool translateCall(const User &U, MachineIRBuilder &MIRBuilder);
242
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  bool translateInvoke(const User &U, MachineIRBuilder &MIRBuilder);
244
245
  bool translateLandingPad(const User &U, MachineIRBuilder &MIRBuilder);
246
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  /// Translate one of LLVM's cast instructions into MachineInstrs, with the
248
  /// given generic Opcode.
249
  bool translateCast(unsigned Opcode, const User &U,
250
                     MachineIRBuilder &MIRBuilder);
251
252
  /// Translate a phi instruction.
253
  bool translatePHI(const User &U, MachineIRBuilder &MIRBuilder);
254
255
  /// Translate a comparison (icmp or fcmp) instruction or constant.
256
  bool translateCompare(const User &U, MachineIRBuilder &MIRBuilder);
257
258
  /// Translate an integer compare instruction (or constant).
259
1.04M
  bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) {
260
1.04M
    return translateCompare(U, MIRBuilder);
261
1.04M
  }
262
263
  /// Translate a floating-point compare instruction (or constant).
264
17.1k
  bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) {
265
17.1k
    return translateCompare(U, MIRBuilder);
266
17.1k
  }
267
268
  /// Add remaining operands onto phis we've translated. Executed after all
269
  /// MachineBasicBlocks for the function have been created.
270
  void finishPendingPhis();
271
272
  /// Translate \p Inst into a binary operation \p Opcode.
273
  /// \pre \p U is a binary operation.
274
  bool translateBinaryOp(unsigned Opcode, const User &U,
275
                         MachineIRBuilder &MIRBuilder);
276
277
  /// Translate branch (br) instruction.
278
  /// \pre \p U is a branch instruction.
279
  bool translateBr(const User &U, MachineIRBuilder &MIRBuilder);
280
281
  bool translateSwitch(const User &U, MachineIRBuilder &MIRBuilder);
282
283
  bool translateIndirectBr(const User &U, MachineIRBuilder &MIRBuilder);
284
285
  bool translateExtractValue(const User &U, MachineIRBuilder &MIRBuilder);
286
287
  bool translateInsertValue(const User &U, MachineIRBuilder &MIRBuilder);
288
289
  bool translateSelect(const User &U, MachineIRBuilder &MIRBuilder);
290
291
  bool translateGetElementPtr(const User &U, MachineIRBuilder &MIRBuilder);
292
293
  bool translateAlloca(const User &U, MachineIRBuilder &MIRBuilder);
294
295
  /// Translate return (ret) instruction.
296
  /// The target needs to implement CallLowering::lowerReturn for
297
  /// this to succeed.
298
  /// \pre \p U is a return instruction.
299
  bool translateRet(const User &U, MachineIRBuilder &MIRBuilder);
300
301
  bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder);
302
303
  bool translateFNeg(const User &U, MachineIRBuilder &MIRBuilder);
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305
372k
  bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) {
306
372k
    return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder);
307
372k
  }
308
90.5k
  bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) {
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90.5k
    return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder);
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90.5k
  }
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105k
  bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) {
312
105k
    return translateBinaryOp(TargetOpcode::G_AND, U, MIRBuilder);
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105k
  }
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82.2k
  bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) {
315
82.2k
    return translateBinaryOp(TargetOpcode::G_MUL, U, MIRBuilder);
316
82.2k
  }
317
38.7k
  bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) {
318
38.7k
    return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder);
319
38.7k
  }
320
10.5k
  bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) {
321
10.5k
    return translateBinaryOp(TargetOpcode::G_XOR, U, MIRBuilder);
322
10.5k
  }
323
324
7.60k
  bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) {
325
7.60k
    return translateBinaryOp(TargetOpcode::G_UDIV, U, MIRBuilder);
326
7.60k
  }
327
10.2k
  bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) {
328
10.2k
    return translateBinaryOp(TargetOpcode::G_SDIV, U, MIRBuilder);
329
10.2k
  }
330
1.16k
  bool translateURem(const User &U, MachineIRBuilder &MIRBuilder) {
331
1.16k
    return translateBinaryOp(TargetOpcode::G_UREM, U, MIRBuilder);
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1.16k
  }
333
2.56k
  bool translateSRem(const User &U, MachineIRBuilder &MIRBuilder) {
334
2.56k
    return translateBinaryOp(TargetOpcode::G_SREM, U, MIRBuilder);
335
2.56k
  }
336
36.7k
  bool translateIntToPtr(const User &U, MachineIRBuilder &MIRBuilder) {
337
36.7k
    return translateCast(TargetOpcode::G_INTTOPTR, U, MIRBuilder);
338
36.7k
  }
339
69.0k
  bool translatePtrToInt(const User &U, MachineIRBuilder &MIRBuilder) {
340
69.0k
    return translateCast(TargetOpcode::G_PTRTOINT, U, MIRBuilder);
341
69.0k
  }
342
169k
  bool translateTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
343
169k
    return translateCast(TargetOpcode::G_TRUNC, U, MIRBuilder);
344
169k
  }
345
4.05k
  bool translateFPTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
346
4.05k
    return translateCast(TargetOpcode::G_FPTRUNC, U, MIRBuilder);
347
4.05k
  }
348
12.8k
  bool translateFPExt(const User &U, MachineIRBuilder &MIRBuilder) {
349
12.8k
    return translateCast(TargetOpcode::G_FPEXT, U, MIRBuilder);
350
12.8k
  }
351
3.26k
  bool translateFPToUI(const User &U, MachineIRBuilder &MIRBuilder) {
352
3.26k
    return translateCast(TargetOpcode::G_FPTOUI, U, MIRBuilder);
353
3.26k
  }
354
2.58k
  bool translateFPToSI(const User &U, MachineIRBuilder &MIRBuilder) {
355
2.58k
    return translateCast(TargetOpcode::G_FPTOSI, U, MIRBuilder);
356
2.58k
  }
357
14.8k
  bool translateUIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
358
14.8k
    return translateCast(TargetOpcode::G_UITOFP, U, MIRBuilder);
359
14.8k
  }
360
29.6k
  bool translateSIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
361
29.6k
    return translateCast(TargetOpcode::G_SITOFP, U, MIRBuilder);
362
29.6k
  }
363
12.2k
  bool translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder) {
364
12.2k
    return true;
365
12.2k
  }
366
162k
  bool translateSExt(const User &U, MachineIRBuilder &MIRBuilder) {
367
162k
    return translateCast(TargetOpcode::G_SEXT, U, MIRBuilder);
368
162k
  }
369
370
105k
  bool translateZExt(const User &U, MachineIRBuilder &MIRBuilder) {
371
105k
    return translateCast(TargetOpcode::G_ZEXT, U, MIRBuilder);
372
105k
  }
373
374
64.3k
  bool translateShl(const User &U, MachineIRBuilder &MIRBuilder) {
375
64.3k
    return translateBinaryOp(TargetOpcode::G_SHL, U, MIRBuilder);
376
64.3k
  }
377
38.4k
  bool translateLShr(const User &U, MachineIRBuilder &MIRBuilder) {
378
38.4k
    return translateBinaryOp(TargetOpcode::G_LSHR, U, MIRBuilder);
379
38.4k
  }
380
15.1k
  bool translateAShr(const User &U, MachineIRBuilder &MIRBuilder) {
381
15.1k
    return translateBinaryOp(TargetOpcode::G_ASHR, U, MIRBuilder);
382
15.1k
  }
383
384
51.6k
  bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) {
385
51.6k
    return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder);
386
51.6k
  }
387
48.1k
  bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) {
388
48.1k
    return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder);
389
48.1k
  }
390
36.9k
  bool translateFDiv(const User &U, MachineIRBuilder &MIRBuilder) {
391
36.9k
    return translateBinaryOp(TargetOpcode::G_FDIV, U, MIRBuilder);
392
36.9k
  }
393
35
  bool translateFRem(const User &U, MachineIRBuilder &MIRBuilder) {
394
35
    return translateBinaryOp(TargetOpcode::G_FREM, U, MIRBuilder);
395
35
  }
396
397
  bool translateVAArg(const User &U, MachineIRBuilder &MIRBuilder);
398
399
  bool translateInsertElement(const User &U, MachineIRBuilder &MIRBuilder);
400
401
  bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder);
402
403
  bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder);
404
405
  bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder);
406
  bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder);
407
408
  // Stubs to keep the compiler happy while we implement the rest of the
409
  // translation.
410
0
  bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) {
411
0
    return false;
412
0
  }
413
0
  bool translateCleanupRet(const User &U, MachineIRBuilder &MIRBuilder) {
414
0
    return false;
415
0
  }
416
0
  bool translateCatchRet(const User &U, MachineIRBuilder &MIRBuilder) {
417
0
    return false;
418
0
  }
419
0
  bool translateCatchSwitch(const User &U, MachineIRBuilder &MIRBuilder) {
420
0
    return false;
421
0
  }
422
1.39k
  bool translateFence(const User &U, MachineIRBuilder &MIRBuilder) {
423
1.39k
    return false;
424
1.39k
  }
425
2
  bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) {
426
2
    return translateCast(TargetOpcode::G_ADDRSPACE_CAST, U, MIRBuilder);
427
2
  }
428
0
  bool translateCleanupPad(const User &U, MachineIRBuilder &MIRBuilder) {
429
0
    return false;
430
0
  }
431
0
  bool translateCatchPad(const User &U, MachineIRBuilder &MIRBuilder) {
432
0
    return false;
433
0
  }
434
0
  bool translateUserOp1(const User &U, MachineIRBuilder &MIRBuilder) {
435
0
    return false;
436
0
  }
437
0
  bool translateUserOp2(const User &U, MachineIRBuilder &MIRBuilder) {
438
0
    return false;
439
0
  }
440
441
  /// @}
442
443
  // Builder for machine instruction a la IRBuilder.
444
  // I.e., compared to regular MIBuilder, this one also inserts the instruction
445
  // in the current block, it can creates block, etc., basically a kind of
446
  // IRBuilder, but for Machine IR.
447
  MachineIRBuilder CurBuilder;
448
449
  // Builder set to the entry block (just after ABI lowering instructions). Used
450
  // as a convenient location for Constants.
451
  MachineIRBuilder EntryBuilder;
452
453
  // The MachineFunction currently being translated.
454
  MachineFunction *MF;
455
456
  /// MachineRegisterInfo used to create virtual registers.
457
  MachineRegisterInfo *MRI = nullptr;
458
459
  const DataLayout *DL;
460
461
  /// Current target configuration. Controls how the pass handles errors.
462
  const TargetPassConfig *TPC;
463
464
  /// Current optimization remark emitter. Used to report failures.
465
  std::unique_ptr<OptimizationRemarkEmitter> ORE;
466
467
  // * Insert all the code needed to materialize the constants
468
  // at the proper place. E.g., Entry block or dominator block
469
  // of each constant depending on how fancy we want to be.
470
  // * Clear the different maps.
471
  void finalizeFunction();
472
473
  /// Get the VRegs that represent \p Val.
474
  /// Non-aggregate types have just one corresponding VReg and the list can be
475
  /// used as a single "unsigned". Aggregates get flattened. If such VRegs do
476
  /// not exist, they are created.
477
  ArrayRef<unsigned> getOrCreateVRegs(const Value &Val);
478
479
19.8M
  unsigned getOrCreateVReg(const Value &Val) {
480
19.8M
    auto Regs = getOrCreateVRegs(Val);
481
19.8M
    if (Regs.empty())
482
366k
      return 0;
483
19.4M
    assert(Regs.size() == 1 &&
484
19.4M
           "attempt to get single VReg for aggregate or void");
485
19.4M
    return Regs[0];
486
19.4M
  }
487
488
  /// Allocate some vregs and offsets in the VMap. Then populate just the
489
  /// offsets while leaving the vregs empty.
490
  ValueToVRegInfo::VRegListT &allocateVRegs(const Value &Val);
491
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  /// Get the frame index that represents \p Val.
493
  /// If such VReg does not exist, it is created.
494
  int getOrCreateFrameIndex(const AllocaInst &AI);
495
496
  /// Get the alignment of the given memory operation instruction. This will
497
  /// either be the explicitly specified value or the ABI-required alignment for
498
  /// the type being accessed (according to the Module's DataLayout).
499
  unsigned getMemOpAlignment(const Instruction &I);
500
501
  /// Get the MachineBasicBlock that represents \p BB. Specifically, the block
502
  /// returned will be the head of the translated block (suitable for branch
503
  /// destinations).
504
  MachineBasicBlock &getMBB(const BasicBlock &BB);
505
506
  /// Record \p NewPred as a Machine predecessor to `Edge.second`, corresponding
507
  /// to `Edge.first` at the IR level. This is used when IRTranslation creates
508
  /// multiple MachineBasicBlocks for a given IR block and the CFG is no longer
509
  /// represented simply by the IR-level CFG.
510
  void addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred);
511
512
  /// Returns the Machine IR predecessors for the given IR CFG edge. Usually
513
  /// this is just the single MachineBasicBlock corresponding to the predecessor
514
  /// in the IR. More complex lowering can result in multiple MachineBasicBlocks
515
  /// preceding the original though (e.g. switch instructions).
516
1.26M
  SmallVector<MachineBasicBlock *, 1> getMachinePredBBs(CFGEdge Edge) {
517
1.26M
    auto RemappedEdge = MachinePreds.find(Edge);
518
1.26M
    if (RemappedEdge != MachinePreds.end())
519
11.1k
      return RemappedEdge->second;
520
1.25M
    return SmallVector<MachineBasicBlock *, 4>(1, &getMBB(*Edge.first));
521
1.25M
  }
522
523
public:
524
  // Ctor, nothing fancy.
525
  IRTranslator();
526
527
6.83k
  StringRef getPassName() const override { return "IRTranslator"; }
528
529
  void getAnalysisUsage(AnalysisUsage &AU) const override;
530
531
  // Algo:
532
  //   CallLowering = MF.subtarget.getCallLowering()
533
  //   F = MF.getParent()
534
  //   MIRBuilder.reset(MF)
535
  //   getMBB(F.getEntryBB())
536
  //   CallLowering->translateArguments(MIRBuilder, F, ValToVReg)
537
  //   for each bb in F
538
  //     getMBB(bb)
539
  //     for each inst in bb
540
  //       if (!translate(MIRBuilder, inst, ValToVReg, ConstantToSequence))
541
  //         report_fatal_error("Don't know how to translate input");
542
  //   finalize()
543
  bool runOnMachineFunction(MachineFunction &MF) override;
544
};
545
546
} // end namespace llvm
547
548
#endif // LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H