Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
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//===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file declares the API for the instruction selector.
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/// This class is responsible for selecting machine instructions.
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/// It's implemented by the target. It's used by the InstructionSelect pass.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
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#define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/CodeGenCoverage.h"
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#include "llvm/Support/LowLevelTypeImpl.h"
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#include <bitset>
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#include <cstddef>
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#include <cstdint>
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#include <functional>
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#include <initializer_list>
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#include <vector>
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namespace llvm {
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class APInt;
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class APFloat;
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class MachineInstr;
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class MachineInstrBuilder;
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class MachineFunction;
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class MachineOperand;
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class MachineRegisterInfo;
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class RegisterBankInfo;
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class TargetInstrInfo;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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/// Container class for CodeGen predicate results.
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/// This is convenient because std::bitset does not have a constructor
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/// with an initializer list of set bits.
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///
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/// Each InstructionSelector subclass should define a PredicateBitset class
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/// with:
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///   const unsigned MAX_SUBTARGET_PREDICATES = 192;
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///   using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
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/// and updating the constant to suit the target. Tablegen provides a suitable
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/// definition for the predicates in use in <Target>GenGlobalISel.inc when
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/// GET_GLOBALISEL_PREDICATE_BITSET is defined.
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template <std::size_t MaxPredicates>
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class PredicateBitsetImpl : public std::bitset<MaxPredicates> {
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public:
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  // Cannot inherit constructors because it's not supported by VC++..
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6.55M
  PredicateBitsetImpl() = default;
llvm::PredicateBitsetImpl<22ul>::PredicateBitsetImpl()
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Source
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6.06M
  PredicateBitsetImpl() = default;
llvm::PredicateBitsetImpl<46ul>::PredicateBitsetImpl()
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111k
  PredicateBitsetImpl() = default;
llvm::PredicateBitsetImpl<70ul>::PredicateBitsetImpl()
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118k
  PredicateBitsetImpl() = default;
llvm::PredicateBitsetImpl<42ul>::PredicateBitsetImpl()
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126k
  PredicateBitsetImpl() = default;
llvm::PredicateBitsetImpl<114ul>::PredicateBitsetImpl()
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135k
  PredicateBitsetImpl() = default;
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  PredicateBitsetImpl(const std::bitset<MaxPredicates> &B)
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5.94M
      : std::bitset<MaxPredicates>(B) {}
llvm::PredicateBitsetImpl<22ul>::PredicateBitsetImpl(std::__1::bitset<22ul> const&)
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62
5.94M
      : std::bitset<MaxPredicates>(B) {}
llvm::PredicateBitsetImpl<46ul>::PredicateBitsetImpl(std::__1::bitset<46ul> const&)
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1.34k
      : std::bitset<MaxPredicates>(B) {}
llvm::PredicateBitsetImpl<70ul>::PredicateBitsetImpl(std::__1::bitset<70ul> const&)
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1.11k
      : std::bitset<MaxPredicates>(B) {}
llvm::PredicateBitsetImpl<42ul>::PredicateBitsetImpl(std::__1::bitset<42ul> const&)
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1.40k
      : std::bitset<MaxPredicates>(B) {}
llvm::PredicateBitsetImpl<114ul>::PredicateBitsetImpl(std::__1::bitset<114ul> const&)
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2.27k
      : std::bitset<MaxPredicates>(B) {}
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25.0M
  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
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25.0M
    for (auto I : Init)
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57.9M
      std::bitset<MaxPredicates>::set(I);
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25.0M
  }
llvm::PredicateBitsetImpl<22ul>::PredicateBitsetImpl(std::initializer_list<unsigned int>)
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64
1.74M
  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
65
1.74M
    for (auto I : Init)
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2.15M
      std::bitset<MaxPredicates>::set(I);
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1.74M
  }
llvm::PredicateBitsetImpl<46ul>::PredicateBitsetImpl(std::initializer_list<unsigned int>)
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64
1.95M
  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
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1.95M
    for (auto I : Init)
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6.47M
      std::bitset<MaxPredicates>::set(I);
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1.95M
  }
llvm::PredicateBitsetImpl<70ul>::PredicateBitsetImpl(std::initializer_list<unsigned int>)
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64
6.57M
  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
65
6.57M
    for (auto I : Init)
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12.8M
      std::bitset<MaxPredicates>::set(I);
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6.57M
  }
llvm::PredicateBitsetImpl<42ul>::PredicateBitsetImpl(std::initializer_list<unsigned int>)
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64
7.40M
  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
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7.40M
    for (auto I : Init)
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25.4M
      std::bitset<MaxPredicates>::set(I);
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7.40M
  }
llvm::PredicateBitsetImpl<114ul>::PredicateBitsetImpl(std::initializer_list<unsigned int>)
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64
7.32M
  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
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7.32M
    for (auto I : Init)
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10.9M
      std::bitset<MaxPredicates>::set(I);
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  }
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};
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enum {
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  /// Begin a try-block to attempt a match and jump to OnFail if it is
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  /// unsuccessful.
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  /// - OnFail - The MatchTable entry at which to resume if the match fails.
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  ///
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  /// FIXME: This ought to take an argument indicating the number of try-blocks
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  ///        to exit on failure. It's usually one but the last match attempt of
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  ///        a block will need more. The (implemented) alternative is to tack a
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  ///        GIM_Reject on the end of each try-block which is simpler but
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  ///        requires an extra opcode and iteration in the interpreter on each
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  ///        failed match.
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  GIM_Try,
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  /// Switch over the opcode on the specified instruction
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  /// - InsnID - Instruction ID
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  /// - LowerBound - numerically minimum opcode supported
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  /// - UpperBound - numerically maximum + 1 opcode supported
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  /// - Default - failure jump target
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  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
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  GIM_SwitchOpcode,
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  /// Switch over the LLT on the specified instruction operand
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - LowerBound - numerically minimum Type ID supported
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  /// - UpperBound - numerically maximum + 1 Type ID supported
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  /// - Default - failure jump target
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  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
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  GIM_SwitchType,
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  /// Record the specified instruction
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  /// - NewInsnID - Instruction ID to define
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  GIM_RecordInsn,
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  /// Check the feature bits
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  /// - Expected features
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  GIM_CheckFeatures,
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  /// Check the opcode on the specified instruction
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  /// - InsnID - Instruction ID
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  /// - Expected opcode
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  GIM_CheckOpcode,
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  /// Check the instruction has the right number of operands
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  /// - InsnID - Instruction ID
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  /// - Expected number of operands
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  GIM_CheckNumOperands,
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  /// Check an immediate predicate on the specified instruction
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  /// - InsnID - Instruction ID
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  /// - The predicate to test
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  GIM_CheckI64ImmPredicate,
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  /// Check an immediate predicate on the specified instruction via an APInt.
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  /// - InsnID - Instruction ID
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  /// - The predicate to test
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  GIM_CheckAPIntImmPredicate,
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  /// Check a floating point immediate predicate on the specified instruction.
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  /// - InsnID - Instruction ID
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  /// - The predicate to test
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  GIM_CheckAPFloatImmPredicate,
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  /// Check a memory operation has the specified atomic ordering.
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  /// - InsnID - Instruction ID
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  /// - Ordering - The AtomicOrdering value
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  GIM_CheckAtomicOrdering,
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  GIM_CheckAtomicOrderingOrStrongerThan,
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  GIM_CheckAtomicOrderingWeakerThan,
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  /// Check the size of the memory access for the given machine memory operand.
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  /// - InsnID - Instruction ID
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  /// - MMOIdx - MMO index
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  /// - Size - The size in bytes of the memory access
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  GIM_CheckMemorySizeEqualTo,
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  /// Check the address space of the memory access for the given machine memory
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  /// operand.
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  /// - InsnID - Instruction ID
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  /// - MMOIdx - MMO index
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  /// - NumAddrSpace - Number of valid address spaces
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  /// - AddrSpaceN - An allowed space of the memory access
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  /// - AddrSpaceN+1 ...
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  GIM_CheckMemoryAddressSpace,
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  /// Check the size of the memory access for the given machine memory operand
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  /// against the size of an operand.
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  /// - InsnID - Instruction ID
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  /// - MMOIdx - MMO index
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  /// - OpIdx - The operand index to compare the MMO against
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  GIM_CheckMemorySizeEqualToLLT,
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  GIM_CheckMemorySizeLessThanLLT,
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  GIM_CheckMemorySizeGreaterThanLLT,
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  /// Check a generic C++ instruction predicate
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  /// - InsnID - Instruction ID
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  /// - PredicateID - The ID of the predicate function to call
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  GIM_CheckCxxInsnPredicate,
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  /// Check the type for the specified operand
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - Expected type
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  GIM_CheckType,
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  /// Check the type of a pointer to any address space.
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - SizeInBits - The size of the pointer value in bits.
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  GIM_CheckPointerToAny,
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  /// Check the register bank for the specified operand
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - Expected register bank (specified as a register class)
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  GIM_CheckRegBankForClass,
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  /// Check the operand matches a complex predicate
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - RendererID - The renderer to hold the result
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  /// - Complex predicate ID
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  GIM_CheckComplexPattern,
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  /// Check the operand is a specific integer
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - Expected integer
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  GIM_CheckConstantInt,
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  /// Check the operand is a specific literal integer (i.e. MO.isImm() or
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  /// MO.isCImm() is true).
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - Expected integer
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  GIM_CheckLiteralInt,
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  /// Check the operand is a specific intrinsic ID
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - Expected Intrinsic ID
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  GIM_CheckIntrinsicID,
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  /// Check the specified operand is an MBB
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  GIM_CheckIsMBB,
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  /// Check if the specified operand is safe to fold into the current
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  /// instruction.
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  /// - InsnID - Instruction ID
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  GIM_CheckIsSafeToFold,
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  /// Check the specified operands are identical.
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - OtherInsnID - Other instruction ID
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  /// - OtherOpIdx - Other operand index
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  GIM_CheckIsSameOperand,
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  /// Fail the current try-block, or completely fail to match if there is no
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  /// current try-block.
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  GIM_Reject,
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  //=== Renderers ===
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  /// Mutate an instruction
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  /// - NewInsnID - Instruction ID to define
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  /// - OldInsnID - Instruction ID to mutate
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  /// - NewOpcode - The new opcode to use
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  GIR_MutateOpcode,
232
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  /// Build a new instruction
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  /// - InsnID - Instruction ID to define
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  /// - Opcode - The new opcode to use
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  GIR_BuildMI,
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  /// Copy an operand to the specified instruction
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  /// - NewInsnID - Instruction ID to modify
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  /// - OldInsnID - Instruction ID to copy from
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  /// - OpIdx - The operand to copy
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  GIR_Copy,
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  /// Copy an operand to the specified instruction or add a zero register if the
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  /// operand is a zero immediate.
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  /// - NewInsnID - Instruction ID to modify
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  /// - OldInsnID - Instruction ID to copy from
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  /// - OpIdx - The operand to copy
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  /// - ZeroReg - The zero register to use
250
  GIR_CopyOrAddZeroReg,
251
  /// Copy an operand to the specified instruction
252
  /// - NewInsnID - Instruction ID to modify
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  /// - OldInsnID - Instruction ID to copy from
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  /// - OpIdx - The operand to copy
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  /// - SubRegIdx - The subregister to copy
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  GIR_CopySubReg,
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  /// Add an implicit register def to the specified instruction
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  /// - InsnID - Instruction ID to modify
260
  /// - RegNum - The register to add
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  GIR_AddImplicitDef,
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  /// Add an implicit register use to the specified instruction
263
  /// - InsnID - Instruction ID to modify
264
  /// - RegNum - The register to add
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  GIR_AddImplicitUse,
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  /// Add an register to the specified instruction
267
  /// - InsnID - Instruction ID to modify
268
  /// - RegNum - The register to add
269
  GIR_AddRegister,
270
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  /// Add a temporary register to the specified instruction
272
  /// - InsnID - Instruction ID to modify
273
  /// - TempRegID - The temporary register ID to add
274
  /// - TempRegFlags - The register flags to set
275
  GIR_AddTempRegister,
276
277
  /// Add an immediate to the specified instruction
278
  /// - InsnID - Instruction ID to modify
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  /// - Imm - The immediate to add
280
  GIR_AddImm,
281
  /// Render complex operands to the specified instruction
282
  /// - InsnID - Instruction ID to modify
283
  /// - RendererID - The renderer to call
284
  GIR_ComplexRenderer,
285
286
  /// Render sub-operands of complex operands to the specified instruction
287
  /// - InsnID - Instruction ID to modify
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  /// - RendererID - The renderer to call
289
  /// - RenderOpID - The suboperand to render.
290
  GIR_ComplexSubOperandRenderer,
291
  /// Render operands to the specified instruction using a custom function
292
  /// - InsnID - Instruction ID to modify
293
  /// - OldInsnID - Instruction ID to get the matched operand from
294
  /// - RendererFnID - Custom renderer function to call
295
  GIR_CustomRenderer,
296
297
  /// Render a G_CONSTANT operator as a sign-extended immediate.
298
  /// - NewInsnID - Instruction ID to modify
299
  /// - OldInsnID - Instruction ID to copy from
300
  /// The operand index is implicitly 1.
301
  GIR_CopyConstantAsSImm,
302
303
  /// Render a G_FCONSTANT operator as a sign-extended immediate.
304
  /// - NewInsnID - Instruction ID to modify
305
  /// - OldInsnID - Instruction ID to copy from
306
  /// The operand index is implicitly 1.
307
  GIR_CopyFConstantAsFPImm,
308
309
  /// Constrain an instruction operand to a register class.
310
  /// - InsnID - Instruction ID to modify
311
  /// - OpIdx - Operand index
312
  /// - RCEnum - Register class enumeration value
313
  GIR_ConstrainOperandRC,
314
315
  /// Constrain an instructions operands according to the instruction
316
  /// description.
317
  /// - InsnID - Instruction ID to modify
318
  GIR_ConstrainSelectedInstOperands,
319
320
  /// Merge all memory operands into instruction.
321
  /// - InsnID - Instruction ID to modify
322
  /// - MergeInsnID... - One or more Instruction ID to merge into the result.
323
  /// - GIU_MergeMemOperands_EndOfList - Terminates the list of instructions to
324
  ///                                    merge.
325
  GIR_MergeMemOperands,
326
327
  /// Erase from parent.
328
  /// - InsnID - Instruction ID to erase
329
  GIR_EraseFromParent,
330
331
  /// Create a new temporary register that's not constrained.
332
  /// - TempRegID - The temporary register ID to initialize.
333
  /// - Expected type
334
  GIR_MakeTempReg,
335
336
  /// A successful emission
337
  GIR_Done,
338
339
  /// Increment the rule coverage counter.
340
  /// - RuleID - The ID of the rule that was covered.
341
  GIR_Coverage,
342
343
  /// Keeping track of the number of the GI opcodes. Must be the last entry.
344
  GIU_NumOpcodes,
345
};
346
347
enum {
348
  /// Indicates the end of the variable-length MergeInsnID list in a
349
  /// GIR_MergeMemOperands opcode.
350
  GIU_MergeMemOperands_EndOfList = -1,
351
};
352
353
/// Provides the logic to select generic machine instructions.
354
class InstructionSelector {
355
public:
356
34.0k
  virtual ~InstructionSelector() = default;
357
358
  /// Select the (possibly generic) instruction \p I to only use target-specific
359
  /// opcodes. It is OK to insert multiple instructions, but they cannot be
360
  /// generic pre-isel instructions.
361
  ///
362
  /// \returns whether selection succeeded.
363
  /// \pre  I.getParent() && I.getParent()->getParent()
364
  /// \post
365
  ///   if returns true:
366
  ///     for I in all mutated/inserted instructions:
367
  ///       !isPreISelGenericOpcode(I.getOpcode())
368
  virtual bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const = 0;
369
370
protected:
371
  using ComplexRendererFns =
372
      Optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
373
  using RecordedMIVector = SmallVector<MachineInstr *, 4>;
374
  using NewMIVector = SmallVector<MachineInstrBuilder, 4>;
375
376
  struct MatcherState {
377
    std::vector<ComplexRendererFns::value_type> Renderers;
378
    RecordedMIVector MIs;
379
    DenseMap<unsigned, unsigned> TempRegisters;
380
381
    MatcherState(unsigned MaxRenderers);
382
  };
383
384
public:
385
  template <class PredicateBitset, class ComplexMatcherMemFn,
386
            class CustomRendererFn>
387
  struct ISelInfoTy {
388
    ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
389
               const PredicateBitset *FeatureBitsets,
390
               const ComplexMatcherMemFn *ComplexPredicates,
391
               const CustomRendererFn *CustomRenderers)
392
        : TypeObjects(TypeObjects),
393
          FeatureBitsets(FeatureBitsets),
394
          ComplexPredicates(ComplexPredicates),
395
46.7k
          CustomRenderers(CustomRenderers) {
396
46.7k
397
789k
      for (size_t I = 0; I < NumTypeObjects; 
++I742k
)
398
742k
        TypeIDMap[TypeObjects[I]] = I;
399
46.7k
    }
AArch64InstructionSelector.cpp:llvm::InstructionSelector::ISelInfoTy<llvm::PredicateBitsetImpl<22ul>, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::AArch64InstructionSelector::*)(llvm::MachineOperand&) const, void ((anonymous namespace)::AArch64InstructionSelector::*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const>::ISelInfoTy(llvm::LLT const*, unsigned long, llvm::PredicateBitsetImpl<22ul> const*, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::AArch64InstructionSelector::* const*)(llvm::MachineOperand&) const, void ((anonymous namespace)::AArch64InstructionSelector::* const*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const)
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395
9.10k
          CustomRenderers(CustomRenderers) {
396
9.10k
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109k
      for (size_t I = 0; I < NumTypeObjects; 
++I100k
)
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100k
        TypeIDMap[TypeObjects[I]] = I;
399
9.10k
    }
llvm::InstructionSelector::ISelInfoTy<llvm::PredicateBitsetImpl<46ul>, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > (llvm::AMDGPUInstructionSelector::*)(llvm::MachineOperand&) const, void (llvm::AMDGPUInstructionSelector::*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const>::ISelInfoTy(llvm::LLT const*, unsigned long, llvm::PredicateBitsetImpl<46ul> const*, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > (llvm::AMDGPUInstructionSelector::* const*)(llvm::MachineOperand&) const, void (llvm::AMDGPUInstructionSelector::* const*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const)
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Source
395
3.64k
          CustomRenderers(CustomRenderers) {
396
3.64k
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65.5k
      for (size_t I = 0; I < NumTypeObjects; 
++I61.8k
)
398
61.8k
        TypeIDMap[TypeObjects[I]] = I;
399
3.64k
    }
ARMInstructionSelector.cpp:llvm::InstructionSelector::ISelInfoTy<llvm::PredicateBitsetImpl<70ul>, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::ARMInstructionSelector::*)(llvm::MachineOperand&) const, void ((anonymous namespace)::ARMInstructionSelector::*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const>::ISelInfoTy(llvm::LLT const*, unsigned long, llvm::PredicateBitsetImpl<70ul> const*, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::ARMInstructionSelector::* const*)(llvm::MachineOperand&) const, void ((anonymous namespace)::ARMInstructionSelector::* const*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const)
Line
Count
Source
395
7.46k
          CustomRenderers(CustomRenderers) {
396
7.46k
397
104k
      for (size_t I = 0; I < NumTypeObjects; 
++I96.9k
)
398
96.9k
        TypeIDMap[TypeObjects[I]] = I;
399
7.46k
    }
MipsInstructionSelector.cpp:llvm::InstructionSelector::ISelInfoTy<llvm::PredicateBitsetImpl<42ul>, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::MipsInstructionSelector::*)(llvm::MachineOperand&) const, void ((anonymous namespace)::MipsInstructionSelector::*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const>::ISelInfoTy(llvm::LLT const*, unsigned long, llvm::PredicateBitsetImpl<42ul> const*, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::MipsInstructionSelector::* const*)(llvm::MachineOperand&) const, void ((anonymous namespace)::MipsInstructionSelector::* const*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const)
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          CustomRenderers(CustomRenderers) {
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      for (size_t I = 0; I < NumTypeObjects; 
++I101k
)
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        TypeIDMap[TypeObjects[I]] = I;
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    }
X86InstructionSelector.cpp:llvm::InstructionSelector::ISelInfoTy<llvm::PredicateBitsetImpl<114ul>, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::X86InstructionSelector::*)(llvm::MachineOperand&) const, void ((anonymous namespace)::X86InstructionSelector::*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const>::ISelInfoTy(llvm::LLT const*, unsigned long, llvm::PredicateBitsetImpl<114ul> const*, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::X86InstructionSelector::* const*)(llvm::MachineOperand&) const, void ((anonymous namespace)::X86InstructionSelector::* const*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const)
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          CustomRenderers(CustomRenderers) {
396
15.2k
397
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      for (size_t I = 0; I < NumTypeObjects; 
++I381k
)
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        TypeIDMap[TypeObjects[I]] = I;
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    }
400
    const LLT *TypeObjects;
401
    const PredicateBitset *FeatureBitsets;
402
    const ComplexMatcherMemFn *ComplexPredicates;
403
    const CustomRendererFn *CustomRenderers;
404
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    SmallDenseMap<LLT, unsigned, 64> TypeIDMap;
406
  };
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protected:
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  InstructionSelector();
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  /// Execute a given matcher table and return true if the match was successful
412
  /// and false otherwise.
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  template <class TgtInstructionSelector, class PredicateBitset,
414
            class ComplexMatcherMemFn, class CustomRendererFn>
415
  bool executeMatchTable(
416
      TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
417
      const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn>
418
          &ISelInfo,
419
      const int64_t *MatchTable, const TargetInstrInfo &TII,
420
      MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
421
      const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
422
      CodeGenCoverage &CoverageInfo) const;
423
424
0
  virtual const int64_t *getMatchTable() const {
425
0
    llvm_unreachable("Should have been overridden by tablegen if used");
426
0
  }
427
428
0
  virtual bool testImmPredicate_I64(unsigned, int64_t) const {
429
0
    llvm_unreachable(
430
0
        "Subclasses must override this with a tablegen-erated function");
431
0
  }
432
0
  virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
433
0
    llvm_unreachable(
434
0
        "Subclasses must override this with a tablegen-erated function");
435
0
  }
436
0
  virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
437
0
    llvm_unreachable(
438
0
        "Subclasses must override this with a tablegen-erated function");
439
0
  }
440
0
  virtual bool testMIPredicate_MI(unsigned, const MachineInstr &) const {
441
0
    llvm_unreachable(
442
0
        "Subclasses must override this with a tablegen-erated function");
443
0
  }
444
445
  /// Constrain a register operand of an instruction \p I to a specified
446
  /// register class. This could involve inserting COPYs before (for uses) or
447
  /// after (for defs) and may replace the operand of \p I.
448
  /// \returns whether operand regclass constraining succeeded.
449
  bool constrainOperandRegToRegClass(MachineInstr &I, unsigned OpIdx,
450
                                     const TargetRegisterClass &RC,
451
                                     const TargetInstrInfo &TII,
452
                                     const TargetRegisterInfo &TRI,
453
                                     const RegisterBankInfo &RBI) const;
454
455
  bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
456
                         const MachineRegisterInfo &MRI) const;
457
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  /// Return true if the specified operand is a G_GEP with a G_CONSTANT on the
459
  /// right-hand side. GlobalISel's separation of pointer and integer types
460
  /// means that we don't need to worry about G_OR with equivalent semantics.
461
  bool isBaseWithConstantOffset(const MachineOperand &Root,
462
                                const MachineRegisterInfo &MRI) const;
463
464
  /// Return true if MI can obviously be folded into IntoMI.
465
  /// MI and IntoMI do not need to be in the same basic blocks, but MI must
466
  /// preceed IntoMI.
467
  bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const;
468
};
469
470
} // end namespace llvm
471
472
#endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H