Coverage Report

Created: 2018-07-19 03:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
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//===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file declares the API for the instruction selector.
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/// This class is responsible for selecting machine instructions.
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/// It's implemented by the target. It's used by the InstructionSelect pass.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
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#define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/CodeGenCoverage.h"
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#include "llvm/Support/LowLevelTypeImpl.h"
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#include <bitset>
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#include <cstddef>
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#include <cstdint>
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#include <functional>
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#include <initializer_list>
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#include <vector>
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namespace llvm {
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class APInt;
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class APFloat;
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class MachineInstr;
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class MachineInstrBuilder;
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class MachineFunction;
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class MachineOperand;
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class MachineRegisterInfo;
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class RegisterBankInfo;
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class TargetInstrInfo;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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/// Container class for CodeGen predicate results.
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/// This is convenient because std::bitset does not have a constructor
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/// with an initializer list of set bits.
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///
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/// Each InstructionSelector subclass should define a PredicateBitset class
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/// with:
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///   const unsigned MAX_SUBTARGET_PREDICATES = 192;
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///   using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
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/// and updating the constant to suit the target. Tablegen provides a suitable
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/// definition for the predicates in use in <Target>GenGlobalISel.inc when
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/// GET_GLOBALISEL_PREDICATE_BITSET is defined.
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template <std::size_t MaxPredicates>
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class PredicateBitsetImpl : public std::bitset<MaxPredicates> {
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public:
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  // Cannot inherit constructors because it's not supported by VC++..
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4.98M
  PredicateBitsetImpl() = default;
llvm::PredicateBitsetImpl<15ul>::PredicateBitsetImpl()
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4.55M
  PredicateBitsetImpl() = default;
llvm::PredicateBitsetImpl<32ul>::PredicateBitsetImpl()
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95.5k
  PredicateBitsetImpl() = default;
llvm::PredicateBitsetImpl<64ul>::PredicateBitsetImpl()
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Source
60
104k
  PredicateBitsetImpl() = default;
llvm::PredicateBitsetImpl<41ul>::PredicateBitsetImpl()
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60
110k
  PredicateBitsetImpl() = default;
llvm::PredicateBitsetImpl<114ul>::PredicateBitsetImpl()
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60
117k
  PredicateBitsetImpl() = default;
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  PredicateBitsetImpl(const std::bitset<MaxPredicates> &B)
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4.44M
      : std::bitset<MaxPredicates>(B) {}
llvm::PredicateBitsetImpl<15ul>::PredicateBitsetImpl(std::__1::bitset<15ul> const&)
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63
4.44M
      : std::bitset<MaxPredicates>(B) {}
llvm::PredicateBitsetImpl<32ul>::PredicateBitsetImpl(std::__1::bitset<32ul> const&)
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Source
63
53
      : std::bitset<MaxPredicates>(B) {}
llvm::PredicateBitsetImpl<64ul>::PredicateBitsetImpl(std::__1::bitset<64ul> const&)
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63
706
      : std::bitset<MaxPredicates>(B) {}
llvm::PredicateBitsetImpl<41ul>::PredicateBitsetImpl(std::__1::bitset<41ul> const&)
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63
13
      : std::bitset<MaxPredicates>(B) {}
llvm::PredicateBitsetImpl<114ul>::PredicateBitsetImpl(std::__1::bitset<114ul> const&)
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63
1.91k
      : std::bitset<MaxPredicates>(B) {}
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18.3M
  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
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18.3M
    for (auto I : Init)
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40.1M
      std::bitset<MaxPredicates>::set(I);
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18.3M
  }
llvm::PredicateBitsetImpl<15ul>::PredicateBitsetImpl(std::initializer_list<unsigned int>)
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Source
65
1.18M
  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
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1.18M
    for (auto I : Init)
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1.36M
      std::bitset<MaxPredicates>::set(I);
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1.18M
  }
llvm::PredicateBitsetImpl<32ul>::PredicateBitsetImpl(std::initializer_list<unsigned int>)
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65
545k
  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
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545k
    for (auto I : Init)
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1.00M
      std::bitset<MaxPredicates>::set(I);
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545k
  }
llvm::PredicateBitsetImpl<64ul>::PredicateBitsetImpl(std::initializer_list<unsigned int>)
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65
5.09M
  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
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5.09M
    for (auto I : Init)
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10.2M
      std::bitset<MaxPredicates>::set(I);
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5.09M
  }
llvm::PredicateBitsetImpl<41ul>::PredicateBitsetImpl(std::initializer_list<unsigned int>)
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65
5.73M
  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
66
5.73M
    for (auto I : Init)
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19.1M
      std::bitset<MaxPredicates>::set(I);
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5.73M
  }
llvm::PredicateBitsetImpl<114ul>::PredicateBitsetImpl(std::initializer_list<unsigned int>)
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65
5.75M
  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
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5.75M
    for (auto I : Init)
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8.39M
      std::bitset<MaxPredicates>::set(I);
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5.75M
  }
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};
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enum {
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  /// Begin a try-block to attempt a match and jump to OnFail if it is
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  /// unsuccessful.
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  /// - OnFail - The MatchTable entry at which to resume if the match fails.
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  ///
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  /// FIXME: This ought to take an argument indicating the number of try-blocks
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  ///        to exit on failure. It's usually one but the last match attempt of
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  ///        a block will need more. The (implemented) alternative is to tack a
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  ///        GIM_Reject on the end of each try-block which is simpler but
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  ///        requires an extra opcode and iteration in the interpreter on each
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  ///        failed match.
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  GIM_Try,
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  /// Switch over the opcode on the specified instruction
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  /// - InsnID - Instruction ID
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  /// - LowerBound - numerically minimum opcode supported
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  /// - UpperBound - numerically maximum + 1 opcode supported
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  /// - Default - failure jump target
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  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
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  GIM_SwitchOpcode,
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  /// Switch over the LLT on the specified instruction operand
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - LowerBound - numerically minimum Type ID supported
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  /// - UpperBound - numerically maximum + 1 Type ID supported
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  /// - Default - failure jump target
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  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
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  GIM_SwitchType,
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  /// Record the specified instruction
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  /// - NewInsnID - Instruction ID to define
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  GIM_RecordInsn,
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  /// Check the feature bits
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  /// - Expected features
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  GIM_CheckFeatures,
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  /// Check the opcode on the specified instruction
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  /// - InsnID - Instruction ID
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  /// - Expected opcode
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  GIM_CheckOpcode,
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  /// Check the instruction has the right number of operands
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  /// - InsnID - Instruction ID
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  /// - Expected number of operands
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  GIM_CheckNumOperands,
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  /// Check an immediate predicate on the specified instruction
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  /// - InsnID - Instruction ID
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  /// - The predicate to test
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  GIM_CheckI64ImmPredicate,
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  /// Check an immediate predicate on the specified instruction via an APInt.
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  /// - InsnID - Instruction ID
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  /// - The predicate to test
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  GIM_CheckAPIntImmPredicate,
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  /// Check a floating point immediate predicate on the specified instruction.
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  /// - InsnID - Instruction ID
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  /// - The predicate to test
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  GIM_CheckAPFloatImmPredicate,
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  /// Check a memory operation has the specified atomic ordering.
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  /// - InsnID - Instruction ID
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  /// - Ordering - The AtomicOrdering value
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  GIM_CheckAtomicOrdering,
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  GIM_CheckAtomicOrderingOrStrongerThan,
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  GIM_CheckAtomicOrderingWeakerThan,
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  /// Check the size of the memory access for the given machine memory operand.
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  /// - InsnID - Instruction ID
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  /// - MMOIdx - MMO index
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  /// - Size - The size in bytes of the memory access
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  GIM_CheckMemorySizeEqualTo,
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  /// Check the size of the memory access for the given machine memory operand
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  /// against the size of an operand.
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  /// - InsnID - Instruction ID
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  /// - MMOIdx - MMO index
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  /// - OpIdx - The operand index to compare the MMO against
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  GIM_CheckMemorySizeEqualToLLT,
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  GIM_CheckMemorySizeLessThanLLT,
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  GIM_CheckMemorySizeGreaterThanLLT,
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  /// Check a generic C++ instruction predicate
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  /// - InsnID - Instruction ID
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  /// - PredicateID - The ID of the predicate function to call
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  GIM_CheckCxxInsnPredicate,
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  /// Check the type for the specified operand
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - Expected type
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  GIM_CheckType,
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  /// Check the type of a pointer to any address space.
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - SizeInBits - The size of the pointer value in bits.
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  GIM_CheckPointerToAny,
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  /// Check the register bank for the specified operand
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - Expected register bank (specified as a register class)
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  GIM_CheckRegBankForClass,
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  /// Check the operand matches a complex predicate
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - RendererID - The renderer to hold the result
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  /// - Complex predicate ID
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  GIM_CheckComplexPattern,
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  /// Check the operand is a specific integer
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - Expected integer
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  GIM_CheckConstantInt,
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  /// Check the operand is a specific literal integer (i.e. MO.isImm() or
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  /// MO.isCImm() is true).
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - Expected integer
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  GIM_CheckLiteralInt,
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  /// Check the operand is a specific intrinsic ID
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - Expected Intrinsic ID
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  GIM_CheckIntrinsicID,
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  /// Check the specified operand is an MBB
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  GIM_CheckIsMBB,
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  /// Check if the specified operand is safe to fold into the current
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  /// instruction.
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  /// - InsnID - Instruction ID
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  GIM_CheckIsSafeToFold,
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  /// Check the specified operands are identical.
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  /// - InsnID - Instruction ID
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  /// - OpIdx - Operand index
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  /// - OtherInsnID - Other instruction ID
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  /// - OtherOpIdx - Other operand index
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  GIM_CheckIsSameOperand,
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  /// Fail the current try-block, or completely fail to match if there is no
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  /// current try-block.
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  GIM_Reject,
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  //=== Renderers ===
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  /// Mutate an instruction
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  /// - NewInsnID - Instruction ID to define
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  /// - OldInsnID - Instruction ID to mutate
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  /// - NewOpcode - The new opcode to use
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  GIR_MutateOpcode,
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  /// Build a new instruction
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  /// - InsnID - Instruction ID to define
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  /// - Opcode - The new opcode to use
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  GIR_BuildMI,
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  /// Copy an operand to the specified instruction
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  /// - NewInsnID - Instruction ID to modify
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  /// - OldInsnID - Instruction ID to copy from
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  /// - OpIdx - The operand to copy
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  GIR_Copy,
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  /// Copy an operand to the specified instruction or add a zero register if the
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  /// operand is a zero immediate.
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  /// - NewInsnID - Instruction ID to modify
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  /// - OldInsnID - Instruction ID to copy from
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  /// - OpIdx - The operand to copy
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  /// - ZeroReg - The zero register to use
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  GIR_CopyOrAddZeroReg,
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  /// Copy an operand to the specified instruction
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  /// - NewInsnID - Instruction ID to modify
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  /// - OldInsnID - Instruction ID to copy from
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  /// - OpIdx - The operand to copy
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  /// - SubRegIdx - The subregister to copy
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  GIR_CopySubReg,
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  /// Add an implicit register def to the specified instruction
250
  /// - InsnID - Instruction ID to modify
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  /// - RegNum - The register to add
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  GIR_AddImplicitDef,
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  /// Add an implicit register use to the specified instruction
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  /// - InsnID - Instruction ID to modify
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  /// - RegNum - The register to add
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  GIR_AddImplicitUse,
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  /// Add an register to the specified instruction
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  /// - InsnID - Instruction ID to modify
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  /// - RegNum - The register to add
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  GIR_AddRegister,
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  /// Add a temporary register to the specified instruction
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  /// - InsnID - Instruction ID to modify
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  /// - TempRegID - The temporary register ID to add
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  /// - TempRegFlags - The register flags to set
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  GIR_AddTempRegister,
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  /// Add an immediate to the specified instruction
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  /// - InsnID - Instruction ID to modify
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  /// - Imm - The immediate to add
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  GIR_AddImm,
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  /// Render complex operands to the specified instruction
273
  /// - InsnID - Instruction ID to modify
274
  /// - RendererID - The renderer to call
275
  GIR_ComplexRenderer,
276
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  /// Render sub-operands of complex operands to the specified instruction
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  /// - InsnID - Instruction ID to modify
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  /// - RendererID - The renderer to call
280
  /// - RenderOpID - The suboperand to render.
281
  GIR_ComplexSubOperandRenderer,
282
  /// Render operands to the specified instruction using a custom function
283
  /// - InsnID - Instruction ID to modify
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  /// - OldInsnID - Instruction ID to get the matched operand from
285
  /// - RendererFnID - Custom renderer function to call
286
  GIR_CustomRenderer,
287
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  /// Render a G_CONSTANT operator as a sign-extended immediate.
289
  /// - NewInsnID - Instruction ID to modify
290
  /// - OldInsnID - Instruction ID to copy from
291
  /// The operand index is implicitly 1.
292
  GIR_CopyConstantAsSImm,
293
294
  /// Render a G_FCONSTANT operator as a sign-extended immediate.
295
  /// - NewInsnID - Instruction ID to modify
296
  /// - OldInsnID - Instruction ID to copy from
297
  /// The operand index is implicitly 1.
298
  GIR_CopyFConstantAsFPImm,
299
300
  /// Constrain an instruction operand to a register class.
301
  /// - InsnID - Instruction ID to modify
302
  /// - OpIdx - Operand index
303
  /// - RCEnum - Register class enumeration value
304
  GIR_ConstrainOperandRC,
305
306
  /// Constrain an instructions operands according to the instruction
307
  /// description.
308
  /// - InsnID - Instruction ID to modify
309
  GIR_ConstrainSelectedInstOperands,
310
311
  /// Merge all memory operands into instruction.
312
  /// - InsnID - Instruction ID to modify
313
  /// - MergeInsnID... - One or more Instruction ID to merge into the result.
314
  /// - GIU_MergeMemOperands_EndOfList - Terminates the list of instructions to
315
  ///                                    merge.
316
  GIR_MergeMemOperands,
317
318
  /// Erase from parent.
319
  /// - InsnID - Instruction ID to erase
320
  GIR_EraseFromParent,
321
322
  /// Create a new temporary register that's not constrained.
323
  /// - TempRegID - The temporary register ID to initialize.
324
  /// - Expected type
325
  GIR_MakeTempReg,
326
327
  /// A successful emission
328
  GIR_Done,
329
330
  /// Increment the rule coverage counter.
331
  /// - RuleID - The ID of the rule that was covered.
332
  GIR_Coverage,
333
334
  /// Keeping track of the number of the GI opcodes. Must be the last entry.
335
  GIU_NumOpcodes,
336
};
337
338
enum {
339
  /// Indicates the end of the variable-length MergeInsnID list in a
340
  /// GIR_MergeMemOperands opcode.
341
  GIU_MergeMemOperands_EndOfList = -1,
342
};
343
344
/// Provides the logic to select generic machine instructions.
345
class InstructionSelector {
346
public:
347
27.7k
  virtual ~InstructionSelector() = default;
348
349
  /// Select the (possibly generic) instruction \p I to only use target-specific
350
  /// opcodes. It is OK to insert multiple instructions, but they cannot be
351
  /// generic pre-isel instructions.
352
  ///
353
  /// \returns whether selection succeeded.
354
  /// \pre  I.getParent() && I.getParent()->getParent()
355
  /// \post
356
  ///   if returns true:
357
  ///     for I in all mutated/inserted instructions:
358
  ///       !isPreISelGenericOpcode(I.getOpcode())
359
  virtual bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const = 0;
360
361
protected:
362
  using ComplexRendererFns =
363
      Optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
364
  using RecordedMIVector = SmallVector<MachineInstr *, 4>;
365
  using NewMIVector = SmallVector<MachineInstrBuilder, 4>;
366
367
  struct MatcherState {
368
    std::vector<ComplexRendererFns::value_type> Renderers;
369
    RecordedMIVector MIs;
370
    DenseMap<unsigned, unsigned> TempRegisters;
371
372
    MatcherState(unsigned MaxRenderers);
373
  };
374
375
public:
376
  template <class PredicateBitset, class ComplexMatcherMemFn,
377
            class CustomRendererFn>
378
  struct ISelInfoTy {
379
    ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
380
               const PredicateBitset *FeatureBitsets,
381
               const ComplexMatcherMemFn *ComplexPredicates,
382
               const CustomRendererFn *CustomRenderers)
383
        : TypeObjects(TypeObjects),
384
          FeatureBitsets(FeatureBitsets),
385
          ComplexPredicates(ComplexPredicates),
386
39.3k
          CustomRenderers(CustomRenderers) {
387
39.3k
388
616k
      for (size_t I = 0; I < NumTypeObjects; 
++I576k
)
389
576k
        TypeIDMap[TypeObjects[I]] = I;
390
39.3k
    }
AArch64InstructionSelector.cpp:llvm::InstructionSelector::ISelInfoTy<llvm::PredicateBitsetImpl<15ul>, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::AArch64InstructionSelector::*)(llvm::MachineOperand&) const, void ((anonymous namespace)::AArch64InstructionSelector::*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const>::ISelInfoTy(llvm::LLT const*, unsigned long, llvm::PredicateBitsetImpl<15ul> const*, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::AArch64InstructionSelector::* const*)(llvm::MachineOperand&) const, void ((anonymous namespace)::AArch64InstructionSelector::* const*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const)
Line
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Source
386
8.44k
          CustomRenderers(CustomRenderers) {
387
8.44k
388
101k
      for (size_t I = 0; I < NumTypeObjects; 
++I92.8k
)
389
92.8k
        TypeIDMap[TypeObjects[I]] = I;
390
8.44k
    }
llvm::InstructionSelector::ISelInfoTy<llvm::PredicateBitsetImpl<32ul>, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > (llvm::AMDGPUInstructionSelector::*)(llvm::MachineOperand&) const, void (llvm::AMDGPUInstructionSelector::*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const>::ISelInfoTy(llvm::LLT const*, unsigned long, llvm::PredicateBitsetImpl<32ul> const*, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > (llvm::AMDGPUInstructionSelector::* const*)(llvm::MachineOperand&) const, void (llvm::AMDGPUInstructionSelector::* const*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const)
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386
2.28k
          CustomRenderers(CustomRenderers) {
387
2.28k
388
27.3k
      for (size_t I = 0; I < NumTypeObjects; 
++I25.0k
)
389
25.0k
        TypeIDMap[TypeObjects[I]] = I;
390
2.28k
    }
ARMInstructionSelector.cpp:llvm::InstructionSelector::ISelInfoTy<llvm::PredicateBitsetImpl<64ul>, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::ARMInstructionSelector::*)(llvm::MachineOperand&) const, void ((anonymous namespace)::ARMInstructionSelector::*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const>::ISelInfoTy(llvm::LLT const*, unsigned long, llvm::PredicateBitsetImpl<64ul> const*, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::ARMInstructionSelector::* const*)(llvm::MachineOperand&) const, void ((anonymous namespace)::ARMInstructionSelector::* const*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const)
Line
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Source
386
6.58k
          CustomRenderers(CustomRenderers) {
387
6.58k
388
72.4k
      for (size_t I = 0; I < NumTypeObjects; 
++I65.8k
)
389
65.8k
        TypeIDMap[TypeObjects[I]] = I;
390
6.58k
    }
MipsInstructionSelector.cpp:llvm::InstructionSelector::ISelInfoTy<llvm::PredicateBitsetImpl<41ul>, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::MipsInstructionSelector::*)(llvm::MachineOperand&) const, void ((anonymous namespace)::MipsInstructionSelector::*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const>::ISelInfoTy(llvm::LLT const*, unsigned long, llvm::PredicateBitsetImpl<41ul> const*, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::MipsInstructionSelector::* const*)(llvm::MachineOperand&) const, void ((anonymous namespace)::MipsInstructionSelector::* const*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const)
Line
Count
Source
386
9.89k
          CustomRenderers(CustomRenderers) {
387
9.89k
388
98.9k
      for (size_t I = 0; I < NumTypeObjects; 
++I89.0k
)
389
89.0k
        TypeIDMap[TypeObjects[I]] = I;
390
9.89k
    }
X86InstructionSelector.cpp:llvm::InstructionSelector::ISelInfoTy<llvm::PredicateBitsetImpl<114ul>, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::X86InstructionSelector::*)(llvm::MachineOperand&) const, void ((anonymous namespace)::X86InstructionSelector::*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const>::ISelInfoTy(llvm::LLT const*, unsigned long, llvm::PredicateBitsetImpl<114ul> const*, llvm::Optional<llvm::SmallVector<std::__1::function<void (llvm::MachineInstrBuilder&)>, 4u> > ((anonymous namespace)::X86InstructionSelector::* const*)(llvm::MachineOperand&) const, void ((anonymous namespace)::X86InstructionSelector::* const*)(llvm::MachineInstrBuilder&, llvm::MachineInstr const&) const)
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          CustomRenderers(CustomRenderers) {
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      for (size_t I = 0; I < NumTypeObjects; 
++I304k
)
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        TypeIDMap[TypeObjects[I]] = I;
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    }
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    const LLT *TypeObjects;
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    const PredicateBitset *FeatureBitsets;
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    const ComplexMatcherMemFn *ComplexPredicates;
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    const CustomRendererFn *CustomRenderers;
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    SmallDenseMap<LLT, unsigned, 64> TypeIDMap;
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  };
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protected:
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  InstructionSelector();
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  /// Execute a given matcher table and return true if the match was successful
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  /// and false otherwise.
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  template <class TgtInstructionSelector, class PredicateBitset,
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            class ComplexMatcherMemFn, class CustomRendererFn>
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  bool executeMatchTable(
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      TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
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      const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn>
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          &ISelInfo,
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      const int64_t *MatchTable, const TargetInstrInfo &TII,
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      MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
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      const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
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      CodeGenCoverage &CoverageInfo) const;
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0
  virtual const int64_t *getMatchTable() const {
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0
    llvm_unreachable("Should have been overridden by tablegen if used");
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0
  }
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  virtual bool testImmPredicate_I64(unsigned, int64_t) const {
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    llvm_unreachable(
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0
        "Subclasses must override this with a tablegen-erated function");
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0
  }
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  virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
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0
    llvm_unreachable(
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0
        "Subclasses must override this with a tablegen-erated function");
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0
  }
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0
  virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
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0
    llvm_unreachable(
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0
        "Subclasses must override this with a tablegen-erated function");
430
0
  }
431
0
  virtual bool testMIPredicate_MI(unsigned, const MachineInstr &) const {
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0
    llvm_unreachable(
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0
        "Subclasses must override this with a tablegen-erated function");
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0
  }
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  /// Constrain a register operand of an instruction \p I to a specified
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  /// register class. This could involve inserting COPYs before (for uses) or
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  /// after (for defs) and may replace the operand of \p I.
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  /// \returns whether operand regclass constraining succeeded.
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  bool constrainOperandRegToRegClass(MachineInstr &I, unsigned OpIdx,
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                                     const TargetRegisterClass &RC,
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                                     const TargetInstrInfo &TII,
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                                     const TargetRegisterInfo &TRI,
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                                     const RegisterBankInfo &RBI) const;
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  bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
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                         const MachineRegisterInfo &MRI) const;
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  /// Return true if the specified operand is a G_GEP with a G_CONSTANT on the
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  /// right-hand side. GlobalISel's separation of pointer and integer types
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  /// means that we don't need to worry about G_OR with equivalent semantics.
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  bool isBaseWithConstantOffset(const MachineOperand &Root,
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                                const MachineRegisterInfo &MRI) const;
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  /// Return true if MI can obviously be folded into IntoMI.
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  /// MI and IntoMI do not need to be in the same basic blocks, but MI must
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  /// preceed IntoMI.
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  bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const;
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H