Coverage Report

Created: 2018-07-19 03:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
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//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the MachineIRBuilder class.
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/// This is a helper class to build MachineInstr.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
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#define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
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#include "llvm/CodeGen/GlobalISel/Types.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DebugLoc.h"
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namespace llvm {
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// Forward declarations.
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class MachineFunction;
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class MachineInstr;
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class TargetInstrInfo;
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/// Class which stores all the state required in a MachineIRBuilder.
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/// Since MachineIRBuilders will only store state in this object, it allows
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/// to transfer BuilderState between different kinds of MachineIRBuilders.
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struct MachineIRBuilderState {
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  /// MachineFunction under construction.
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  MachineFunction *MF;
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  /// Information used to access the description of the opcodes.
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  const TargetInstrInfo *TII;
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  /// Information used to verify types are consistent and to create virtual registers.
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  MachineRegisterInfo *MRI;
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  /// Debug location to be set to any instruction we create.
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  DebugLoc DL;
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  /// \name Fields describing the insertion point.
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  /// @{
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  MachineBasicBlock *MBB;
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  MachineBasicBlock::iterator II;
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  /// @}
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  std::function<void(MachineInstr *)> InsertedInstr;
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};
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/// Helper class to build MachineInstr.
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/// It keeps internally the insertion point and debug location for all
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/// the new instructions we want to create.
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/// This information can be modify via the related setters.
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class MachineIRBuilderBase {
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  MachineIRBuilderState State;
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23.2M
  const TargetInstrInfo &getTII() {
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23.2M
    assert(State.TII && "TargetInstrInfo is not set");
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23.2M
    return *State.TII;
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23.2M
  }
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  void validateTruncExt(unsigned Dst, unsigned Src, bool IsExtend);
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protected:
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1.87M
  unsigned getDestFromArg(unsigned Reg) { return Reg; }
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861k
  unsigned getDestFromArg(LLT Ty) {
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861k
    return getMF().getRegInfo().createGenericVirtualRegister(Ty);
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861k
  }
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0
  unsigned getDestFromArg(const TargetRegisterClass *RC) {
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0
    return getMF().getRegInfo().createVirtualRegister(RC);
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0
  }
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1.56M
  void addUseFromArg(MachineInstrBuilder &MIB, unsigned Reg) {
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1.56M
    MIB.addUse(Reg);
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  }
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71.9k
  void addUseFromArg(MachineInstrBuilder &MIB, const MachineInstrBuilder &UseMIB) {
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    MIB.addUse(UseMIB->getOperand(0).getReg());
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  }
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2.10M
  void addUsesFromArgs(MachineInstrBuilder &MIB) { }
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  template<typename UseArgTy, typename ... UseArgsTy>
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<unsigned int&, unsigned int&, unsigned int&>(llvm::MachineInstrBuilder&, unsigned int&&&, unsigned int&&&, unsigned int&&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<unsigned int&, unsigned int&>(llvm::MachineInstrBuilder&, unsigned int&&&, unsigned int&&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<unsigned int&>(llvm::MachineInstrBuilder&, unsigned int&&&)
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1.12M
  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<llvm::MachineInstrBuilder&, unsigned int&>(llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&&&, unsigned int&&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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1
    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&>(llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&&&, llvm::MachineInstrBuilder&&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<llvm::MachineInstrBuilder&>(llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<unsigned int>(llvm::MachineInstrBuilder&, unsigned int&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
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  unsigned getRegFromArg(unsigned Reg) { return Reg; }
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  unsigned getRegFromArg(const MachineInstrBuilder &MIB) {
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    return MIB->getOperand(0).getReg();
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  }
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  void validateBinaryOp(unsigned Res, unsigned Op0, unsigned Op1);
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public:
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  /// Some constructors for easy use.
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  MachineIRBuilderBase() = default;
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  MachineIRBuilderBase(MachineFunction &MF) { setMF(MF); }
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  MachineIRBuilderBase(MachineInstr &MI) : MachineIRBuilderBase(*MI.getMF()) {
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    setInstr(MI);
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  }
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  MachineIRBuilderBase(const MachineIRBuilderState &BState) : State(BState) {}
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  /// Getter for the function we currently build.
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  MachineFunction &getMF() {
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    assert(State.MF && "MachineFunction is not set");
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    return *State.MF;
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  }
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  /// Getter for DebugLoc
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  const DebugLoc &getDL() { return State.DL; }
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  /// Getter for MRI
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  MachineRegisterInfo *getMRI() { return State.MRI; }
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  /// Getter for the State
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  MachineIRBuilderState &getState() { return State; }
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  /// Getter for the basic block we currently build.
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  MachineBasicBlock &getMBB() {
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    assert(State.MBB && "MachineBasicBlock is not set");
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    return *State.MBB;
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  }
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  /// Current insertion point for new instructions.
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  MachineBasicBlock::iterator getInsertPt() { return State.II; }
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  /// Set the insertion point before the specified position.
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  /// \pre MBB must be in getMF().
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  /// \pre II must be a valid iterator in MBB.
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  void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II);
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  /// @}
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  /// \name Setters for the insertion point.
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  /// @{
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  /// Set the MachineFunction where to build instructions.
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  void setMF(MachineFunction &);
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  /// Set the insertion point to the  end of \p MBB.
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  /// \pre \p MBB must be contained by getMF().
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  void setMBB(MachineBasicBlock &MBB);
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  /// Set the insertion point to before MI.
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  /// \pre MI must be in getMF().
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  void setInstr(MachineInstr &MI);
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  /// @}
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  /// \name Control where instructions we create are recorded (typically for
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  /// visiting again later during legalization).
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  /// @{
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  void recordInsertion(MachineInstr *InsertedInstr) const;
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  void recordInsertions(std::function<void(MachineInstr *)> InsertedInstr);
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  void stopRecordingInsertions();
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  /// @}
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  /// Set the debug location to \p DL for all the next build instructions.
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  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
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  /// Get the current instruction's debug location.
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0
  DebugLoc getDebugLoc() { return State.DL; }
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  /// Build and insert <empty> = \p Opcode <empty>.
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  /// The insertion point is the one set by the last call of either
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  /// setBasicBlock or setMI.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  MachineInstrBuilder buildInstr(unsigned Opcode);
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  /// Build but don't insert <empty> = \p Opcode <empty>.
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  ///
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  /// \pre setMF, setBasicBlock or setMI  must have been called.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
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  /// Insert an existing instruction at the insertion point.
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  MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
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  /// Build and insert a DBG_VALUE instruction expressing the fact that the
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  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
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  MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
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                                          const MDNode *Expr);
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  /// Build and insert a DBG_VALUE instruction expressing the fact that the
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  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
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  /// Expr).
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  MachineInstrBuilder buildIndirectDbgValue(unsigned Reg,
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                                            const MDNode *Variable,
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                                            const MDNode *Expr);
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  /// Build and insert a DBG_VALUE instruction expressing the fact that the
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  /// associated \p Variable lives in the stack slot specified by \p FI
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  /// (suitably modified by \p Expr).
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  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
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                                      const MDNode *Expr);
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  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
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  /// given by \p C (suitably modified by \p Expr).
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  MachineInstrBuilder buildConstDbgValue(const Constant &C,
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                                         const MDNode *Variable,
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                                         const MDNode *Expr);
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  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
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  ///
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  /// G_FRAME_INDEX materializes the address of an alloca value or other
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  /// stack-based object.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res must be a generic virtual register with pointer type.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx);
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  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
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  ///
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  /// G_GLOBAL_VALUE materializes the address of the specified global
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  /// into \p Res.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res must be a generic virtual register with pointer type
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  ///      in the same address space as \p GV.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV);
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  /// Build and insert \p Res = G_GEP \p Op0, \p Op1
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  ///
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  /// G_GEP adds \p Op1 bytes to the pointer specified by \p Op0,
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  /// storing the resulting pointer in \p Res.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
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  ///      type.
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  /// \pre \p Op1 must be a generic virtual register with scalar type.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0,
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                               unsigned Op1);
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  /// Materialize and insert \p Res = G_GEP \p Op0, (G_CONSTANT \p Value)
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  ///
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  /// G_GEP adds \p Value bytes to the pointer specified by \p Op0,
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  /// storing the resulting pointer in \p Res. If \p Value is zero then no
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  /// G_GEP or G_CONSTANT will be created and \pre Op0 will be assigned to
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  /// \p Res.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Op0 must be a generic virtual register with pointer type.
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  /// \pre \p ValueTy must be a scalar type.
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  /// \pre \p Res must be 0. This is to detect confusion between
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  ///      materializeGEP() and buildGEP().
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  /// \post \p Res will either be a new generic virtual register of the same
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  ///       type as \p Op0 or \p Op0 itself.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  Optional<MachineInstrBuilder> materializeGEP(unsigned &Res, unsigned Op0,
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                                               const LLT &ValueTy,
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                                               uint64_t Value);
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  /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
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  ///
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  /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
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  /// pointer properties. This has the effect of rounding the address *down* to
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  /// a specified alignment in bits.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
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  ///      type.
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  /// \pre \p NumBits must be an integer representing the number of low bits to
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  ///      be cleared in \p Op0.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0,
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                                   uint32_t NumBits);
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  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
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  /// \p Op1, \p CarryIn
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  ///
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  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
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  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
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  /// arithmetic.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
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  ///      with the same scalar type.
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  /// \pre \p CarryOut and \p CarryIn must be generic virtual
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  ///      registers with the same scalar type (typically s1)
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  ///
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  /// \return The newly created instruction.
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  MachineInstrBuilder buildUAdde(unsigned Res, unsigned CarryOut, unsigned Op0,
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                                 unsigned Op1, unsigned CarryIn);
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  /// Build and insert \p Res = G_ANYEXT \p Op0
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  ///
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  /// G_ANYEXT produces a register of the specified width, with bits 0 to
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  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
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  /// (i.e. this is neither zero nor sign-extension). For a vector register,
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  /// each element is extended individually.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be smaller than \p Res
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  ///
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  /// \return The newly created instruction.
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  MachineInstrBuilder buildAnyExt(unsigned Res, unsigned Op);
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  template <typename DstType, typename ArgType>
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36.0k
  MachineInstrBuilder buildAnyExt(DstType &&Res, ArgType &&Arg) {
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36.0k
    return buildAnyExt(getDestFromArg(Res), getRegFromArg(Arg));
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36.0k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildAnyExt<llvm::LLT, unsigned int&>(llvm::LLT&&, unsigned int&&&)
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15.6k
  MachineInstrBuilder buildAnyExt(DstType &&Res, ArgType &&Arg) {
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15.6k
    return buildAnyExt(getDestFromArg(Res), getRegFromArg(Arg));
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15.6k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildAnyExt<llvm::LLT&, unsigned int&>(llvm::LLT&&&, unsigned int&&&)
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20.3k
  MachineInstrBuilder buildAnyExt(DstType &&Res, ArgType &&Arg) {
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20.3k
    return buildAnyExt(getDestFromArg(Res), getRegFromArg(Arg));
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20.3k
  }
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  /// Build and insert \p Res = G_SEXT \p Op
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  ///
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  /// G_SEXT produces a register of the specified width, with bits 0 to
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  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
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  /// high bit of \p Op (i.e. 2s-complement sign extended).
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be smaller than \p Res
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  ///
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  /// \return The newly created instruction.
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  template <typename DstType, typename ArgType>
336
  MachineInstrBuilder buildSExt(DstType &&Res, ArgType &&Arg) {
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    return buildSExt(getDestFromArg(Res), getRegFromArg(Arg));
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  }
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  MachineInstrBuilder buildSExt(unsigned Res, unsigned Op);
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341
  /// Build and insert \p Res = G_ZEXT \p Op
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  ///
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  /// G_ZEXT produces a register of the specified width, with bits 0 to
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  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
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  /// register, each element is extended individually.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be smaller than \p Res
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  ///
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  /// \return The newly created instruction.
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  template <typename DstType, typename ArgType>
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7.46k
  MachineInstrBuilder buildZExt(DstType &&Res, ArgType &&Arg) {
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7.46k
    return buildZExt(getDestFromArg(Res), getRegFromArg(Arg));
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7.46k
  }
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  MachineInstrBuilder buildZExt(unsigned Res, unsigned Op);
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359
  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
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  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
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  ///  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be a generic virtual register with scalar or vector type.
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  ///
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  /// \return The newly created instruction.
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  template <typename DstTy, typename UseArgTy>
368
  MachineInstrBuilder buildSExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) {
369
    return buildSExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use));
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  }
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  MachineInstrBuilder buildSExtOrTrunc(unsigned Res, unsigned Op);
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373
  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
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  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
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  ///  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be a generic virtual register with scalar or vector type.
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  ///
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  /// \return The newly created instruction.
381
  template <typename DstTy, typename UseArgTy>
382
  MachineInstrBuilder buildZExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) {
383
    return buildZExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use));
384
  }
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  MachineInstrBuilder buildZExtOrTrunc(unsigned Res, unsigned Op);
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387
  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
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  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
389
  ///  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res must be a generic virtual register with scalar or vector type.
392
  /// \pre \p Op must be a generic virtual register with scalar or vector type.
393
  ///
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  /// \return The newly created instruction.
395
  template <typename DstTy, typename UseArgTy>
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164k
  MachineInstrBuilder buildAnyExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) {
397
164k
    return buildAnyExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use));
398
164k
  }
399
  MachineInstrBuilder buildAnyExtOrTrunc(unsigned Res, unsigned Op);
400
401
  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
402
  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
403
  /// \p Op.
404
  ///  ///
405
  /// \pre setBasicBlock or setMI must have been called.
406
  /// \pre \p Res must be a generic virtual register with scalar or vector type.
407
  /// \pre \p Op must be a generic virtual register with scalar or vector type.
408
  ///
409
  /// \return The newly created instruction.
410
  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, unsigned Res,
411
                                      unsigned Op);
412
413
  /// Build and insert an appropriate cast between two registers of equal size.
414
  template <typename DstType, typename ArgType>
415
  MachineInstrBuilder buildCast(DstType &&Res, ArgType &&Arg) {
416
    return buildCast(getDestFromArg(Res), getRegFromArg(Arg));
417
  }
418
  MachineInstrBuilder buildCast(unsigned Dst, unsigned Src);
419
420
  /// Build and insert G_BR \p Dest
421
  ///
422
  /// G_BR is an unconditional branch to \p Dest.
423
  ///
424
  /// \pre setBasicBlock or setMI must have been called.
425
  ///
426
  /// \return a MachineInstrBuilder for the newly created instruction.
427
  MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
428
429
  /// Build and insert G_BRCOND \p Tst, \p Dest
430
  ///
431
  /// G_BRCOND is a conditional branch to \p Dest.
432
  ///
433
  /// \pre setBasicBlock or setMI must have been called.
434
  /// \pre \p Tst must be a generic virtual register with scalar
435
  ///      type. At the beginning of legalization, this will be a single
436
  ///      bit (s1). Targets with interesting flags registers may change
437
  ///      this. For a wider type, whether the branch is taken must only
438
  ///      depend on bit 0 (for now).
439
  ///
440
  /// \return The newly created instruction.
441
  MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest);
442
443
  /// Build and insert G_BRINDIRECT \p Tgt
444
  ///
445
  /// G_BRINDIRECT is an indirect branch to \p Tgt.
446
  ///
447
  /// \pre setBasicBlock or setMI must have been called.
448
  /// \pre \p Tgt must be a generic virtual register with pointer type.
449
  ///
450
  /// \return a MachineInstrBuilder for the newly created instruction.
451
  MachineInstrBuilder buildBrIndirect(unsigned Tgt);
452
453
  /// Build and insert \p Res = G_CONSTANT \p Val
454
  ///
455
  /// G_CONSTANT is an integer constant with the specified size and value. \p
456
  /// Val will be extended or truncated to the size of \p Reg.
457
  ///
458
  /// \pre setBasicBlock or setMI must have been called.
459
  /// \pre \p Res must be a generic virtual register with scalar or pointer
460
  ///      type.
461
  ///
462
  /// \return The newly created instruction.
463
  MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val);
464
465
  /// Build and insert \p Res = G_CONSTANT \p Val
466
  ///
467
  /// G_CONSTANT is an integer constant with the specified size and value.
468
  ///
469
  /// \pre setBasicBlock or setMI must have been called.
470
  /// \pre \p Res must be a generic virtual register with scalar type.
471
  ///
472
  /// \return The newly created instruction.
473
  MachineInstrBuilder buildConstant(unsigned Res, int64_t Val);
474
475
  template <typename DstType>
476
164k
  MachineInstrBuilder buildConstant(DstType &&Res, int64_t Val) {
477
164k
    return buildConstant(getDestFromArg(Res), Val);
478
164k
  }
479
  /// Build and insert \p Res = G_FCONSTANT \p Val
480
  ///
481
  /// G_FCONSTANT is a floating-point constant with the specified size and
482
  /// value.
483
  ///
484
  /// \pre setBasicBlock or setMI must have been called.
485
  /// \pre \p Res must be a generic virtual register with scalar type.
486
  ///
487
  /// \return The newly created instruction.
488
  template <typename DstType>
489
2.00k
  MachineInstrBuilder buildFConstant(DstType &&Res, const ConstantFP &Val) {
490
2.00k
    return buildFConstant(getDestFromArg(Res), Val);
491
2.00k
  }
492
  MachineInstrBuilder buildFConstant(unsigned Res, const ConstantFP &Val);
493
494
  template <typename DstType>
495
  MachineInstrBuilder buildFConstant(DstType &&Res, double Val) {
496
    return buildFConstant(getDestFromArg(Res), Val);
497
  }
498
  MachineInstrBuilder buildFConstant(unsigned Res, double Val);
499
500
  /// Build and insert \p Res = COPY Op
501
  ///
502
  /// Register-to-register COPY sets \p Res to \p Op.
503
  ///
504
  /// \pre setBasicBlock or setMI must have been called.
505
  ///
506
  /// \return a MachineInstrBuilder for the newly created instruction.
507
  MachineInstrBuilder buildCopy(unsigned Res, unsigned Op);
508
  template <typename DstType, typename SrcType>
509
85.0k
  MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src) {
510
85.0k
    return buildCopy(getDestFromArg(Res), getRegFromArg(Src));
511
85.0k
  }
AArch64CallLowering.cpp:llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildCopy<unsigned int&, llvm::AArch64::$_4>(unsigned int&&&, llvm::AArch64::$_4&&)
Line
Count
Source
509
61.5k
  MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src) {
510
61.5k
    return buildCopy(getDestFromArg(Res), getRegFromArg(Src));
511
61.5k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildCopy<llvm::LLT, unsigned int&>(llvm::LLT&&, unsigned int&&&)
Line
Count
Source
509
23.4k
  MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src) {
510
23.4k
    return buildCopy(getDestFromArg(Res), getRegFromArg(Src));
511
23.4k
  }
ARMCallLowering.cpp:llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildCopy<unsigned int&, llvm::ARM::$_4>(unsigned int&&&, llvm::ARM::$_4&&)
Line
Count
Source
509
102
  MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src) {
510
102
    return buildCopy(getDestFromArg(Res), getRegFromArg(Src));
511
102
  }
MipsCallLowering.cpp:llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildCopy<unsigned int&, llvm::Mips::$_4>(unsigned int&&&, llvm::Mips::$_4&&)
Line
Count
Source
509
2
  MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src) {
510
2
    return buildCopy(getDestFromArg(Res), getRegFromArg(Src));
511
2
  }
512
513
  /// Build and insert `Res = G_LOAD Addr, MMO`.
514
  ///
515
  /// Loads the value stored at \p Addr. Puts the result in \p Res.
516
  ///
517
  /// \pre setBasicBlock or setMI must have been called.
518
  /// \pre \p Res must be a generic virtual register.
519
  /// \pre \p Addr must be a generic virtual register with pointer type.
520
  ///
521
  /// \return a MachineInstrBuilder for the newly created instruction.
522
  MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr,
523
                                MachineMemOperand &MMO);
524
525
  /// Build and insert `Res = <opcode> Addr, MMO`.
526
  ///
527
  /// Loads the value stored at \p Addr. Puts the result in \p Res.
528
  ///
529
  /// \pre setBasicBlock or setMI must have been called.
530
  /// \pre \p Res must be a generic virtual register.
531
  /// \pre \p Addr must be a generic virtual register with pointer type.
532
  ///
533
  /// \return a MachineInstrBuilder for the newly created instruction.
534
  MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res,
535
                                     unsigned Addr, MachineMemOperand &MMO);
536
537
  /// Build and insert `G_STORE Val, Addr, MMO`.
538
  ///
539
  /// Stores the value \p Val to \p Addr.
540
  ///
541
  /// \pre setBasicBlock or setMI must have been called.
542
  /// \pre \p Val must be a generic virtual register.
543
  /// \pre \p Addr must be a generic virtual register with pointer type.
544
  ///
545
  /// \return a MachineInstrBuilder for the newly created instruction.
546
  MachineInstrBuilder buildStore(unsigned Val, unsigned Addr,
547
                                 MachineMemOperand &MMO);
548
549
  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
550
  ///
551
  /// \pre setBasicBlock or setMI must have been called.
552
  /// \pre \p Res and \p Src must be generic virtual registers.
553
  ///
554
  /// \return a MachineInstrBuilder for the newly created instruction.
555
  MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index);
556
557
  /// Build and insert \p Res = IMPLICIT_DEF.
558
459
  template <typename DstType> MachineInstrBuilder buildUndef(DstType &&Res) {
559
459
    return buildUndef(getDestFromArg(Res));
560
459
  }
561
  MachineInstrBuilder buildUndef(unsigned Res);
562
563
  /// Build and insert instructions to put \p Ops together at the specified p
564
  /// Indices to form a larger register.
565
  ///
566
  /// If the types of the input registers are uniform and cover the entirity of
567
  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
568
  /// followed by a sequence of G_INSERT instructions.
569
  ///
570
  /// \pre setBasicBlock or setMI must have been called.
571
  /// \pre The final element of the sequence must not extend past the end of the
572
  ///      destination register.
573
  /// \pre The bits defined by each Op (derived from index and scalar size) must
574
  ///      not overlap.
575
  /// \pre \p Indices must be in ascending order of bit position.
576
  void buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
577
                     ArrayRef<uint64_t> Indices);
578
579
  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
580
  ///
581
  /// G_MERGE_VALUES combines the input elements contiguously into a larger
582
  /// register.
583
  ///
584
  /// \pre setBasicBlock or setMI must have been called.
585
  /// \pre The entire register \p Res (and no more) must be covered by the input
586
  ///      registers.
587
  /// \pre The type of all \p Ops registers must be identical.
588
  ///
589
  /// \return a MachineInstrBuilder for the newly created instruction.
590
  MachineInstrBuilder buildMerge(unsigned Res, ArrayRef<unsigned> Ops);
591
592
  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
593
  ///
594
  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
595
  ///
596
  /// \pre setBasicBlock or setMI must have been called.
597
  /// \pre The entire register \p Res (and no more) must be covered by the input
598
  ///      registers.
599
  /// \pre The type of all \p Res registers must be identical.
600
  ///
601
  /// \return a MachineInstrBuilder for the newly created instruction.
602
  MachineInstrBuilder buildUnmerge(ArrayRef<unsigned> Res, unsigned Op);
603
604
  MachineInstrBuilder buildInsert(unsigned Res, unsigned Src,
605
                                  unsigned Op, unsigned Index);
606
607
  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
608
  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
609
  /// result register definition unless \p Reg is NoReg (== 0). The second
610
  /// operand will be the intrinsic's ID.
611
  ///
612
  /// Callers are expected to add the required definitions and uses afterwards.
613
  ///
614
  /// \pre setBasicBlock or setMI must have been called.
615
  ///
616
  /// \return a MachineInstrBuilder for the newly created instruction.
617
  MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, unsigned Res,
618
                                     bool HasSideEffects);
619
620
  /// Build and insert \p Res = G_FPTRUNC \p Op
621
  ///
622
  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
623
  ///
624
  /// \pre setBasicBlock or setMI must have been called.
625
  /// \pre \p Res must be a generic virtual register with scalar or vector type.
626
  /// \pre \p Op must be a generic virtual register with scalar or vector type.
627
  /// \pre \p Res must be smaller than \p Op
628
  ///
629
  /// \return The newly created instruction.
630
  template <typename DstType, typename SrcType>
631
  MachineInstrBuilder buildFPTrunc(DstType &&Res, SrcType &&Src) {
632
    return buildFPTrunc(getDestFromArg(Res), getRegFromArg(Src));
633
  }
634
  MachineInstrBuilder buildFPTrunc(unsigned Res, unsigned Op);
635
636
  /// Build and insert \p Res = G_TRUNC \p Op
637
  ///
638
  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
639
  /// truncated independently before being packed into the destination.
640
  ///
641
  /// \pre setBasicBlock or setMI must have been called.
642
  /// \pre \p Res must be a generic virtual register with scalar or vector type.
643
  /// \pre \p Op must be a generic virtual register with scalar or vector type.
644
  /// \pre \p Res must be smaller than \p Op
645
  ///
646
  /// \return The newly created instruction.
647
  MachineInstrBuilder buildTrunc(unsigned Res, unsigned Op);
648
  template <typename DstType, typename SrcType>
649
23.4k
  MachineInstrBuilder buildTrunc(DstType &&Res, SrcType &&Src) {
650
23.4k
    return buildTrunc(getDestFromArg(Res), getRegFromArg(Src));
651
23.4k
  }
652
653
  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
654
  ///
655
  /// \pre setBasicBlock or setMI must have been called.
656
657
  /// \pre \p Res must be a generic virtual register with scalar or
658
  ///      vector type. Typically this starts as s1 or <N x s1>.
659
  /// \pre \p Op0 and Op1 must be generic virtual registers with the
660
  ///      same number of elements as \p Res. If \p Res is a scalar,
661
  ///      \p Op0 must be either a scalar or pointer.
662
  /// \pre \p Pred must be an integer predicate.
663
  ///
664
  /// \return a MachineInstrBuilder for the newly created instruction.
665
  MachineInstrBuilder buildICmp(CmpInst::Predicate Pred,
666
                                unsigned Res, unsigned Op0, unsigned Op1);
667
668
  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
669
  ///
670
  /// \pre setBasicBlock or setMI must have been called.
671
672
  /// \pre \p Res must be a generic virtual register with scalar or
673
  ///      vector type. Typically this starts as s1 or <N x s1>.
674
  /// \pre \p Op0 and Op1 must be generic virtual registers with the
675
  ///      same number of elements as \p Res (or scalar, if \p Res is
676
  ///      scalar).
677
  /// \pre \p Pred must be a floating-point predicate.
678
  ///
679
  /// \return a MachineInstrBuilder for the newly created instruction.
680
  MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred,
681
                                unsigned Res, unsigned Op0, unsigned Op1);
682
683
  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
684
  ///
685
  /// \pre setBasicBlock or setMI must have been called.
686
  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
687
  ///      with the same type.
688
  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
689
  ///      vector type. If vector then it must have the same number of
690
  ///      elements as the other parameters.
691
  ///
692
  /// \return a MachineInstrBuilder for the newly created instruction.
693
  MachineInstrBuilder buildSelect(unsigned Res, unsigned Tst,
694
                                  unsigned Op0, unsigned Op1);
695
696
  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
697
  /// \p Elt, \p Idx
698
  ///
699
  /// \pre setBasicBlock or setMI must have been called.
700
  /// \pre \p Res and \p Val must be a generic virtual register
701
  //       with the same vector type.
702
  /// \pre \p Elt and \p Idx must be a generic virtual register
703
  ///      with scalar type.
704
  ///
705
  /// \return The newly created instruction.
706
  MachineInstrBuilder buildInsertVectorElement(unsigned Res, unsigned Val,
707
                                               unsigned Elt, unsigned Idx);
708
709
  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
710
  ///
711
  /// \pre setBasicBlock or setMI must have been called.
712
  /// \pre \p Res must be a generic virtual register with scalar type.
713
  /// \pre \p Val must be a generic virtual register with vector type.
714
  /// \pre \p Idx must be a generic virtual register with scalar type.
715
  ///
716
  /// \return The newly created instruction.
717
  MachineInstrBuilder buildExtractVectorElement(unsigned Res, unsigned Val,
718
                                                unsigned Idx);
719
720
  /// Build and insert `OldValRes<def>, SuccessRes<def> =
721
  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
722
  ///
723
  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
724
  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
725
  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
726
  ///
727
  /// \pre setBasicBlock or setMI must have been called.
728
  /// \pre \p OldValRes must be a generic virtual register of scalar type.
729
  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
730
  ///      will be assigned 0 on failure and 1 on success.
731
  /// \pre \p Addr must be a generic virtual register with pointer type.
732
  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
733
  ///      registers of the same type.
734
  ///
735
  /// \return a MachineInstrBuilder for the newly created instruction.
736
  MachineInstrBuilder
737
  buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes,
738
                                unsigned Addr, unsigned CmpVal, unsigned NewVal,
739
                                MachineMemOperand &MMO);
740
741
  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
742
  /// MMO`.
743
  ///
744
  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
745
  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
746
  /// Addr in \p Res.
747
  ///
748
  /// \pre setBasicBlock or setMI must have been called.
749
  /// \pre \p OldValRes must be a generic virtual register of scalar type.
750
  /// \pre \p Addr must be a generic virtual register with pointer type.
751
  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
752
  ///      registers of the same type.
753
  ///
754
  /// \return a MachineInstrBuilder for the newly created instruction.
755
  MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
756
                                         unsigned CmpVal, unsigned NewVal,
757
                                         MachineMemOperand &MMO);
758
759
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
760
  ///
761
  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
762
  /// original value from \p Addr in \p OldValRes. The modification is
763
  /// determined by the opcode.
764
  ///
765
  /// \pre setBasicBlock or setMI must have been called.
766
  /// \pre \p OldValRes must be a generic virtual register.
767
  /// \pre \p Addr must be a generic virtual register with pointer type.
768
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
769
  ///      same type.
770
  ///
771
  /// \return a MachineInstrBuilder for the newly created instruction.
772
  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes,
773
                                     unsigned Addr, unsigned Val,
774
                                     MachineMemOperand &MMO);
775
776
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
777
  ///
778
  /// Atomically replace the value at \p Addr with \p Val. Puts the original
779
  /// value from \p Addr in \p OldValRes.
780
  ///
781
  /// \pre setBasicBlock or setMI must have been called.
782
  /// \pre \p OldValRes must be a generic virtual register.
783
  /// \pre \p Addr must be a generic virtual register with pointer type.
784
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
785
  ///      same type.
786
  ///
787
  /// \return a MachineInstrBuilder for the newly created instruction.
788
  MachineInstrBuilder buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
789
                                         unsigned Val, MachineMemOperand &MMO);
790
791
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
792
  ///
793
  /// Atomically replace the value at \p Addr with the addition of \p Val and
794
  /// the original value. Puts the original value from \p Addr in \p OldValRes.
795
  ///
796
  /// \pre setBasicBlock or setMI must have been called.
797
  /// \pre \p OldValRes must be a generic virtual register.
798
  /// \pre \p Addr must be a generic virtual register with pointer type.
799
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
800
  ///      same type.
801
  ///
802
  /// \return a MachineInstrBuilder for the newly created instruction.
803
  MachineInstrBuilder buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
804
                                         unsigned Val, MachineMemOperand &MMO);
805
806
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
807
  ///
808
  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
809
  /// the original value. Puts the original value from \p Addr in \p OldValRes.
810
  ///
811
  /// \pre setBasicBlock or setMI must have been called.
812
  /// \pre \p OldValRes must be a generic virtual register.
813
  /// \pre \p Addr must be a generic virtual register with pointer type.
814
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
815
  ///      same type.
816
  ///
817
  /// \return a MachineInstrBuilder for the newly created instruction.
818
  MachineInstrBuilder buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
819
                                         unsigned Val, MachineMemOperand &MMO);
820
821
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
822
  ///
823
  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
824
  /// the original value. Puts the original value from \p Addr in \p OldValRes.
825
  ///
826
  /// \pre setBasicBlock or setMI must have been called.
827
  /// \pre \p OldValRes must be a generic virtual register.
828
  /// \pre \p Addr must be a generic virtual register with pointer type.
829
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
830
  ///      same type.
831
  ///
832
  /// \return a MachineInstrBuilder for the newly created instruction.
833
  MachineInstrBuilder buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
834
                                         unsigned Val, MachineMemOperand &MMO);
835
836
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
837
  ///
838
  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
839
  /// and the original value. Puts the original value from \p Addr in \p
840
  /// OldValRes.
841
  ///
842
  /// \pre setBasicBlock or setMI must have been called.
843
  /// \pre \p OldValRes must be a generic virtual register.
844
  /// \pre \p Addr must be a generic virtual register with pointer type.
845
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
846
  ///      same type.
847
  ///
848
  /// \return a MachineInstrBuilder for the newly created instruction.
849
  MachineInstrBuilder buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
850
                                         unsigned Val, MachineMemOperand &MMO);
851
852
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
853
  ///
854
  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
855
  /// the original value. Puts the original value from \p Addr in \p OldValRes.
856
  ///
857
  /// \pre setBasicBlock or setMI must have been called.
858
  /// \pre \p OldValRes must be a generic virtual register.
859
  /// \pre \p Addr must be a generic virtual register with pointer type.
860
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
861
  ///      same type.
862
  ///
863
  /// \return a MachineInstrBuilder for the newly created instruction.
864
  MachineInstrBuilder buildAtomicRMWOr(unsigned OldValRes, unsigned Addr,
865
                                       unsigned Val, MachineMemOperand &MMO);
866
867
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
868
  ///
869
  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
870
  /// the original value. Puts the original value from \p Addr in \p OldValRes.
871
  ///
872
  /// \pre setBasicBlock or setMI must have been called.
873
  /// \pre \p OldValRes must be a generic virtual register.
874
  /// \pre \p Addr must be a generic virtual register with pointer type.
875
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
876
  ///      same type.
877
  ///
878
  /// \return a MachineInstrBuilder for the newly created instruction.
879
  MachineInstrBuilder buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
880
                                        unsigned Val, MachineMemOperand &MMO);
881
882
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
883
  ///
884
  /// Atomically replace the value at \p Addr with the signed maximum of \p
885
  /// Val and the original value. Puts the original value from \p Addr in \p
886
  /// OldValRes.
887
  ///
888
  /// \pre setBasicBlock or setMI must have been called.
889
  /// \pre \p OldValRes must be a generic virtual register.
890
  /// \pre \p Addr must be a generic virtual register with pointer type.
891
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
892
  ///      same type.
893
  ///
894
  /// \return a MachineInstrBuilder for the newly created instruction.
895
  MachineInstrBuilder buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
896
                                        unsigned Val, MachineMemOperand &MMO);
897
898
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
899
  ///
900
  /// Atomically replace the value at \p Addr with the signed minimum of \p
901
  /// Val and the original value. Puts the original value from \p Addr in \p
902
  /// OldValRes.
903
  ///
904
  /// \pre setBasicBlock or setMI must have been called.
905
  /// \pre \p OldValRes must be a generic virtual register.
906
  /// \pre \p Addr must be a generic virtual register with pointer type.
907
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
908
  ///      same type.
909
  ///
910
  /// \return a MachineInstrBuilder for the newly created instruction.
911
  MachineInstrBuilder buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
912
                                        unsigned Val, MachineMemOperand &MMO);
913
914
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
915
  ///
916
  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
917
  /// Val and the original value. Puts the original value from \p Addr in \p
918
  /// OldValRes.
919
  ///
920
  /// \pre setBasicBlock or setMI must have been called.
921
  /// \pre \p OldValRes must be a generic virtual register.
922
  /// \pre \p Addr must be a generic virtual register with pointer type.
923
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
924
  ///      same type.
925
  ///
926
  /// \return a MachineInstrBuilder for the newly created instruction.
927
  MachineInstrBuilder buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
928
                                         unsigned Val, MachineMemOperand &MMO);
929
930
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
931
  ///
932
  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
933
  /// Val and the original value. Puts the original value from \p Addr in \p
934
  /// OldValRes.
935
  ///
936
  /// \pre setBasicBlock or setMI must have been called.
937
  /// \pre \p OldValRes must be a generic virtual register.
938
  /// \pre \p Addr must be a generic virtual register with pointer type.
939
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
940
  ///      same type.
941
  ///
942
  /// \return a MachineInstrBuilder for the newly created instruction.
943
  MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
944
                                         unsigned Val, MachineMemOperand &MMO);
945
};
946
947
/// A CRTP class that contains methods for building instructions that can
948
/// be constant folded. MachineIRBuilders that want to inherit from this will
949
/// need to implement buildBinaryOp (for constant folding binary ops).
950
/// Alternatively, they can implement buildInstr(Opc, Dst, Uses...) to perform
951
/// additional folding for Opc.
952
template <typename Base>
953
class FoldableInstructionsBuilder : public MachineIRBuilderBase {
954
881k
  Base &base() { return static_cast<Base &>(*this); }
955
956
public:
957
  using MachineIRBuilderBase::MachineIRBuilderBase;
958
  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
959
  ///
960
  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
961
  /// truncated to their width.
962
  ///
963
  /// \pre setBasicBlock or setMI must have been called.
964
  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
965
  ///      with the same (scalar or vector) type).
966
  ///
967
  /// \return a MachineInstrBuilder for the newly created instruction.
968
969
292
  MachineInstrBuilder buildAdd(unsigned Dst, unsigned Src0, unsigned Src1) {
970
292
    return base().buildBinaryOp(TargetOpcode::G_ADD, Dst, Src0, Src1);
971
292
  }
972
  template <typename DstTy, typename... UseArgsTy>
973
  MachineInstrBuilder buildAdd(DstTy &&Ty, UseArgsTy &&... UseArgs) {
974
    unsigned Res = base().getDestFromArg(Ty);
975
    return base().buildAdd(Res, (base().getRegFromArg(UseArgs))...);
976
  }
977
978
  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
979
  ///
980
  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
981
  /// truncated to their width.
982
  ///
983
  /// \pre setBasicBlock or setMI must have been called.
984
  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
985
  ///      with the same (scalar or vector) type).
986
  ///
987
  /// \return a MachineInstrBuilder for the newly created instruction.
988
989
2.95k
  MachineInstrBuilder buildSub(unsigned Dst, unsigned Src0, unsigned Src1) {
990
2.95k
    return base().buildBinaryOp(TargetOpcode::G_SUB, Dst, Src0, Src1);
991
2.95k
  }
992
  template <typename DstTy, typename... UseArgsTy>
993
  MachineInstrBuilder buildSub(DstTy &&Ty, UseArgsTy &&... UseArgs) {
994
    unsigned Res = base().getDestFromArg(Ty);
995
    return base().buildSub(Res, (base().getRegFromArg(UseArgs))...);
996
  }
997
998
  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
999
  ///
1000
  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1001
  /// truncated to their width.
1002
  ///
1003
  /// \pre setBasicBlock or setMI must have been called.
1004
  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1005
  ///      with the same (scalar or vector) type).
1006
  ///
1007
  /// \return a MachineInstrBuilder for the newly created instruction.
1008
145k
  MachineInstrBuilder buildMul(unsigned Dst, unsigned Src0, unsigned Src1) {
1009
145k
    return base().buildBinaryOp(TargetOpcode::G_MUL, Dst, Src0, Src1);
1010
145k
  }
1011
  template <typename DstTy, typename... UseArgsTy>
1012
  MachineInstrBuilder buildMul(DstTy &&Ty, UseArgsTy &&... UseArgs) {
1013
    unsigned Res = base().getDestFromArg(Ty);
1014
    return base().buildMul(Res, (base().getRegFromArg(UseArgs))...);
1015
  }
1016
1017
  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1018
  ///
1019
  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1020
  /// Op1.
1021
  ///
1022
  /// \pre setBasicBlock or setMI must have been called.
1023
  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1024
  ///      with the same (scalar or vector) type).
1025
  ///
1026
  /// \return a MachineInstrBuilder for the newly created instruction.
1027
1028
146k
  MachineInstrBuilder buildAnd(unsigned Dst, unsigned Src0, unsigned Src1) {
1029
146k
    return base().buildBinaryOp(TargetOpcode::G_AND, Dst, Src0, Src1);
1030
146k
  }
1031
  template <typename DstTy, typename... UseArgsTy>
1032
146k
  MachineInstrBuilder buildAnd(DstTy &&Ty, UseArgsTy &&... UseArgs) {
1033
146k
    unsigned Res = base().getDestFromArg(Ty);
1034
146k
    return base().buildAnd(Res, (base().getRegFromArg(UseArgs))...);
1035
146k
  }
1036
1037
  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1038
  ///
1039
  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1040
  /// Op1.
1041
  ///
1042
  /// \pre setBasicBlock or setMI must have been called.
1043
  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1044
  ///      with the same (scalar or vector) type).
1045
  ///
1046
  /// \return a MachineInstrBuilder for the newly created instruction.
1047
13
  MachineInstrBuilder buildOr(unsigned Dst, unsigned Src0, unsigned Src1) {
1048
13
    return base().buildBinaryOp(TargetOpcode::G_OR, Dst, Src0, Src1);
1049
13
  }
1050
  template <typename DstTy, typename... UseArgsTy>
1051
  MachineInstrBuilder buildOr(DstTy &&Ty, UseArgsTy &&... UseArgs) {
1052
    unsigned Res = base().getDestFromArg(Ty);
1053
    return base().buildOr(Res, (base().getRegFromArg(UseArgs))...);
1054
  }
1055
};
1056
1057
class MachineIRBuilder : public FoldableInstructionsBuilder<MachineIRBuilder> {
1058
public:
1059
  using FoldableInstructionsBuilder<
1060
      MachineIRBuilder>::FoldableInstructionsBuilder;
1061
  MachineInstrBuilder buildBinaryOp(unsigned Opcode, unsigned Dst,
1062
295k
                                    unsigned Src0, unsigned Src1) {
1063
295k
    validateBinaryOp(Dst, Src0, Src1);
1064
295k
    return buildInstr(Opcode).addDef(Dst).addUse(Src0).addUse(Src1);
1065
295k
  }
1066
  using FoldableInstructionsBuilder<MachineIRBuilder>::buildInstr;
1067
  /// DAG like Generic method for building arbitrary instructions as above.
1068
  /// \Opc opcode for the instruction.
1069
  /// \Ty Either LLT/TargetRegisterClass/unsigned types for Dst
1070
  /// \Args Variadic list of uses of types(unsigned/MachineInstrBuilder)
1071
  /// Uses of type MachineInstrBuilder will perform
1072
  /// getOperand(0).getReg() to convert to register.
1073
  template <typename DstTy, typename... UseArgsTy>
1074
  MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty,
1075
2.10M
                                 UseArgsTy &&... Args) {
1076
2.10M
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1077
2.10M
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1078
2.10M
    return MIB;
1079
2.10M
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<unsigned int&>(unsigned int, unsigned int&&&)
Line
Count
Source
1075
504k
                                 UseArgsTy &&... Args) {
1076
504k
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1077
504k
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1078
504k
    return MIB;
1079
504k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<unsigned int&, unsigned int&, unsigned int&, unsigned int&>(unsigned int, unsigned int&&&, unsigned int&&&, unsigned int&&&, unsigned int&&&)
Line
Count
Source
1075
1
                                 UseArgsTy &&... Args) {
1076
1
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1077
1
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1078
1
    return MIB;
1079
1
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<llvm::LLT&, unsigned int&, unsigned int&>(unsigned int, llvm::LLT&&&, unsigned int&&&, unsigned int&&&)
Line
Count
Source
1075
1
                                 UseArgsTy &&... Args) {
1076
1
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1077
1
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1078
1
    return MIB;
1079
1
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<unsigned int&, llvm::MachineInstrBuilder&, unsigned int&>(unsigned int, unsigned int&&&, llvm::MachineInstrBuilder&&&, unsigned int&&&)
Line
Count
Source
1075
1
                                 UseArgsTy &&... Args) {
1076
1
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1077
1
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1078
1
    return MIB;
1079
1
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<llvm::LLT&, llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&>(unsigned int, llvm::LLT&&&, llvm::MachineInstrBuilder&&&, llvm::MachineInstrBuilder&&&)
Line
Count
Source
1075
17.9k
                                 UseArgsTy &&... Args) {
1076
17.9k
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1077
17.9k
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1078
17.9k
    return MIB;
1079
17.9k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<unsigned int&, llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&>(unsigned int, unsigned int&&&, llvm::MachineInstrBuilder&&&, llvm::MachineInstrBuilder&&&)
Line
Count
Source
1075
17.9k
                                 UseArgsTy &&... Args) {
1076
17.9k
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1077
17.9k
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1078
17.9k
    return MIB;
1079
17.9k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<llvm::LLT&, unsigned int>(unsigned int, llvm::LLT&&&, unsigned int&&)
Line
Count
Source
1075
445k
                                 UseArgsTy &&... Args) {
1076
445k
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1077
445k
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1078
445k
    return MIB;
1079
445k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<unsigned int, unsigned int&>(unsigned int, unsigned int&&, unsigned int&&&)
Line
Count
Source
1075
1.12M
                                 UseArgsTy &&... Args) {
1076
1.12M
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1077
1.12M
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1078
1.12M
    return MIB;
1079
1.12M
  }
1080
};
1081
1082
} // End namespace llvm.
1083
#endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H