Coverage Report

Created: 2018-09-23 16:00

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
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//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the MachineIRBuilder class.
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/// This is a helper class to build MachineInstr.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
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#define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
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#include "llvm/CodeGen/GlobalISel/Types.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DebugLoc.h"
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namespace llvm {
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// Forward declarations.
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class MachineFunction;
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class MachineInstr;
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class TargetInstrInfo;
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/// Class which stores all the state required in a MachineIRBuilder.
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/// Since MachineIRBuilders will only store state in this object, it allows
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/// to transfer BuilderState between different kinds of MachineIRBuilders.
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struct MachineIRBuilderState {
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  /// MachineFunction under construction.
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  MachineFunction *MF;
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  /// Information used to access the description of the opcodes.
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  const TargetInstrInfo *TII;
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  /// Information used to verify types are consistent and to create virtual registers.
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  MachineRegisterInfo *MRI;
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  /// Debug location to be set to any instruction we create.
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  DebugLoc DL;
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  /// \name Fields describing the insertion point.
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  /// @{
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  MachineBasicBlock *MBB;
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  MachineBasicBlock::iterator II;
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  /// @}
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  std::function<void(MachineInstr *)> InsertedInstr;
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};
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/// Helper class to build MachineInstr.
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/// It keeps internally the insertion point and debug location for all
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/// the new instructions we want to create.
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/// This information can be modify via the related setters.
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class MachineIRBuilderBase {
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  MachineIRBuilderState State;
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23.8M
  const TargetInstrInfo &getTII() {
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23.8M
    assert(State.TII && "TargetInstrInfo is not set");
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23.8M
    return *State.TII;
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23.8M
  }
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  void validateTruncExt(unsigned Dst, unsigned Src, bool IsExtend);
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protected:
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1.91M
  unsigned getDestFromArg(unsigned Reg) { return Reg; }
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877k
  unsigned getDestFromArg(LLT Ty) {
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877k
    return getMF().getRegInfo().createGenericVirtualRegister(Ty);
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  }
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  unsigned getDestFromArg(const TargetRegisterClass *RC) {
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    return getMF().getRegInfo().createVirtualRegister(RC);
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  }
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1.58M
  void addUseFromArg(MachineInstrBuilder &MIB, unsigned Reg) {
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1.58M
    MIB.addUse(Reg);
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1.58M
  }
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81.7k
  void addUseFromArg(MachineInstrBuilder &MIB, const MachineInstrBuilder &UseMIB) {
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    MIB.addUse(UseMIB->getOperand(0).getReg());
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  }
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2.15M
  void addUsesFromArgs(MachineInstrBuilder &MIB) { }
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  template<typename UseArgTy, typename ... UseArgsTy>
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<unsigned int const&>(llvm::MachineInstrBuilder&, unsigned int const&&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&>(llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&&&, llvm::MachineInstrBuilder&&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<llvm::MachineInstrBuilder&>(llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&&&)
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40.8k
  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<unsigned int&, unsigned int&, unsigned int&>(llvm::MachineInstrBuilder&, unsigned int&&&, unsigned int&&&, unsigned int&&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<unsigned int&, unsigned int&>(llvm::MachineInstrBuilder&, unsigned int&&&, unsigned int&&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<unsigned int&>(llvm::MachineInstrBuilder&, unsigned int&&&)
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1.13M
  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<llvm::MachineInstrBuilder&, unsigned int&>(llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&&&, unsigned int&&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<unsigned int>(llvm::MachineInstrBuilder&, unsigned int&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder>(llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&&&, llvm::MachineInstrBuilder&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<llvm::MachineInstrBuilder>(llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<unsigned int&, llvm::MachineInstrBuilder&>(llvm::MachineInstrBuilder&, unsigned int&&&, llvm::MachineInstrBuilder&&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<unsigned int&, llvm::MachineInstrBuilder>(llvm::MachineInstrBuilder&, unsigned int&&&, llvm::MachineInstrBuilder&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
void llvm::MachineIRBuilderBase::addUsesFromArgs<llvm::MachineInstrBuilder, llvm::MachineInstrBuilder&>(llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&&, llvm::MachineInstrBuilder&&&)
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  void addUsesFromArgs(MachineInstrBuilder &MIB, UseArgTy &&Arg1, UseArgsTy &&... Args) {
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    addUseFromArg(MIB, Arg1);
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    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
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  }
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  unsigned getRegFromArg(unsigned Reg) { return Reg; }
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  unsigned getRegFromArg(const MachineInstrBuilder &MIB) {
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    return MIB->getOperand(0).getReg();
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  }
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  void validateBinaryOp(unsigned Res, unsigned Op0, unsigned Op1);
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public:
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  /// Some constructors for easy use.
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  MachineIRBuilderBase() = default;
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  MachineIRBuilderBase(MachineFunction &MF) { setMF(MF); }
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  MachineIRBuilderBase(MachineInstr &MI) : MachineIRBuilderBase(*MI.getMF()) {
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    setInstr(MI);
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  }
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  MachineIRBuilderBase(const MachineIRBuilderState &BState) : State(BState) {}
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  /// Getter for the function we currently build.
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  MachineFunction &getMF() {
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    assert(State.MF && "MachineFunction is not set");
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    return *State.MF;
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  }
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  /// Getter for DebugLoc
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  const DebugLoc &getDL() { return State.DL; }
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  /// Getter for MRI
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  MachineRegisterInfo *getMRI() { return State.MRI; }
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  /// Getter for the State
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  MachineIRBuilderState &getState() { return State; }
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  /// Getter for the basic block we currently build.
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  MachineBasicBlock &getMBB() {
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    assert(State.MBB && "MachineBasicBlock is not set");
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    return *State.MBB;
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  }
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  /// Current insertion point for new instructions.
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  MachineBasicBlock::iterator getInsertPt() { return State.II; }
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  /// Set the insertion point before the specified position.
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  /// \pre MBB must be in getMF().
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  /// \pre II must be a valid iterator in MBB.
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  void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II);
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  /// @}
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  /// \name Setters for the insertion point.
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  /// @{
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  /// Set the MachineFunction where to build instructions.
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  void setMF(MachineFunction &);
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  /// Set the insertion point to the  end of \p MBB.
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  /// \pre \p MBB must be contained by getMF().
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  void setMBB(MachineBasicBlock &MBB);
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  /// Set the insertion point to before MI.
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  /// \pre MI must be in getMF().
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  void setInstr(MachineInstr &MI);
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  /// @}
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  /// \name Control where instructions we create are recorded (typically for
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  /// visiting again later during legalization).
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  /// @{
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  void recordInsertion(MachineInstr *InsertedInstr) const;
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  void recordInsertions(std::function<void(MachineInstr *)> InsertedInstr);
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  void stopRecordingInsertions();
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  /// @}
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  /// Set the debug location to \p DL for all the next build instructions.
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  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
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  /// Get the current instruction's debug location.
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  DebugLoc getDebugLoc() { return State.DL; }
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  /// Build and insert <empty> = \p Opcode <empty>.
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  /// The insertion point is the one set by the last call of either
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  /// setBasicBlock or setMI.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  MachineInstrBuilder buildInstr(unsigned Opcode);
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  /// Build but don't insert <empty> = \p Opcode <empty>.
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  ///
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  /// \pre setMF, setBasicBlock or setMI  must have been called.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
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  /// Insert an existing instruction at the insertion point.
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  MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
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  /// Build and insert a DBG_VALUE instruction expressing the fact that the
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  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
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  MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
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                                          const MDNode *Expr);
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  /// Build and insert a DBG_VALUE instruction expressing the fact that the
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  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
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  /// Expr).
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  MachineInstrBuilder buildIndirectDbgValue(unsigned Reg,
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                                            const MDNode *Variable,
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                                            const MDNode *Expr);
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  /// Build and insert a DBG_VALUE instruction expressing the fact that the
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  /// associated \p Variable lives in the stack slot specified by \p FI
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  /// (suitably modified by \p Expr).
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  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
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                                      const MDNode *Expr);
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  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
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  /// given by \p C (suitably modified by \p Expr).
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  MachineInstrBuilder buildConstDbgValue(const Constant &C,
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                                         const MDNode *Variable,
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                                         const MDNode *Expr);
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  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
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  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
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  MachineInstrBuilder buildDbgLabel(const MDNode *Label);
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  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
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  ///
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  /// G_FRAME_INDEX materializes the address of an alloca value or other
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  /// stack-based object.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res must be a generic virtual register with pointer type.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx);
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  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
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  ///
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  /// G_GLOBAL_VALUE materializes the address of the specified global
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  /// into \p Res.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res must be a generic virtual register with pointer type
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  ///      in the same address space as \p GV.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV);
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  /// Build and insert \p Res = G_GEP \p Op0, \p Op1
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  ///
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  /// G_GEP adds \p Op1 bytes to the pointer specified by \p Op0,
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  /// storing the resulting pointer in \p Res.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
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  ///      type.
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  /// \pre \p Op1 must be a generic virtual register with scalar type.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0,
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                               unsigned Op1);
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  /// Materialize and insert \p Res = G_GEP \p Op0, (G_CONSTANT \p Value)
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  ///
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  /// G_GEP adds \p Value bytes to the pointer specified by \p Op0,
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  /// storing the resulting pointer in \p Res. If \p Value is zero then no
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  /// G_GEP or G_CONSTANT will be created and \pre Op0 will be assigned to
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  /// \p Res.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Op0 must be a generic virtual register with pointer type.
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  /// \pre \p ValueTy must be a scalar type.
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  /// \pre \p Res must be 0. This is to detect confusion between
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  ///      materializeGEP() and buildGEP().
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  /// \post \p Res will either be a new generic virtual register of the same
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  ///       type as \p Op0 or \p Op0 itself.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  Optional<MachineInstrBuilder> materializeGEP(unsigned &Res, unsigned Op0,
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                                               const LLT &ValueTy,
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                                               uint64_t Value);
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  /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
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  ///
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  /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
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  /// pointer properties. This has the effect of rounding the address *down* to
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  /// a specified alignment in bits.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
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  ///      type.
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  /// \pre \p NumBits must be an integer representing the number of low bits to
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  ///      be cleared in \p Op0.
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  ///
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  /// \return a MachineInstrBuilder for the newly created instruction.
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  MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0,
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                                   uint32_t NumBits);
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  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
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  /// \p Op1, \p CarryIn
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  ///
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  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
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  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
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  /// arithmetic.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
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  ///      with the same scalar type.
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  /// \pre \p CarryOut and \p CarryIn must be generic virtual
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  ///      registers with the same scalar type (typically s1)
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  ///
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  /// \return The newly created instruction.
303
  MachineInstrBuilder buildUAdde(unsigned Res, unsigned CarryOut, unsigned Op0,
304
                                 unsigned Op1, unsigned CarryIn);
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  /// Build and insert \p Res = G_ANYEXT \p Op0
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  ///
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  /// G_ANYEXT produces a register of the specified width, with bits 0 to
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  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
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  /// (i.e. this is neither zero nor sign-extension). For a vector register,
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  /// each element is extended individually.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be smaller than \p Res
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  ///
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  /// \return The newly created instruction.
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  MachineInstrBuilder buildAnyExt(unsigned Res, unsigned Op);
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  template <typename DstType, typename ArgType>
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38.1k
  MachineInstrBuilder buildAnyExt(DstType &&Res, ArgType &&Arg) {
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    return buildAnyExt(getDestFromArg(Res), getRegFromArg(Arg));
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  }
llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildAnyExt<llvm::LLT, unsigned int&>(llvm::LLT&&, unsigned int&&&)
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15.7k
  MachineInstrBuilder buildAnyExt(DstType &&Res, ArgType &&Arg) {
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    return buildAnyExt(getDestFromArg(Res), getRegFromArg(Arg));
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  }
llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildAnyExt<llvm::LLT&, unsigned int&>(llvm::LLT&&&, unsigned int&&&)
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  MachineInstrBuilder buildAnyExt(DstType &&Res, ArgType &&Arg) {
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    return buildAnyExt(getDestFromArg(Res), getRegFromArg(Arg));
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  }
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  /// Build and insert \p Res = G_SEXT \p Op
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  ///
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  /// G_SEXT produces a register of the specified width, with bits 0 to
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  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
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  /// high bit of \p Op (i.e. 2s-complement sign extended).
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be smaller than \p Res
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  ///
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  /// \return The newly created instruction.
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  template <typename DstType, typename ArgType>
340
  MachineInstrBuilder buildSExt(DstType &&Res, ArgType &&Arg) {
341
    return buildSExt(getDestFromArg(Res), getRegFromArg(Arg));
342
  }
343
  MachineInstrBuilder buildSExt(unsigned Res, unsigned Op);
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  /// Build and insert \p Res = G_ZEXT \p Op
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  ///
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  /// G_ZEXT produces a register of the specified width, with bits 0 to
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  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
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  /// register, each element is extended individually.
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  ///
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  /// \pre setBasicBlock or setMI must have been called.
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  /// \pre \p Res must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be a generic virtual register with scalar or vector type.
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  /// \pre \p Op must be smaller than \p Res
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  ///
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  /// \return The newly created instruction.
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  template <typename DstType, typename ArgType>
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7.51k
  MachineInstrBuilder buildZExt(DstType &&Res, ArgType &&Arg) {
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7.51k
    return buildZExt(getDestFromArg(Res), getRegFromArg(Arg));
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  }
llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildZExt<llvm::LLT, unsigned int&>(llvm::LLT&&, unsigned int&&&)
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7.51k
  MachineInstrBuilder buildZExt(DstType &&Res, ArgType &&Arg) {
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7.51k
    return buildZExt(getDestFromArg(Res), getRegFromArg(Arg));
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  }
llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildZExt<llvm::LLT&, unsigned int>(llvm::LLT&&&, unsigned int&&)
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5
  MachineInstrBuilder buildZExt(DstType &&Res, ArgType &&Arg) {
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5
    return buildZExt(getDestFromArg(Res), getRegFromArg(Arg));
360
5
  }
361
  MachineInstrBuilder buildZExt(unsigned Res, unsigned Op);
362
363
  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
364
  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
365
  ///  ///
366
  /// \pre setBasicBlock or setMI must have been called.
367
  /// \pre \p Res must be a generic virtual register with scalar or vector type.
368
  /// \pre \p Op must be a generic virtual register with scalar or vector type.
369
  ///
370
  /// \return The newly created instruction.
371
  template <typename DstTy, typename UseArgTy>
372
  MachineInstrBuilder buildSExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) {
373
    return buildSExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use));
374
  }
375
  MachineInstrBuilder buildSExtOrTrunc(unsigned Res, unsigned Op);
376
377
  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
378
  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
379
  ///  ///
380
  /// \pre setBasicBlock or setMI must have been called.
381
  /// \pre \p Res must be a generic virtual register with scalar or vector type.
382
  /// \pre \p Op must be a generic virtual register with scalar or vector type.
383
  ///
384
  /// \return The newly created instruction.
385
  template <typename DstTy, typename UseArgTy>
386
  MachineInstrBuilder buildZExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) {
387
    return buildZExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use));
388
  }
389
  MachineInstrBuilder buildZExtOrTrunc(unsigned Res, unsigned Op);
390
391
  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
392
  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
393
  ///  ///
394
  /// \pre setBasicBlock or setMI must have been called.
395
  /// \pre \p Res must be a generic virtual register with scalar or vector type.
396
  /// \pre \p Op must be a generic virtual register with scalar or vector type.
397
  ///
398
  /// \return The newly created instruction.
399
  template <typename DstTy, typename UseArgTy>
400
166k
  MachineInstrBuilder buildAnyExtOrTrunc(DstTy &&Dst, UseArgTy &&Use) {
401
166k
    return buildAnyExtOrTrunc(getDestFromArg(Dst), getRegFromArg(Use));
402
166k
  }
403
  MachineInstrBuilder buildAnyExtOrTrunc(unsigned Res, unsigned Op);
404
405
  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
406
  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
407
  /// \p Op.
408
  ///  ///
409
  /// \pre setBasicBlock or setMI must have been called.
410
  /// \pre \p Res must be a generic virtual register with scalar or vector type.
411
  /// \pre \p Op must be a generic virtual register with scalar or vector type.
412
  ///
413
  /// \return The newly created instruction.
414
  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, unsigned Res,
415
                                      unsigned Op);
416
417
  /// Build and insert an appropriate cast between two registers of equal size.
418
  template <typename DstType, typename ArgType>
419
  MachineInstrBuilder buildCast(DstType &&Res, ArgType &&Arg) {
420
    return buildCast(getDestFromArg(Res), getRegFromArg(Arg));
421
  }
422
  MachineInstrBuilder buildCast(unsigned Dst, unsigned Src);
423
424
  /// Build and insert G_BR \p Dest
425
  ///
426
  /// G_BR is an unconditional branch to \p Dest.
427
  ///
428
  /// \pre setBasicBlock or setMI must have been called.
429
  ///
430
  /// \return a MachineInstrBuilder for the newly created instruction.
431
  MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
432
433
  /// Build and insert G_BRCOND \p Tst, \p Dest
434
  ///
435
  /// G_BRCOND is a conditional branch to \p Dest.
436
  ///
437
  /// \pre setBasicBlock or setMI must have been called.
438
  /// \pre \p Tst must be a generic virtual register with scalar
439
  ///      type. At the beginning of legalization, this will be a single
440
  ///      bit (s1). Targets with interesting flags registers may change
441
  ///      this. For a wider type, whether the branch is taken must only
442
  ///      depend on bit 0 (for now).
443
  ///
444
  /// \return The newly created instruction.
445
  MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest);
446
447
  /// Build and insert G_BRINDIRECT \p Tgt
448
  ///
449
  /// G_BRINDIRECT is an indirect branch to \p Tgt.
450
  ///
451
  /// \pre setBasicBlock or setMI must have been called.
452
  /// \pre \p Tgt must be a generic virtual register with pointer type.
453
  ///
454
  /// \return a MachineInstrBuilder for the newly created instruction.
455
  MachineInstrBuilder buildBrIndirect(unsigned Tgt);
456
457
  /// Build and insert \p Res = G_CONSTANT \p Val
458
  ///
459
  /// G_CONSTANT is an integer constant with the specified size and value. \p
460
  /// Val will be extended or truncated to the size of \p Reg.
461
  ///
462
  /// \pre setBasicBlock or setMI must have been called.
463
  /// \pre \p Res must be a generic virtual register with scalar or pointer
464
  ///      type.
465
  ///
466
  /// \return The newly created instruction.
467
  MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val);
468
469
  /// Build and insert \p Res = G_CONSTANT \p Val
470
  ///
471
  /// G_CONSTANT is an integer constant with the specified size and value.
472
  ///
473
  /// \pre setBasicBlock or setMI must have been called.
474
  /// \pre \p Res must be a generic virtual register with scalar type.
475
  ///
476
  /// \return The newly created instruction.
477
  MachineInstrBuilder buildConstant(unsigned Res, int64_t Val);
478
479
  template <typename DstType>
480
166k
  MachineInstrBuilder buildConstant(DstType &&Res, int64_t Val) {
481
166k
    return buildConstant(getDestFromArg(Res), Val);
482
166k
  }
483
  /// Build and insert \p Res = G_FCONSTANT \p Val
484
  ///
485
  /// G_FCONSTANT is a floating-point constant with the specified size and
486
  /// value.
487
  ///
488
  /// \pre setBasicBlock or setMI must have been called.
489
  /// \pre \p Res must be a generic virtual register with scalar type.
490
  ///
491
  /// \return The newly created instruction.
492
  template <typename DstType>
493
2.01k
  MachineInstrBuilder buildFConstant(DstType &&Res, const ConstantFP &Val) {
494
2.01k
    return buildFConstant(getDestFromArg(Res), Val);
495
2.01k
  }
496
  MachineInstrBuilder buildFConstant(unsigned Res, const ConstantFP &Val);
497
498
  template <typename DstType>
499
  MachineInstrBuilder buildFConstant(DstType &&Res, double Val) {
500
    return buildFConstant(getDestFromArg(Res), Val);
501
  }
502
  MachineInstrBuilder buildFConstant(unsigned Res, double Val);
503
504
  /// Build and insert \p Res = COPY Op
505
  ///
506
  /// Register-to-register COPY sets \p Res to \p Op.
507
  ///
508
  /// \pre setBasicBlock or setMI must have been called.
509
  ///
510
  /// \return a MachineInstrBuilder for the newly created instruction.
511
  MachineInstrBuilder buildCopy(unsigned Res, unsigned Op);
512
  template <typename DstType, typename SrcType>
513
86.0k
  MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src) {
514
86.0k
    return buildCopy(getDestFromArg(Res), getRegFromArg(Src));
515
86.0k
  }
AArch64CallLowering.cpp:llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildCopy<unsigned int&, llvm::AArch64::$_4>(unsigned int&&&, llvm::AArch64::$_4&&)
Line
Count
Source
513
61.8k
  MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src) {
514
61.8k
    return buildCopy(getDestFromArg(Res), getRegFromArg(Src));
515
61.8k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildCopy<llvm::LLT, unsigned int&>(llvm::LLT&&, unsigned int&&&)
Line
Count
Source
513
24.0k
  MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src) {
514
24.0k
    return buildCopy(getDestFromArg(Res), getRegFromArg(Src));
515
24.0k
  }
ARMCallLowering.cpp:llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildCopy<unsigned int&, llvm::ARM::$_4>(unsigned int&&&, llvm::ARM::$_4&&)
Line
Count
Source
513
102
  MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src) {
514
102
    return buildCopy(getDestFromArg(Res), getRegFromArg(Src));
515
102
  }
MipsCallLowering.cpp:llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildCopy<unsigned int&, llvm::Mips::$_4>(unsigned int&&&, llvm::Mips::$_4&&)
Line
Count
Source
513
8
  MachineInstrBuilder buildCopy(DstType &&Res, SrcType &&Src) {
514
8
    return buildCopy(getDestFromArg(Res), getRegFromArg(Src));
515
8
  }
516
517
  /// Build and insert `Res = G_LOAD Addr, MMO`.
518
  ///
519
  /// Loads the value stored at \p Addr. Puts the result in \p Res.
520
  ///
521
  /// \pre setBasicBlock or setMI must have been called.
522
  /// \pre \p Res must be a generic virtual register.
523
  /// \pre \p Addr must be a generic virtual register with pointer type.
524
  ///
525
  /// \return a MachineInstrBuilder for the newly created instruction.
526
  MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr,
527
                                MachineMemOperand &MMO);
528
529
  /// Build and insert `Res = <opcode> Addr, MMO`.
530
  ///
531
  /// Loads the value stored at \p Addr. Puts the result in \p Res.
532
  ///
533
  /// \pre setBasicBlock or setMI must have been called.
534
  /// \pre \p Res must be a generic virtual register.
535
  /// \pre \p Addr must be a generic virtual register with pointer type.
536
  ///
537
  /// \return a MachineInstrBuilder for the newly created instruction.
538
  MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res,
539
                                     unsigned Addr, MachineMemOperand &MMO);
540
541
  /// Build and insert `G_STORE Val, Addr, MMO`.
542
  ///
543
  /// Stores the value \p Val to \p Addr.
544
  ///
545
  /// \pre setBasicBlock or setMI must have been called.
546
  /// \pre \p Val must be a generic virtual register.
547
  /// \pre \p Addr must be a generic virtual register with pointer type.
548
  ///
549
  /// \return a MachineInstrBuilder for the newly created instruction.
550
  MachineInstrBuilder buildStore(unsigned Val, unsigned Addr,
551
                                 MachineMemOperand &MMO);
552
553
  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
554
  ///
555
  /// \pre setBasicBlock or setMI must have been called.
556
  /// \pre \p Res and \p Src must be generic virtual registers.
557
  ///
558
  /// \return a MachineInstrBuilder for the newly created instruction.
559
  MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index);
560
561
  /// Build and insert \p Res = IMPLICIT_DEF.
562
1.35k
  template <typename DstType> MachineInstrBuilder buildUndef(DstType &&Res) {
563
1.35k
    return buildUndef(getDestFromArg(Res));
564
1.35k
  }
565
  MachineInstrBuilder buildUndef(unsigned Res);
566
567
  /// Build and insert instructions to put \p Ops together at the specified p
568
  /// Indices to form a larger register.
569
  ///
570
  /// If the types of the input registers are uniform and cover the entirity of
571
  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
572
  /// followed by a sequence of G_INSERT instructions.
573
  ///
574
  /// \pre setBasicBlock or setMI must have been called.
575
  /// \pre The final element of the sequence must not extend past the end of the
576
  ///      destination register.
577
  /// \pre The bits defined by each Op (derived from index and scalar size) must
578
  ///      not overlap.
579
  /// \pre \p Indices must be in ascending order of bit position.
580
  void buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
581
                     ArrayRef<uint64_t> Indices);
582
583
  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
584
  ///
585
  /// G_MERGE_VALUES combines the input elements contiguously into a larger
586
  /// register.
587
  ///
588
  /// \pre setBasicBlock or setMI must have been called.
589
  /// \pre The entire register \p Res (and no more) must be covered by the input
590
  ///      registers.
591
  /// \pre The type of all \p Ops registers must be identical.
592
  ///
593
  /// \return a MachineInstrBuilder for the newly created instruction.
594
  MachineInstrBuilder buildMerge(unsigned Res, ArrayRef<unsigned> Ops);
595
596
  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
597
  ///
598
  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
599
  ///
600
  /// \pre setBasicBlock or setMI must have been called.
601
  /// \pre The entire register \p Res (and no more) must be covered by the input
602
  ///      registers.
603
  /// \pre The type of all \p Res registers must be identical.
604
  ///
605
  /// \return a MachineInstrBuilder for the newly created instruction.
606
  MachineInstrBuilder buildUnmerge(ArrayRef<unsigned> Res, unsigned Op);
607
608
  MachineInstrBuilder buildInsert(unsigned Res, unsigned Src,
609
                                  unsigned Op, unsigned Index);
610
611
  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
612
  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
613
  /// result register definition unless \p Reg is NoReg (== 0). The second
614
  /// operand will be the intrinsic's ID.
615
  ///
616
  /// Callers are expected to add the required definitions and uses afterwards.
617
  ///
618
  /// \pre setBasicBlock or setMI must have been called.
619
  ///
620
  /// \return a MachineInstrBuilder for the newly created instruction.
621
  MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, unsigned Res,
622
                                     bool HasSideEffects);
623
624
  /// Build and insert \p Res = G_FPTRUNC \p Op
625
  ///
626
  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
627
  ///
628
  /// \pre setBasicBlock or setMI must have been called.
629
  /// \pre \p Res must be a generic virtual register with scalar or vector type.
630
  /// \pre \p Op must be a generic virtual register with scalar or vector type.
631
  /// \pre \p Res must be smaller than \p Op
632
  ///
633
  /// \return The newly created instruction.
634
  template <typename DstType, typename SrcType>
635
  MachineInstrBuilder buildFPTrunc(DstType &&Res, SrcType &&Src) {
636
    return buildFPTrunc(getDestFromArg(Res), getRegFromArg(Src));
637
  }
638
  MachineInstrBuilder buildFPTrunc(unsigned Res, unsigned Op);
639
640
  /// Build and insert \p Res = G_TRUNC \p Op
641
  ///
642
  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
643
  /// truncated independently before being packed into the destination.
644
  ///
645
  /// \pre setBasicBlock or setMI must have been called.
646
  /// \pre \p Res must be a generic virtual register with scalar or vector type.
647
  /// \pre \p Op must be a generic virtual register with scalar or vector type.
648
  /// \pre \p Res must be smaller than \p Op
649
  ///
650
  /// \return The newly created instruction.
651
  MachineInstrBuilder buildTrunc(unsigned Res, unsigned Op);
652
  template <typename DstType, typename SrcType>
653
24.0k
  MachineInstrBuilder buildTrunc(DstType &&Res, SrcType &&Src) {
654
24.0k
    return buildTrunc(getDestFromArg(Res), getRegFromArg(Src));
655
24.0k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildTrunc<unsigned int&, llvm::MachineInstrBuilder&>(unsigned int&&&, llvm::MachineInstrBuilder&&&)
Line
Count
Source
653
24.0k
  MachineInstrBuilder buildTrunc(DstType &&Res, SrcType &&Src) {
654
24.0k
    return buildTrunc(getDestFromArg(Res), getRegFromArg(Src));
655
24.0k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildTrunc<unsigned int, llvm::MachineInstrBuilder&>(unsigned int&&, llvm::MachineInstrBuilder&&&)
Line
Count
Source
653
2
  MachineInstrBuilder buildTrunc(DstType &&Res, SrcType &&Src) {
654
2
    return buildTrunc(getDestFromArg(Res), getRegFromArg(Src));
655
2
  }
656
657
  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
658
  ///
659
  /// \pre setBasicBlock or setMI must have been called.
660
661
  /// \pre \p Res must be a generic virtual register with scalar or
662
  ///      vector type. Typically this starts as s1 or <N x s1>.
663
  /// \pre \p Op0 and Op1 must be generic virtual registers with the
664
  ///      same number of elements as \p Res. If \p Res is a scalar,
665
  ///      \p Op0 must be either a scalar or pointer.
666
  /// \pre \p Pred must be an integer predicate.
667
  ///
668
  /// \return a MachineInstrBuilder for the newly created instruction.
669
  MachineInstrBuilder buildICmp(CmpInst::Predicate Pred,
670
                                unsigned Res, unsigned Op0, unsigned Op1);
671
  template <typename DstTy, typename... UseArgsTy>
672
  MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, DstTy &&Dst,
673
4
                                UseArgsTy &&... UseArgs) {
674
4
    return buildICmp(Pred, getDestFromArg(Dst), getRegFromArg(UseArgs)...);
675
4
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildICmp<unsigned int, llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&>(llvm::CmpInst::Predicate, unsigned int&&, llvm::MachineInstrBuilder&&&, llvm::MachineInstrBuilder&&&)
Line
Count
Source
673
2
                                UseArgsTy &&... UseArgs) {
674
2
    return buildICmp(Pred, getDestFromArg(Dst), getRegFromArg(UseArgs)...);
675
2
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilderBase::buildICmp<llvm::LLT, unsigned int&, llvm::MachineInstrBuilder&>(llvm::CmpInst::Predicate, llvm::LLT&&, unsigned int&&&, llvm::MachineInstrBuilder&&&)
Line
Count
Source
673
2
                                UseArgsTy &&... UseArgs) {
674
2
    return buildICmp(Pred, getDestFromArg(Dst), getRegFromArg(UseArgs)...);
675
2
  }
676
677
  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
678
  ///
679
  /// \pre setBasicBlock or setMI must have been called.
680
681
  /// \pre \p Res must be a generic virtual register with scalar or
682
  ///      vector type. Typically this starts as s1 or <N x s1>.
683
  /// \pre \p Op0 and Op1 must be generic virtual registers with the
684
  ///      same number of elements as \p Res (or scalar, if \p Res is
685
  ///      scalar).
686
  /// \pre \p Pred must be a floating-point predicate.
687
  ///
688
  /// \return a MachineInstrBuilder for the newly created instruction.
689
  MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred,
690
                                unsigned Res, unsigned Op0, unsigned Op1);
691
692
  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
693
  ///
694
  /// \pre setBasicBlock or setMI must have been called.
695
  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
696
  ///      with the same type.
697
  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
698
  ///      vector type. If vector then it must have the same number of
699
  ///      elements as the other parameters.
700
  ///
701
  /// \return a MachineInstrBuilder for the newly created instruction.
702
  MachineInstrBuilder buildSelect(unsigned Res, unsigned Tst,
703
                                  unsigned Op0, unsigned Op1);
704
  template <typename DstTy, typename... UseArgsTy>
705
2
  MachineInstrBuilder buildSelect(DstTy &&Dst, UseArgsTy &&... UseArgs) {
706
2
    return buildSelect(getDestFromArg(Dst), getRegFromArg(UseArgs)...);
707
2
  }
708
709
  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
710
  /// \p Elt, \p Idx
711
  ///
712
  /// \pre setBasicBlock or setMI must have been called.
713
  /// \pre \p Res and \p Val must be a generic virtual register
714
  //       with the same vector type.
715
  /// \pre \p Elt and \p Idx must be a generic virtual register
716
  ///      with scalar type.
717
  ///
718
  /// \return The newly created instruction.
719
  MachineInstrBuilder buildInsertVectorElement(unsigned Res, unsigned Val,
720
                                               unsigned Elt, unsigned Idx);
721
722
  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
723
  ///
724
  /// \pre setBasicBlock or setMI must have been called.
725
  /// \pre \p Res must be a generic virtual register with scalar type.
726
  /// \pre \p Val must be a generic virtual register with vector type.
727
  /// \pre \p Idx must be a generic virtual register with scalar type.
728
  ///
729
  /// \return The newly created instruction.
730
  MachineInstrBuilder buildExtractVectorElement(unsigned Res, unsigned Val,
731
                                                unsigned Idx);
732
733
  /// Build and insert `OldValRes<def>, SuccessRes<def> =
734
  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
735
  ///
736
  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
737
  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
738
  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
739
  ///
740
  /// \pre setBasicBlock or setMI must have been called.
741
  /// \pre \p OldValRes must be a generic virtual register of scalar type.
742
  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
743
  ///      will be assigned 0 on failure and 1 on success.
744
  /// \pre \p Addr must be a generic virtual register with pointer type.
745
  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
746
  ///      registers of the same type.
747
  ///
748
  /// \return a MachineInstrBuilder for the newly created instruction.
749
  MachineInstrBuilder
750
  buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes,
751
                                unsigned Addr, unsigned CmpVal, unsigned NewVal,
752
                                MachineMemOperand &MMO);
753
754
  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
755
  /// MMO`.
756
  ///
757
  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
758
  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
759
  /// Addr in \p Res.
760
  ///
761
  /// \pre setBasicBlock or setMI must have been called.
762
  /// \pre \p OldValRes must be a generic virtual register of scalar type.
763
  /// \pre \p Addr must be a generic virtual register with pointer type.
764
  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
765
  ///      registers of the same type.
766
  ///
767
  /// \return a MachineInstrBuilder for the newly created instruction.
768
  MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
769
                                         unsigned CmpVal, unsigned NewVal,
770
                                         MachineMemOperand &MMO);
771
772
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
773
  ///
774
  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
775
  /// original value from \p Addr in \p OldValRes. The modification is
776
  /// determined by the opcode.
777
  ///
778
  /// \pre setBasicBlock or setMI must have been called.
779
  /// \pre \p OldValRes must be a generic virtual register.
780
  /// \pre \p Addr must be a generic virtual register with pointer type.
781
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
782
  ///      same type.
783
  ///
784
  /// \return a MachineInstrBuilder for the newly created instruction.
785
  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes,
786
                                     unsigned Addr, unsigned Val,
787
                                     MachineMemOperand &MMO);
788
789
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
790
  ///
791
  /// Atomically replace the value at \p Addr with \p Val. Puts the original
792
  /// value from \p Addr in \p OldValRes.
793
  ///
794
  /// \pre setBasicBlock or setMI must have been called.
795
  /// \pre \p OldValRes must be a generic virtual register.
796
  /// \pre \p Addr must be a generic virtual register with pointer type.
797
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
798
  ///      same type.
799
  ///
800
  /// \return a MachineInstrBuilder for the newly created instruction.
801
  MachineInstrBuilder buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
802
                                         unsigned Val, MachineMemOperand &MMO);
803
804
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
805
  ///
806
  /// Atomically replace the value at \p Addr with the addition of \p Val and
807
  /// the original value. Puts the original value from \p Addr in \p OldValRes.
808
  ///
809
  /// \pre setBasicBlock or setMI must have been called.
810
  /// \pre \p OldValRes must be a generic virtual register.
811
  /// \pre \p Addr must be a generic virtual register with pointer type.
812
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
813
  ///      same type.
814
  ///
815
  /// \return a MachineInstrBuilder for the newly created instruction.
816
  MachineInstrBuilder buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
817
                                         unsigned Val, MachineMemOperand &MMO);
818
819
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
820
  ///
821
  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
822
  /// the original value. Puts the original value from \p Addr in \p OldValRes.
823
  ///
824
  /// \pre setBasicBlock or setMI must have been called.
825
  /// \pre \p OldValRes must be a generic virtual register.
826
  /// \pre \p Addr must be a generic virtual register with pointer type.
827
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
828
  ///      same type.
829
  ///
830
  /// \return a MachineInstrBuilder for the newly created instruction.
831
  MachineInstrBuilder buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
832
                                         unsigned Val, MachineMemOperand &MMO);
833
834
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
835
  ///
836
  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
837
  /// the original value. Puts the original value from \p Addr in \p OldValRes.
838
  ///
839
  /// \pre setBasicBlock or setMI must have been called.
840
  /// \pre \p OldValRes must be a generic virtual register.
841
  /// \pre \p Addr must be a generic virtual register with pointer type.
842
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
843
  ///      same type.
844
  ///
845
  /// \return a MachineInstrBuilder for the newly created instruction.
846
  MachineInstrBuilder buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
847
                                         unsigned Val, MachineMemOperand &MMO);
848
849
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
850
  ///
851
  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
852
  /// and the original value. Puts the original value from \p Addr in \p
853
  /// OldValRes.
854
  ///
855
  /// \pre setBasicBlock or setMI must have been called.
856
  /// \pre \p OldValRes must be a generic virtual register.
857
  /// \pre \p Addr must be a generic virtual register with pointer type.
858
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
859
  ///      same type.
860
  ///
861
  /// \return a MachineInstrBuilder for the newly created instruction.
862
  MachineInstrBuilder buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
863
                                         unsigned Val, MachineMemOperand &MMO);
864
865
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
866
  ///
867
  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
868
  /// the original value. Puts the original value from \p Addr in \p OldValRes.
869
  ///
870
  /// \pre setBasicBlock or setMI must have been called.
871
  /// \pre \p OldValRes must be a generic virtual register.
872
  /// \pre \p Addr must be a generic virtual register with pointer type.
873
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
874
  ///      same type.
875
  ///
876
  /// \return a MachineInstrBuilder for the newly created instruction.
877
  MachineInstrBuilder buildAtomicRMWOr(unsigned OldValRes, unsigned Addr,
878
                                       unsigned Val, MachineMemOperand &MMO);
879
880
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
881
  ///
882
  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
883
  /// the original value. Puts the original value from \p Addr in \p OldValRes.
884
  ///
885
  /// \pre setBasicBlock or setMI must have been called.
886
  /// \pre \p OldValRes must be a generic virtual register.
887
  /// \pre \p Addr must be a generic virtual register with pointer type.
888
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
889
  ///      same type.
890
  ///
891
  /// \return a MachineInstrBuilder for the newly created instruction.
892
  MachineInstrBuilder buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
893
                                        unsigned Val, MachineMemOperand &MMO);
894
895
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
896
  ///
897
  /// Atomically replace the value at \p Addr with the signed maximum of \p
898
  /// Val and the original value. Puts the original value from \p Addr in \p
899
  /// OldValRes.
900
  ///
901
  /// \pre setBasicBlock or setMI must have been called.
902
  /// \pre \p OldValRes must be a generic virtual register.
903
  /// \pre \p Addr must be a generic virtual register with pointer type.
904
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
905
  ///      same type.
906
  ///
907
  /// \return a MachineInstrBuilder for the newly created instruction.
908
  MachineInstrBuilder buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
909
                                        unsigned Val, MachineMemOperand &MMO);
910
911
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
912
  ///
913
  /// Atomically replace the value at \p Addr with the signed minimum of \p
914
  /// Val and the original value. Puts the original value from \p Addr in \p
915
  /// OldValRes.
916
  ///
917
  /// \pre setBasicBlock or setMI must have been called.
918
  /// \pre \p OldValRes must be a generic virtual register.
919
  /// \pre \p Addr must be a generic virtual register with pointer type.
920
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
921
  ///      same type.
922
  ///
923
  /// \return a MachineInstrBuilder for the newly created instruction.
924
  MachineInstrBuilder buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
925
                                        unsigned Val, MachineMemOperand &MMO);
926
927
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
928
  ///
929
  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
930
  /// Val and the original value. Puts the original value from \p Addr in \p
931
  /// OldValRes.
932
  ///
933
  /// \pre setBasicBlock or setMI must have been called.
934
  /// \pre \p OldValRes must be a generic virtual register.
935
  /// \pre \p Addr must be a generic virtual register with pointer type.
936
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
937
  ///      same type.
938
  ///
939
  /// \return a MachineInstrBuilder for the newly created instruction.
940
  MachineInstrBuilder buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
941
                                         unsigned Val, MachineMemOperand &MMO);
942
943
  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
944
  ///
945
  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
946
  /// Val and the original value. Puts the original value from \p Addr in \p
947
  /// OldValRes.
948
  ///
949
  /// \pre setBasicBlock or setMI must have been called.
950
  /// \pre \p OldValRes must be a generic virtual register.
951
  /// \pre \p Addr must be a generic virtual register with pointer type.
952
  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
953
  ///      same type.
954
  ///
955
  /// \return a MachineInstrBuilder for the newly created instruction.
956
  MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
957
                                         unsigned Val, MachineMemOperand &MMO);
958
959
  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
960
  ///
961
  /// G_BLOCK_ADDR computes the address of a basic block.
962
  ///
963
  /// \pre setBasicBlock or setMI must have been called.
964
  /// \pre \p Res must be a generic virtual register of a pointer type.
965
  ///
966
  /// \return The newly created instruction.
967
  MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA);
968
};
969
970
/// A CRTP class that contains methods for building instructions that can
971
/// be constant folded. MachineIRBuilders that want to inherit from this will
972
/// need to implement buildBinaryOp (for constant folding binary ops).
973
/// Alternatively, they can implement buildInstr(Opc, Dst, Uses...) to perform
974
/// additional folding for Opc.
975
template <typename Base>
976
class FoldableInstructionsBuilder : public MachineIRBuilderBase {
977
886k
  Base &base() { return static_cast<Base &>(*this); }
978
979
public:
980
  using MachineIRBuilderBase::MachineIRBuilderBase;
981
  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
982
  ///
983
  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
984
  /// truncated to their width.
985
  ///
986
  /// \pre setBasicBlock or setMI must have been called.
987
  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
988
  ///      with the same (scalar or vector) type).
989
  ///
990
  /// \return a MachineInstrBuilder for the newly created instruction.
991
992
292
  MachineInstrBuilder buildAdd(unsigned Dst, unsigned Src0, unsigned Src1) {
993
292
    return base().buildBinaryOp(TargetOpcode::G_ADD, Dst, Src0, Src1);
994
292
  }
995
  template <typename DstTy, typename... UseArgsTy>
996
  MachineInstrBuilder buildAdd(DstTy &&Ty, UseArgsTy &&... UseArgs) {
997
    unsigned Res = base().getDestFromArg(Ty);
998
    return base().buildAdd(Res, (base().getRegFromArg(UseArgs))...);
999
  }
1000
1001
  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1002
  ///
1003
  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1004
  /// truncated to their width.
1005
  ///
1006
  /// \pre setBasicBlock or setMI must have been called.
1007
  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1008
  ///      with the same (scalar or vector) type).
1009
  ///
1010
  /// \return a MachineInstrBuilder for the newly created instruction.
1011
1012
3.45k
  MachineInstrBuilder buildSub(unsigned Dst, unsigned Src0, unsigned Src1) {
1013
3.45k
    return base().buildBinaryOp(TargetOpcode::G_SUB, Dst, Src0, Src1);
1014
3.45k
  }
1015
  template <typename DstTy, typename... UseArgsTy>
1016
  MachineInstrBuilder buildSub(DstTy &&Ty, UseArgsTy &&... UseArgs) {
1017
    unsigned Res = base().getDestFromArg(Ty);
1018
    return base().buildSub(Res, (base().getRegFromArg(UseArgs))...);
1019
  }
1020
1021
  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1022
  ///
1023
  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1024
  /// truncated to their width.
1025
  ///
1026
  /// \pre setBasicBlock or setMI must have been called.
1027
  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1028
  ///      with the same (scalar or vector) type).
1029
  ///
1030
  /// \return a MachineInstrBuilder for the newly created instruction.
1031
154k
  MachineInstrBuilder buildMul(unsigned Dst, unsigned Src0, unsigned Src1) {
1032
154k
    return base().buildBinaryOp(TargetOpcode::G_MUL, Dst, Src0, Src1);
1033
154k
  }
1034
  template <typename DstTy, typename... UseArgsTy>
1035
  MachineInstrBuilder buildMul(DstTy &&Ty, UseArgsTy &&... UseArgs) {
1036
    unsigned Res = base().getDestFromArg(Ty);
1037
    return base().buildMul(Res, (base().getRegFromArg(UseArgs))...);
1038
  }
1039
1040
  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1041
  ///
1042
  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1043
  /// Op1.
1044
  ///
1045
  /// \pre setBasicBlock or setMI must have been called.
1046
  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1047
  ///      with the same (scalar or vector) type).
1048
  ///
1049
  /// \return a MachineInstrBuilder for the newly created instruction.
1050
1051
145k
  MachineInstrBuilder buildAnd(unsigned Dst, unsigned Src0, unsigned Src1) {
1052
145k
    return base().buildBinaryOp(TargetOpcode::G_AND, Dst, Src0, Src1);
1053
145k
  }
1054
  template <typename DstTy, typename... UseArgsTy>
1055
145k
  MachineInstrBuilder buildAnd(DstTy &&Ty, UseArgsTy &&... UseArgs) {
1056
145k
    unsigned Res = base().getDestFromArg(Ty);
1057
145k
    return base().buildAnd(Res, (base().getRegFromArg(UseArgs))...);
1058
145k
  }
1059
1060
  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1061
  ///
1062
  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1063
  /// Op1.
1064
  ///
1065
  /// \pre setBasicBlock or setMI must have been called.
1066
  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1067
  ///      with the same (scalar or vector) type).
1068
  ///
1069
  /// \return a MachineInstrBuilder for the newly created instruction.
1070
13
  MachineInstrBuilder buildOr(unsigned Dst, unsigned Src0, unsigned Src1) {
1071
13
    return base().buildBinaryOp(TargetOpcode::G_OR, Dst, Src0, Src1);
1072
13
  }
1073
  template <typename DstTy, typename... UseArgsTy>
1074
  MachineInstrBuilder buildOr(DstTy &&Ty, UseArgsTy &&... UseArgs) {
1075
    unsigned Res = base().getDestFromArg(Ty);
1076
    return base().buildOr(Res, (base().getRegFromArg(UseArgs))...);
1077
  }
1078
};
1079
1080
class MachineIRBuilder : public FoldableInstructionsBuilder<MachineIRBuilder> {
1081
public:
1082
  using FoldableInstructionsBuilder<
1083
      MachineIRBuilder>::FoldableInstructionsBuilder;
1084
  MachineInstrBuilder buildBinaryOp(unsigned Opcode, unsigned Dst,
1085
303k
                                    unsigned Src0, unsigned Src1) {
1086
303k
    validateBinaryOp(Dst, Src0, Src1);
1087
303k
    return buildInstr(Opcode).addDef(Dst).addUse(Src0).addUse(Src1);
1088
303k
  }
1089
  using FoldableInstructionsBuilder<MachineIRBuilder>::buildInstr;
1090
  /// DAG like Generic method for building arbitrary instructions as above.
1091
  /// \Opc opcode for the instruction.
1092
  /// \Ty Either LLT/TargetRegisterClass/unsigned types for Dst
1093
  /// \Args Variadic list of uses of types(unsigned/MachineInstrBuilder)
1094
  /// Uses of type MachineInstrBuilder will perform
1095
  /// getOperand(0).getReg() to convert to register.
1096
  template <typename DstTy, typename... UseArgsTy>
1097
  MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty,
1098
2.15M
                                 UseArgsTy &&... Args) {
1099
2.15M
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
2.15M
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
2.15M
    return MIB;
1102
2.15M
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<llvm::TargetRegisterClass const*>(unsigned int, llvm::TargetRegisterClass const*&&)
Line
Count
Source
1098
4
                                 UseArgsTy &&... Args) {
1099
4
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
4
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
4
    return MIB;
1102
4
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<llvm::LLT&, llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&>(unsigned int, llvm::LLT&&&, llvm::MachineInstrBuilder&&&, llvm::MachineInstrBuilder&&&)
Line
Count
Source
1098
20.4k
                                 UseArgsTy &&... Args) {
1099
20.4k
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
20.4k
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
20.4k
    return MIB;
1102
20.4k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<unsigned int&, llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder&>(unsigned int, unsigned int&&&, llvm::MachineInstrBuilder&&&, llvm::MachineInstrBuilder&&&)
Line
Count
Source
1098
20.4k
                                 UseArgsTy &&... Args) {
1099
20.4k
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
20.4k
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
20.4k
    return MIB;
1102
20.4k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<unsigned int&>(unsigned int, unsigned int&&&)
Line
Count
Source
1098
523k
                                 UseArgsTy &&... Args) {
1099
523k
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
523k
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
523k
    return MIB;
1102
523k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<unsigned int const&, unsigned int const&>(unsigned int, unsigned int const&&&, unsigned int const&&&)
Line
Count
Source
1098
32
                                 UseArgsTy &&... Args) {
1099
32
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
32
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
32
    return MIB;
1102
32
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<unsigned int&, unsigned int&, unsigned int&, unsigned int&>(unsigned int, unsigned int&&&, unsigned int&&&, unsigned int&&&, unsigned int&&&)
Line
Count
Source
1098
1
                                 UseArgsTy &&... Args) {
1099
1
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
1
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
1
    return MIB;
1102
1
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<llvm::LLT&, unsigned int&, unsigned int&>(unsigned int, llvm::LLT&&&, unsigned int&&&, unsigned int&&&)
Line
Count
Source
1098
1
                                 UseArgsTy &&... Args) {
1099
1
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
1
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
1
    return MIB;
1102
1
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<unsigned int&, llvm::MachineInstrBuilder&, unsigned int&>(unsigned int, unsigned int&&&, llvm::MachineInstrBuilder&&&, unsigned int&&&)
Line
Count
Source
1098
1
                                 UseArgsTy &&... Args) {
1099
1
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
1
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
1
    return MIB;
1102
1
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<llvm::LLT&, unsigned int>(unsigned int, llvm::LLT&&&, unsigned int&&)
Line
Count
Source
1098
451k
                                 UseArgsTy &&... Args) {
1099
451k
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
451k
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
451k
    return MIB;
1102
451k
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<unsigned int, unsigned int&>(unsigned int, unsigned int&&, unsigned int&&&)
Line
Count
Source
1098
1.13M
                                 UseArgsTy &&... Args) {
1099
1.13M
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
1.13M
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
1.13M
    return MIB;
1102
1.13M
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<llvm::LLT&, llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder>(unsigned int, llvm::LLT&&&, llvm::MachineInstrBuilder&&&, llvm::MachineInstrBuilder&&)
Line
Count
Source
1098
7
                                 UseArgsTy &&... Args) {
1099
7
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
7
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
7
    return MIB;
1102
7
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<llvm::LLT&, llvm::MachineInstrBuilder&>(unsigned int, llvm::LLT&&&, llvm::MachineInstrBuilder&&&)
Line
Count
Source
1098
14
                                 UseArgsTy &&... Args) {
1099
14
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
14
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
14
    return MIB;
1102
14
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<llvm::LLT&, unsigned int&>(unsigned int, llvm::LLT&&&, unsigned int&&&)
Line
Count
Source
1098
3
                                 UseArgsTy &&... Args) {
1099
3
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
3
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
3
    return MIB;
1102
3
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<llvm::LLT&, unsigned int&, llvm::MachineInstrBuilder&>(unsigned int, llvm::LLT&&&, unsigned int&&&, llvm::MachineInstrBuilder&&&)
Line
Count
Source
1098
7
                                 UseArgsTy &&... Args) {
1099
7
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
7
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
7
    return MIB;
1102
7
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<llvm::LLT&, unsigned int&, llvm::MachineInstrBuilder>(unsigned int, llvm::LLT&&&, unsigned int&&&, llvm::MachineInstrBuilder&&)
Line
Count
Source
1098
5
                                 UseArgsTy &&... Args) {
1099
5
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
5
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
5
    return MIB;
1102
5
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<unsigned int, llvm::MachineInstrBuilder, llvm::MachineInstrBuilder&>(unsigned int, unsigned int&&, llvm::MachineInstrBuilder&&, llvm::MachineInstrBuilder&&&)
Line
Count
Source
1098
1
                                 UseArgsTy &&... Args) {
1099
1
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
1
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
1
    return MIB;
1102
1
  }
llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildInstr<unsigned int, llvm::MachineInstrBuilder&, llvm::MachineInstrBuilder>(unsigned int, unsigned int&&, llvm::MachineInstrBuilder&&&, llvm::MachineInstrBuilder&&)
Line
Count
Source
1098
1
                                 UseArgsTy &&... Args) {
1099
1
    auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty));
1100
1
    addUsesFromArgs(MIB, std::forward<UseArgsTy>(Args)...);
1101
1
    return MIB;
1102
1
  }
1103
};
1104
1105
} // End namespace llvm.
1106
#endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H