Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
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//===- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file declares the API for the register bank info.
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/// This API is responsible for handling the register banks.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
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#define LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Hashing.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cassert>
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#include <initializer_list>
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#include <memory>
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namespace llvm {
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class MachineInstr;
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class MachineRegisterInfo;
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class raw_ostream;
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class RegisterBank;
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class TargetInstrInfo;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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/// Holds all the information related to register banks.
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class RegisterBankInfo {
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public:
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  /// Helper struct that represents how a value is partially mapped
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  /// into a register.
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  /// The StartIdx and Length represent what region of the orginal
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  /// value this partial mapping covers.
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  /// This can be represented as a Mask of contiguous bit starting
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  /// at StartIdx bit and spanning Length bits.
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  /// StartIdx is the number of bits from the less significant bits.
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  struct PartialMapping {
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    /// Number of bits at which this partial mapping starts in the
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    /// original value.  The bits are counted from less significant
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    /// bits to most significant bits.
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    unsigned StartIdx;
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    /// Length of this mapping in bits. This is how many bits this
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    /// partial mapping covers in the original value:
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    /// from StartIdx to StartIdx + Length -1.
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    unsigned Length;
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    /// Register bank where the partial value lives.
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    const RegisterBank *RegBank;
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    PartialMapping() = default;
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    /// Provide a shortcut for quickly building PartialMapping.
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    PartialMapping(unsigned StartIdx, unsigned Length,
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                   const RegisterBank &RegBank)
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9.47M
        : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {}
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    /// \return the index of in the original value of the most
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    /// significant bit that this partial mapping covers.
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0
    unsigned getHighBitIdx() const { return StartIdx + Length - 1; }
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    /// Print this partial mapping on dbgs() stream.
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    void dump() const;
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    /// Print this partial mapping on \p OS;
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    void print(raw_ostream &OS) const;
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    /// Check that the Mask is compatible with the RegBank.
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    /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
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    /// there is no way this mapping is valid.
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    ///
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    /// \note This method does not check anything when assertions are disabled.
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    ///
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    /// \return True is the check was successful.
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    bool verify() const;
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  };
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  /// Helper struct that represents how a value is mapped through
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  /// different register banks.
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  ///
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  /// \note: So far we do not have any users of the complex mappings
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  /// (mappings with more than one partial mapping), but when we do,
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  /// we would have needed to duplicate partial mappings.
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  /// The alternative could be to use an array of pointers of partial
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  /// mapping (i.e., PartialMapping **BreakDown) and duplicate the
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  /// pointers instead.
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  ///
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  /// E.g.,
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  /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
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  /// can expand the
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  /// <2 x 32-bit> add into 2 x 32-bit add.
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  ///
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  /// Currently the TableGen-like file would look like:
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  /// \code
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  /// PartialMapping[] = {
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  /// /*32-bit add*/    {0, 32, GPR}, // Scalar entry repeated for first vec elt.
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  /// /*2x32-bit add*/  {0, 32, GPR}, {32, 32, GPR},
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  /// /*<2x32-bit> vadd {0, 64, VPR}
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  /// }; // PartialMapping duplicated.
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  ///
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  /// ValueMapping[] {
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  ///   /*plain 32-bit add*/ {&PartialMapping[0], 1},
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  ///   /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2},
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  ///   /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1}
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  /// };
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  /// \endcode
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  ///
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  /// With the array of pointer, we would have:
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  /// \code
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  /// PartialMapping[] = {
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  /// /*32-bit add lower */ {0, 32, GPR},
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  /// /*32-bit add upper */ {32, 32, GPR},
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  /// /*<2x32-bit> vadd {0, 64, VPR}
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  /// }; // No more duplication.
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  ///
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  /// BreakDowns[] = {
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  /// /*AddBreakDown*/ &PartialMapping[0],
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  /// /*2xAddBreakDown*/ &PartialMapping[0], &PartialMapping[1],
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  /// /*VAddBreakDown*/ &PartialMapping[2]
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  /// }; // Addresses of PartialMapping duplicated (smaller).
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  ///
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  /// ValueMapping[] {
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  ///   /*plain 32-bit add*/ {&BreakDowns[0], 1},
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  ///   /*expanded vadd on 2xadd*/ {&BreakDowns[1], 2},
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  ///   /*plain <2x32-bit> vadd*/ {&BreakDowns[3], 1}
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  /// };
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  /// \endcode
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  ///
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  /// Given that a PartialMapping is actually small, the code size
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  /// impact is actually a degradation. Moreover the compile time will
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  /// be hit by the additional indirection.
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  /// If PartialMapping gets bigger we may reconsider.
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  struct ValueMapping {
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    /// How the value is broken down between the different register banks.
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    const PartialMapping *BreakDown;
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    /// Number of partial mapping to break down this value.
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    unsigned NumBreakDowns;
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    /// The default constructor creates an invalid (isValid() == false)
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    /// instance.
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    ValueMapping() : ValueMapping(nullptr, 0) {}
Unexecuted instantiation: llvm::RegisterBankInfo::ValueMapping::ValueMapping()
llvm::RegisterBankInfo::ValueMapping::ValueMapping()
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237k
    ValueMapping() : ValueMapping(nullptr, 0) {}
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    /// Initialize a ValueMapping with the given parameter.
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    /// \p BreakDown needs to have a life time at least as long
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    /// as this instance.
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    ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns)
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14.0M
        : BreakDown(BreakDown), NumBreakDowns(NumBreakDowns) {}
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    /// Iterators through the PartialMappings.
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11.8k
    const PartialMapping *begin() const { return BreakDown; }
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0
    const PartialMapping *end() const { return BreakDown + NumBreakDowns; }
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    /// \return true if all partial mappings are the same size and register
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    /// bank.
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    bool partsAllUniform() const;
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    /// Check if this ValueMapping is valid.
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14.4M
    bool isValid() const { return BreakDown && NumBreakDowns; }
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    /// Verify that this mapping makes sense for a value of
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    /// \p MeaningfulBitWidth.
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    /// \note This method does not check anything when assertions are disabled.
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    ///
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    /// \return True is the check was successful.
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    bool verify(unsigned MeaningfulBitWidth) const;
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    /// Print this on dbgs() stream.
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    void dump() const;
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    /// Print this on \p OS;
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    void print(raw_ostream &OS) const;
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  };
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  /// Helper class that represents how the value of an instruction may be
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  /// mapped and what is the related cost of such mapping.
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  class InstructionMapping {
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    /// Identifier of the mapping.
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    /// This is used to communicate between the target and the optimizers
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    /// which mapping should be realized.
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    unsigned ID = InvalidMappingID;
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    /// Cost of this mapping.
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    unsigned Cost = 0;
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    /// Mapping of all the operands.
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    const ValueMapping *OperandsMapping = nullptr;
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    /// Number of operands.
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    unsigned NumOperands = 0;
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38.5M
    const ValueMapping &getOperandMapping(unsigned i) {
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38.5M
      assert(i < getNumOperands() && "Out of bound operand");
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38.5M
      return OperandsMapping[i];
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38.5M
    }
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  public:
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    /// Constructor for the mapping of an instruction.
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    /// \p NumOperands must be equal to number of all the operands of
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    /// the related instruction.
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    /// The rationale is that it is more efficient for the optimizers
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    /// to be able to assume that the mapping of the ith operand is
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    /// at the index i.
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    InstructionMapping(unsigned ID, unsigned Cost,
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                       const ValueMapping *OperandsMapping,
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                       unsigned NumOperands)
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        : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping),
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          NumOperands(NumOperands) {
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138k
    }
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    /// Default constructor.
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    /// Use this constructor to express that the mapping is invalid.
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    InstructionMapping() = default;
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    /// Get the cost.
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16.2M
    unsigned getCost() const { return Cost; }
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    /// Get the ID.
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33.0M
    unsigned getID() const { return ID; }
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    /// Get the number of operands.
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48.8M
    unsigned getNumOperands() const { return NumOperands; }
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    /// Get the value mapping of the ith operand.
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    /// \pre The mapping for the ith operand has been set.
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    /// \pre The ith operand is a register.
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38.5M
    const ValueMapping &getOperandMapping(unsigned i) const {
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38.5M
      const ValueMapping &ValMapping =
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38.5M
          const_cast<InstructionMapping *>(this)->getOperandMapping(i);
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38.5M
      return ValMapping;
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38.5M
    }
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    /// Set the mapping for all the operands.
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    /// In other words, OpdsMapping should hold at least getNumOperands
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    /// ValueMapping.
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0
    void setOperandsMapping(const ValueMapping *OpdsMapping) {
247
0
      OperandsMapping = OpdsMapping;
248
0
    }
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    /// Check whether this object is valid.
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    /// This is a lightweight check for obvious wrong instance.
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16.8M
    bool isValid() const {
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16.8M
      return getID() != InvalidMappingID && 
OperandsMapping16.8M
;
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16.8M
    }
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    /// Verifiy that this mapping makes sense for \p MI.
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    /// \pre \p MI must be connected to a MachineFunction.
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    ///
259
    /// \note This method does not check anything when assertions are disabled.
260
    ///
261
    /// \return True is the check was successful.
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    bool verify(const MachineInstr &MI) const;
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    /// Print this on dbgs() stream.
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    void dump() const;
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    /// Print this on \p OS;
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    void print(raw_ostream &OS) const;
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  };
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  /// Convenient type to represent the alternatives for mapping an
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  /// instruction.
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  /// \todo When we move to TableGen this should be an array ref.
274
  using InstructionMappings = SmallVector<const InstructionMapping *, 4>;
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  /// Helper class used to get/create the virtual registers that will be used
277
  /// to replace the MachineOperand when applying a mapping.
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  class OperandsMapper {
279
    /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the
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    /// OpIdx-th operand starts. -1 means we do not have such mapping yet.
281
    /// Note: We use a SmallVector to avoid heap allocation for most cases.
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    SmallVector<int, 8> OpToNewVRegIdx;
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    /// Hold the registers that will be used to map MI with InstrMapping.
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    SmallVector<Register, 8> NewVRegs;
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    /// Current MachineRegisterInfo, used to create new virtual registers.
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    MachineRegisterInfo &MRI;
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    /// Instruction being remapped.
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    MachineInstr &MI;
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    /// New mapping of the instruction.
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    const InstructionMapping &InstrMapping;
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296
    /// Constant value identifying that the index in OpToNewVRegIdx
297
    /// for an operand has not been set yet.
298
    static const int DontKnowIdx;
299
300
    /// Get the range in NewVRegs to store all the partial
301
    /// values for the \p OpIdx-th operand.
302
    ///
303
    /// \return The iterator range for the space created.
304
    //
305
    /// \pre getMI().getOperand(OpIdx).isReg()
306
    iterator_range<SmallVectorImpl<Register>::iterator>
307
    getVRegsMem(unsigned OpIdx);
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309
    /// Get the end iterator for a range starting at \p StartIdx and
310
    /// spannig \p NumVal in NewVRegs.
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    /// \pre StartIdx + NumVal <= NewVRegs.size()
312
    SmallVectorImpl<Register>::const_iterator
313
    getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const;
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    SmallVectorImpl<Register>::iterator getNewVRegsEnd(unsigned StartIdx,
315
                                                       unsigned NumVal);
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  public:
318
    /// Create an OperandsMapper that will hold the information to apply \p
319
    /// InstrMapping to \p MI.
320
    /// \pre InstrMapping.verify(MI)
321
    OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping,
322
                   MachineRegisterInfo &MRI);
323
324
    /// \name Getters.
325
    /// @{
326
    /// The MachineInstr being remapped.
327
16.2M
    MachineInstr &getMI() const { return MI; }
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    /// The final mapping of the instruction.
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32.5M
    const InstructionMapping &getInstrMapping() const { return InstrMapping; }
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332
    /// The MachineRegisterInfo we used to realize the mapping.
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16.2M
    MachineRegisterInfo &getMRI() const { return MRI; }
334
    /// @}
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    /// Create as many new virtual registers as needed for the mapping of the \p
337
    /// OpIdx-th operand.
338
    /// The number of registers is determined by the number of breakdown for the
339
    /// related operand in the instruction mapping.
340
    /// The type of the new registers is a plain scalar of the right size.
341
    /// The proper type is expected to be set when the mapping is applied to
342
    /// the instruction(s) that realizes the mapping.
343
    ///
344
    /// \pre getMI().getOperand(OpIdx).isReg()
345
    ///
346
    /// \post All the partial mapping of the \p OpIdx-th operand have been
347
    /// assigned a new virtual register.
348
    void createVRegs(unsigned OpIdx);
349
350
    /// Set the virtual register of the \p PartialMapIdx-th partial mapping of
351
    /// the OpIdx-th operand to \p NewVReg.
352
    ///
353
    /// \pre getMI().getOperand(OpIdx).isReg()
354
    /// \pre getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() >
355
    /// PartialMapIdx
356
    /// \pre NewReg != 0
357
    ///
358
    /// \post the \p PartialMapIdx-th register of the value mapping of the \p
359
    /// OpIdx-th operand has been set.
360
    void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg);
361
362
    /// Get all the virtual registers required to map the \p OpIdx-th operand of
363
    /// the instruction.
364
    ///
365
    /// This return an empty range when createVRegs or setVRegs has not been
366
    /// called.
367
    /// The iterator may be invalidated by a call to setVRegs or createVRegs.
368
    ///
369
    /// When \p ForDebug is true, we will not check that the list of new virtual
370
    /// registers does not contain uninitialized values.
371
    ///
372
    /// \pre getMI().getOperand(OpIdx).isReg()
373
    /// \pre ForDebug || All partial mappings have been set a register
374
    iterator_range<SmallVectorImpl<Register>::const_iterator>
375
    getVRegs(unsigned OpIdx, bool ForDebug = false) const;
376
377
    /// Print this operands mapper on dbgs() stream.
378
    void dump() const;
379
380
    /// Print this operands mapper on \p OS stream.
381
    void print(raw_ostream &OS, bool ForDebug = false) const;
382
  };
383
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protected:
385
  /// Hold the set of supported register banks.
386
  RegisterBank **RegBanks;
387
388
  /// Total number of register banks.
389
  unsigned NumRegBanks;
390
391
  /// Keep dynamically allocated PartialMapping in a separate map.
392
  /// This shouldn't be needed when everything gets TableGen'ed.
393
  mutable DenseMap<unsigned, std::unique_ptr<const PartialMapping>>
394
      MapOfPartialMappings;
395
396
  /// Keep dynamically allocated ValueMapping in a separate map.
397
  /// This shouldn't be needed when everything gets TableGen'ed.
398
  mutable DenseMap<unsigned, std::unique_ptr<const ValueMapping>>
399
      MapOfValueMappings;
400
401
  /// Keep dynamically allocated array of ValueMapping in a separate map.
402
  /// This shouldn't be needed when everything gets TableGen'ed.
403
  mutable DenseMap<unsigned, std::unique_ptr<ValueMapping[]>>
404
      MapOfOperandsMappings;
405
406
  /// Keep dynamically allocated InstructionMapping in a separate map.
407
  /// This shouldn't be needed when everything gets TableGen'ed.
408
  mutable DenseMap<unsigned, std::unique_ptr<const InstructionMapping>>
409
      MapOfInstructionMappings;
410
411
  /// Getting the minimal register class of a physreg is expensive.
412
  /// Cache this information as we get it.
413
  mutable DenseMap<unsigned, const TargetRegisterClass *> PhysRegMinimalRCs;
414
415
  /// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks
416
  /// RegisterBank instances.
417
  RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks);
418
419
  /// This constructor is meaningless.
420
  /// It just provides a default constructor that can be used at link time
421
  /// when GlobalISel is not built.
422
  /// That way, targets can still inherit from this class without doing
423
  /// crazy gymnastic to avoid link time failures.
424
  /// \note That works because the constructor is inlined.
425
0
  RegisterBankInfo() {
426
0
    llvm_unreachable("This constructor should not be executed");
427
0
  }
428
429
  /// Get the register bank identified by \p ID.
430
30.0M
  RegisterBank &getRegBank(unsigned ID) {
431
30.0M
    assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
432
30.0M
    return *RegBanks[ID];
433
30.0M
  }
434
435
  /// Get the MinimalPhysRegClass for Reg.
436
  /// \pre Reg is a physical register.
437
  const TargetRegisterClass &
438
  getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const;
439
440
  /// Try to get the mapping of \p MI.
441
  /// See getInstrMapping for more details on what a mapping represents.
442
  ///
443
  /// Unlike getInstrMapping the returned InstructionMapping may be invalid
444
  /// (isValid() == false).
445
  /// This means that the target independent code is not smart enough
446
  /// to get the mapping of \p MI and thus, the target has to provide the
447
  /// information for \p MI.
448
  ///
449
  /// This implementation is able to get the mapping of:
450
  /// - Target specific instructions by looking at the encoding constraints.
451
  /// - Any instruction if all the register operands have already been assigned
452
  ///   a register, a register class, or a register bank.
453
  /// - Copies and phis if at least one of the operands has been assigned a
454
  ///   register, a register class, or a register bank.
455
  /// In other words, this method will likely fail to find a mapping for
456
  /// any generic opcode that has not been lowered by target specific code.
457
  const InstructionMapping &getInstrMappingImpl(const MachineInstr &MI) const;
458
459
  /// Get the uniquely generated PartialMapping for the
460
  /// given arguments.
461
  const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length,
462
                                          const RegisterBank &RegBank) const;
463
464
  /// \name Methods to get a uniquely generated ValueMapping.
465
  /// @{
466
467
  /// The most common ValueMapping consists of a single PartialMapping.
468
  /// Feature a method for that.
469
  const ValueMapping &getValueMapping(unsigned StartIdx, unsigned Length,
470
                                      const RegisterBank &RegBank) const;
471
472
  /// Get the ValueMapping for the given arguments.
473
  const ValueMapping &getValueMapping(const PartialMapping *BreakDown,
474
                                      unsigned NumBreakDowns) const;
475
  /// @}
476
477
  /// \name Methods to get a uniquely generated array of ValueMapping.
478
  /// @{
479
480
  /// Get the uniquely generated array of ValueMapping for the
481
  /// elements of between \p Begin and \p End.
482
  ///
483
  /// Elements that are nullptr will be replaced by
484
  /// invalid ValueMapping (ValueMapping::isValid == false).
485
  ///
486
  /// \pre The pointers on ValueMapping between \p Begin and \p End
487
  /// must uniquely identify a ValueMapping. Otherwise, there is no
488
  /// guarantee that the return instance will be unique, i.e., another
489
  /// OperandsMapping could have the same content.
490
  template <typename Iterator>
491
  const ValueMapping *getOperandsMapping(Iterator Begin, Iterator End) const;
492
493
  /// Get the uniquely generated array of ValueMapping for the
494
  /// elements of \p OpdsMapping.
495
  ///
496
  /// Elements of \p OpdsMapping that are nullptr will be replaced by
497
  /// invalid ValueMapping (ValueMapping::isValid == false).
498
  const ValueMapping *getOperandsMapping(
499
      const SmallVectorImpl<const ValueMapping *> &OpdsMapping) const;
500
501
  /// Get the uniquely generated array of ValueMapping for the
502
  /// given arguments.
503
  ///
504
  /// Arguments that are nullptr will be replaced by invalid
505
  /// ValueMapping (ValueMapping::isValid == false).
506
  const ValueMapping *getOperandsMapping(
507
      std::initializer_list<const ValueMapping *> OpdsMapping) const;
508
  /// @}
509
510
  /// \name Methods to get a uniquely generated InstructionMapping.
511
  /// @{
512
513
private:
514
  /// Method to get a uniquely generated InstructionMapping.
515
  const InstructionMapping &
516
  getInstructionMappingImpl(bool IsInvalid, unsigned ID = InvalidMappingID,
517
                            unsigned Cost = 0,
518
                            const ValueMapping *OperandsMapping = nullptr,
519
                            unsigned NumOperands = 0) const;
520
521
public:
522
  /// Method to get a uniquely generated InstructionMapping.
523
  const InstructionMapping &
524
  getInstructionMapping(unsigned ID, unsigned Cost,
525
                        const ValueMapping *OperandsMapping,
526
16.2M
                        unsigned NumOperands) const {
527
16.2M
    return getInstructionMappingImpl(/*IsInvalid*/ false, ID, Cost,
528
16.2M
                                     OperandsMapping, NumOperands);
529
16.2M
  }
530
531
  /// Method to get a uniquely generated invalid InstructionMapping.
532
4.40k
  const InstructionMapping &getInvalidInstructionMapping() const {
533
4.40k
    return getInstructionMappingImpl(/*IsInvalid*/ true);
534
4.40k
  }
535
  /// @}
536
537
  /// Get the register bank for the \p OpIdx-th operand of \p MI form
538
  /// the encoding constraints, if any.
539
  ///
540
  /// \return A register bank that covers the register class of the
541
  /// related encoding constraints or nullptr if \p MI did not provide
542
  /// enough information to deduce it.
543
  const RegisterBank *
544
  getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
545
                            const TargetInstrInfo &TII,
546
                            const TargetRegisterInfo &TRI) const;
547
548
  /// Helper method to apply something that is like the default mapping.
549
  /// Basically, that means that \p OpdMapper.getMI() is left untouched
550
  /// aside from the reassignment of the register operand that have been
551
  /// remapped.
552
  ///
553
  /// The type of all the new registers that have been created by the
554
  /// mapper are properly remapped to the type of the original registers
555
  /// they replace. In other words, the semantic of the instruction does
556
  /// not change, only the register banks.
557
  ///
558
  /// If the mapping of one of the operand spans several registers, this
559
  /// method will abort as this is not like a default mapping anymore.
560
  ///
561
  /// \pre For OpIdx in {0..\p OpdMapper.getMI().getNumOperands())
562
  ///        the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.
563
  static void applyDefaultMapping(const OperandsMapper &OpdMapper);
564
565
  /// See ::applyMapping.
566
0
  virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const {
567
0
    llvm_unreachable("The target has to implement that part");
568
0
  }
569
570
public:
571
34.0k
  virtual ~RegisterBankInfo() = default;
572
573
  /// Get the register bank identified by \p ID.
574
30.0M
  const RegisterBank &getRegBank(unsigned ID) const {
575
30.0M
    return const_cast<RegisterBankInfo *>(this)->getRegBank(ID);
576
30.0M
  }
577
578
  /// Get the register bank of \p Reg.
579
  /// If Reg has not been assigned a register, a register class,
580
  /// or a register bank, then this returns nullptr.
581
  ///
582
  /// \pre Reg != 0 (NoRegister)
583
  const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
584
                                 const TargetRegisterInfo &TRI) const;
585
586
  /// Get the total number of register banks.
587
2.06k
  unsigned getNumRegBanks() const { return NumRegBanks; }
588
589
  /// Get a register bank that covers \p RC.
590
  ///
591
  /// \pre \p RC is a user-defined register class (as opposed as one
592
  /// generated by TableGen).
593
  ///
594
  /// \note The mapping RC -> RegBank could be built while adding the
595
  /// coverage for the register banks. However, we do not do it, because,
596
  /// at least for now, we only need this information for register classes
597
  /// that are used in the description of instruction. In other words,
598
  /// there are just a handful of them and we do not want to waste space.
599
  ///
600
  /// \todo This should be TableGen'ed.
601
  virtual const RegisterBank &
602
0
  getRegBankFromRegClass(const TargetRegisterClass &RC) const {
603
0
    llvm_unreachable("The target must override this method");
604
0
  }
605
606
  /// Get the cost of a copy from \p B to \p A, or put differently,
607
  /// get the cost of A = COPY B. Since register banks may cover
608
  /// different size, \p Size specifies what will be the size in bits
609
  /// that will be copied around.
610
  ///
611
  /// \note Since this is a copy, both registers have the same size.
612
  virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
613
5.04M
                            unsigned Size) const {
614
5.04M
    // Optimistically assume that copies are coalesced. I.e., when
615
5.04M
    // they are on the same bank, they are free.
616
5.04M
    // Otherwise assume a non-zero cost of 1. The targets are supposed
617
5.04M
    // to override that properly anyway if they care.
618
5.04M
    return &A != &B;
619
5.04M
  }
620
621
  /// \returns true if emitting a copy from \p Src to \p Dst is impossible.
622
  bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src,
623
905k
                  unsigned Size) const {
624
905k
    return copyCost(Dst, Src, Size) == std::numeric_limits<unsigned>::max();
625
905k
  }
626
627
  /// Get the cost of using \p ValMapping to decompose a register. This is
628
  /// similar to ::copyCost, except for cases where multiple copy-like
629
  /// operations need to be inserted. If the register is used as a source
630
  /// operand and already has a bank assigned, \p CurBank is non-null.
631
  virtual unsigned getBreakDownCost(const ValueMapping &ValMapping,
632
0
                                    const RegisterBank *CurBank = nullptr) const {
633
0
    return std::numeric_limits<unsigned>::max();
634
0
  }
635
636
  /// Constrain the (possibly generic) virtual register \p Reg to \p RC.
637
  ///
638
  /// \pre \p Reg is a virtual register that either has a bank or a class.
639
  /// \returns The constrained register class, or nullptr if there is none.
640
  /// \note This is a generic variant of MachineRegisterInfo::constrainRegClass
641
  /// \note Use MachineRegisterInfo::constrainRegAttrs instead for any non-isel
642
  /// purpose, including non-select passes of GlobalISel
643
  static const TargetRegisterClass *
644
  constrainGenericRegister(Register Reg, const TargetRegisterClass &RC,
645
                           MachineRegisterInfo &MRI);
646
647
  /// Identifier used when the related instruction mapping instance
648
  /// is generated by target independent code.
649
  /// Make sure not to use that identifier to avoid possible collision.
650
  static const unsigned DefaultMappingID;
651
652
  /// Identifier used when the related instruction mapping instance
653
  /// is generated by the default constructor.
654
  /// Make sure not to use that identifier.
655
  static const unsigned InvalidMappingID;
656
657
  /// Get the mapping of the different operands of \p MI
658
  /// on the register bank.
659
  /// This mapping should be the direct translation of \p MI.
660
  /// In other words, when \p MI is mapped with the returned mapping,
661
  /// only the register banks of the operands of \p MI need to be updated.
662
  /// In particular, neither the opcode nor the type of \p MI needs to be
663
  /// updated for this direct mapping.
664
  ///
665
  /// The target independent implementation gives a mapping based on
666
  /// the register classes for the target specific opcode.
667
  /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping.
668
  /// Make sure you do not use that ID for the alternative mapping
669
  /// for MI. See getInstrAlternativeMappings for the alternative
670
  /// mappings.
671
  ///
672
  /// For instance, if \p MI is a vector add, the mapping should
673
  /// not be a scalarization of the add.
674
  ///
675
  /// \post returnedVal.verify(MI).
676
  ///
677
  /// \note If returnedVal does not verify MI, this would probably mean
678
  /// that the target does not support that instruction.
679
  virtual const InstructionMapping &
680
  getInstrMapping(const MachineInstr &MI) const;
681
682
  /// Get the alternative mappings for \p MI.
683
  /// Alternative in the sense different from getInstrMapping.
684
  virtual InstructionMappings
685
  getInstrAlternativeMappings(const MachineInstr &MI) const;
686
687
  /// Get the possible mapping for \p MI.
688
  /// A mapping defines where the different operands may live and at what cost.
689
  /// For instance, let us consider:
690
  /// v0(16) = G_ADD <2 x i8> v1, v2
691
  /// The possible mapping could be:
692
  ///
693
  /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)},
694
  ///                              /*v2*/{(0xFFFF, VPR)}}
695
  /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)},
696
  ///                                /*v1*/{(0x00FF, GPR),(0xFF00, GPR)},
697
  ///                                /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}}
698
  ///
699
  /// \note The first alternative of the returned mapping should be the
700
  /// direct translation of \p MI current form.
701
  ///
702
  /// \post !returnedVal.empty().
703
  InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const;
704
705
  /// Apply \p OpdMapper.getInstrMapping() to \p OpdMapper.getMI().
706
  /// After this call \p OpdMapper.getMI() may not be valid anymore.
707
  /// \p OpdMapper.getInstrMapping().getID() carries the information of
708
  /// what has been chosen to map \p OpdMapper.getMI(). This ID is set
709
  /// by the various getInstrXXXMapping method.
710
  ///
711
  /// Therefore, getting the mapping and applying it should be kept in
712
  /// sync.
713
16.2M
  void applyMapping(const OperandsMapper &OpdMapper) const {
714
16.2M
    // The only mapping we know how to handle is the default mapping.
715
16.2M
    if (OpdMapper.getInstrMapping().getID() == DefaultMappingID)
716
16.2M
      return applyDefaultMapping(OpdMapper);
717
2.96k
    // For other mapping, the target needs to do the right thing.
718
2.96k
    // If that means calling applyDefaultMapping, fine, but this
719
2.96k
    // must be explicitly stated.
720
2.96k
    applyMappingImpl(OpdMapper);
721
2.96k
  }
722
723
  /// Get the size in bits of \p Reg.
724
  /// Utility method to get the size of any registers. Unlike
725
  /// MachineRegisterInfo::getSize, the register does not need to be a
726
  /// virtual register.
727
  ///
728
  /// \pre \p Reg != 0 (NoRegister).
729
  unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI,
730
                         const TargetRegisterInfo &TRI) const;
731
732
  /// Check that information hold by this instance make sense for the
733
  /// given \p TRI.
734
  ///
735
  /// \note This method does not check anything when assertions are disabled.
736
  ///
737
  /// \return True is the check was successful.
738
  bool verify(const TargetRegisterInfo &TRI) const;
739
};
740
741
inline raw_ostream &
742
operator<<(raw_ostream &OS,
743
0
           const RegisterBankInfo::PartialMapping &PartMapping) {
744
0
  PartMapping.print(OS);
745
0
  return OS;
746
0
}
747
748
inline raw_ostream &
749
0
operator<<(raw_ostream &OS, const RegisterBankInfo::ValueMapping &ValMapping) {
750
0
  ValMapping.print(OS);
751
0
  return OS;
752
0
}
753
754
inline raw_ostream &
755
operator<<(raw_ostream &OS,
756
0
           const RegisterBankInfo::InstructionMapping &InstrMapping) {
757
0
  InstrMapping.print(OS);
758
0
  return OS;
759
0
}
760
761
inline raw_ostream &
762
0
operator<<(raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper) {
763
0
  OpdMapper.print(OS, /*ForDebug*/ false);
764
0
  return OS;
765
0
}
766
767
/// Hashing function for PartialMapping.
768
/// It is required for the hashing of ValueMapping.
769
hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping);
770
771
} // end namespace llvm
772
773
#endif // LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H