Coverage Report

Created: 2018-09-23 16:00

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
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//===- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ---------------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file declares the API for the register bank info.
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/// This API is responsible for handling the register banks.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
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#define LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Hashing.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cassert>
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#include <initializer_list>
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#include <memory>
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namespace llvm {
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class MachineInstr;
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class MachineRegisterInfo;
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class raw_ostream;
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class RegisterBank;
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class TargetInstrInfo;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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/// Holds all the information related to register banks.
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class RegisterBankInfo {
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public:
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  /// Helper struct that represents how a value is partially mapped
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  /// into a register.
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  /// The StartIdx and Length represent what region of the orginal
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  /// value this partial mapping covers.
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  /// This can be represented as a Mask of contiguous bit starting
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  /// at StartIdx bit and spanning Length bits.
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  /// StartIdx is the number of bits from the less significant bits.
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  struct PartialMapping {
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    /// Number of bits at which this partial mapping starts in the
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    /// original value.  The bits are counted from less significant
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    /// bits to most significant bits.
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    unsigned StartIdx;
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    /// Length of this mapping in bits. This is how many bits this
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    /// partial mapping covers in the original value:
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    /// from StartIdx to StartIdx + Length -1.
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    unsigned Length;
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    /// Register bank where the partial value lives.
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    const RegisterBank *RegBank;
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61
    PartialMapping() = default;
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    /// Provide a shortcut for quickly building PartialMapping.
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    PartialMapping(unsigned StartIdx, unsigned Length,
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                   const RegisterBank &RegBank)
66
3.44M
        : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {}
67
68
    /// \return the index of in the original value of the most
69
    /// significant bit that this partial mapping covers.
70
0
    unsigned getHighBitIdx() const { return StartIdx + Length - 1; }
71
72
    /// Print this partial mapping on dbgs() stream.
73
    void dump() const;
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75
    /// Print this partial mapping on \p OS;
76
    void print(raw_ostream &OS) const;
77
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    /// Check that the Mask is compatible with the RegBank.
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    /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
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    /// there is no way this mapping is valid.
81
    ///
82
    /// \note This method does not check anything when assertions are disabled.
83
    ///
84
    /// \return True is the check was successful.
85
    bool verify() const;
86
  };
87
88
  /// Helper struct that represents how a value is mapped through
89
  /// different register banks.
90
  ///
91
  /// \note: So far we do not have any users of the complex mappings
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  /// (mappings with more than one partial mapping), but when we do,
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  /// we would have needed to duplicate partial mappings.
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  /// The alternative could be to use an array of pointers of partial
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  /// mapping (i.e., PartialMapping **BreakDown) and duplicate the
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  /// pointers instead.
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  ///
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  /// E.g.,
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  /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
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  /// can expand the
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  /// <2 x 32-bit> add into 2 x 32-bit add.
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  ///
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  /// Currently the TableGen-like file would look like:
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  /// \code
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  /// PartialMapping[] = {
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  /// /*32-bit add*/ {0, 32, GPR},
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  /// /*2x32-bit add*/ {0, 32, GPR}, {0, 32, GPR}, // <-- Same entry 3x
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  /// /*<2x32-bit> vadd {0, 64, VPR}
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  /// }; // PartialMapping duplicated.
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  ///
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  /// ValueMapping[] {
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  ///   /*plain 32-bit add*/ {&PartialMapping[0], 1},
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  ///   /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2},
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  ///   /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1}
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  /// };
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  /// \endcode
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  ///
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  /// With the array of pointer, we would have:
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  /// \code
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  /// PartialMapping[] = {
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  /// /*32-bit add*/ {0, 32, GPR},
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  /// /*<2x32-bit> vadd {0, 64, VPR}
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  /// }; // No more duplication.
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  ///
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  /// BreakDowns[] = {
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  /// /*AddBreakDown*/ &PartialMapping[0],
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  /// /*2xAddBreakDown*/ &PartialMapping[0], &PartialMapping[0],
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  /// /*VAddBreakDown*/ &PartialMapping[1]
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  /// }; // Addresses of PartialMapping duplicated (smaller).
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  ///
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  /// ValueMapping[] {
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  ///   /*plain 32-bit add*/ {&BreakDowns[0], 1},
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  ///   /*expanded vadd on 2xadd*/ {&BreakDowns[1], 2},
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  ///   /*plain <2x32-bit> vadd*/ {&BreakDowns[3], 1}
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  /// };
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  /// \endcode
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  ///
138
  /// Given that a PartialMapping is actually small, the code size
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  /// impact is actually a degradation. Moreover the compile time will
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  /// be hit by the additional indirection.
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  /// If PartialMapping gets bigger we may reconsider.
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  struct ValueMapping {
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    /// How the value is broken down between the different register banks.
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    const PartialMapping *BreakDown;
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    /// Number of partial mapping to break down this value.
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    unsigned NumBreakDowns;
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    /// The default constructor creates an invalid (isValid() == false)
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    /// instance.
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182k
    ValueMapping() : ValueMapping(nullptr, 0) {}
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    /// Initialize a ValueMapping with the given parameter.
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    /// \p BreakDown needs to have a life time at least as long
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    /// as this instance.
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    ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns)
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10.6M
        : BreakDown(BreakDown), NumBreakDowns(NumBreakDowns) {}
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    /// Iterators through the PartialMappings.
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8.91k
    const PartialMapping *begin() const { return BreakDown; }
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0
    const PartialMapping *end() const { return BreakDown + NumBreakDowns; }
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    /// Check if this ValueMapping is valid.
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11.7M
    bool isValid() const { return BreakDown && NumBreakDowns; }
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    /// Verify that this mapping makes sense for a value of
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    /// \p MeaningfulBitWidth.
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    /// \note This method does not check anything when assertions are disabled.
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    ///
170
    /// \return True is the check was successful.
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    bool verify(unsigned MeaningfulBitWidth) const;
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    /// Print this on dbgs() stream.
174
    void dump() const;
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    /// Print this on \p OS;
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    void print(raw_ostream &OS) const;
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  };
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  /// Helper class that represents how the value of an instruction may be
181
  /// mapped and what is the related cost of such mapping.
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  class InstructionMapping {
183
    /// Identifier of the mapping.
184
    /// This is used to communicate between the target and the optimizers
185
    /// which mapping should be realized.
186
    unsigned ID = InvalidMappingID;
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    /// Cost of this mapping.
189
    unsigned Cost = 0;
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    /// Mapping of all the operands.
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    const ValueMapping *OperandsMapping;
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    /// Number of operands.
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    unsigned NumOperands = 0;
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197
32.7M
    const ValueMapping &getOperandMapping(unsigned i) {
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32.7M
      assert(i < getNumOperands() && "Out of bound operand");
199
32.7M
      return OperandsMapping[i];
200
32.7M
    }
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202
  public:
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    /// Constructor for the mapping of an instruction.
204
    /// \p NumOperands must be equal to number of all the operands of
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    /// the related instruction.
206
    /// The rationale is that it is more efficient for the optimizers
207
    /// to be able to assume that the mapping of the ith operand is
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    /// at the index i.
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    ///
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    /// \pre ID != InvalidMappingID
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    InstructionMapping(unsigned ID, unsigned Cost,
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                       const ValueMapping *OperandsMapping,
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                       unsigned NumOperands)
214
        : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping),
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112k
          NumOperands(NumOperands) {
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112k
      assert(getID() != InvalidMappingID &&
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112k
             "Use the default constructor for invalid mapping");
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112k
    }
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    /// Default constructor.
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    /// Use this constructor to express that the mapping is invalid.
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    InstructionMapping() = default;
223
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    /// Get the cost.
225
14.3M
    unsigned getCost() const { return Cost; }
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    /// Get the ID.
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29.1M
    unsigned getID() const { return ID; }
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    /// Get the number of operands.
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43.1M
    unsigned getNumOperands() const { return NumOperands; }
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    /// Get the value mapping of the ith operand.
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    /// \pre The mapping for the ith operand has been set.
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    /// \pre The ith operand is a register.
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32.7M
    const ValueMapping &getOperandMapping(unsigned i) const {
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32.7M
      const ValueMapping &ValMapping =
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32.7M
          const_cast<InstructionMapping *>(this)->getOperandMapping(i);
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32.7M
      return ValMapping;
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32.7M
    }
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    /// Set the mapping for all the operands.
243
    /// In other words, OpdsMapping should hold at least getNumOperands
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    /// ValueMapping.
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0
    void setOperandsMapping(const ValueMapping *OpdsMapping) {
246
0
      OperandsMapping = OpdsMapping;
247
0
    }
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    /// Check whether this object is valid.
250
    /// This is a lightweight check for obvious wrong instance.
251
14.8M
    bool isValid() const {
252
14.8M
      return getID() != InvalidMappingID && 
OperandsMapping14.8M
;
253
14.8M
    }
254
255
    /// Verifiy that this mapping makes sense for \p MI.
256
    /// \pre \p MI must be connected to a MachineFunction.
257
    ///
258
    /// \note This method does not check anything when assertions are disabled.
259
    ///
260
    /// \return True is the check was successful.
261
    bool verify(const MachineInstr &MI) const;
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263
    /// Print this on dbgs() stream.
264
    void dump() const;
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    /// Print this on \p OS;
267
    void print(raw_ostream &OS) const;
268
  };
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270
  /// Convenient type to represent the alternatives for mapping an
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  /// instruction.
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  /// \todo When we move to TableGen this should be an array ref.
273
  using InstructionMappings = SmallVector<const InstructionMapping *, 4>;
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275
  /// Helper class used to get/create the virtual registers that will be used
276
  /// to replace the MachineOperand when applying a mapping.
277
  class OperandsMapper {
278
    /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the
279
    /// OpIdx-th operand starts. -1 means we do not have such mapping yet.
280
    /// Note: We use a SmallVector to avoid heap allocation for most cases.
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    SmallVector<int, 8> OpToNewVRegIdx;
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283
    /// Hold the registers that will be used to map MI with InstrMapping.
284
    SmallVector<unsigned, 8> NewVRegs;
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286
    /// Current MachineRegisterInfo, used to create new virtual registers.
287
    MachineRegisterInfo &MRI;
288
289
    /// Instruction being remapped.
290
    MachineInstr &MI;
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292
    /// New mapping of the instruction.
293
    const InstructionMapping &InstrMapping;
294
295
    /// Constant value identifying that the index in OpToNewVRegIdx
296
    /// for an operand has not been set yet.
297
    static const int DontKnowIdx;
298
299
    /// Get the range in NewVRegs to store all the partial
300
    /// values for the \p OpIdx-th operand.
301
    ///
302
    /// \return The iterator range for the space created.
303
    //
304
    /// \pre getMI().getOperand(OpIdx).isReg()
305
    iterator_range<SmallVectorImpl<unsigned>::iterator>
306
    getVRegsMem(unsigned OpIdx);
307
308
    /// Get the end iterator for a range starting at \p StartIdx and
309
    /// spannig \p NumVal in NewVRegs.
310
    /// \pre StartIdx + NumVal <= NewVRegs.size()
311
    SmallVectorImpl<unsigned>::const_iterator
312
    getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const;
313
    SmallVectorImpl<unsigned>::iterator getNewVRegsEnd(unsigned StartIdx,
314
                                                       unsigned NumVal);
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316
  public:
317
    /// Create an OperandsMapper that will hold the information to apply \p
318
    /// InstrMapping to \p MI.
319
    /// \pre InstrMapping.verify(MI)
320
    OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping,
321
                   MachineRegisterInfo &MRI);
322
323
    /// \name Getters.
324
    /// @{
325
    /// The MachineInstr being remapped.
326
14.3M
    MachineInstr &getMI() const { return MI; }
327
328
    /// The final mapping of the instruction.
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28.8M
    const InstructionMapping &getInstrMapping() const { return InstrMapping; }
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331
    /// The MachineRegisterInfo we used to realize the mapping.
332
14.3M
    MachineRegisterInfo &getMRI() const { return MRI; }
333
    /// @}
334
335
    /// Create as many new virtual registers as needed for the mapping of the \p
336
    /// OpIdx-th operand.
337
    /// The number of registers is determined by the number of breakdown for the
338
    /// related operand in the instruction mapping.
339
    /// The type of the new registers is a plain scalar of the right size.
340
    /// The proper type is expected to be set when the mapping is applied to
341
    /// the instruction(s) that realizes the mapping.
342
    ///
343
    /// \pre getMI().getOperand(OpIdx).isReg()
344
    ///
345
    /// \post All the partial mapping of the \p OpIdx-th operand have been
346
    /// assigned a new virtual register.
347
    void createVRegs(unsigned OpIdx);
348
349
    /// Set the virtual register of the \p PartialMapIdx-th partial mapping of
350
    /// the OpIdx-th operand to \p NewVReg.
351
    ///
352
    /// \pre getMI().getOperand(OpIdx).isReg()
353
    /// \pre getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() >
354
    /// PartialMapIdx
355
    /// \pre NewReg != 0
356
    ///
357
    /// \post the \p PartialMapIdx-th register of the value mapping of the \p
358
    /// OpIdx-th operand has been set.
359
    void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg);
360
361
    /// Get all the virtual registers required to map the \p OpIdx-th operand of
362
    /// the instruction.
363
    ///
364
    /// This return an empty range when createVRegs or setVRegs has not been
365
    /// called.
366
    /// The iterator may be invalidated by a call to setVRegs or createVRegs.
367
    ///
368
    /// When \p ForDebug is true, we will not check that the list of new virtual
369
    /// registers does not contain uninitialized values.
370
    ///
371
    /// \pre getMI().getOperand(OpIdx).isReg()
372
    /// \pre ForDebug || All partial mappings have been set a register
373
    iterator_range<SmallVectorImpl<unsigned>::const_iterator>
374
    getVRegs(unsigned OpIdx, bool ForDebug = false) const;
375
376
    /// Print this operands mapper on dbgs() stream.
377
    void dump() const;
378
379
    /// Print this operands mapper on \p OS stream.
380
    void print(raw_ostream &OS, bool ForDebug = false) const;
381
  };
382
383
protected:
384
  /// Hold the set of supported register banks.
385
  RegisterBank **RegBanks;
386
387
  /// Total number of register banks.
388
  unsigned NumRegBanks;
389
390
  /// Keep dynamically allocated PartialMapping in a separate map.
391
  /// This shouldn't be needed when everything gets TableGen'ed.
392
  mutable DenseMap<unsigned, std::unique_ptr<const PartialMapping>>
393
      MapOfPartialMappings;
394
395
  /// Keep dynamically allocated ValueMapping in a separate map.
396
  /// This shouldn't be needed when everything gets TableGen'ed.
397
  mutable DenseMap<unsigned, std::unique_ptr<const ValueMapping>>
398
      MapOfValueMappings;
399
400
  /// Keep dynamically allocated array of ValueMapping in a separate map.
401
  /// This shouldn't be needed when everything gets TableGen'ed.
402
  mutable DenseMap<unsigned, std::unique_ptr<ValueMapping[]>>
403
      MapOfOperandsMappings;
404
405
  /// Keep dynamically allocated InstructionMapping in a separate map.
406
  /// This shouldn't be needed when everything gets TableGen'ed.
407
  mutable DenseMap<unsigned, std::unique_ptr<const InstructionMapping>>
408
      MapOfInstructionMappings;
409
410
  /// Getting the minimal register class of a physreg is expensive.
411
  /// Cache this information as we get it.
412
  mutable DenseMap<unsigned, const TargetRegisterClass *> PhysRegMinimalRCs;
413
414
  /// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks
415
  /// RegisterBank instances.
416
  RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks);
417
418
  /// This constructor is meaningless.
419
  /// It just provides a default constructor that can be used at link time
420
  /// when GlobalISel is not built.
421
  /// That way, targets can still inherit from this class without doing
422
  /// crazy gymnastic to avoid link time failures.
423
  /// \note That works because the constructor is inlined.
424
  RegisterBankInfo() {
425
    llvm_unreachable("This constructor should not be executed");
426
  }
427
428
  /// Get the register bank identified by \p ID.
429
14.2M
  RegisterBank &getRegBank(unsigned ID) {
430
14.2M
    assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
431
14.2M
    return *RegBanks[ID];
432
14.2M
  }
433
434
  /// Get the MinimalPhysRegClass for Reg.
435
  /// \pre Reg is a physical register.
436
  const TargetRegisterClass &
437
  getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const;
438
439
  /// Try to get the mapping of \p MI.
440
  /// See getInstrMapping for more details on what a mapping represents.
441
  ///
442
  /// Unlike getInstrMapping the returned InstructionMapping may be invalid
443
  /// (isValid() == false).
444
  /// This means that the target independent code is not smart enough
445
  /// to get the mapping of \p MI and thus, the target has to provide the
446
  /// information for \p MI.
447
  ///
448
  /// This implementation is able to get the mapping of:
449
  /// - Target specific instructions by looking at the encoding constraints.
450
  /// - Any instruction if all the register operands have already been assigned
451
  ///   a register, a register class, or a register bank.
452
  /// - Copies and phis if at least one of the operands has been assigned a
453
  ///   register, a register class, or a register bank.
454
  /// In other words, this method will likely fail to find a mapping for
455
  /// any generic opcode that has not been lowered by target specific code.
456
  const InstructionMapping &getInstrMappingImpl(const MachineInstr &MI) const;
457
458
  /// Get the uniquely generated PartialMapping for the
459
  /// given arguments.
460
  const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length,
461
                                          const RegisterBank &RegBank) const;
462
463
  /// \name Methods to get a uniquely generated ValueMapping.
464
  /// @{
465
466
  /// The most common ValueMapping consists of a single PartialMapping.
467
  /// Feature a method for that.
468
  const ValueMapping &getValueMapping(unsigned StartIdx, unsigned Length,
469
                                      const RegisterBank &RegBank) const;
470
471
  /// Get the ValueMapping for the given arguments.
472
  const ValueMapping &getValueMapping(const PartialMapping *BreakDown,
473
                                      unsigned NumBreakDowns) const;
474
  /// @}
475
476
  /// \name Methods to get a uniquely generated array of ValueMapping.
477
  /// @{
478
479
  /// Get the uniquely generated array of ValueMapping for the
480
  /// elements of between \p Begin and \p End.
481
  ///
482
  /// Elements that are nullptr will be replaced by
483
  /// invalid ValueMapping (ValueMapping::isValid == false).
484
  ///
485
  /// \pre The pointers on ValueMapping between \p Begin and \p End
486
  /// must uniquely identify a ValueMapping. Otherwise, there is no
487
  /// guarantee that the return instance will be unique, i.e., another
488
  /// OperandsMapping could have the same content.
489
  template <typename Iterator>
490
  const ValueMapping *getOperandsMapping(Iterator Begin, Iterator End) const;
491
492
  /// Get the uniquely generated array of ValueMapping for the
493
  /// elements of \p OpdsMapping.
494
  ///
495
  /// Elements of \p OpdsMapping that are nullptr will be replaced by
496
  /// invalid ValueMapping (ValueMapping::isValid == false).
497
  const ValueMapping *getOperandsMapping(
498
      const SmallVectorImpl<const ValueMapping *> &OpdsMapping) const;
499
500
  /// Get the uniquely generated array of ValueMapping for the
501
  /// given arguments.
502
  ///
503
  /// Arguments that are nullptr will be replaced by invalid
504
  /// ValueMapping (ValueMapping::isValid == false).
505
  const ValueMapping *getOperandsMapping(
506
      std::initializer_list<const ValueMapping *> OpdsMapping) const;
507
  /// @}
508
509
  /// \name Methods to get a uniquely generated InstructionMapping.
510
  /// @{
511
512
private:
513
  /// Method to get a uniquely generated InstructionMapping.
514
  const InstructionMapping &
515
  getInstructionMappingImpl(bool IsInvalid, unsigned ID = InvalidMappingID,
516
                            unsigned Cost = 0,
517
                            const ValueMapping *OperandsMapping = nullptr,
518
                            unsigned NumOperands = 0) const;
519
520
public:
521
  /// Method to get a uniquely generated InstructionMapping.
522
  const InstructionMapping &
523
  getInstructionMapping(unsigned ID, unsigned Cost,
524
                        const ValueMapping *OperandsMapping,
525
14.3M
                        unsigned NumOperands) const {
526
14.3M
    return getInstructionMappingImpl(/*IsInvalid*/ false, ID, Cost,
527
14.3M
                                     OperandsMapping, NumOperands);
528
14.3M
  }
529
530
  /// Method to get a uniquely generated invalid InstructionMapping.
531
536
  const InstructionMapping &getInvalidInstructionMapping() const {
532
536
    return getInstructionMappingImpl(/*IsInvalid*/ true);
533
536
  }
534
  /// @}
535
536
  /// Get the register bank for the \p OpIdx-th operand of \p MI form
537
  /// the encoding constraints, if any.
538
  ///
539
  /// \return A register bank that covers the register class of the
540
  /// related encoding constraints or nullptr if \p MI did not provide
541
  /// enough information to deduce it.
542
  const RegisterBank *
543
  getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
544
                            const TargetInstrInfo &TII,
545
                            const TargetRegisterInfo &TRI) const;
546
547
  /// Helper method to apply something that is like the default mapping.
548
  /// Basically, that means that \p OpdMapper.getMI() is left untouched
549
  /// aside from the reassignment of the register operand that have been
550
  /// remapped.
551
  ///
552
  /// The type of all the new registers that have been created by the
553
  /// mapper are properly remapped to the type of the original registers
554
  /// they replace. In other words, the semantic of the instruction does
555
  /// not change, only the register banks.
556
  ///
557
  /// If the mapping of one of the operand spans several registers, this
558
  /// method will abort as this is not like a default mapping anymore.
559
  ///
560
  /// \pre For OpIdx in {0..\p OpdMapper.getMI().getNumOperands())
561
  ///        the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.
562
  static void applyDefaultMapping(const OperandsMapper &OpdMapper);
563
564
  /// See ::applyMapping.
565
0
  virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const {
566
0
    llvm_unreachable("The target has to implement that part");
567
0
  }
568
569
public:
570
28.7k
  virtual ~RegisterBankInfo() = default;
571
572
  /// Get the register bank identified by \p ID.
573
14.2M
  const RegisterBank &getRegBank(unsigned ID) const {
574
14.2M
    return const_cast<RegisterBankInfo *>(this)->getRegBank(ID);
575
14.2M
  }
576
577
  /// Get the register bank of \p Reg.
578
  /// If Reg has not been assigned a register, a register class,
579
  /// or a register bank, then this returns nullptr.
580
  ///
581
  /// \pre Reg != 0 (NoRegister)
582
  const RegisterBank *getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
583
                                 const TargetRegisterInfo &TRI) const;
584
585
  /// Get the total number of register banks.
586
1.05k
  unsigned getNumRegBanks() const { return NumRegBanks; }
587
588
  /// Get a register bank that covers \p RC.
589
  ///
590
  /// \pre \p RC is a user-defined register class (as opposed as one
591
  /// generated by TableGen).
592
  ///
593
  /// \note The mapping RC -> RegBank could be built while adding the
594
  /// coverage for the register banks. However, we do not do it, because,
595
  /// at least for now, we only need this information for register classes
596
  /// that are used in the description of instruction. In other words,
597
  /// there are just a handful of them and we do not want to waste space.
598
  ///
599
  /// \todo This should be TableGen'ed.
600
  virtual const RegisterBank &
601
0
  getRegBankFromRegClass(const TargetRegisterClass &RC) const {
602
0
    llvm_unreachable("The target must override this method");
603
0
  }
604
605
  /// Get the cost of a copy from \p B to \p A, or put differently,
606
  /// get the cost of A = COPY B. Since register banks may cover
607
  /// different size, \p Size specifies what will be the size in bits
608
  /// that will be copied around.
609
  ///
610
  /// \note Since this is a copy, both registers have the same size.
611
  virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
612
4.54M
                            unsigned Size) const {
613
4.54M
    // Optimistically assume that copies are coalesced. I.e., when
614
4.54M
    // they are on the same bank, they are free.
615
4.54M
    // Otherwise assume a non-zero cost of 1. The targets are supposed
616
4.54M
    // to override that properly anyway if they care.
617
4.54M
    return &A != &B;
618
4.54M
  }
619
620
  /// Constrain the (possibly generic) virtual register \p Reg to \p RC.
621
  ///
622
  /// \pre \p Reg is a virtual register that either has a bank or a class.
623
  /// \returns The constrained register class, or nullptr if there is none.
624
  /// \note This is a generic variant of MachineRegisterInfo::constrainRegClass
625
  /// \note Use MachineRegisterInfo::constrainRegAttrs instead for any non-isel
626
  /// purpose, including non-select passes of GlobalISel
627
  static const TargetRegisterClass *
628
  constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC,
629
                           MachineRegisterInfo &MRI);
630
631
  /// Identifier used when the related instruction mapping instance
632
  /// is generated by target independent code.
633
  /// Make sure not to use that identifier to avoid possible collision.
634
  static const unsigned DefaultMappingID;
635
636
  /// Identifier used when the related instruction mapping instance
637
  /// is generated by the default constructor.
638
  /// Make sure not to use that identifier.
639
  static const unsigned InvalidMappingID;
640
641
  /// Get the mapping of the different operands of \p MI
642
  /// on the register bank.
643
  /// This mapping should be the direct translation of \p MI.
644
  /// In other words, when \p MI is mapped with the returned mapping,
645
  /// only the register banks of the operands of \p MI need to be updated.
646
  /// In particular, neither the opcode nor the type of \p MI needs to be
647
  /// updated for this direct mapping.
648
  ///
649
  /// The target independent implementation gives a mapping based on
650
  /// the register classes for the target specific opcode.
651
  /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping.
652
  /// Make sure you do not use that ID for the alternative mapping
653
  /// for MI. See getInstrAlternativeMappings for the alternative
654
  /// mappings.
655
  ///
656
  /// For instance, if \p MI is a vector add, the mapping should
657
  /// not be a scalarization of the add.
658
  ///
659
  /// \post returnedVal.verify(MI).
660
  ///
661
  /// \note If returnedVal does not verify MI, this would probably mean
662
  /// that the target does not support that instruction.
663
  virtual const InstructionMapping &
664
  getInstrMapping(const MachineInstr &MI) const;
665
666
  /// Get the alternative mappings for \p MI.
667
  /// Alternative in the sense different from getInstrMapping.
668
  virtual InstructionMappings
669
  getInstrAlternativeMappings(const MachineInstr &MI) const;
670
671
  /// Get the possible mapping for \p MI.
672
  /// A mapping defines where the different operands may live and at what cost.
673
  /// For instance, let us consider:
674
  /// v0(16) = G_ADD <2 x i8> v1, v2
675
  /// The possible mapping could be:
676
  ///
677
  /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)},
678
  ///                              /*v2*/{(0xFFFF, VPR)}}
679
  /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)},
680
  ///                                /*v1*/{(0x00FF, GPR),(0xFF00, GPR)},
681
  ///                                /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}}
682
  ///
683
  /// \note The first alternative of the returned mapping should be the
684
  /// direct translation of \p MI current form.
685
  ///
686
  /// \post !returnedVal.empty().
687
  InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const;
688
689
  /// Apply \p OpdMapper.getInstrMapping() to \p OpdMapper.getMI().
690
  /// After this call \p OpdMapper.getMI() may not be valid anymore.
691
  /// \p OpdMapper.getInstrMapping().getID() carries the information of
692
  /// what has been chosen to map \p OpdMapper.getMI(). This ID is set
693
  /// by the various getInstrXXXMapping method.
694
  ///
695
  /// Therefore, getting the mapping and applying it should be kept in
696
  /// sync.
697
14.3M
  void applyMapping(const OperandsMapper &OpdMapper) const {
698
14.3M
    // The only mapping we know how to handle is the default mapping.
699
14.3M
    if (OpdMapper.getInstrMapping().getID() == DefaultMappingID)
700
14.3M
      return applyDefaultMapping(OpdMapper);
701
366
    // For other mapping, the target needs to do the right thing.
702
366
    // If that means calling applyDefaultMapping, fine, but this
703
366
    // must be explicitly stated.
704
366
    applyMappingImpl(OpdMapper);
705
366
  }
706
707
  /// Get the size in bits of \p Reg.
708
  /// Utility method to get the size of any registers. Unlike
709
  /// MachineRegisterInfo::getSize, the register does not need to be a
710
  /// virtual register.
711
  ///
712
  /// \pre \p Reg != 0 (NoRegister).
713
  unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI,
714
                         const TargetRegisterInfo &TRI) const;
715
716
  /// Check that information hold by this instance make sense for the
717
  /// given \p TRI.
718
  ///
719
  /// \note This method does not check anything when assertions are disabled.
720
  ///
721
  /// \return True is the check was successful.
722
  bool verify(const TargetRegisterInfo &TRI) const;
723
};
724
725
inline raw_ostream &
726
operator<<(raw_ostream &OS,
727
0
           const RegisterBankInfo::PartialMapping &PartMapping) {
728
0
  PartMapping.print(OS);
729
0
  return OS;
730
0
}
731
732
inline raw_ostream &
733
0
operator<<(raw_ostream &OS, const RegisterBankInfo::ValueMapping &ValMapping) {
734
0
  ValMapping.print(OS);
735
0
  return OS;
736
0
}
737
738
inline raw_ostream &
739
operator<<(raw_ostream &OS,
740
0
           const RegisterBankInfo::InstructionMapping &InstrMapping) {
741
0
  InstrMapping.print(OS);
742
0
  return OS;
743
0
}
744
745
inline raw_ostream &
746
0
operator<<(raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper) {
747
0
  OpdMapper.print(OS, /*ForDebug*/ false);
748
0
  return OS;
749
0
}
750
751
/// Hashing function for PartialMapping.
752
/// It is required for the hashing of ValueMapping.
753
hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping);
754
755
} // end namespace llvm
756
757
#endif // LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H