Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
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//==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file declares the API of helper functions used throughout the
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/// GlobalISel pipeline.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
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#define LLVM_CODEGEN_GLOBALISEL_UTILS_H
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/Register.h"
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namespace llvm {
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class AnalysisUsage;
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class MachineFunction;
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class MachineInstr;
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class MachineOperand;
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class MachineOptimizationRemarkEmitter;
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class MachineOptimizationRemarkMissed;
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class MachineRegisterInfo;
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class MCInstrDesc;
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class RegisterBankInfo;
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class TargetInstrInfo;
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class TargetPassConfig;
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class TargetRegisterInfo;
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class TargetRegisterClass;
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class Twine;
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class ConstantFP;
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class APFloat;
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/// Try to constrain Reg to the specified register class. If this fails,
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/// create a new virtual register in the correct class.
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///
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/// \return The virtual register constrained to the right register class.
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unsigned constrainRegToClass(MachineRegisterInfo &MRI,
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                             const TargetInstrInfo &TII,
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                             const RegisterBankInfo &RBI, unsigned Reg,
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                             const TargetRegisterClass &RegClass);
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/// Constrain the Register operand OpIdx, so that it is now constrained to the
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/// TargetRegisterClass passed as an argument (RegClass).
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/// If this fails, create a new virtual register in the correct class and
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/// insert a COPY before \p InsertPt if it is a use or after if it is a
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/// definition. The debug location of \p InsertPt is used for the new copy.
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///
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/// \return The virtual register constrained to the right register class.
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unsigned constrainOperandRegClass(const MachineFunction &MF,
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                                  const TargetRegisterInfo &TRI,
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                                  MachineRegisterInfo &MRI,
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                                  const TargetInstrInfo &TII,
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                                  const RegisterBankInfo &RBI,
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                                  MachineInstr &InsertPt,
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                                  const TargetRegisterClass &RegClass,
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                                  const MachineOperand &RegMO, unsigned OpIdx);
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/// Try to constrain Reg so that it is usable by argument OpIdx of the
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/// provided MCInstrDesc \p II. If this fails, create a new virtual
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/// register in the correct class and insert a COPY before \p InsertPt
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/// if it is a use or after if it is a definition.
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/// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
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/// with RegClass obtained from the MCInstrDesc. The debug location of \p
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/// InsertPt is used for the new copy.
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///
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/// \return The virtual register constrained to the right register class.
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unsigned constrainOperandRegClass(const MachineFunction &MF,
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                                  const TargetRegisterInfo &TRI,
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                                  MachineRegisterInfo &MRI,
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                                  const TargetInstrInfo &TII,
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                                  const RegisterBankInfo &RBI,
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                                  MachineInstr &InsertPt, const MCInstrDesc &II,
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                                  const MachineOperand &RegMO, unsigned OpIdx);
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/// Mutate the newly-selected instruction \p I to constrain its (possibly
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/// generic) virtual register operands to the instruction's register class.
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/// This could involve inserting COPYs before (for uses) or after (for defs).
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/// This requires the number of operands to match the instruction description.
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/// \returns whether operand regclass constraining succeeded.
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///
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// FIXME: Not all instructions have the same number of operands. We should
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// probably expose a constrain helper per operand and let the target selector
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// constrain individual registers, like fast-isel.
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bool constrainSelectedInstRegOperands(MachineInstr &I,
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                                      const TargetInstrInfo &TII,
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                                      const TargetRegisterInfo &TRI,
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                                      const RegisterBankInfo &RBI);
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/// Check whether an instruction \p MI is dead: it only defines dead virtual
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/// registers, and doesn't have other side effects.
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bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
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/// Report an ISel error as a missed optimization remark to the LLVMContext's
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/// diagnostic stream.  Set the FailedISel MachineFunction property.
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void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
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                        MachineOptimizationRemarkEmitter &MORE,
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                        MachineOptimizationRemarkMissed &R);
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void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
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                        MachineOptimizationRemarkEmitter &MORE,
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                        const char *PassName, StringRef Msg,
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                        const MachineInstr &MI);
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/// If \p VReg is defined by a G_CONSTANT fits in int64_t
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/// returns it.
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Optional<int64_t> getConstantVRegVal(unsigned VReg,
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                                     const MachineRegisterInfo &MRI);
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/// Simple struct used to hold a constant integer value and a virtual
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/// register.
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struct ValueAndVReg {
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  int64_t Value;
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  unsigned VReg;
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};
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/// If \p VReg is defined by a statically evaluable chain of
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/// instructions rooted on a G_CONSTANT (\p LookThroughInstrs == true)
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/// and that constant fits in int64_t, returns its value as well as
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/// the virtual register defined by this G_CONSTANT.
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/// When \p LookThroughInstrs == false, this function behaves like
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/// getConstantVRegVal.
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Optional<ValueAndVReg>
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getConstantVRegValWithLookThrough(unsigned VReg, const MachineRegisterInfo &MRI,
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                                  bool LookThroughInstrs = true);
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const ConstantFP* getConstantFPVRegVal(unsigned VReg,
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                                       const MachineRegisterInfo &MRI);
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/// See if Reg is defined by an single def instruction that is
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/// Opcode. Also try to do trivial folding if it's a COPY with
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/// same types. Returns null otherwise.
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MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
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                           const MachineRegisterInfo &MRI);
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/// Find the def instruction for \p Reg, folding away any trivial copies. Note
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/// it may still return a COPY, if it changes the type. May return nullptr if \p
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/// Reg is not a generic virtual register.
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MachineInstr *getDefIgnoringCopies(Register Reg,
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                                   const MachineRegisterInfo &MRI);
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/// Returns an APFloat from Val converted to the appropriate size.
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APFloat getAPFloatFromSize(double Val, unsigned Size);
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/// Modify analysis usage so it preserves passes required for the SelectionDAG
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/// fallback.
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void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU);
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Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const unsigned Op1,
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                                  const unsigned Op2,
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                                  const MachineRegisterInfo &MRI);
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/// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
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/// this returns if \p Val can be assumed to never be a signaling NaN.
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bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
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                     bool SNaN = false);
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/// Returns true if \p Val can be assumed to never be a signaling NaN.
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inline bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI) {
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  return isKnownNeverNaN(Val, MRI, true);
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}
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} // End namespace llvm.
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#endif