Coverage Report

Created: 2019-02-23 12:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/ISDOpcodes.h
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//===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares codegen opcodes and related utilities.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_ISDOPCODES_H
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#define LLVM_CODEGEN_ISDOPCODES_H
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namespace llvm {
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/// ISD namespace - This namespace contains an enum which represents all of the
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/// SelectionDAG node types and value types.
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///
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namespace ISD {
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  //===--------------------------------------------------------------------===//
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  /// ISD::NodeType enum - This enum defines the target-independent operators
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  /// for a SelectionDAG.
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  ///
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  /// Targets may also define target-dependent operator codes for SDNodes. For
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  /// example, on x86, these are the enum values in the X86ISD namespace.
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  /// Targets should aim to use target-independent operators to model their
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  /// instruction sets as much as possible, and only use target-dependent
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  /// operators when they have special requirements.
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  ///
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  /// Finally, during and after selection proper, SNodes may use special
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  /// operator codes that correspond directly with MachineInstr opcodes. These
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  /// are used to represent selected instructions. See the isMachineOpcode()
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  /// and getMachineOpcode() member functions of SDNode.
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  ///
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  enum NodeType {
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    /// DELETED_NODE - This is an illegal value that is used to catch
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    /// errors.  This opcode is not a legal opcode for any node.
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    DELETED_NODE,
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    /// EntryToken - This is the marker used to indicate the start of a region.
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    EntryToken,
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    /// TokenFactor - This node takes multiple tokens as input and produces a
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    /// single token result. This is used to represent the fact that the operand
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    /// operators are independent of each other.
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    TokenFactor,
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    /// AssertSext, AssertZext - These nodes record if a register contains a
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    /// value that has already been zero or sign extended from a narrower type.
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    /// These nodes take two operands.  The first is the node that has already
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    /// been extended, and the second is a value type node indicating the width
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    /// of the extension
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    AssertSext, AssertZext,
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    /// Various leaf nodes.
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    BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
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    Constant, ConstantFP,
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    GlobalAddress, GlobalTLSAddress, FrameIndex,
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    JumpTable, ConstantPool, ExternalSymbol, BlockAddress,
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    /// The address of the GOT
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    GLOBAL_OFFSET_TABLE,
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    /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
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    /// llvm.returnaddress on the DAG.  These nodes take one operand, the index
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    /// of the frame or return address to return.  An index of zero corresponds
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    /// to the current function's frame or return address, an index of one to
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    /// the parent's frame or return address, and so on.
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    FRAMEADDR, RETURNADDR, ADDROFRETURNADDR, SPONENTRY,
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    /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
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    /// Materializes the offset from the local object pointer of another
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    /// function to a particular local object passed to llvm.localescape. The
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    /// operand is the MCSymbol label used to represent this offset, since
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    /// typically the offset is not known until after code generation of the
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    /// parent.
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    LOCAL_RECOVER,
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    /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on
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    /// the DAG, which implements the named register global variables extension.
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    READ_REGISTER,
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    WRITE_REGISTER,
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    /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
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    /// first (possible) on-stack argument. This is needed for correct stack
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    /// adjustment during unwind.
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    FRAME_TO_ARGS_OFFSET,
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    /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical
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    /// Frame Address (CFA), generally the value of the stack pointer at the
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    /// call site in the previous frame.
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    EH_DWARF_CFA,
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    /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
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    /// 'eh_return' gcc dwarf builtin, which is used to return from
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    /// exception. The general meaning is: adjust stack by OFFSET and pass
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    /// execution to HANDLER. Many platform-related details also :)
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    EH_RETURN,
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    /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
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    /// This corresponds to the eh.sjlj.setjmp intrinsic.
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    /// It takes an input chain and a pointer to the jump buffer as inputs
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    /// and returns an outchain.
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    EH_SJLJ_SETJMP,
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    /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
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    /// This corresponds to the eh.sjlj.longjmp intrinsic.
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    /// It takes an input chain and a pointer to the jump buffer as inputs
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    /// and returns an outchain.
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    EH_SJLJ_LONGJMP,
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    /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN)
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    /// The target initializes the dispatch table here.
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    EH_SJLJ_SETUP_DISPATCH,
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    /// TargetConstant* - Like Constant*, but the DAG does not do any folding,
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    /// simplification, or lowering of the constant. They are used for constants
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    /// which are known to fit in the immediate fields of their users, or for
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    /// carrying magic numbers which are not values which need to be
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    /// materialized in registers.
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    TargetConstant,
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    TargetConstantFP,
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    /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
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    /// anything else with this node, and this is valid in the target-specific
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    /// dag, turning into a GlobalAddress operand.
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    TargetGlobalAddress,
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    TargetGlobalTLSAddress,
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    TargetFrameIndex,
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    TargetJumpTable,
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    TargetConstantPool,
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    TargetExternalSymbol,
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    TargetBlockAddress,
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    MCSymbol,
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    /// TargetIndex - Like a constant pool entry, but with completely
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    /// target-dependent semantics. Holds target flags, a 32-bit index, and a
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    /// 64-bit index. Targets can use this however they like.
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    TargetIndex,
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    /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
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    /// This node represents a target intrinsic function with no side effects.
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    /// The first operand is the ID number of the intrinsic from the
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    /// llvm::Intrinsic namespace.  The operands to the intrinsic follow.  The
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    /// node returns the result of the intrinsic.
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    INTRINSIC_WO_CHAIN,
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    /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
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    /// This node represents a target intrinsic function with side effects that
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    /// returns a result.  The first operand is a chain pointer.  The second is
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    /// the ID number of the intrinsic from the llvm::Intrinsic namespace.  The
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    /// operands to the intrinsic follow.  The node has two results, the result
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    /// of the intrinsic and an output chain.
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    INTRINSIC_W_CHAIN,
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    /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
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    /// This node represents a target intrinsic function with side effects that
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    /// does not return a result.  The first operand is a chain pointer.  The
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    /// second is the ID number of the intrinsic from the llvm::Intrinsic
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    /// namespace.  The operands to the intrinsic follow.
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    INTRINSIC_VOID,
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    /// CopyToReg - This node has three operands: a chain, a register number to
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    /// set to this value, and a value.
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    CopyToReg,
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    /// CopyFromReg - This node indicates that the input value is a virtual or
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    /// physical register that is defined outside of the scope of this
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    /// SelectionDAG.  The register is available from the RegisterSDNode object.
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    CopyFromReg,
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    /// UNDEF - An undefined node.
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    UNDEF,
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    /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
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    /// a Constant, which is required to be operand #1) half of the integer or
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    /// float value specified as operand #0.  This is only for use before
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    /// legalization, for values that will be broken into multiple registers.
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    EXTRACT_ELEMENT,
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    /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
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    /// Given two values of the same integer value type, this produces a value
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    /// twice as big.  Like EXTRACT_ELEMENT, this can only be used before
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    /// legalization. The lower part of the composite value should be in
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    /// element 0 and the upper part should be in element 1.
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    BUILD_PAIR,
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    /// MERGE_VALUES - This node takes multiple discrete operands and returns
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    /// them all as its individual results.  This nodes has exactly the same
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    /// number of inputs and outputs. This node is useful for some pieces of the
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    /// code generator that want to think about a single node with multiple
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    /// results, not multiple nodes.
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    MERGE_VALUES,
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    /// Simple integer binary arithmetic operators.
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    ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
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    /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
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    /// a signed/unsigned value of type i[2*N], and return the full value as
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    /// two results, each of type iN.
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    SMUL_LOHI, UMUL_LOHI,
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    /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
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    /// remainder result.
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    SDIVREM, UDIVREM,
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    /// CARRY_FALSE - This node is used when folding other nodes,
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    /// like ADDC/SUBC, which indicate the carry result is always false.
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    CARRY_FALSE,
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    /// Carry-setting nodes for multiple precision addition and subtraction.
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    /// These nodes take two operands of the same value type, and produce two
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    /// results.  The first result is the normal add or sub result, the second
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    /// result is the carry flag result.
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    /// FIXME: These nodes are deprecated in favor of ADDCARRY and SUBCARRY.
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    /// They are kept around for now to provide a smooth transition path
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    /// toward the use of ADDCARRY/SUBCARRY and will eventually be removed.
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    ADDC, SUBC,
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    /// Carry-using nodes for multiple precision addition and subtraction. These
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    /// nodes take three operands: The first two are the normal lhs and rhs to
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    /// the add or sub, and the third is the input carry flag.  These nodes
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    /// produce two results; the normal result of the add or sub, and the output
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    /// carry flag.  These nodes both read and write a carry flag to allow them
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    /// to them to be chained together for add and sub of arbitrarily large
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    /// values.
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    ADDE, SUBE,
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    /// Carry-using nodes for multiple precision addition and subtraction.
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    /// These nodes take three operands: The first two are the normal lhs and
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    /// rhs to the add or sub, and the third is a boolean indicating if there
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    /// is an incoming carry. These nodes produce two results: the normal
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    /// result of the add or sub, and the output carry so they can be chained
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    /// together. The use of this opcode is preferable to adde/sube if the
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    /// target supports it, as the carry is a regular value rather than a
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    /// glue, which allows further optimisation.
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    ADDCARRY, SUBCARRY,
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    /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
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    /// These nodes take two operands: the normal LHS and RHS to the add. They
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    /// produce two results: the normal result of the add, and a boolean that
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    /// indicates if an overflow occurred (*not* a flag, because it may be store
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    /// to memory, etc.).  If the type of the boolean is not i1 then the high
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    /// bits conform to getBooleanContents.
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    /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
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    SADDO, UADDO,
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    /// Same for subtraction.
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    SSUBO, USUBO,
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    /// Same for multiplication.
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    SMULO, UMULO,
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    /// RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2
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    /// integers with the same bit width (W). If the true value of LHS + RHS
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    /// exceeds the largest value that can be represented by W bits, the
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    /// resulting value is this maximum value. Otherwise, if this value is less
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    /// than the smallest value that can be represented by W bits, the
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    /// resulting value is this minimum value.
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    SADDSAT, UADDSAT,
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    /// RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2
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    /// integers with the same bit width (W). If the true value of LHS - RHS
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    /// exceeds the largest value that can be represented by W bits, the
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    /// resulting value is this maximum value. Otherwise, if this value is less
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    /// than the smallest value that can be represented by W bits, the
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    /// resulting value is this minimum value.
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    SSUBSAT, USUBSAT,
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    /// RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on
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    /// 2 integers with the same width and scale. SCALE represents the scale of
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    /// both operands as fixed point numbers. This SCALE parameter must be a
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    /// constant integer. A scale of zero is effectively performing
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    /// multiplication on 2 integers.
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    SMULFIX, UMULFIX,
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    /// Simple binary floating point operators.
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    FADD, FSUB, FMUL, FDIV, FREM,
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    /// Constrained versions of the binary floating point operators.
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    /// These will be lowered to the simple operators before final selection.
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    /// They are used to limit optimizations while the DAG is being
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    /// optimized.
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    STRICT_FADD, STRICT_FSUB, STRICT_FMUL, STRICT_FDIV, STRICT_FREM,
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    STRICT_FMA,
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    /// Constrained versions of libm-equivalent floating point intrinsics.
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    /// These will be lowered to the equivalent non-constrained pseudo-op
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    /// (or expanded to the equivalent library call) before final selection.
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    /// They are used to limit optimizations while the DAG is being optimized.
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    STRICT_FSQRT, STRICT_FPOW, STRICT_FPOWI, STRICT_FSIN, STRICT_FCOS,
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    STRICT_FEXP, STRICT_FEXP2, STRICT_FLOG, STRICT_FLOG10, STRICT_FLOG2,
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    STRICT_FRINT, STRICT_FNEARBYINT, STRICT_FMAXNUM, STRICT_FMINNUM,
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    STRICT_FCEIL, STRICT_FFLOOR, STRICT_FROUND, STRICT_FTRUNC,
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    /// FMA - Perform a * b + c with no intermediate rounding step.
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    FMA,
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    /// FMAD - Perform a * b + c, while getting the same result as the
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    /// separately rounded operations.
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    FMAD,
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    /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.  NOTE: This
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    /// DAG node does not require that X and Y have the same type, just that
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    /// they are both floating point.  X and the result must have the same type.
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    /// FCOPYSIGN(f32, f64) is allowed.
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    FCOPYSIGN,
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    /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
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    /// value as an integer 0/1 value.
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    FGETSIGN,
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    /// Returns platform specific canonical encoding of a floating point number.
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    FCANONICALIZE,
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    /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the
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    /// specified, possibly variable, elements.  The number of elements is
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    /// required to be a power of two.  The types of the operands must all be
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    /// the same and must match the vector element type, except that integer
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    /// types are allowed to be larger than the element type, in which case
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    /// the operands are implicitly truncated.
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    BUILD_VECTOR,
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    /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
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    /// at IDX replaced with VAL.  If the type of VAL is larger than the vector
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    /// element type then VAL is truncated before replacement.
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    INSERT_VECTOR_ELT,
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    /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
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    /// identified by the (potentially variable) element number IDX.  If the
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    /// return type is an integer type larger than the element type of the
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    /// vector, the result is extended to the width of the return type. In
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    /// that case, the high bits are undefined.
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    EXTRACT_VECTOR_ELT,
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    /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
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    /// vector type with the same length and element type, this produces a
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    /// concatenated vector result value, with length equal to the sum of the
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    /// lengths of the input vectors.
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    CONCAT_VECTORS,
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    /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector
347
    /// with VECTOR2 inserted into VECTOR1 at the (potentially
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    /// variable) element number IDX, which must be a multiple of the
349
    /// VECTOR2 vector length.  The elements of VECTOR1 starting at
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    /// IDX are overwritten with VECTOR2.  Elements IDX through
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    /// vector_length(VECTOR2) must be valid VECTOR1 indices.
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    INSERT_SUBVECTOR,
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    /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an
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    /// vector value) starting with the element number IDX, which must be a
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    /// constant multiple of the result vector length.
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    EXTRACT_SUBVECTOR,
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    /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
360
    /// VEC1/VEC2.  A VECTOR_SHUFFLE node also contains an array of constant int
361
    /// values that indicate which value (or undef) each result element will
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    /// get.  These constant ints are accessible through the
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    /// ShuffleVectorSDNode class.  This is quite similar to the Altivec
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    /// 'vperm' instruction, except that the indices must be constants and are
365
    /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
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    VECTOR_SHUFFLE,
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    /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
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    /// scalar value into element 0 of the resultant vector type.  The top
370
    /// elements 1 to N-1 of the N-element vector are undefined.  The type
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    /// of the operand must match the vector element type, except when they
372
    /// are integer types.  In this case the operand is allowed to be wider
373
    /// than the vector element type, and is implicitly truncated to it.
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    SCALAR_TO_VECTOR,
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    /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
377
    /// producing an unsigned/signed value of type i[2*N], then return the top
378
    /// part.
379
    MULHU, MULHS,
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    /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned
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    /// integers.
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    SMIN, SMAX, UMIN, UMAX,
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    /// Bitwise operators - logical and, logical or, logical xor.
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    AND, OR, XOR,
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    /// ABS - Determine the unsigned absolute value of a signed integer value of
389
    /// the same bitwidth.
390
    /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow
391
    /// is performed.
392
    ABS,
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    /// Shift and rotation operations.  After legalization, the type of the
395
    /// shift amount is known to be TLI.getShiftAmountTy().  Before legalization
396
    /// the shift amount can be any type, but care must be taken to ensure it is
397
    /// large enough.  TLI.getShiftAmountTy() is i8 on some targets, but before
398
    /// legalization, types like i1024 can occur and i8 doesn't have enough bits
399
    /// to represent the shift amount.
400
    /// When the 1st operand is a vector, the shift amount must be in the same
401
    /// type. (TLI.getShiftAmountTy() will return the same type when the input
402
    /// type is a vector.)
403
    /// For rotates and funnel shifts, the shift amount is treated as an unsigned
404
    /// amount modulo the element size of the first operand.
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    ///
406
    /// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount.
407
    /// fshl(X,Y,Z): (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
408
    /// fshr(X,Y,Z): (X << (BW - (Z % BW))) | (Y >> (Z % BW))
409
    SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR,
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    /// Byte Swap and Counting operators.
412
    BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE,
413
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    /// Bit counting operators with an undefined result for zero inputs.
415
    CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,
416
417
    /// Select(COND, TRUEVAL, FALSEVAL).  If the type of the boolean COND is not
418
    /// i1 then the high bits must conform to getBooleanContents.
419
    SELECT,
420
421
    /// Select with a vector condition (op #0) and two vector operands (ops #1
422
    /// and #2), returning a vector result.  All vectors have the same length.
423
    /// Much like the scalar select and setcc, each bit in the condition selects
424
    /// whether the corresponding result element is taken from op #1 or op #2.
425
    /// At first, the VSELECT condition is of vXi1 type. Later, targets may
426
    /// change the condition type in order to match the VSELECT node using a
427
    /// pattern. The condition follows the BooleanContent format of the target.
428
    VSELECT,
429
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    /// Select with condition operator - This selects between a true value and
431
    /// a false value (ops #2 and #3) based on the boolean result of comparing
432
    /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
433
    /// condition code in op #4, a CondCodeSDNode.
434
    SELECT_CC,
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436
    /// SetCC operator - This evaluates to a true value iff the condition is
437
    /// true.  If the result value type is not i1 then the high bits conform
438
    /// to getBooleanContents.  The operands to this are the left and right
439
    /// operands to compare (ops #0, and #1) and the condition code to compare
440
    /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
441
    /// then the result type must also be a vector type.
442
    SETCC,
443
444
    /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
445
    /// op #2 is a boolean indicating if there is an incoming carry. This
446
    /// operator checks the result of "LHS - RHS - Carry", and can be used to
447
    /// compare two wide integers:
448
    /// (setcccarry lhshi rhshi (subcarry lhslo rhslo) cc).
449
    /// Only valid for integers.
450
    SETCCCARRY,
451
452
    /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
453
    /// integer shift operations.  The operation ordering is:
454
    ///       [Lo,Hi] = op [LoLHS,HiLHS], Amt
455
    SHL_PARTS, SRA_PARTS, SRL_PARTS,
456
457
    /// Conversion operators.  These are all single input single output
458
    /// operations.  For all of these, the result type must be strictly
459
    /// wider or narrower (depending on the operation) than the source
460
    /// type.
461
462
    /// SIGN_EXTEND - Used for integer types, replicating the sign bit
463
    /// into new bits.
464
    SIGN_EXTEND,
465
466
    /// ZERO_EXTEND - Used for integer types, zeroing the new bits.
467
    ZERO_EXTEND,
468
469
    /// ANY_EXTEND - Used for integer types.  The high bits are undefined.
470
    ANY_EXTEND,
471
472
    /// TRUNCATE - Completely drop the high bits.
473
    TRUNCATE,
474
475
    /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign
476
    /// depends on the first letter) to floating point.
477
    SINT_TO_FP,
478
    UINT_TO_FP,
479
480
    /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
481
    /// sign extend a small value in a large integer register (e.g. sign
482
    /// extending the low 8 bits of a 32-bit register to fill the top 24 bits
483
    /// with the 7th bit).  The size of the smaller type is indicated by the 1th
484
    /// operand, a ValueType node.
485
    SIGN_EXTEND_INREG,
486
487
    /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
488
    /// in-register any-extension of the low lanes of an integer vector. The
489
    /// result type must have fewer elements than the operand type, and those
490
    /// elements must be larger integer types such that the total size of the
491
    /// operand type is less than or equal to the size of the result type. Each
492
    /// of the low operand elements is any-extended into the corresponding,
493
    /// wider result elements with the high bits becoming undef.
494
    /// NOTE: The type legalizer prefers to make the operand and result size
495
    /// the same to allow expansion to shuffle vector during op legalization.
496
    ANY_EXTEND_VECTOR_INREG,
497
498
    /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
499
    /// in-register sign-extension of the low lanes of an integer vector. The
500
    /// result type must have fewer elements than the operand type, and those
501
    /// elements must be larger integer types such that the total size of the
502
    /// operand type is less than or equal to the size of the result type. Each
503
    /// of the low operand elements is sign-extended into the corresponding,
504
    /// wider result elements.
505
    /// NOTE: The type legalizer prefers to make the operand and result size
506
    /// the same to allow expansion to shuffle vector during op legalization.
507
    SIGN_EXTEND_VECTOR_INREG,
508
509
    /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an
510
    /// in-register zero-extension of the low lanes of an integer vector. The
511
    /// result type must have fewer elements than the operand type, and those
512
    /// elements must be larger integer types such that the total size of the
513
    /// operand type is less than or equal to the size of the result type. Each
514
    /// of the low operand elements is zero-extended into the corresponding,
515
    /// wider result elements.
516
    /// NOTE: The type legalizer prefers to make the operand and result size
517
    /// the same to allow expansion to shuffle vector during op legalization.
518
    ZERO_EXTEND_VECTOR_INREG,
519
520
    /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
521
    /// integer. These have the same semantics as fptosi and fptoui in IR. If
522
    /// the FP value cannot fit in the integer type, the results are undefined.
523
    FP_TO_SINT,
524
    FP_TO_UINT,
525
526
    /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
527
    /// down to the precision of the destination VT.  TRUNC is a flag, which is
528
    /// always an integer that is zero or one.  If TRUNC is 0, this is a
529
    /// normal rounding, if it is 1, this FP_ROUND is known to not change the
530
    /// value of Y.
531
    ///
532
    /// The TRUNC = 1 case is used in cases where we know that the value will
533
    /// not be modified by the node, because Y is not using any of the extra
534
    /// precision of source type.  This allows certain transformations like
535
    /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
536
    /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
537
    FP_ROUND,
538
539
    /// FLT_ROUNDS_ - Returns current rounding mode:
540
    /// -1 Undefined
541
    ///  0 Round to 0
542
    ///  1 Round to nearest
543
    ///  2 Round to +inf
544
    ///  3 Round to -inf
545
    FLT_ROUNDS_,
546
547
    /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and
548
    /// rounds it to a floating point value.  It then promotes it and returns it
549
    /// in a register of the same size.  This operation effectively just
550
    /// discards excess precision.  The type to round down to is specified by
551
    /// the VT operand, a VTSDNode.
552
    FP_ROUND_INREG,
553
554
    /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
555
    FP_EXTEND,
556
557
    /// BITCAST - This operator converts between integer, vector and FP
558
    /// values, as if the value was stored to memory with one type and loaded
559
    /// from the same address with the other type (or equivalently for vector
560
    /// format conversions, etc).  The source and result are required to have
561
    /// the same bit size (e.g.  f32 <-> i32).  This can also be used for
562
    /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
563
    /// getNode().
564
    ///
565
    /// This operator is subtly different from the bitcast instruction from
566
    /// LLVM-IR since this node may change the bits in the register. For
567
    /// example, this occurs on big-endian NEON and big-endian MSA where the
568
    /// layout of the bits in the register depends on the vector type and this
569
    /// operator acts as a shuffle operation for some vector type combinations.
570
    BITCAST,
571
572
    /// ADDRSPACECAST - This operator converts between pointers of different
573
    /// address spaces.
574
    ADDRSPACECAST,
575
576
    /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions
577
    /// and truncation for half-precision (16 bit) floating numbers. These nodes
578
    /// form a semi-softened interface for dealing with f16 (as an i16), which
579
    /// is often a storage-only type but has native conversions.
580
    FP16_TO_FP, FP_TO_FP16,
581
582
    /// Perform various unary floating-point operations inspired by libm. For
583
    /// FPOWI, the result is undefined if if the integer operand doesn't fit
584
    /// into 32 bits.
585
    FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW,
586
    FLOG, FLOG2, FLOG10, FEXP, FEXP2,
587
    FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR,
588
    /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
589
    /// values.
590
    //
591
    /// In the case where a single input is a NaN (either signaling or quiet),
592
    /// the non-NaN input is returned.
593
    ///
594
    /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
595
    FMINNUM, FMAXNUM,
596
597
    /// FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on
598
    /// two values, following the IEEE-754 2008 definition. This differs from
599
    /// FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
600
    /// signaling NaN, returns a quiet NaN.
601
    FMINNUM_IEEE, FMAXNUM_IEEE,
602
603
    /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
604
    /// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
605
    /// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics.
606
    FMINIMUM, FMAXIMUM,
607
608
    /// FSINCOS - Compute both fsin and fcos as a single operation.
609
    FSINCOS,
610
611
    /// LOAD and STORE have token chains as their first operand, then the same
612
    /// operands as an LLVM load/store instruction, then an offset node that
613
    /// is added / subtracted from the base pointer to form the address (for
614
    /// indexed memory ops).
615
    LOAD, STORE,
616
617
    /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned
618
    /// to a specified boundary.  This node always has two return values: a new
619
    /// stack pointer value and a chain. The first operand is the token chain,
620
    /// the second is the number of bytes to allocate, and the third is the
621
    /// alignment boundary.  The size is guaranteed to be a multiple of the
622
    /// stack alignment, and the alignment is guaranteed to be bigger than the
623
    /// stack alignment (if required) or 0 to get standard stack alignment.
624
    DYNAMIC_STACKALLOC,
625
626
    /// Control flow instructions.  These all have token chains.
627
628
    /// BR - Unconditional branch.  The first operand is the chain
629
    /// operand, the second is the MBB to branch to.
630
    BR,
631
632
    /// BRIND - Indirect branch.  The first operand is the chain, the second
633
    /// is the value to branch to, which must be of the same type as the
634
    /// target's pointer type.
635
    BRIND,
636
637
    /// BR_JT - Jumptable branch. The first operand is the chain, the second
638
    /// is the jumptable index, the last one is the jumptable entry index.
639
    BR_JT,
640
641
    /// BRCOND - Conditional branch.  The first operand is the chain, the
642
    /// second is the condition, the third is the block to branch to if the
643
    /// condition is true.  If the type of the condition is not i1, then the
644
    /// high bits must conform to getBooleanContents.
645
    BRCOND,
646
647
    /// BR_CC - Conditional branch.  The behavior is like that of SELECT_CC, in
648
    /// that the condition is represented as condition code, and two nodes to
649
    /// compare, rather than as a combined SetCC node.  The operands in order
650
    /// are chain, cc, lhs, rhs, block to branch to if condition is true.
651
    BR_CC,
652
653
    /// INLINEASM - Represents an inline asm block.  This node always has two
654
    /// return values: a chain and a flag result.  The inputs are as follows:
655
    ///   Operand #0  : Input chain.
656
    ///   Operand #1  : a ExternalSymbolSDNode with a pointer to the asm string.
657
    ///   Operand #2  : a MDNodeSDNode with the !srcloc metadata.
658
    ///   Operand #3  : HasSideEffect, IsAlignStack bits.
659
    ///   After this, it is followed by a list of operands with this format:
660
    ///     ConstantSDNode: Flags that encode whether it is a mem or not, the
661
    ///                     of operands that follow, etc.  See InlineAsm.h.
662
    ///     ... however many operands ...
663
    ///   Operand #last: Optional, an incoming flag.
664
    ///
665
    /// The variable width operands are required to represent target addressing
666
    /// modes as a single "operand", even though they may have multiple
667
    /// SDOperands.
668
    INLINEASM,
669
670
    /// INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
671
    INLINEASM_BR,
672
673
    /// EH_LABEL - Represents a label in mid basic block used to track
674
    /// locations needed for debug and exception handling tables.  These nodes
675
    /// take a chain as input and return a chain.
676
    EH_LABEL,
677
678
    /// ANNOTATION_LABEL - Represents a mid basic block label used by
679
    /// annotations. This should remain within the basic block and be ordered
680
    /// with respect to other call instructions, but loads and stores may float
681
    /// past it.
682
    ANNOTATION_LABEL,
683
684
    /// CATCHPAD - Represents a catchpad instruction.
685
    CATCHPAD,
686
687
    /// CATCHRET - Represents a return from a catch block funclet. Used for
688
    /// MSVC compatible exception handling. Takes a chain operand and a
689
    /// destination basic block operand.
690
    CATCHRET,
691
692
    /// CLEANUPRET - Represents a return from a cleanup block funclet.  Used for
693
    /// MSVC compatible exception handling. Takes only a chain operand.
694
    CLEANUPRET,
695
696
    /// STACKSAVE - STACKSAVE has one operand, an input chain.  It produces a
697
    /// value, the same type as the pointer type for the system, and an output
698
    /// chain.
699
    STACKSAVE,
700
701
    /// STACKRESTORE has two operands, an input chain and a pointer to restore
702
    /// to it returns an output chain.
703
    STACKRESTORE,
704
705
    /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end
706
    /// of a call sequence, and carry arbitrary information that target might
707
    /// want to know.  The first operand is a chain, the rest are specified by
708
    /// the target and not touched by the DAG optimizers.
709
    /// Targets that may use stack to pass call arguments define additional
710
    /// operands:
711
    /// - size of the call frame part that must be set up within the
712
    ///   CALLSEQ_START..CALLSEQ_END pair,
713
    /// - part of the call frame prepared prior to CALLSEQ_START.
714
    /// Both these parameters must be constants, their sum is the total call
715
    /// frame size.
716
    /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
717
    CALLSEQ_START,  // Beginning of a call sequence
718
    CALLSEQ_END,    // End of a call sequence
719
720
    /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
721
    /// and the alignment. It returns a pair of values: the vaarg value and a
722
    /// new chain.
723
    VAARG,
724
725
    /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer,
726
    /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
727
    /// source.
728
    VACOPY,
729
730
    /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain,
731
    /// pointer, and a SRCVALUE.
732
    VAEND, VASTART,
733
734
    /// SRCVALUE - This is a node type that holds a Value* that is used to
735
    /// make reference to a value in the LLVM IR.
736
    SRCVALUE,
737
738
    /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to
739
    /// reference metadata in the IR.
740
    MDNODE_SDNODE,
741
742
    /// PCMARKER - This corresponds to the pcmarker intrinsic.
743
    PCMARKER,
744
745
    /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
746
    /// It produces a chain and one i64 value. The only operand is a chain.
747
    /// If i64 is not legal, the result will be expanded into smaller values.
748
    /// Still, it returns an i64, so targets should set legality for i64.
749
    /// The result is the content of the architecture-specific cycle
750
    /// counter-like register (or other high accuracy low latency clock source).
751
    READCYCLECOUNTER,
752
753
    /// HANDLENODE node - Used as a handle for various purposes.
754
    HANDLENODE,
755
756
    /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.  It
757
    /// takes as input a token chain, the pointer to the trampoline, the pointer
758
    /// to the nested function, the pointer to pass for the 'nest' parameter, a
759
    /// SRCVALUE for the trampoline and another for the nested function
760
    /// (allowing targets to access the original Function*).
761
    /// It produces a token chain as output.
762
    INIT_TRAMPOLINE,
763
764
    /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
765
    /// It takes a pointer to the trampoline and produces a (possibly) new
766
    /// pointer to the same trampoline with platform-specific adjustments
767
    /// applied.  The pointer it returns points to an executable block of code.
768
    ADJUST_TRAMPOLINE,
769
770
    /// TRAP - Trapping instruction
771
    TRAP,
772
773
    /// DEBUGTRAP - Trap intended to get the attention of a debugger.
774
    DEBUGTRAP,
775
776
    /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand
777
    /// is the chain.  The other operands are the address to prefetch,
778
    /// read / write specifier, locality specifier and instruction / data cache
779
    /// specifier.
780
    PREFETCH,
781
782
    /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
783
    /// This corresponds to the fence instruction. It takes an input chain, and
784
    /// two integer constants: an AtomicOrdering and a SynchronizationScope.
785
    ATOMIC_FENCE,
786
787
    /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
788
    /// This corresponds to "load atomic" instruction.
789
    ATOMIC_LOAD,
790
791
    /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val)
792
    /// This corresponds to "store atomic" instruction.
793
    ATOMIC_STORE,
794
795
    /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
796
    /// For double-word atomic operations:
797
    /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi,
798
    ///                                          swapLo, swapHi)
799
    /// This corresponds to the cmpxchg instruction.
800
    ATOMIC_CMP_SWAP,
801
802
    /// Val, Success, OUTCHAIN
803
    ///     = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap)
804
    /// N.b. this is still a strong cmpxchg operation, so
805
    /// Success == "Val == cmp".
806
    ATOMIC_CMP_SWAP_WITH_SUCCESS,
807
808
    /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
809
    /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
810
    /// For double-word atomic operations:
811
    /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
812
    /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi)
813
    /// These correspond to the atomicrmw instruction.
814
    ATOMIC_SWAP,
815
    ATOMIC_LOAD_ADD,
816
    ATOMIC_LOAD_SUB,
817
    ATOMIC_LOAD_AND,
818
    ATOMIC_LOAD_CLR,
819
    ATOMIC_LOAD_OR,
820
    ATOMIC_LOAD_XOR,
821
    ATOMIC_LOAD_NAND,
822
    ATOMIC_LOAD_MIN,
823
    ATOMIC_LOAD_MAX,
824
    ATOMIC_LOAD_UMIN,
825
    ATOMIC_LOAD_UMAX,
826
    ATOMIC_LOAD_FADD,
827
    ATOMIC_LOAD_FSUB,
828
829
    // Masked load and store - consecutive vector load and store operations
830
    // with additional mask operand that prevents memory accesses to the
831
    // masked-off lanes.
832
    //
833
    // Val, OutChain = MLOAD(BasePtr, Mask, PassThru)
834
    // OutChain = MSTORE(Value, BasePtr, Mask)
835
    MLOAD, MSTORE,
836
837
    // Masked gather and scatter - load and store operations for a vector of
838
    // random addresses with additional mask operand that prevents memory
839
    // accesses to the masked-off lanes.
840
    //
841
    // Val, OutChain = GATHER(InChain, PassThru, Mask, BasePtr, Index, Scale)
842
    // OutChain = SCATTER(InChain, Value, Mask, BasePtr, Index, Scale)
843
    //
844
    // The Index operand can have more vector elements than the other operands
845
    // due to type legalization. The extra elements are ignored.
846
    MGATHER, MSCATTER,
847
848
    /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
849
    /// is the chain and the second operand is the alloca pointer.
850
    LIFETIME_START, LIFETIME_END,
851
852
    /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the
853
    /// beginning and end of GC transition  sequence, and carry arbitrary
854
    /// information that target might need for lowering.  The first operand is
855
    /// a chain, the rest are specified by the target and not touched by the DAG
856
    /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be
857
    /// nested.
858
    GC_TRANSITION_START,
859
    GC_TRANSITION_END,
860
861
    /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of
862
    /// the most recent dynamic alloca. For most targets that would be 0, but
863
    /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time
864
    /// known nonzero constant. The only operand here is the chain.
865
    GET_DYNAMIC_AREA_OFFSET,
866
867
    /// Generic reduction nodes. These nodes represent horizontal vector
868
    /// reduction operations, producing a scalar result.
869
    /// The STRICT variants perform reductions in sequential order. The first
870
    /// operand is an initial scalar accumulator value, and the second operand
871
    /// is the vector to reduce.
872
    VECREDUCE_STRICT_FADD, VECREDUCE_STRICT_FMUL,
873
    /// These reductions are non-strict, and have a single vector operand.
874
    VECREDUCE_FADD, VECREDUCE_FMUL,
875
    VECREDUCE_ADD, VECREDUCE_MUL,
876
    VECREDUCE_AND, VECREDUCE_OR, VECREDUCE_XOR,
877
    VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN,
878
    /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
879
    VECREDUCE_FMAX, VECREDUCE_FMIN,
880
881
    /// BUILTIN_OP_END - This must be the last enum value in this list.
882
    /// The target-specific pre-isel opcode values start here.
883
    BUILTIN_OP_END
884
  };
885
886
  /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
887
  /// which do not reference a specific memory location should be less than
888
  /// this value. Those that do must not be less than this value, and can
889
  /// be used with SelectionDAG::getMemIntrinsicNode.
890
  static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+400;
891
892
  //===--------------------------------------------------------------------===//
893
  /// MemIndexedMode enum - This enum defines the load / store indexed
894
  /// addressing modes.
895
  ///
896
  /// UNINDEXED    "Normal" load / store. The effective address is already
897
  ///              computed and is available in the base pointer. The offset
898
  ///              operand is always undefined. In addition to producing a
899
  ///              chain, an unindexed load produces one value (result of the
900
  ///              load); an unindexed store does not produce a value.
901
  ///
902
  /// PRE_INC      Similar to the unindexed mode where the effective address is
903
  /// PRE_DEC      the value of the base pointer add / subtract the offset.
904
  ///              It considers the computation as being folded into the load /
905
  ///              store operation (i.e. the load / store does the address
906
  ///              computation as well as performing the memory transaction).
907
  ///              The base operand is always undefined. In addition to
908
  ///              producing a chain, pre-indexed load produces two values
909
  ///              (result of the load and the result of the address
910
  ///              computation); a pre-indexed store produces one value (result
911
  ///              of the address computation).
912
  ///
913
  /// POST_INC     The effective address is the value of the base pointer. The
914
  /// POST_DEC     value of the offset operand is then added to / subtracted
915
  ///              from the base after memory transaction. In addition to
916
  ///              producing a chain, post-indexed load produces two values
917
  ///              (the result of the load and the result of the base +/- offset
918
  ///              computation); a post-indexed store produces one value (the
919
  ///              the result of the base +/- offset computation).
920
  enum MemIndexedMode {
921
    UNINDEXED = 0,
922
    PRE_INC,
923
    PRE_DEC,
924
    POST_INC,
925
    POST_DEC
926
  };
927
928
  static const int LAST_INDEXED_MODE = POST_DEC + 1;
929
930
  //===--------------------------------------------------------------------===//
931
  /// LoadExtType enum - This enum defines the three variants of LOADEXT
932
  /// (load with extension).
933
  ///
934
  /// SEXTLOAD loads the integer operand and sign extends it to a larger
935
  ///          integer result type.
936
  /// ZEXTLOAD loads the integer operand and zero extends it to a larger
937
  ///          integer result type.
938
  /// EXTLOAD  is used for two things: floating point extending loads and
939
  ///          integer extending loads [the top bits are undefined].
940
  enum LoadExtType {
941
    NON_EXTLOAD = 0,
942
    EXTLOAD,
943
    SEXTLOAD,
944
    ZEXTLOAD
945
  };
946
947
  static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
948
949
  NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
950
951
  //===--------------------------------------------------------------------===//
952
  /// ISD::CondCode enum - These are ordered carefully to make the bitfields
953
  /// below work out, when considering SETFALSE (something that never exists
954
  /// dynamically) as 0.  "U" -> Unsigned (for integer operands) or Unordered
955
  /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
956
  /// to.  If the "N" column is 1, the result of the comparison is undefined if
957
  /// the input is a NAN.
958
  ///
959
  /// All of these (except for the 'always folded ops') should be handled for
960
  /// floating point.  For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
961
  /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
962
  ///
963
  /// Note that these are laid out in a specific order to allow bit-twiddling
964
  /// to transform conditions.
965
  enum CondCode {
966
    // Opcode          N U L G E       Intuitive operation
967
    SETFALSE,      //    0 0 0 0       Always false (always folded)
968
    SETOEQ,        //    0 0 0 1       True if ordered and equal
969
    SETOGT,        //    0 0 1 0       True if ordered and greater than
970
    SETOGE,        //    0 0 1 1       True if ordered and greater than or equal
971
    SETOLT,        //    0 1 0 0       True if ordered and less than
972
    SETOLE,        //    0 1 0 1       True if ordered and less than or equal
973
    SETONE,        //    0 1 1 0       True if ordered and operands are unequal
974
    SETO,          //    0 1 1 1       True if ordered (no nans)
975
    SETUO,         //    1 0 0 0       True if unordered: isnan(X) | isnan(Y)
976
    SETUEQ,        //    1 0 0 1       True if unordered or equal
977
    SETUGT,        //    1 0 1 0       True if unordered or greater than
978
    SETUGE,        //    1 0 1 1       True if unordered, greater than, or equal
979
    SETULT,        //    1 1 0 0       True if unordered or less than
980
    SETULE,        //    1 1 0 1       True if unordered, less than, or equal
981
    SETUNE,        //    1 1 1 0       True if unordered or not equal
982
    SETTRUE,       //    1 1 1 1       Always true (always folded)
983
    // Don't care operations: undefined if the input is a nan.
984
    SETFALSE2,     //  1 X 0 0 0       Always false (always folded)
985
    SETEQ,         //  1 X 0 0 1       True if equal
986
    SETGT,         //  1 X 0 1 0       True if greater than
987
    SETGE,         //  1 X 0 1 1       True if greater than or equal
988
    SETLT,         //  1 X 1 0 0       True if less than
989
    SETLE,         //  1 X 1 0 1       True if less than or equal
990
    SETNE,         //  1 X 1 1 0       True if not equal
991
    SETTRUE2,      //  1 X 1 1 1       Always true (always folded)
992
993
    SETCC_INVALID       // Marker value.
994
  };
995
996
  /// Return true if this is a setcc instruction that performs a signed
997
  /// comparison when used with integer operands.
998
1.99M
  inline bool isSignedIntSetCC(CondCode Code) {
999
1.99M
    return Code == SETGT || 
Code == SETGE1.89M
||
Code == SETLT1.87M
||
Code == SETLE1.73M
;
1000
1.99M
  }
1001
1002
  /// Return true if this is a setcc instruction that performs an unsigned
1003
  /// comparison when used with integer operands.
1004
35.6k
  inline bool isUnsignedIntSetCC(CondCode Code) {
1005
35.6k
    return Code == SETUGT || 
Code == SETUGE33.6k
||
Code == SETULT33.0k
||
Code == SETULE29.1k
;
1006
35.6k
  }
1007
1008
  /// Return true if the specified condition returns true if the two operands to
1009
  /// the condition are equal. Note that if one of the two operands is a NaN,
1010
  /// this value is meaningless.
1011
9.93k
  inline bool isTrueWhenEqual(CondCode Cond) {
1012
9.93k
    return ((int)Cond & 1) != 0;
1013
9.93k
  }
1014
1015
  /// This function returns 0 if the condition is always false if an operand is
1016
  /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
1017
  /// the condition is undefined if the operand is a NaN.
1018
2.96k
  inline unsigned getUnorderedFlavor(CondCode Cond) {
1019
2.96k
    return ((int)Cond >> 3) & 3;
1020
2.96k
  }
1021
1022
  /// Return the operation corresponding to !(X op Y), where 'op' is a valid
1023
  /// SetCC operation.
1024
  CondCode getSetCCInverse(CondCode Operation, bool isInteger);
1025
1026
  /// Return the operation corresponding to (Y op X) when given the operation
1027
  /// for (X op Y).
1028
  CondCode getSetCCSwappedOperands(CondCode Operation);
1029
1030
  /// Return the result of a logical OR between different comparisons of
1031
  /// identical values: ((X op1 Y) | (X op2 Y)). This function returns
1032
  /// SETCC_INVALID if it is not possible to represent the resultant comparison.
1033
  CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
1034
1035
  /// Return the result of a logical AND between different comparisons of
1036
  /// identical values: ((X op1 Y) & (X op2 Y)). This function returns
1037
  /// SETCC_INVALID if it is not possible to represent the resultant comparison.
1038
  CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
1039
1040
} // end llvm::ISD namespace
1041
1042
} // end llvm namespace
1043
1044
#endif