Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/ISDOpcodes.h
Line
Count
Source
1
//===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This file declares codegen opcodes and related utilities.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#ifndef LLVM_CODEGEN_ISDOPCODES_H
15
#define LLVM_CODEGEN_ISDOPCODES_H
16
17
namespace llvm {
18
19
/// ISD namespace - This namespace contains an enum which represents all of the
20
/// SelectionDAG node types and value types.
21
///
22
namespace ISD {
23
24
  //===--------------------------------------------------------------------===//
25
  /// ISD::NodeType enum - This enum defines the target-independent operators
26
  /// for a SelectionDAG.
27
  ///
28
  /// Targets may also define target-dependent operator codes for SDNodes. For
29
  /// example, on x86, these are the enum values in the X86ISD namespace.
30
  /// Targets should aim to use target-independent operators to model their
31
  /// instruction sets as much as possible, and only use target-dependent
32
  /// operators when they have special requirements.
33
  ///
34
  /// Finally, during and after selection proper, SNodes may use special
35
  /// operator codes that correspond directly with MachineInstr opcodes. These
36
  /// are used to represent selected instructions. See the isMachineOpcode()
37
  /// and getMachineOpcode() member functions of SDNode.
38
  ///
39
  enum NodeType {
40
    /// DELETED_NODE - This is an illegal value that is used to catch
41
    /// errors.  This opcode is not a legal opcode for any node.
42
    DELETED_NODE,
43
44
    /// EntryToken - This is the marker used to indicate the start of a region.
45
    EntryToken,
46
47
    /// TokenFactor - This node takes multiple tokens as input and produces a
48
    /// single token result. This is used to represent the fact that the operand
49
    /// operators are independent of each other.
50
    TokenFactor,
51
52
    /// AssertSext, AssertZext - These nodes record if a register contains a
53
    /// value that has already been zero or sign extended from a narrower type.
54
    /// These nodes take two operands.  The first is the node that has already
55
    /// been extended, and the second is a value type node indicating the width
56
    /// of the extension
57
    AssertSext, AssertZext,
58
59
    /// Various leaf nodes.
60
    BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
61
    Constant, ConstantFP,
62
    GlobalAddress, GlobalTLSAddress, FrameIndex,
63
    JumpTable, ConstantPool, ExternalSymbol, BlockAddress,
64
65
    /// The address of the GOT
66
    GLOBAL_OFFSET_TABLE,
67
68
    /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
69
    /// llvm.returnaddress on the DAG.  These nodes take one operand, the index
70
    /// of the frame or return address to return.  An index of zero corresponds
71
    /// to the current function's frame or return address, an index of one to
72
    /// the parent's frame or return address, and so on.
73
    FRAMEADDR, RETURNADDR, ADDROFRETURNADDR, SPONENTRY,
74
75
    /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
76
    /// Materializes the offset from the local object pointer of another
77
    /// function to a particular local object passed to llvm.localescape. The
78
    /// operand is the MCSymbol label used to represent this offset, since
79
    /// typically the offset is not known until after code generation of the
80
    /// parent.
81
    LOCAL_RECOVER,
82
83
    /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on
84
    /// the DAG, which implements the named register global variables extension.
85
    READ_REGISTER,
86
    WRITE_REGISTER,
87
88
    /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
89
    /// first (possible) on-stack argument. This is needed for correct stack
90
    /// adjustment during unwind.
91
    FRAME_TO_ARGS_OFFSET,
92
93
    /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical
94
    /// Frame Address (CFA), generally the value of the stack pointer at the
95
    /// call site in the previous frame.
96
    EH_DWARF_CFA,
97
98
    /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
99
    /// 'eh_return' gcc dwarf builtin, which is used to return from
100
    /// exception. The general meaning is: adjust stack by OFFSET and pass
101
    /// execution to HANDLER. Many platform-related details also :)
102
    EH_RETURN,
103
104
    /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
105
    /// This corresponds to the eh.sjlj.setjmp intrinsic.
106
    /// It takes an input chain and a pointer to the jump buffer as inputs
107
    /// and returns an outchain.
108
    EH_SJLJ_SETJMP,
109
110
    /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
111
    /// This corresponds to the eh.sjlj.longjmp intrinsic.
112
    /// It takes an input chain and a pointer to the jump buffer as inputs
113
    /// and returns an outchain.
114
    EH_SJLJ_LONGJMP,
115
116
    /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN)
117
    /// The target initializes the dispatch table here.
118
    EH_SJLJ_SETUP_DISPATCH,
119
120
    /// TargetConstant* - Like Constant*, but the DAG does not do any folding,
121
    /// simplification, or lowering of the constant. They are used for constants
122
    /// which are known to fit in the immediate fields of their users, or for
123
    /// carrying magic numbers which are not values which need to be
124
    /// materialized in registers.
125
    TargetConstant,
126
    TargetConstantFP,
127
128
    /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
129
    /// anything else with this node, and this is valid in the target-specific
130
    /// dag, turning into a GlobalAddress operand.
131
    TargetGlobalAddress,
132
    TargetGlobalTLSAddress,
133
    TargetFrameIndex,
134
    TargetJumpTable,
135
    TargetConstantPool,
136
    TargetExternalSymbol,
137
    TargetBlockAddress,
138
139
    MCSymbol,
140
141
    /// TargetIndex - Like a constant pool entry, but with completely
142
    /// target-dependent semantics. Holds target flags, a 32-bit index, and a
143
    /// 64-bit index. Targets can use this however they like.
144
    TargetIndex,
145
146
    /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
147
    /// This node represents a target intrinsic function with no side effects.
148
    /// The first operand is the ID number of the intrinsic from the
149
    /// llvm::Intrinsic namespace.  The operands to the intrinsic follow.  The
150
    /// node returns the result of the intrinsic.
151
    INTRINSIC_WO_CHAIN,
152
153
    /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
154
    /// This node represents a target intrinsic function with side effects that
155
    /// returns a result.  The first operand is a chain pointer.  The second is
156
    /// the ID number of the intrinsic from the llvm::Intrinsic namespace.  The
157
    /// operands to the intrinsic follow.  The node has two results, the result
158
    /// of the intrinsic and an output chain.
159
    INTRINSIC_W_CHAIN,
160
161
    /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
162
    /// This node represents a target intrinsic function with side effects that
163
    /// does not return a result.  The first operand is a chain pointer.  The
164
    /// second is the ID number of the intrinsic from the llvm::Intrinsic
165
    /// namespace.  The operands to the intrinsic follow.
166
    INTRINSIC_VOID,
167
168
    /// CopyToReg - This node has three operands: a chain, a register number to
169
    /// set to this value, and a value.
170
    CopyToReg,
171
172
    /// CopyFromReg - This node indicates that the input value is a virtual or
173
    /// physical register that is defined outside of the scope of this
174
    /// SelectionDAG.  The register is available from the RegisterSDNode object.
175
    CopyFromReg,
176
177
    /// UNDEF - An undefined node.
178
    UNDEF,
179
180
    /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
181
    /// a Constant, which is required to be operand #1) half of the integer or
182
    /// float value specified as operand #0.  This is only for use before
183
    /// legalization, for values that will be broken into multiple registers.
184
    EXTRACT_ELEMENT,
185
186
    /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
187
    /// Given two values of the same integer value type, this produces a value
188
    /// twice as big.  Like EXTRACT_ELEMENT, this can only be used before
189
    /// legalization. The lower part of the composite value should be in
190
    /// element 0 and the upper part should be in element 1.
191
    BUILD_PAIR,
192
193
    /// MERGE_VALUES - This node takes multiple discrete operands and returns
194
    /// them all as its individual results.  This nodes has exactly the same
195
    /// number of inputs and outputs. This node is useful for some pieces of the
196
    /// code generator that want to think about a single node with multiple
197
    /// results, not multiple nodes.
198
    MERGE_VALUES,
199
200
    /// Simple integer binary arithmetic operators.
201
    ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
202
203
    /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
204
    /// a signed/unsigned value of type i[2*N], and return the full value as
205
    /// two results, each of type iN.
206
    SMUL_LOHI, UMUL_LOHI,
207
208
    /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
209
    /// remainder result.
210
    SDIVREM, UDIVREM,
211
212
    /// CARRY_FALSE - This node is used when folding other nodes,
213
    /// like ADDC/SUBC, which indicate the carry result is always false.
214
    CARRY_FALSE,
215
216
    /// Carry-setting nodes for multiple precision addition and subtraction.
217
    /// These nodes take two operands of the same value type, and produce two
218
    /// results.  The first result is the normal add or sub result, the second
219
    /// result is the carry flag result.
220
    /// FIXME: These nodes are deprecated in favor of ADDCARRY and SUBCARRY.
221
    /// They are kept around for now to provide a smooth transition path
222
    /// toward the use of ADDCARRY/SUBCARRY and will eventually be removed.
223
    ADDC, SUBC,
224
225
    /// Carry-using nodes for multiple precision addition and subtraction. These
226
    /// nodes take three operands: The first two are the normal lhs and rhs to
227
    /// the add or sub, and the third is the input carry flag.  These nodes
228
    /// produce two results; the normal result of the add or sub, and the output
229
    /// carry flag.  These nodes both read and write a carry flag to allow them
230
    /// to them to be chained together for add and sub of arbitrarily large
231
    /// values.
232
    ADDE, SUBE,
233
234
    /// Carry-using nodes for multiple precision addition and subtraction.
235
    /// These nodes take three operands: The first two are the normal lhs and
236
    /// rhs to the add or sub, and the third is a boolean indicating if there
237
    /// is an incoming carry. These nodes produce two results: the normal
238
    /// result of the add or sub, and the output carry so they can be chained
239
    /// together. The use of this opcode is preferable to adde/sube if the
240
    /// target supports it, as the carry is a regular value rather than a
241
    /// glue, which allows further optimisation.
242
    ADDCARRY, SUBCARRY,
243
244
    /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
245
    /// These nodes take two operands: the normal LHS and RHS to the add. They
246
    /// produce two results: the normal result of the add, and a boolean that
247
    /// indicates if an overflow occurred (*not* a flag, because it may be store
248
    /// to memory, etc.).  If the type of the boolean is not i1 then the high
249
    /// bits conform to getBooleanContents.
250
    /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
251
    SADDO, UADDO,
252
253
    /// Same for subtraction.
254
    SSUBO, USUBO,
255
256
    /// Same for multiplication.
257
    SMULO, UMULO,
258
259
    /// RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2
260
    /// integers with the same bit width (W). If the true value of LHS + RHS
261
    /// exceeds the largest value that can be represented by W bits, the
262
    /// resulting value is this maximum value. Otherwise, if this value is less
263
    /// than the smallest value that can be represented by W bits, the
264
    /// resulting value is this minimum value.
265
    SADDSAT, UADDSAT,
266
267
    /// RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2
268
    /// integers with the same bit width (W). If the true value of LHS - RHS
269
    /// exceeds the largest value that can be represented by W bits, the
270
    /// resulting value is this maximum value. Otherwise, if this value is less
271
    /// than the smallest value that can be represented by W bits, the
272
    /// resulting value is this minimum value.
273
    SSUBSAT, USUBSAT,
274
275
    /// Simple binary floating point operators.
276
    FADD, FSUB, FMUL, FDIV, FREM,
277
278
    /// Constrained versions of the binary floating point operators.
279
    /// These will be lowered to the simple operators before final selection.
280
    /// They are used to limit optimizations while the DAG is being
281
    /// optimized.
282
    STRICT_FADD, STRICT_FSUB, STRICT_FMUL, STRICT_FDIV, STRICT_FREM,
283
    STRICT_FMA,
284
285
    /// Constrained versions of libm-equivalent floating point intrinsics.
286
    /// These will be lowered to the equivalent non-constrained pseudo-op
287
    /// (or expanded to the equivalent library call) before final selection.
288
    /// They are used to limit optimizations while the DAG is being optimized.
289
    STRICT_FSQRT, STRICT_FPOW, STRICT_FPOWI, STRICT_FSIN, STRICT_FCOS,
290
    STRICT_FEXP, STRICT_FEXP2, STRICT_FLOG, STRICT_FLOG10, STRICT_FLOG2,
291
    STRICT_FRINT, STRICT_FNEARBYINT, STRICT_FMAXNUM, STRICT_FMINNUM,
292
    STRICT_FCEIL, STRICT_FFLOOR, STRICT_FROUND, STRICT_FTRUNC,
293
294
    /// FMA - Perform a * b + c with no intermediate rounding step.
295
    FMA,
296
297
    /// FMAD - Perform a * b + c, while getting the same result as the
298
    /// separately rounded operations.
299
    FMAD,
300
301
    /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.  NOTE: This
302
    /// DAG node does not require that X and Y have the same type, just that
303
    /// they are both floating point.  X and the result must have the same type.
304
    /// FCOPYSIGN(f32, f64) is allowed.
305
    FCOPYSIGN,
306
307
    /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
308
    /// value as an integer 0/1 value.
309
    FGETSIGN,
310
311
    /// Returns platform specific canonical encoding of a floating point number.
312
    FCANONICALIZE,
313
314
    /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the
315
    /// specified, possibly variable, elements.  The number of elements is
316
    /// required to be a power of two.  The types of the operands must all be
317
    /// the same and must match the vector element type, except that integer
318
    /// types are allowed to be larger than the element type, in which case
319
    /// the operands are implicitly truncated.
320
    BUILD_VECTOR,
321
322
    /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
323
    /// at IDX replaced with VAL.  If the type of VAL is larger than the vector
324
    /// element type then VAL is truncated before replacement.
325
    INSERT_VECTOR_ELT,
326
327
    /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
328
    /// identified by the (potentially variable) element number IDX.  If the
329
    /// return type is an integer type larger than the element type of the
330
    /// vector, the result is extended to the width of the return type. In
331
    /// that case, the high bits are undefined.
332
    EXTRACT_VECTOR_ELT,
333
334
    /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
335
    /// vector type with the same length and element type, this produces a
336
    /// concatenated vector result value, with length equal to the sum of the
337
    /// lengths of the input vectors.
338
    CONCAT_VECTORS,
339
340
    /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector
341
    /// with VECTOR2 inserted into VECTOR1 at the (potentially
342
    /// variable) element number IDX, which must be a multiple of the
343
    /// VECTOR2 vector length.  The elements of VECTOR1 starting at
344
    /// IDX are overwritten with VECTOR2.  Elements IDX through
345
    /// vector_length(VECTOR2) must be valid VECTOR1 indices.
346
    INSERT_SUBVECTOR,
347
348
    /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an
349
    /// vector value) starting with the element number IDX, which must be a
350
    /// constant multiple of the result vector length.
351
    EXTRACT_SUBVECTOR,
352
353
    /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
354
    /// VEC1/VEC2.  A VECTOR_SHUFFLE node also contains an array of constant int
355
    /// values that indicate which value (or undef) each result element will
356
    /// get.  These constant ints are accessible through the
357
    /// ShuffleVectorSDNode class.  This is quite similar to the Altivec
358
    /// 'vperm' instruction, except that the indices must be constants and are
359
    /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
360
    VECTOR_SHUFFLE,
361
362
    /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
363
    /// scalar value into element 0 of the resultant vector type.  The top
364
    /// elements 1 to N-1 of the N-element vector are undefined.  The type
365
    /// of the operand must match the vector element type, except when they
366
    /// are integer types.  In this case the operand is allowed to be wider
367
    /// than the vector element type, and is implicitly truncated to it.
368
    SCALAR_TO_VECTOR,
369
370
    /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
371
    /// producing an unsigned/signed value of type i[2*N], then return the top
372
    /// part.
373
    MULHU, MULHS,
374
375
    /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned
376
    /// integers.
377
    SMIN, SMAX, UMIN, UMAX,
378
379
    /// Bitwise operators - logical and, logical or, logical xor.
380
    AND, OR, XOR,
381
382
    /// ABS - Determine the unsigned absolute value of a signed integer value of
383
    /// the same bitwidth.
384
    /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow
385
    /// is performed.
386
    ABS,
387
388
    /// Shift and rotation operations.  After legalization, the type of the
389
    /// shift amount is known to be TLI.getShiftAmountTy().  Before legalization
390
    /// the shift amount can be any type, but care must be taken to ensure it is
391
    /// large enough.  TLI.getShiftAmountTy() is i8 on some targets, but before
392
    /// legalization, types like i1024 can occur and i8 doesn't have enough bits
393
    /// to represent the shift amount.
394
    /// When the 1st operand is a vector, the shift amount must be in the same
395
    /// type. (TLI.getShiftAmountTy() will return the same type when the input
396
    /// type is a vector.)
397
    /// For rotates, the shift amount is treated as an unsigned amount modulo
398
    /// the element size of the first operand.
399
    SHL, SRA, SRL, ROTL, ROTR,
400
401
    /// Byte Swap and Counting operators.
402
    BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE,
403
404
    /// Bit counting operators with an undefined result for zero inputs.
405
    CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,
406
407
    /// Select(COND, TRUEVAL, FALSEVAL).  If the type of the boolean COND is not
408
    /// i1 then the high bits must conform to getBooleanContents.
409
    SELECT,
410
411
    /// Select with a vector condition (op #0) and two vector operands (ops #1
412
    /// and #2), returning a vector result.  All vectors have the same length.
413
    /// Much like the scalar select and setcc, each bit in the condition selects
414
    /// whether the corresponding result element is taken from op #1 or op #2.
415
    /// At first, the VSELECT condition is of vXi1 type. Later, targets may
416
    /// change the condition type in order to match the VSELECT node using a
417
    /// pattern. The condition follows the BooleanContent format of the target.
418
    VSELECT,
419
420
    /// Select with condition operator - This selects between a true value and
421
    /// a false value (ops #2 and #3) based on the boolean result of comparing
422
    /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
423
    /// condition code in op #4, a CondCodeSDNode.
424
    SELECT_CC,
425
426
    /// SetCC operator - This evaluates to a true value iff the condition is
427
    /// true.  If the result value type is not i1 then the high bits conform
428
    /// to getBooleanContents.  The operands to this are the left and right
429
    /// operands to compare (ops #0, and #1) and the condition code to compare
430
    /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
431
    /// then the result type must also be a vector type.
432
    SETCC,
433
434
    /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
435
    /// op #2 is a boolean indicating if there is an incoming carry. This
436
    /// operator checks the result of "LHS - RHS - Carry", and can be used to
437
    /// compare two wide integers:
438
    /// (setcccarry lhshi rhshi (subcarry lhslo rhslo) cc).
439
    /// Only valid for integers.
440
    SETCCCARRY,
441
442
    /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
443
    /// integer shift operations.  The operation ordering is:
444
    ///       [Lo,Hi] = op [LoLHS,HiLHS], Amt
445
    SHL_PARTS, SRA_PARTS, SRL_PARTS,
446
447
    /// Conversion operators.  These are all single input single output
448
    /// operations.  For all of these, the result type must be strictly
449
    /// wider or narrower (depending on the operation) than the source
450
    /// type.
451
452
    /// SIGN_EXTEND - Used for integer types, replicating the sign bit
453
    /// into new bits.
454
    SIGN_EXTEND,
455
456
    /// ZERO_EXTEND - Used for integer types, zeroing the new bits.
457
    ZERO_EXTEND,
458
459
    /// ANY_EXTEND - Used for integer types.  The high bits are undefined.
460
    ANY_EXTEND,
461
462
    /// TRUNCATE - Completely drop the high bits.
463
    TRUNCATE,
464
465
    /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign
466
    /// depends on the first letter) to floating point.
467
    SINT_TO_FP,
468
    UINT_TO_FP,
469
470
    /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
471
    /// sign extend a small value in a large integer register (e.g. sign
472
    /// extending the low 8 bits of a 32-bit register to fill the top 24 bits
473
    /// with the 7th bit).  The size of the smaller type is indicated by the 1th
474
    /// operand, a ValueType node.
475
    SIGN_EXTEND_INREG,
476
477
    /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
478
    /// in-register any-extension of the low lanes of an integer vector. The
479
    /// result type must have fewer elements than the operand type, and those
480
    /// elements must be larger integer types such that the total size of the
481
    /// operand type is less than or equal to the size of the result type. Each
482
    /// of the low operand elements is any-extended into the corresponding,
483
    /// wider result elements with the high bits becoming undef.
484
    /// NOTE: The type legalizer prefers to make the operand and result size
485
    /// the same to allow expansion to shuffle vector during op legalization.
486
    ANY_EXTEND_VECTOR_INREG,
487
488
    /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
489
    /// in-register sign-extension of the low lanes of an integer vector. The
490
    /// result type must have fewer elements than the operand type, and those
491
    /// elements must be larger integer types such that the total size of the
492
    /// operand type is less than or equal to the size of the result type. Each
493
    /// of the low operand elements is sign-extended into the corresponding,
494
    /// wider result elements.
495
    /// NOTE: The type legalizer prefers to make the operand and result size
496
    /// the same to allow expansion to shuffle vector during op legalization.
497
    SIGN_EXTEND_VECTOR_INREG,
498
499
    /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an
500
    /// in-register zero-extension of the low lanes of an integer vector. The
501
    /// result type must have fewer elements than the operand type, and those
502
    /// elements must be larger integer types such that the total size of the
503
    /// operand type is less than or equal to the size of the result type. Each
504
    /// of the low operand elements is zero-extended into the corresponding,
505
    /// wider result elements.
506
    /// NOTE: The type legalizer prefers to make the operand and result size
507
    /// the same to allow expansion to shuffle vector during op legalization.
508
    ZERO_EXTEND_VECTOR_INREG,
509
510
    /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
511
    /// integer. These have the same semantics as fptosi and fptoui in IR. If
512
    /// the FP value cannot fit in the integer type, the results are undefined.
513
    FP_TO_SINT,
514
    FP_TO_UINT,
515
516
    /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
517
    /// down to the precision of the destination VT.  TRUNC is a flag, which is
518
    /// always an integer that is zero or one.  If TRUNC is 0, this is a
519
    /// normal rounding, if it is 1, this FP_ROUND is known to not change the
520
    /// value of Y.
521
    ///
522
    /// The TRUNC = 1 case is used in cases where we know that the value will
523
    /// not be modified by the node, because Y is not using any of the extra
524
    /// precision of source type.  This allows certain transformations like
525
    /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
526
    /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
527
    FP_ROUND,
528
529
    /// FLT_ROUNDS_ - Returns current rounding mode:
530
    /// -1 Undefined
531
    ///  0 Round to 0
532
    ///  1 Round to nearest
533
    ///  2 Round to +inf
534
    ///  3 Round to -inf
535
    FLT_ROUNDS_,
536
537
    /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and
538
    /// rounds it to a floating point value.  It then promotes it and returns it
539
    /// in a register of the same size.  This operation effectively just
540
    /// discards excess precision.  The type to round down to is specified by
541
    /// the VT operand, a VTSDNode.
542
    FP_ROUND_INREG,
543
544
    /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
545
    FP_EXTEND,
546
547
    /// BITCAST - This operator converts between integer, vector and FP
548
    /// values, as if the value was stored to memory with one type and loaded
549
    /// from the same address with the other type (or equivalently for vector
550
    /// format conversions, etc).  The source and result are required to have
551
    /// the same bit size (e.g.  f32 <-> i32).  This can also be used for
552
    /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
553
    /// getNode().
554
    ///
555
    /// This operator is subtly different from the bitcast instruction from
556
    /// LLVM-IR since this node may change the bits in the register. For
557
    /// example, this occurs on big-endian NEON and big-endian MSA where the
558
    /// layout of the bits in the register depends on the vector type and this
559
    /// operator acts as a shuffle operation for some vector type combinations.
560
    BITCAST,
561
562
    /// ADDRSPACECAST - This operator converts between pointers of different
563
    /// address spaces.
564
    ADDRSPACECAST,
565
566
    /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions
567
    /// and truncation for half-precision (16 bit) floating numbers. These nodes
568
    /// form a semi-softened interface for dealing with f16 (as an i16), which
569
    /// is often a storage-only type but has native conversions.
570
    FP16_TO_FP, FP_TO_FP16,
571
572
    /// Perform various unary floating-point operations inspired by libm.
573
    FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW,
574
    FLOG, FLOG2, FLOG10, FEXP, FEXP2,
575
    FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR,
576
    /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
577
    /// values.
578
    //
579
    /// In the case where a single input is a NaN (either signaling or quiet),
580
    /// the non-NaN input is returned.
581
    ///
582
    /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
583
    FMINNUM, FMAXNUM,
584
585
    /// FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on
586
    /// two values, following the IEEE-754 2008 definition. This differs from
587
    /// FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
588
    /// signaling NaN, returns a quiet NaN.
589
    FMINNUM_IEEE, FMAXNUM_IEEE,
590
591
    /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
592
    /// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
593
    /// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics.
594
    FMINIMUM, FMAXIMUM,
595
596
    /// FSINCOS - Compute both fsin and fcos as a single operation.
597
    FSINCOS,
598
599
    /// LOAD and STORE have token chains as their first operand, then the same
600
    /// operands as an LLVM load/store instruction, then an offset node that
601
    /// is added / subtracted from the base pointer to form the address (for
602
    /// indexed memory ops).
603
    LOAD, STORE,
604
605
    /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned
606
    /// to a specified boundary.  This node always has two return values: a new
607
    /// stack pointer value and a chain. The first operand is the token chain,
608
    /// the second is the number of bytes to allocate, and the third is the
609
    /// alignment boundary.  The size is guaranteed to be a multiple of the
610
    /// stack alignment, and the alignment is guaranteed to be bigger than the
611
    /// stack alignment (if required) or 0 to get standard stack alignment.
612
    DYNAMIC_STACKALLOC,
613
614
    /// Control flow instructions.  These all have token chains.
615
616
    /// BR - Unconditional branch.  The first operand is the chain
617
    /// operand, the second is the MBB to branch to.
618
    BR,
619
620
    /// BRIND - Indirect branch.  The first operand is the chain, the second
621
    /// is the value to branch to, which must be of the same type as the
622
    /// target's pointer type.
623
    BRIND,
624
625
    /// BR_JT - Jumptable branch. The first operand is the chain, the second
626
    /// is the jumptable index, the last one is the jumptable entry index.
627
    BR_JT,
628
629
    /// BRCOND - Conditional branch.  The first operand is the chain, the
630
    /// second is the condition, the third is the block to branch to if the
631
    /// condition is true.  If the type of the condition is not i1, then the
632
    /// high bits must conform to getBooleanContents.
633
    BRCOND,
634
635
    /// BR_CC - Conditional branch.  The behavior is like that of SELECT_CC, in
636
    /// that the condition is represented as condition code, and two nodes to
637
    /// compare, rather than as a combined SetCC node.  The operands in order
638
    /// are chain, cc, lhs, rhs, block to branch to if condition is true.
639
    BR_CC,
640
641
    /// INLINEASM - Represents an inline asm block.  This node always has two
642
    /// return values: a chain and a flag result.  The inputs are as follows:
643
    ///   Operand #0  : Input chain.
644
    ///   Operand #1  : a ExternalSymbolSDNode with a pointer to the asm string.
645
    ///   Operand #2  : a MDNodeSDNode with the !srcloc metadata.
646
    ///   Operand #3  : HasSideEffect, IsAlignStack bits.
647
    ///   After this, it is followed by a list of operands with this format:
648
    ///     ConstantSDNode: Flags that encode whether it is a mem or not, the
649
    ///                     of operands that follow, etc.  See InlineAsm.h.
650
    ///     ... however many operands ...
651
    ///   Operand #last: Optional, an incoming flag.
652
    ///
653
    /// The variable width operands are required to represent target addressing
654
    /// modes as a single "operand", even though they may have multiple
655
    /// SDOperands.
656
    INLINEASM,
657
658
    /// EH_LABEL - Represents a label in mid basic block used to track
659
    /// locations needed for debug and exception handling tables.  These nodes
660
    /// take a chain as input and return a chain.
661
    EH_LABEL,
662
663
    /// ANNOTATION_LABEL - Represents a mid basic block label used by
664
    /// annotations. This should remain within the basic block and be ordered
665
    /// with respect to other call instructions, but loads and stores may float
666
    /// past it.
667
    ANNOTATION_LABEL,
668
669
    /// CATCHPAD - Represents a catchpad instruction.
670
    CATCHPAD,
671
672
    /// CATCHRET - Represents a return from a catch block funclet. Used for
673
    /// MSVC compatible exception handling. Takes a chain operand and a
674
    /// destination basic block operand.
675
    CATCHRET,
676
677
    /// CLEANUPRET - Represents a return from a cleanup block funclet.  Used for
678
    /// MSVC compatible exception handling. Takes only a chain operand.
679
    CLEANUPRET,
680
681
    /// STACKSAVE - STACKSAVE has one operand, an input chain.  It produces a
682
    /// value, the same type as the pointer type for the system, and an output
683
    /// chain.
684
    STACKSAVE,
685
686
    /// STACKRESTORE has two operands, an input chain and a pointer to restore
687
    /// to it returns an output chain.
688
    STACKRESTORE,
689
690
    /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end
691
    /// of a call sequence, and carry arbitrary information that target might
692
    /// want to know.  The first operand is a chain, the rest are specified by
693
    /// the target and not touched by the DAG optimizers.
694
    /// Targets that may use stack to pass call arguments define additional
695
    /// operands:
696
    /// - size of the call frame part that must be set up within the
697
    ///   CALLSEQ_START..CALLSEQ_END pair,
698
    /// - part of the call frame prepared prior to CALLSEQ_START.
699
    /// Both these parameters must be constants, their sum is the total call
700
    /// frame size.
701
    /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
702
    CALLSEQ_START,  // Beginning of a call sequence
703
    CALLSEQ_END,    // End of a call sequence
704
705
    /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
706
    /// and the alignment. It returns a pair of values: the vaarg value and a
707
    /// new chain.
708
    VAARG,
709
710
    /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer,
711
    /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
712
    /// source.
713
    VACOPY,
714
715
    /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain,
716
    /// pointer, and a SRCVALUE.
717
    VAEND, VASTART,
718
719
    /// SRCVALUE - This is a node type that holds a Value* that is used to
720
    /// make reference to a value in the LLVM IR.
721
    SRCVALUE,
722
723
    /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to
724
    /// reference metadata in the IR.
725
    MDNODE_SDNODE,
726
727
    /// PCMARKER - This corresponds to the pcmarker intrinsic.
728
    PCMARKER,
729
730
    /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
731
    /// It produces a chain and one i64 value. The only operand is a chain.
732
    /// If i64 is not legal, the result will be expanded into smaller values.
733
    /// Still, it returns an i64, so targets should set legality for i64.
734
    /// The result is the content of the architecture-specific cycle
735
    /// counter-like register (or other high accuracy low latency clock source).
736
    READCYCLECOUNTER,
737
738
    /// HANDLENODE node - Used as a handle for various purposes.
739
    HANDLENODE,
740
741
    /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.  It
742
    /// takes as input a token chain, the pointer to the trampoline, the pointer
743
    /// to the nested function, the pointer to pass for the 'nest' parameter, a
744
    /// SRCVALUE for the trampoline and another for the nested function
745
    /// (allowing targets to access the original Function*).
746
    /// It produces a token chain as output.
747
    INIT_TRAMPOLINE,
748
749
    /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
750
    /// It takes a pointer to the trampoline and produces a (possibly) new
751
    /// pointer to the same trampoline with platform-specific adjustments
752
    /// applied.  The pointer it returns points to an executable block of code.
753
    ADJUST_TRAMPOLINE,
754
755
    /// TRAP - Trapping instruction
756
    TRAP,
757
758
    /// DEBUGTRAP - Trap intended to get the attention of a debugger.
759
    DEBUGTRAP,
760
761
    /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand
762
    /// is the chain.  The other operands are the address to prefetch,
763
    /// read / write specifier, locality specifier and instruction / data cache
764
    /// specifier.
765
    PREFETCH,
766
767
    /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
768
    /// This corresponds to the fence instruction. It takes an input chain, and
769
    /// two integer constants: an AtomicOrdering and a SynchronizationScope.
770
    ATOMIC_FENCE,
771
772
    /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
773
    /// This corresponds to "load atomic" instruction.
774
    ATOMIC_LOAD,
775
776
    /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val)
777
    /// This corresponds to "store atomic" instruction.
778
    ATOMIC_STORE,
779
780
    /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
781
    /// For double-word atomic operations:
782
    /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi,
783
    ///                                          swapLo, swapHi)
784
    /// This corresponds to the cmpxchg instruction.
785
    ATOMIC_CMP_SWAP,
786
787
    /// Val, Success, OUTCHAIN
788
    ///     = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap)
789
    /// N.b. this is still a strong cmpxchg operation, so
790
    /// Success == "Val == cmp".
791
    ATOMIC_CMP_SWAP_WITH_SUCCESS,
792
793
    /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
794
    /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
795
    /// For double-word atomic operations:
796
    /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
797
    /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi)
798
    /// These correspond to the atomicrmw instruction.
799
    ATOMIC_SWAP,
800
    ATOMIC_LOAD_ADD,
801
    ATOMIC_LOAD_SUB,
802
    ATOMIC_LOAD_AND,
803
    ATOMIC_LOAD_CLR,
804
    ATOMIC_LOAD_OR,
805
    ATOMIC_LOAD_XOR,
806
    ATOMIC_LOAD_NAND,
807
    ATOMIC_LOAD_MIN,
808
    ATOMIC_LOAD_MAX,
809
    ATOMIC_LOAD_UMIN,
810
    ATOMIC_LOAD_UMAX,
811
812
    // Masked load and store - consecutive vector load and store operations
813
    // with additional mask operand that prevents memory accesses to the
814
    // masked-off lanes.
815
    //
816
    // Val, OutChain = MLOAD(BasePtr, Mask, PassThru)
817
    // OutChain = MSTORE(Value, BasePtr, Mask)
818
    MLOAD, MSTORE,
819
820
    // Masked gather and scatter - load and store operations for a vector of
821
    // random addresses with additional mask operand that prevents memory
822
    // accesses to the masked-off lanes.
823
    //
824
    // Val, OutChain = GATHER(InChain, PassThru, Mask, BasePtr, Index, Scale)
825
    // OutChain = SCATTER(InChain, Value, Mask, BasePtr, Index, Scale)
826
    //
827
    // The Index operand can have more vector elements than the other operands
828
    // due to type legalization. The extra elements are ignored.
829
    MGATHER, MSCATTER,
830
831
    /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
832
    /// is the chain and the second operand is the alloca pointer.
833
    LIFETIME_START, LIFETIME_END,
834
835
    /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the
836
    /// beginning and end of GC transition  sequence, and carry arbitrary
837
    /// information that target might need for lowering.  The first operand is
838
    /// a chain, the rest are specified by the target and not touched by the DAG
839
    /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be
840
    /// nested.
841
    GC_TRANSITION_START,
842
    GC_TRANSITION_END,
843
844
    /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of
845
    /// the most recent dynamic alloca. For most targets that would be 0, but
846
    /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time
847
    /// known nonzero constant. The only operand here is the chain.
848
    GET_DYNAMIC_AREA_OFFSET,
849
850
    /// Generic reduction nodes. These nodes represent horizontal vector
851
    /// reduction operations, producing a scalar result.
852
    /// The STRICT variants perform reductions in sequential order. The first
853
    /// operand is an initial scalar accumulator value, and the second operand
854
    /// is the vector to reduce.
855
    VECREDUCE_STRICT_FADD, VECREDUCE_STRICT_FMUL,
856
    /// These reductions are non-strict, and have a single vector operand.
857
    VECREDUCE_FADD, VECREDUCE_FMUL,
858
    VECREDUCE_ADD, VECREDUCE_MUL,
859
    VECREDUCE_AND, VECREDUCE_OR, VECREDUCE_XOR,
860
    VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN,
861
    /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
862
    VECREDUCE_FMAX, VECREDUCE_FMIN,
863
864
    /// BUILTIN_OP_END - This must be the last enum value in this list.
865
    /// The target-specific pre-isel opcode values start here.
866
    BUILTIN_OP_END
867
  };
868
869
  /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
870
  /// which do not reference a specific memory location should be less than
871
  /// this value. Those that do must not be less than this value, and can
872
  /// be used with SelectionDAG::getMemIntrinsicNode.
873
  static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+400;
874
875
  //===--------------------------------------------------------------------===//
876
  /// MemIndexedMode enum - This enum defines the load / store indexed
877
  /// addressing modes.
878
  ///
879
  /// UNINDEXED    "Normal" load / store. The effective address is already
880
  ///              computed and is available in the base pointer. The offset
881
  ///              operand is always undefined. In addition to producing a
882
  ///              chain, an unindexed load produces one value (result of the
883
  ///              load); an unindexed store does not produce a value.
884
  ///
885
  /// PRE_INC      Similar to the unindexed mode where the effective address is
886
  /// PRE_DEC      the value of the base pointer add / subtract the offset.
887
  ///              It considers the computation as being folded into the load /
888
  ///              store operation (i.e. the load / store does the address
889
  ///              computation as well as performing the memory transaction).
890
  ///              The base operand is always undefined. In addition to
891
  ///              producing a chain, pre-indexed load produces two values
892
  ///              (result of the load and the result of the address
893
  ///              computation); a pre-indexed store produces one value (result
894
  ///              of the address computation).
895
  ///
896
  /// POST_INC     The effective address is the value of the base pointer. The
897
  /// POST_DEC     value of the offset operand is then added to / subtracted
898
  ///              from the base after memory transaction. In addition to
899
  ///              producing a chain, post-indexed load produces two values
900
  ///              (the result of the load and the result of the base +/- offset
901
  ///              computation); a post-indexed store produces one value (the
902
  ///              the result of the base +/- offset computation).
903
  enum MemIndexedMode {
904
    UNINDEXED = 0,
905
    PRE_INC,
906
    PRE_DEC,
907
    POST_INC,
908
    POST_DEC
909
  };
910
911
  static const int LAST_INDEXED_MODE = POST_DEC + 1;
912
913
  //===--------------------------------------------------------------------===//
914
  /// LoadExtType enum - This enum defines the three variants of LOADEXT
915
  /// (load with extension).
916
  ///
917
  /// SEXTLOAD loads the integer operand and sign extends it to a larger
918
  ///          integer result type.
919
  /// ZEXTLOAD loads the integer operand and zero extends it to a larger
920
  ///          integer result type.
921
  /// EXTLOAD  is used for two things: floating point extending loads and
922
  ///          integer extending loads [the top bits are undefined].
923
  enum LoadExtType {
924
    NON_EXTLOAD = 0,
925
    EXTLOAD,
926
    SEXTLOAD,
927
    ZEXTLOAD
928
  };
929
930
  static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
931
932
  NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
933
934
  //===--------------------------------------------------------------------===//
935
  /// ISD::CondCode enum - These are ordered carefully to make the bitfields
936
  /// below work out, when considering SETFALSE (something that never exists
937
  /// dynamically) as 0.  "U" -> Unsigned (for integer operands) or Unordered
938
  /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
939
  /// to.  If the "N" column is 1, the result of the comparison is undefined if
940
  /// the input is a NAN.
941
  ///
942
  /// All of these (except for the 'always folded ops') should be handled for
943
  /// floating point.  For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
944
  /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
945
  ///
946
  /// Note that these are laid out in a specific order to allow bit-twiddling
947
  /// to transform conditions.
948
  enum CondCode {
949
    // Opcode          N U L G E       Intuitive operation
950
    SETFALSE,      //    0 0 0 0       Always false (always folded)
951
    SETOEQ,        //    0 0 0 1       True if ordered and equal
952
    SETOGT,        //    0 0 1 0       True if ordered and greater than
953
    SETOGE,        //    0 0 1 1       True if ordered and greater than or equal
954
    SETOLT,        //    0 1 0 0       True if ordered and less than
955
    SETOLE,        //    0 1 0 1       True if ordered and less than or equal
956
    SETONE,        //    0 1 1 0       True if ordered and operands are unequal
957
    SETO,          //    0 1 1 1       True if ordered (no nans)
958
    SETUO,         //    1 0 0 0       True if unordered: isnan(X) | isnan(Y)
959
    SETUEQ,        //    1 0 0 1       True if unordered or equal
960
    SETUGT,        //    1 0 1 0       True if unordered or greater than
961
    SETUGE,        //    1 0 1 1       True if unordered, greater than, or equal
962
    SETULT,        //    1 1 0 0       True if unordered or less than
963
    SETULE,        //    1 1 0 1       True if unordered, less than, or equal
964
    SETUNE,        //    1 1 1 0       True if unordered or not equal
965
    SETTRUE,       //    1 1 1 1       Always true (always folded)
966
    // Don't care operations: undefined if the input is a nan.
967
    SETFALSE2,     //  1 X 0 0 0       Always false (always folded)
968
    SETEQ,         //  1 X 0 0 1       True if equal
969
    SETGT,         //  1 X 0 1 0       True if greater than
970
    SETGE,         //  1 X 0 1 1       True if greater than or equal
971
    SETLT,         //  1 X 1 0 0       True if less than
972
    SETLE,         //  1 X 1 0 1       True if less than or equal
973
    SETNE,         //  1 X 1 1 0       True if not equal
974
    SETTRUE2,      //  1 X 1 1 1       Always true (always folded)
975
976
    SETCC_INVALID       // Marker value.
977
  };
978
979
  /// Return true if this is a setcc instruction that performs a signed
980
  /// comparison when used with integer operands.
981
2.56M
  inline bool isSignedIntSetCC(CondCode Code) {
982
2.56M
    return Code == SETGT || 
Code == SETGE2.42M
||
Code == SETLT2.38M
||
Code == SETLE2.18M
;
983
2.56M
  }
984
985
  /// Return true if this is a setcc instruction that performs an unsigned
986
  /// comparison when used with integer operands.
987
28.9k
  inline bool isUnsignedIntSetCC(CondCode Code) {
988
28.9k
    return Code == SETUGT || 
Code == SETUGE27.5k
||
Code == SETULT26.9k
||
Code == SETULE23.4k
;
989
28.9k
  }
990
991
  /// Return true if the specified condition returns true if the two operands to
992
  /// the condition are equal. Note that if one of the two operands is a NaN,
993
  /// this value is meaningless.
994
8.59k
  inline bool isTrueWhenEqual(CondCode Cond) {
995
8.59k
    return ((int)Cond & 1) != 0;
996
8.59k
  }
997
998
  /// This function returns 0 if the condition is always false if an operand is
999
  /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
1000
  /// the condition is undefined if the operand is a NaN.
1001
3.38k
  inline unsigned getUnorderedFlavor(CondCode Cond) {
1002
3.38k
    return ((int)Cond >> 3) & 3;
1003
3.38k
  }
1004
1005
  /// Return the operation corresponding to !(X op Y), where 'op' is a valid
1006
  /// SetCC operation.
1007
  CondCode getSetCCInverse(CondCode Operation, bool isInteger);
1008
1009
  /// Return the operation corresponding to (Y op X) when given the operation
1010
  /// for (X op Y).
1011
  CondCode getSetCCSwappedOperands(CondCode Operation);
1012
1013
  /// Return the result of a logical OR between different comparisons of
1014
  /// identical values: ((X op1 Y) | (X op2 Y)). This function returns
1015
  /// SETCC_INVALID if it is not possible to represent the resultant comparison.
1016
  CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
1017
1018
  /// Return the result of a logical AND between different comparisons of
1019
  /// identical values: ((X op1 Y) & (X op2 Y)). This function returns
1020
  /// SETCC_INVALID if it is not possible to represent the resultant comparison.
1021
  CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
1022
1023
} // end llvm::ISD namespace
1024
1025
} // end llvm namespace
1026
1027
#endif