Coverage Report

Created: 2018-11-12 17:33

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/LiveIntervals.h
Line
Count
Source (jump to first uncovered line)
1
//===- LiveIntervals.h - Live Interval Analysis -----------------*- C++ -*-===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
/// \file This file implements the LiveInterval analysis pass.  Given some
11
/// numbering of each the machine instructions (in this implemention depth-first
12
/// order) an interval [i, j) is said to be a live interval for register v if
13
/// there is no instruction with number j' > j such that v is live at j' and
14
/// there is no instruction with number i' < i such that v is live at i'. In
15
/// this implementation intervals can have holes, i.e. an interval might look
16
/// like [1,20), [50,65), [1000,1001).
17
//
18
//===----------------------------------------------------------------------===//
19
20
#ifndef LLVM_CODEGEN_LIVEINTERVALS_H
21
#define LLVM_CODEGEN_LIVEINTERVALS_H
22
23
#include "llvm/ADT/ArrayRef.h"
24
#include "llvm/ADT/IndexedMap.h"
25
#include "llvm/ADT/SmallVector.h"
26
#include "llvm/Analysis/AliasAnalysis.h"
27
#include "llvm/CodeGen/LiveInterval.h"
28
#include "llvm/CodeGen/MachineBasicBlock.h"
29
#include "llvm/CodeGen/MachineFunctionPass.h"
30
#include "llvm/CodeGen/SlotIndexes.h"
31
#include "llvm/CodeGen/TargetRegisterInfo.h"
32
#include "llvm/MC/LaneBitmask.h"
33
#include "llvm/Support/CommandLine.h"
34
#include "llvm/Support/Compiler.h"
35
#include "llvm/Support/ErrorHandling.h"
36
#include <cassert>
37
#include <cstdint>
38
#include <utility>
39
40
namespace llvm {
41
42
extern cl::opt<bool> UseSegmentSetForPhysRegs;
43
44
class BitVector;
45
class LiveRangeCalc;
46
class MachineBlockFrequencyInfo;
47
class MachineDominatorTree;
48
class MachineFunction;
49
class MachineInstr;
50
class MachineRegisterInfo;
51
class raw_ostream;
52
class TargetInstrInfo;
53
class VirtRegMap;
54
55
  class LiveIntervals : public MachineFunctionPass {
56
    MachineFunction* MF;
57
    MachineRegisterInfo* MRI;
58
    const TargetRegisterInfo* TRI;
59
    const TargetInstrInfo* TII;
60
    AliasAnalysis *AA;
61
    SlotIndexes* Indexes;
62
    MachineDominatorTree *DomTree = nullptr;
63
    LiveRangeCalc *LRCalc = nullptr;
64
65
    /// Special pool allocator for VNInfo's (LiveInterval val#).
66
    VNInfo::Allocator VNInfoAllocator;
67
68
    /// Live interval pointers for all the virtual registers.
69
    IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
70
71
    /// Sorted list of instructions with register mask operands. Always use the
72
    /// 'r' slot, RegMasks are normal clobbers, not early clobbers.
73
    SmallVector<SlotIndex, 8> RegMaskSlots;
74
75
    /// This vector is parallel to RegMaskSlots, it holds a pointer to the
76
    /// corresponding register mask.  This pointer can be recomputed as:
77
    ///
78
    ///   MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
79
    ///   unsigned OpNum = findRegMaskOperand(MI);
80
    ///   RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
81
    ///
82
    /// This is kept in a separate vector partly because some standard
83
    /// libraries don't support lower_bound() with mixed objects, partly to
84
    /// improve locality when searching in RegMaskSlots.
85
    /// Also see the comment in LiveInterval::find().
86
    SmallVector<const uint32_t*, 8> RegMaskBits;
87
88
    /// For each basic block number, keep (begin, size) pairs indexing into the
89
    /// RegMaskSlots and RegMaskBits arrays.
90
    /// Note that basic block numbers may not be layout contiguous, that's why
91
    /// we can't just keep track of the first register mask in each basic
92
    /// block.
93
    SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
94
95
    /// Keeps a live range set for each register unit to track fixed physreg
96
    /// interference.
97
    SmallVector<LiveRange*, 0> RegUnitRanges;
98
99
  public:
100
    static char ID;
101
102
    LiveIntervals();
103
    ~LiveIntervals() override;
104
105
    /// Calculate the spill weight to assign to a single instruction.
106
    static float getSpillWeight(bool isDef, bool isUse,
107
                                const MachineBlockFrequencyInfo *MBFI,
108
                                const MachineInstr &MI);
109
110
    /// Calculate the spill weight to assign to a single instruction.
111
    static float getSpillWeight(bool isDef, bool isUse,
112
                                const MachineBlockFrequencyInfo *MBFI,
113
                                const MachineBasicBlock *MBB);
114
115
132M
    LiveInterval &getInterval(unsigned Reg) {
116
132M
      if (hasInterval(Reg))
117
132M
        return *VirtRegIntervals[Reg];
118
335k
      else
119
335k
        return createAndComputeVirtRegInterval(Reg);
120
132M
    }
121
122
37.9M
    const LiveInterval &getInterval(unsigned Reg) const {
123
37.9M
      return const_cast<LiveIntervals*>(this)->getInterval(Reg);
124
37.9M
    }
125
126
141M
    bool hasInterval(unsigned Reg) const {
127
141M
      return VirtRegIntervals.inBounds(Reg) && 
VirtRegIntervals[Reg]141M
;
128
141M
    }
129
130
    /// Interval creation.
131
13.2M
    LiveInterval &createEmptyInterval(unsigned Reg) {
132
13.2M
      assert(!hasInterval(Reg) && "Interval already exists!");
133
13.2M
      VirtRegIntervals.grow(Reg);
134
13.2M
      VirtRegIntervals[Reg] = createInterval(Reg);
135
13.2M
      return *VirtRegIntervals[Reg];
136
13.2M
    }
137
138
12.7M
    LiveInterval &createAndComputeVirtRegInterval(unsigned Reg) {
139
12.7M
      LiveInterval &LI = createEmptyInterval(Reg);
140
12.7M
      computeVirtRegInterval(LI);
141
12.7M
      return LI;
142
12.7M
    }
143
144
    /// Interval removal.
145
4.69M
    void removeInterval(unsigned Reg) {
146
4.69M
      delete VirtRegIntervals[Reg];
147
4.69M
      VirtRegIntervals[Reg] = nullptr;
148
4.69M
    }
149
150
    /// Given a register and an instruction, adds a live segment from that
151
    /// instruction to the end of its MBB.
152
    LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg,
153
                                                 MachineInstr &startInst);
154
155
    /// After removing some uses of a register, shrink its live range to just
156
    /// the remaining uses. This method does not compute reaching defs for new
157
    /// uses, and it doesn't remove dead defs.
158
    /// Dead PHIDef values are marked as unused. New dead machine instructions
159
    /// are added to the dead vector. Returns true if the interval may have been
160
    /// separated into multiple connected components.
161
    bool shrinkToUses(LiveInterval *li,
162
                      SmallVectorImpl<MachineInstr*> *dead = nullptr);
163
164
    /// Specialized version of
165
    /// shrinkToUses(LiveInterval *li, SmallVectorImpl<MachineInstr*> *dead)
166
    /// that works on a subregister live range and only looks at uses matching
167
    /// the lane mask of the subregister range.
168
    /// This may leave the subrange empty which needs to be cleaned up with
169
    /// LiveInterval::removeEmptySubranges() afterwards.
170
    void shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg);
171
172
    /// Extend the live range \p LR to reach all points in \p Indices. The
173
    /// points in the \p Indices array must be jointly dominated by the union
174
    /// of the existing defs in \p LR and points in \p Undefs.
175
    ///
176
    /// PHI-defs are added as needed to maintain SSA form.
177
    ///
178
    /// If a SlotIndex in \p Indices is the end index of a basic block, \p LR
179
    /// will be extended to be live out of the basic block.
180
    /// If a SlotIndex in \p Indices is jointy dominated only by points in
181
    /// \p Undefs, the live range will not be extended to that point.
182
    ///
183
    /// See also LiveRangeCalc::extend().
184
    void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices,
185
                         ArrayRef<SlotIndex> Undefs);
186
187
72.3k
    void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices) {
188
72.3k
      extendToIndices(LR, Indices, /*Undefs=*/{});
189
72.3k
    }
190
191
    /// If \p LR has a live value at \p Kill, prune its live range by removing
192
    /// any liveness reachable from Kill. Add live range end points to
193
    /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
194
    /// value's live range.
195
    ///
196
    /// Calling pruneValue() and extendToIndices() can be used to reconstruct
197
    /// SSA form after adding defs to a virtual register.
198
    void pruneValue(LiveRange &LR, SlotIndex Kill,
199
                    SmallVectorImpl<SlotIndex> *EndPoints);
200
201
    /// This function should not be used. Its intent is to tell you that you are
202
    /// doing something wrong if you call pruneValue directly on a
203
    /// LiveInterval. Indeed, you are supposed to call pruneValue on the main
204
    /// LiveRange and all the LiveRanges of the subranges if any.
205
    LLVM_ATTRIBUTE_UNUSED void pruneValue(LiveInterval &, SlotIndex,
206
0
                                          SmallVectorImpl<SlotIndex> *) {
207
0
      llvm_unreachable(
208
0
          "Use pruneValue on the main LiveRange and on each subrange");
209
0
    }
210
211
109M
    SlotIndexes *getSlotIndexes() const {
212
109M
      return Indexes;
213
109M
    }
214
215
3.82M
    AliasAnalysis *getAliasAnalysis() const {
216
3.82M
      return AA;
217
3.82M
    }
218
219
    /// Returns true if the specified machine instr has been removed or was
220
    /// never entered in the map.
221
10.3M
    bool isNotInMIMap(const MachineInstr &Instr) const {
222
10.3M
      return !Indexes->hasIndex(Instr);
223
10.3M
    }
224
225
    /// Returns the base index of the given instruction.
226
134M
    SlotIndex getInstructionIndex(const MachineInstr &Instr) const {
227
134M
      return Indexes->getInstructionIndex(Instr);
228
134M
    }
229
230
    /// Returns the instruction associated with the given index.
231
31.0M
    MachineInstr* getInstructionFromIndex(SlotIndex index) const {
232
31.0M
      return Indexes->getInstructionFromIndex(index);
233
31.0M
    }
234
235
    /// Return the first index in the given basic block.
236
30.2M
    SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
237
30.2M
      return Indexes->getMBBStartIdx(mbb);
238
30.2M
    }
239
240
    /// Return the last index in the given basic block.
241
11.7M
    SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
242
11.7M
      return Indexes->getMBBEndIdx(mbb);
243
11.7M
    }
244
245
    bool isLiveInToMBB(const LiveRange &LR,
246
773k
                       const MachineBasicBlock *mbb) const {
247
773k
      return LR.liveAt(getMBBStartIdx(mbb));
248
773k
    }
249
250
    bool isLiveOutOfMBB(const LiveRange &LR,
251
1.07M
                        const MachineBasicBlock *mbb) const {
252
1.07M
      return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
253
1.07M
    }
254
255
14.1M
    MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
256
14.1M
      return Indexes->getMBBFromIndex(index);
257
14.1M
    }
258
259
0
    void insertMBBInMaps(MachineBasicBlock *MBB) {
260
0
      Indexes->insertMBBInMaps(MBB);
261
0
      assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
262
0
             "Blocks must be added in order.");
263
0
      RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
264
0
    }
265
266
21.3k
    SlotIndex InsertMachineInstrInMaps(MachineInstr &MI) {
267
21.3k
      return Indexes->insertMachineInstrInMaps(MI);
268
21.3k
    }
269
270
    void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B,
271
141k
                                       MachineBasicBlock::iterator E) {
272
282k
      for (MachineBasicBlock::iterator I = B; I != E; 
++I141k
)
273
141k
        Indexes->insertMachineInstrInMaps(*I);
274
141k
    }
275
276
5.13M
    void RemoveMachineInstrFromMaps(MachineInstr &MI) {
277
5.13M
      Indexes->removeMachineInstrFromMaps(MI);
278
5.13M
    }
279
280
836k
    SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) {
281
836k
      return Indexes->replaceMachineInstrInMaps(MI, NewMI);
282
836k
    }
283
284
20.0M
    VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
285
286
    void getAnalysisUsage(AnalysisUsage &AU) const override;
287
    void releaseMemory() override;
288
289
    /// Pass entry point; Calculates LiveIntervals.
290
    bool runOnMachineFunction(MachineFunction&) override;
291
292
    /// Implement the dump method.
293
    void print(raw_ostream &O, const Module* = nullptr) const override;
294
295
    /// If LI is confined to a single basic block, return a pointer to that
296
    /// block.  If LI is live in to or out of any block, return NULL.
297
    MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
298
299
    /// Returns true if VNI is killed by any PHI-def values in LI.
300
    /// This may conservatively return true to avoid expensive computations.
301
    bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
302
303
    /// Add kill flags to any instruction that kills a virtual register.
304
    void addKillFlags(const VirtRegMap*);
305
306
    /// Call this method to notify LiveIntervals that instruction \p MI has been
307
    /// moved within a basic block. This will update the live intervals for all
308
    /// operands of \p MI. Moves between basic blocks are not supported.
309
    ///
310
    /// \param UpdateFlags Update live intervals for nonallocatable physregs.
311
    void handleMove(MachineInstr &MI, bool UpdateFlags = false);
312
313
    /// Update intervals for operands of \p MI so that they begin/end on the
314
    /// SlotIndex for \p BundleStart.
315
    ///
316
    /// \param UpdateFlags Update live intervals for nonallocatable physregs.
317
    ///
318
    /// Requires MI and BundleStart to have SlotIndexes, and assumes
319
    /// existing liveness is accurate. BundleStart should be the first
320
    /// instruction in the Bundle.
321
    void handleMoveIntoBundle(MachineInstr &MI, MachineInstr &BundleStart,
322
                              bool UpdateFlags = false);
323
324
    /// Update live intervals for instructions in a range of iterators. It is
325
    /// intended for use after target hooks that may insert or remove
326
    /// instructions, and is only efficient for a small number of instructions.
327
    ///
328
    /// OrigRegs is a vector of registers that were originally used by the
329
    /// instructions in the range between the two iterators.
330
    ///
331
    /// Currently, the only only changes that are supported are simple removal
332
    /// and addition of uses.
333
    void repairIntervalsInRange(MachineBasicBlock *MBB,
334
                                MachineBasicBlock::iterator Begin,
335
                                MachineBasicBlock::iterator End,
336
                                ArrayRef<unsigned> OrigRegs);
337
338
    // Register mask functions.
339
    //
340
    // Machine instructions may use a register mask operand to indicate that a
341
    // large number of registers are clobbered by the instruction.  This is
342
    // typically used for calls.
343
    //
344
    // For compile time performance reasons, these clobbers are not recorded in
345
    // the live intervals for individual physical registers.  Instead,
346
    // LiveIntervalAnalysis maintains a sorted list of instructions with
347
    // register mask operands.
348
349
    /// Returns a sorted array of slot indices of all instructions with
350
    /// register mask operands.
351
77.7M
    ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
352
353
    /// Returns a sorted array of slot indices of all instructions with register
354
    /// mask operands in the basic block numbered \p MBBNum.
355
72.7M
    ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
356
72.7M
      std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
357
72.7M
      return getRegMaskSlots().slice(P.first, P.second);
358
72.7M
    }
359
360
    /// Returns an array of register mask pointers corresponding to
361
    /// getRegMaskSlots().
362
75.1M
    ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
363
364
    /// Returns an array of mask pointers corresponding to
365
    /// getRegMaskSlotsInBlock(MBBNum).
366
72.7M
    ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
367
72.7M
      std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
368
72.7M
      return getRegMaskBits().slice(P.first, P.second);
369
72.7M
    }
370
371
    /// Test if \p LI is live across any register mask instructions, and
372
    /// compute a bit mask of physical registers that are not clobbered by any
373
    /// of them.
374
    ///
375
    /// Returns false if \p LI doesn't cross any register mask instructions. In
376
    /// that case, the bit vector is not filled in.
377
    bool checkRegMaskInterference(LiveInterval &LI,
378
                                  BitVector &UsableRegs);
379
380
    // Register unit functions.
381
    //
382
    // Fixed interference occurs when MachineInstrs use physregs directly
383
    // instead of virtual registers. This typically happens when passing
384
    // arguments to a function call, or when instructions require operands in
385
    // fixed registers.
386
    //
387
    // Each physreg has one or more register units, see MCRegisterInfo. We
388
    // track liveness per register unit to handle aliasing registers more
389
    // efficiently.
390
391
    /// Return the live range for register unit \p Unit. It will be computed if
392
    /// it doesn't exist.
393
73.3M
    LiveRange &getRegUnit(unsigned Unit) {
394
73.3M
      LiveRange *LR = RegUnitRanges[Unit];
395
73.3M
      if (!LR) {
396
2.78M
        // Compute missing ranges on demand.
397
2.78M
        // Use segment set to speed-up initial computation of the live range.
398
2.78M
        RegUnitRanges[Unit] = LR = new LiveRange(UseSegmentSetForPhysRegs);
399
2.78M
        computeRegUnitRange(*LR, Unit);
400
2.78M
      }
401
73.3M
      return *LR;
402
73.3M
    }
403
404
    /// Return the live range for register unit \p Unit if it has already been
405
    /// computed, or nullptr if it hasn't been computed yet.
406
68.1M
    LiveRange *getCachedRegUnit(unsigned Unit) {
407
68.1M
      return RegUnitRanges[Unit];
408
68.1M
    }
409
410
1.99M
    const LiveRange *getCachedRegUnit(unsigned Unit) const {
411
1.99M
      return RegUnitRanges[Unit];
412
1.99M
    }
413
414
    /// Remove computed live range for register unit \p Unit. Subsequent uses
415
    /// should rely on on-demand recomputation.
416
860
    void removeRegUnit(unsigned Unit) {
417
860
      delete RegUnitRanges[Unit];
418
860
      RegUnitRanges[Unit] = nullptr;
419
860
    }
420
421
    /// Remove value numbers and related live segments starting at position
422
    /// \p Pos that are part of any liverange of physical register \p Reg or one
423
    /// of its subregisters.
424
    void removePhysRegDefAt(unsigned Reg, SlotIndex Pos);
425
426
    /// Remove value number and related live segments of \p LI and its subranges
427
    /// that start at position \p Pos.
428
    void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos);
429
430
    /// Split separate components in LiveInterval \p LI into separate intervals.
431
    void splitSeparateComponents(LiveInterval &LI,
432
                                 SmallVectorImpl<LiveInterval*> &SplitLIs);
433
434
    /// For live interval \p LI with correct SubRanges construct matching
435
    /// information for the main live range. Expects the main live range to not
436
    /// have any segments or value numbers.
437
    void constructMainRangeFromSubranges(LiveInterval &LI);
438
439
  private:
440
    /// Compute live intervals for all virtual registers.
441
    void computeVirtRegs();
442
443
    /// Compute RegMaskSlots and RegMaskBits.
444
    void computeRegMasks();
445
446
    /// Walk the values in \p LI and check for dead values:
447
    /// - Dead PHIDef values are marked as unused.
448
    /// - Dead operands are marked as such.
449
    /// - Completely dead machine instructions are added to the \p dead vector
450
    ///   if it is not nullptr.
451
    /// Returns true if any PHI value numbers have been removed which may
452
    /// have separated the interval into multiple connected components.
453
    bool computeDeadValues(LiveInterval &LI,
454
                           SmallVectorImpl<MachineInstr*> *dead);
455
456
    static LiveInterval* createInterval(unsigned Reg);
457
458
    void printInstrs(raw_ostream &O) const;
459
    void dumpInstrs() const;
460
461
    void computeLiveInRegUnits();
462
    void computeRegUnitRange(LiveRange&, unsigned Unit);
463
    void computeVirtRegInterval(LiveInterval&);
464
465
    using ShrinkToUsesWorkList = SmallVector<std::pair<SlotIndex, VNInfo*>, 16>;
466
    void extendSegmentsToUses(LiveRange &Segments,
467
                              ShrinkToUsesWorkList &WorkList, unsigned Reg,
468
                              LaneBitmask LaneMask);
469
470
    /// Helper function for repairIntervalsInRange(), walks backwards and
471
    /// creates/modifies live segments in \p LR to match the operands found.
472
    /// Only full operands or operands with subregisters matching \p LaneMask
473
    /// are considered.
474
    void repairOldRegInRange(MachineBasicBlock::iterator Begin,
475
                             MachineBasicBlock::iterator End,
476
                             const SlotIndex endIdx, LiveRange &LR,
477
                             unsigned Reg,
478
                             LaneBitmask LaneMask = LaneBitmask::getAll());
479
480
    class HMEditor;
481
  };
482
483
} // end namespace llvm
484
485
#endif