Coverage Report

Created: 2018-09-19 08:35

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/LivePhysRegs.h
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//===- llvm/CodeGen/LivePhysRegs.h - Live Physical Register Set -*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file implements the LivePhysRegs utility for tracking liveness of
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/// physical registers. This can be used for ad-hoc liveness tracking after
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/// register allocation. You can start with the live-ins/live-outs at the
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/// beginning/end of a block and update the information while walking the
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/// instructions inside the block. This implementation tracks the liveness on a
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/// sub-register granularity.
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///
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/// We assume that the high bits of a physical super-register are not preserved
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/// unless the instruction has an implicit-use operand reading the super-
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/// register.
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///
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/// X86 Example:
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/// %ymm0 = ...
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/// %xmm0 = ... (Kills %xmm0, all %xmm0s sub-registers, and %ymm0)
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///
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/// %ymm0 = ...
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/// %xmm0 = ..., implicit %ymm0 (%ymm0 and all its sub-registers are alive)
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVEPHYSREGS_H
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#define LLVM_CODEGEN_LIVEPHYSREGS_H
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#include "llvm/ADT/SparseSet.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include <cassert>
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#include <utility>
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namespace llvm {
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class MachineInstr;
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class MachineOperand;
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class MachineRegisterInfo;
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class raw_ostream;
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/// A set of physical registers with utility functions to track liveness
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/// when walking backward/forward through a basic block.
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class LivePhysRegs {
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  const TargetRegisterInfo *TRI = nullptr;
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  SparseSet<unsigned> LiveRegs;
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public:
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  /// Constructs an unitialized set. init() needs to be called to initialize it.
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1.21M
  LivePhysRegs() = default;
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  /// Constructs and initializes an empty set.
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121k
  LivePhysRegs(const TargetRegisterInfo &TRI) : TRI(&TRI) {
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121k
    LiveRegs.setUniverse(TRI.getNumRegs());
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  }
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  LivePhysRegs(const LivePhysRegs&) = delete;
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  LivePhysRegs &operator=(const LivePhysRegs&) = delete;
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  /// (re-)initializes and clears the set.
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  void init(const TargetRegisterInfo &TRI) {
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    this->TRI = &TRI;
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    LiveRegs.clear();
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    LiveRegs.setUniverse(TRI.getNumRegs());
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  }
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  /// Clears the set.
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701k
  void clear() { LiveRegs.clear(); }
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  /// Returns true if the set is empty.
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849k
  bool empty() const { return LiveRegs.empty(); }
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  /// Adds a physical register and all its sub-registers to the set.
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22.5M
  void addReg(unsigned Reg) {
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22.5M
    assert(TRI && "LivePhysRegs is not initialized.");
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22.5M
    assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
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22.5M
    for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
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         SubRegs.isValid(); 
++SubRegs70.7M
)
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      LiveRegs.insert(*SubRegs);
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  }
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  /// Removes a physical register, all its sub-registers, and all its
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  /// super-registers from the set.
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  void removeReg(unsigned Reg) {
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    assert(TRI && "LivePhysRegs is not initialized.");
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    assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
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    for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); 
++R67.0M
)
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      LiveRegs.erase(*R);
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  }
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  /// Removes physical registers clobbered by the regmask operand \p MO.
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  void removeRegsInMask(const MachineOperand &MO,
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        SmallVectorImpl<std::pair<unsigned, const MachineOperand*>> *Clobbers =
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        nullptr);
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  /// Returns true if register \p Reg is contained in the set. This also
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  /// works if only the super register of \p Reg has been defined, because
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  /// addReg() always adds all sub-registers to the set as well.
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  /// Note: Returns false if just some sub registers are live, use available()
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  /// when searching a free register.
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5.02M
  bool contains(unsigned Reg) const { return LiveRegs.count(Reg); }
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  /// Returns true if register \p Reg and no aliasing register is in the set.
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  bool available(const MachineRegisterInfo &MRI, unsigned Reg) const;
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  /// Remove defined registers and regmask kills from the set.
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  void removeDefs(const MachineInstr &MI);
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  /// Add uses to the set.
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  void addUses(const MachineInstr &MI);
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  /// Simulates liveness when stepping backwards over an instruction(bundle).
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  /// Remove Defs, add uses. This is the recommended way of calculating
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  /// liveness.
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  void stepBackward(const MachineInstr &MI);
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  /// Simulates liveness when stepping forward over an instruction(bundle).
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  /// Remove killed-uses, add defs. This is the not recommended way, because it
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  /// depends on accurate kill flags. If possible use stepBackward() instead of
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  /// this function. The clobbers set will be the list of registers either
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  /// defined or clobbered by a regmask.  The operand will identify whether this
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  /// is a regmask or register operand.
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  void stepForward(const MachineInstr &MI,
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        SmallVectorImpl<std::pair<unsigned, const MachineOperand*>> &Clobbers);
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  /// Adds all live-in registers of basic block \p MBB.
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  /// Live in registers are the registers in the blocks live-in list and the
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  /// pristine registers.
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  void addLiveIns(const MachineBasicBlock &MBB);
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  /// Adds all live-out registers of basic block \p MBB.
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  /// Live out registers are the union of the live-in registers of the successor
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  /// blocks and pristine registers. Live out registers of the end block are the
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  /// callee saved registers.
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  void addLiveOuts(const MachineBasicBlock &MBB);
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  /// Adds all live-out registers of basic block \p MBB but skips pristine
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  /// registers.
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  void addLiveOutsNoPristines(const MachineBasicBlock &MBB);
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  using const_iterator = SparseSet<unsigned>::const_iterator;
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  const_iterator begin() const { return LiveRegs.begin(); }
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  const_iterator end() const { return LiveRegs.end(); }
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  /// Prints the currently live registers to \p OS.
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  void print(raw_ostream &OS) const;
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  /// Dumps the currently live registers to the debug output.
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  void dump() const;
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private:
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  /// Adds live-in registers from basic block \p MBB, taking associated
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  /// lane masks into consideration.
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  void addBlockLiveIns(const MachineBasicBlock &MBB);
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  /// Adds pristine registers. Pristine registers are callee saved registers
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  /// that are unused in the function.
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  void addPristines(const MachineFunction &MF);
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};
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inline raw_ostream &operator<<(raw_ostream &OS, const LivePhysRegs& LR) {
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  LR.print(OS);
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  return OS;
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}
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/// Computes registers live-in to \p MBB assuming all of its successors
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/// live-in lists are up-to-date. Puts the result into the given LivePhysReg
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/// instance \p LiveRegs.
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void computeLiveIns(LivePhysRegs &LiveRegs, const MachineBasicBlock &MBB);
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/// Recomputes dead and kill flags in \p MBB.
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void recomputeLivenessFlags(MachineBasicBlock &MBB);
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/// Adds registers contained in \p LiveRegs to the block live-in list of \p MBB.
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/// Does not add reserved registers.
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void addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs);
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/// Convenience function combining computeLiveIns() and addLiveIns().
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void computeAndAddLiveIns(LivePhysRegs &LiveRegs,
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                          MachineBasicBlock &MBB);
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/// Convenience function for recomputing live-in's for \p MBB.
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18.4k
static inline void recomputeLiveIns(MachineBasicBlock &MBB) {
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  LivePhysRegs LPR;
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  MBB.clearLiveIns();
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  computeAndAddLiveIns(LPR, MBB);
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}
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} // end namespace llvm
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#endif // LLVM_CODEGEN_LIVEPHYSREGS_H