Coverage Report

Created: 2019-02-21 13:17

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/LiveRangeEdit.h
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//===- LiveRangeEdit.h - Basic tools for split and spill --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The LiveRangeEdit class represents changes done to a virtual register when it
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// is spilled or split.
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//
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// The parent register is never changed. Instead, a number of new virtual
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// registers are created and added to the newRegs vector.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVERANGEEDIT_H
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#define LLVM_CODEGEN_LIVERANGEEDIT_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/None.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include <cassert>
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namespace llvm {
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class LiveIntervals;
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class MachineBlockFrequencyInfo;
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class MachineInstr;
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class MachineLoopInfo;
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class MachineOperand;
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class TargetInstrInfo;
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class TargetRegisterInfo;
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class VirtRegMap;
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class LiveRangeEdit : private MachineRegisterInfo::Delegate {
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public:
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  /// Callback methods for LiveRangeEdit owners.
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  class Delegate {
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    virtual void anchor();
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  public:
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526k
    virtual ~Delegate() = default;
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    /// Called immediately before erasing a dead machine instruction.
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    virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}
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    /// Called when a virtual register is no longer used. Return false to defer
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    /// its deletion from LiveIntervals.
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    virtual bool LRE_CanEraseVirtReg(unsigned) { return true; }
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    /// Called before shrinking the live range of a virtual register.
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    virtual void LRE_WillShrinkVirtReg(unsigned) {}
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    /// Called after cloning a virtual register.
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    /// This is used for new registers representing connected components of Old.
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    virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {}
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  };
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private:
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  LiveInterval *Parent;
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  SmallVectorImpl<unsigned> &NewRegs;
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  MachineRegisterInfo &MRI;
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  LiveIntervals &LIS;
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  VirtRegMap *VRM;
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  const TargetInstrInfo &TII;
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  Delegate *const TheDelegate;
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  /// FirstNew - Index of the first register added to NewRegs.
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  const unsigned FirstNew;
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  /// ScannedRemattable - true when remattable values have been identified.
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  bool ScannedRemattable = false;
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  /// DeadRemats - The saved instructions which have already been dead after
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  /// rematerialization but not deleted yet -- to be done in postOptimization.
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  SmallPtrSet<MachineInstr *, 32> *DeadRemats;
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  /// Remattable - Values defined by remattable instructions as identified by
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  /// tii.isTriviallyReMaterializable().
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  SmallPtrSet<const VNInfo *, 4> Remattable;
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  /// Rematted - Values that were actually rematted, and so need to have their
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  /// live range trimmed or entirely removed.
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  SmallPtrSet<const VNInfo *, 4> Rematted;
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  /// scanRemattable - Identify the Parent values that may rematerialize.
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  void scanRemattable(AliasAnalysis *aa);
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  /// allUsesAvailableAt - Return true if all registers used by OrigMI at
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  /// OrigIdx are also available with the same value at UseIdx.
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  bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
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                          SlotIndex UseIdx) const;
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  /// foldAsLoad - If LI has a single use and a single def that can be folded as
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  /// a load, eliminate the register by folding the def into the use.
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  bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr *> &Dead);
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  using ToShrinkSet = SetVector<LiveInterval *, SmallVector<LiveInterval *, 8>,
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                                SmallPtrSet<LiveInterval *, 8>>;
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  /// Helper for eliminateDeadDefs.
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  void eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
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                        AliasAnalysis *AA);
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  /// MachineRegisterInfo callback to notify when new virtual
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  /// registers are created.
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  void MRI_NoteNewVirtualRegister(unsigned VReg) override;
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  /// Check if MachineOperand \p MO is a last use/kill either in the
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  /// main live range of \p LI or in one of the matching subregister ranges.
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  bool useIsKill(const LiveInterval &LI, const MachineOperand &MO) const;
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  /// Create a new empty interval based on OldReg.
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  LiveInterval &createEmptyIntervalFrom(unsigned OldReg, bool createSubRanges);
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public:
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  /// Create a LiveRangeEdit for breaking down parent into smaller pieces.
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  /// @param parent The register being spilled or split.
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  /// @param newRegs List to receive any new registers created. This needn't be
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  ///                empty initially, any existing registers are ignored.
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  /// @param MF The MachineFunction the live range edit is taking place in.
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  /// @param lis The collection of all live intervals in this function.
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  /// @param vrm Map of virtual registers to physical registers for this
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  ///            function.  If NULL, no virtual register map updates will
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  ///            be done.  This could be the case if called before Regalloc.
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  /// @param deadRemats The collection of all the instructions defining an
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  ///                   original reg and are dead after remat.
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  LiveRangeEdit(LiveInterval *parent, SmallVectorImpl<unsigned> &newRegs,
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                MachineFunction &MF, LiveIntervals &lis, VirtRegMap *vrm,
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                Delegate *delegate = nullptr,
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                SmallPtrSet<MachineInstr *, 32> *deadRemats = nullptr)
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      : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis),
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        VRM(vrm), TII(*MF.getSubtarget().getInstrInfo()), TheDelegate(delegate),
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        FirstNew(newRegs.size()), DeadRemats(deadRemats) {
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    MRI.setDelegate(this);
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  }
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  ~LiveRangeEdit() override { MRI.resetDelegate(this); }
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  LiveInterval &getParent() const {
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    assert(Parent && "No parent LiveInterval");
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    return *Parent;
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  }
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  unsigned getReg() const { return getParent().reg; }
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  /// Iterator for accessing the new registers added by this edit.
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  using iterator = SmallVectorImpl<unsigned>::const_iterator;
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  iterator begin() const { return NewRegs.begin() + FirstNew; }
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  iterator end() const { return NewRegs.end(); }
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  unsigned size() const { return NewRegs.size() - FirstNew; }
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  bool empty() const { return size() == 0; }
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  unsigned get(unsigned idx) const { return NewRegs[idx + FirstNew]; }
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  /// pop_back - It allows LiveRangeEdit users to drop new registers.
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  /// The context is when an original def instruction of a register is
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  /// dead after rematerialization, we still want to keep it for following
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  /// rematerializations. We save the def instruction in DeadRemats,
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  /// and replace the original dst register with a new dummy register so
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  /// the live range of original dst register can be shrinked normally.
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  /// We don't want to allocate phys register for the dummy register, so
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  /// we want to drop it from the NewRegs set.
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  void pop_back() { NewRegs.pop_back(); }
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  ArrayRef<unsigned> regs() const {
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    return makeArrayRef(NewRegs).slice(FirstNew);
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  }
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  /// createFrom - Create a new virtual register based on OldReg.
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  unsigned createFrom(unsigned OldReg);
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  /// create - Create a new register with the same class and original slot as
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  /// parent.
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  LiveInterval &createEmptyInterval() {
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    return createEmptyIntervalFrom(getReg(), true);
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  }
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  unsigned create() { return createFrom(getReg()); }
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  /// anyRematerializable - Return true if any parent values may be
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  /// rematerializable.
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  /// This function must be called before any rematerialization is attempted.
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  bool anyRematerializable(AliasAnalysis *);
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  /// checkRematerializable - Manually add VNI to the list of rematerializable
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  /// values if DefMI may be rematerializable.
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  bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
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                             AliasAnalysis *);
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  /// Remat - Information needed to rematerialize at a specific location.
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  struct Remat {
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    VNInfo *ParentVNI;              // parent_'s value at the remat location.
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    MachineInstr *OrigMI = nullptr; // Instruction defining OrigVNI. It contains
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                                    // the real expr for remat.
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    explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI) {}
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  };
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  /// canRematerializeAt - Determine if ParentVNI can be rematerialized at
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  /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
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  /// When cheapAsAMove is set, only cheap remats are allowed.
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  bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx,
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                          bool cheapAsAMove);
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  /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an
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  /// instruction into MBB before MI. The new instruction is mapped, but
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  /// liveness is not updated.
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  /// Return the SlotIndex of the new instruction.
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  SlotIndex rematerializeAt(MachineBasicBlock &MBB,
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                            MachineBasicBlock::iterator MI, unsigned DestReg,
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                            const Remat &RM, const TargetRegisterInfo &,
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                            bool Late = false);
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  /// markRematerialized - explicitly mark a value as rematerialized after doing
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  /// it manually.
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  void markRematerialized(const VNInfo *ParentVNI) {
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    Rematted.insert(ParentVNI);
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  }
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  /// didRematerialize - Return true if ParentVNI was rematerialized anywhere.
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  bool didRematerialize(const VNInfo *ParentVNI) const {
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    return Rematted.count(ParentVNI);
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  }
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  /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
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  /// to erase it from LIS.
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  void eraseVirtReg(unsigned Reg);
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  /// eliminateDeadDefs - Try to delete machine instructions that are now dead
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  /// (allDefsAreDead returns true). This may cause live intervals to be trimmed
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  /// and further dead efs to be eliminated.
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  /// RegsBeingSpilled lists registers currently being spilled by the register
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  /// allocator.  These registers should not be split into new intervals
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  /// as currently those new intervals are not guaranteed to spill.
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  void eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead,
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                         ArrayRef<unsigned> RegsBeingSpilled = None,
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                         AliasAnalysis *AA = nullptr);
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  /// calculateRegClassAndHint - Recompute register class and hint for each new
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  /// register.
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  void calculateRegClassAndHint(MachineFunction &, const MachineLoopInfo &,
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                                const MachineBlockFrequencyInfo &);
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_LIVERANGEEDIT_H