/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/LiveRegUnits.h
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1 | | //===- llvm/CodeGen/LiveRegUnits.h - Register Unit Set ----------*- C++ -*-===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | /// \file |
10 | | /// A set of register units. It is intended for register liveness tracking. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #ifndef LLVM_CODEGEN_LIVEREGUNITS_H |
15 | | #define LLVM_CODEGEN_LIVEREGUNITS_H |
16 | | |
17 | | #include "llvm/ADT/BitVector.h" |
18 | | #include "llvm/CodeGen/MachineRegisterInfo.h" |
19 | | #include "llvm/CodeGen/TargetRegisterInfo.h" |
20 | | #include "llvm/MC/LaneBitmask.h" |
21 | | #include "llvm/MC/MCRegisterInfo.h" |
22 | | #include <cstdint> |
23 | | |
24 | | namespace llvm { |
25 | | |
26 | | class MachineInstr; |
27 | | class MachineBasicBlock; |
28 | | |
29 | | /// A set of register units used to track register liveness. |
30 | | class LiveRegUnits { |
31 | | const TargetRegisterInfo *TRI = nullptr; |
32 | | BitVector Units; |
33 | | |
34 | | public: |
35 | | /// Constructs a new empty LiveRegUnits set. |
36 | 1.11M | LiveRegUnits() = default; |
37 | | |
38 | | /// Constructs and initialize an empty LiveRegUnits set. |
39 | 355k | LiveRegUnits(const TargetRegisterInfo &TRI) { |
40 | 355k | init(TRI); |
41 | 355k | } |
42 | | |
43 | | /// For a machine instruction \p MI, adds all register units used in |
44 | | /// \p UsedRegUnits and defined or clobbered in \p ModifiedRegUnits. This is |
45 | | /// useful when walking over a range of instructions to track registers |
46 | | /// used or defined seperately. |
47 | | static void accumulateUsedDefed(const MachineInstr &MI, |
48 | | LiveRegUnits &ModifiedRegUnits, |
49 | | LiveRegUnits &UsedRegUnits, |
50 | 38.7M | const TargetRegisterInfo *TRI) { |
51 | 175M | for (ConstMIBundleOperands O(MI); O.isValid(); ++O137M ) { |
52 | 137M | if (O->isRegMask()) |
53 | 1.24M | ModifiedRegUnits.addRegsInMask(O->getRegMask()); |
54 | 137M | if (!O->isReg()) |
55 | 45.5M | continue; |
56 | 91.6M | unsigned Reg = O->getReg(); |
57 | 91.6M | if (!TargetRegisterInfo::isPhysicalRegister(Reg)) |
58 | 445k | continue; |
59 | 91.2M | if (O->isDef()) { |
60 | 35.3M | // Some architectures (e.g. AArch64 XZR/WZR) have registers that are |
61 | 35.3M | // constant and may be used as destinations to indicate the generated |
62 | 35.3M | // value is discarded. No need to track such case as a def. |
63 | 35.3M | if (!TRI->isConstantPhysReg(Reg)) |
64 | 33.1M | ModifiedRegUnits.addReg(Reg); |
65 | 55.8M | } else { |
66 | 55.8M | assert(O->isUse() && "Reg operand not a def and not a use"); |
67 | 55.8M | UsedRegUnits.addReg(Reg); |
68 | 55.8M | } |
69 | 91.2M | } |
70 | 38.7M | return; |
71 | 38.7M | } |
72 | | |
73 | | /// Initialize and clear the set. |
74 | 3.43M | void init(const TargetRegisterInfo &TRI) { |
75 | 3.43M | this->TRI = &TRI; |
76 | 3.43M | Units.reset(); |
77 | 3.43M | Units.resize(TRI.getNumRegUnits()); |
78 | 3.43M | } |
79 | | |
80 | | /// Clears the set. |
81 | 26.6M | void clear() { Units.reset(); } |
82 | | |
83 | | /// Returns true if the set is empty. |
84 | 82.1k | bool empty() const { return Units.none(); } |
85 | | |
86 | | /// Adds register units covered by physical register \p Reg. |
87 | 91.5M | void addReg(MCPhysReg Reg) { |
88 | 184M | for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit93.1M ) |
89 | 93.1M | Units.set(*Unit); |
90 | 91.5M | } |
91 | | |
92 | | /// Adds register units covered by physical register \p Reg that are |
93 | | /// part of the lanemask \p Mask. |
94 | 2.02M | void addRegMasked(MCPhysReg Reg, LaneBitmask Mask) { |
95 | 4.36M | for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit2.33M ) { |
96 | 2.33M | LaneBitmask UnitMask = (*Unit).second; |
97 | 2.33M | if (UnitMask.none() || (UnitMask & Mask).any()1.84M ) |
98 | 2.33M | Units.set((*Unit).first); |
99 | 2.33M | } |
100 | 2.02M | } |
101 | | |
102 | | /// Removes all register units covered by physical register \p Reg. |
103 | 1.49M | void removeReg(MCPhysReg Reg) { |
104 | 3.01M | for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit1.52M ) |
105 | 1.52M | Units.reset(*Unit); |
106 | 1.49M | } |
107 | | |
108 | | /// Removes register units not preserved by the regmask \p RegMask. |
109 | | /// The regmask has the same format as the one in the RegMask machine operand. |
110 | | void removeRegsNotPreserved(const uint32_t *RegMask); |
111 | | |
112 | | /// Adds register units not preserved by the regmask \p RegMask. |
113 | | /// The regmask has the same format as the one in the RegMask machine operand. |
114 | | void addRegsInMask(const uint32_t *RegMask); |
115 | | |
116 | | /// Returns true if no part of physical register \p Reg is live. |
117 | 53.2M | bool available(MCPhysReg Reg) const { |
118 | 100M | for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit47.0M ) { |
119 | 53.4M | if (Units.test(*Unit)) |
120 | 6.35M | return false; |
121 | 53.4M | } |
122 | 53.2M | return true46.8M ; |
123 | 53.2M | } |
124 | | |
125 | | /// Updates liveness when stepping backwards over the instruction \p MI. |
126 | | /// This removes all register units defined or clobbered in \p MI and then |
127 | | /// adds the units used (as in use operands) in \p MI. |
128 | | void stepBackward(const MachineInstr &MI); |
129 | | |
130 | | /// Adds all register units used, defined or clobbered in \p MI. |
131 | | /// This is useful when walking over a range of instruction to find registers |
132 | | /// unused over the whole range. |
133 | | void accumulate(const MachineInstr &MI); |
134 | | |
135 | | /// Adds registers living out of block \p MBB. |
136 | | /// Live out registers are the union of the live-in registers of the successor |
137 | | /// blocks and pristine registers. Live out registers of the end block are the |
138 | | /// callee saved registers. |
139 | | void addLiveOuts(const MachineBasicBlock &MBB); |
140 | | |
141 | | /// Adds registers living into block \p MBB. |
142 | | void addLiveIns(const MachineBasicBlock &MBB); |
143 | | |
144 | | /// Adds all register units marked in the bitvector \p RegUnits. |
145 | 23.3k | void addUnits(const BitVector &RegUnits) { |
146 | 23.3k | Units |= RegUnits; |
147 | 23.3k | } |
148 | | /// Removes all register units marked in the bitvector \p RegUnits. |
149 | 23.1k | void removeUnits(const BitVector &RegUnits) { |
150 | 23.1k | Units.reset(RegUnits); |
151 | 23.1k | } |
152 | | /// Return the internal bitvector representation of the set. |
153 | 161 | const BitVector &getBitVector() const { |
154 | 161 | return Units; |
155 | 161 | } |
156 | | |
157 | | private: |
158 | | /// Adds pristine registers. Pristine registers are callee saved registers |
159 | | /// that are unused in the function. |
160 | | void addPristines(const MachineFunction &MF); |
161 | | }; |
162 | | |
163 | | } // end namespace llvm |
164 | | |
165 | | #endif // LLVM_CODEGEN_LIVEREGUNITS_H |