Coverage Report

Created: 2019-02-15 18:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/LiveRegUnits.h
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//===- llvm/CodeGen/LiveRegUnits.h - Register Unit Set ----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// A set of register units. It is intended for register liveness tracking.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVEREGUNITS_H
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#define LLVM_CODEGEN_LIVEREGUNITS_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/LaneBitmask.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include <cstdint>
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namespace llvm {
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class MachineInstr;
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class MachineBasicBlock;
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/// A set of register units used to track register liveness.
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class LiveRegUnits {
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  const TargetRegisterInfo *TRI = nullptr;
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  BitVector Units;
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public:
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  /// Constructs a new empty LiveRegUnits set.
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1.08M
  LiveRegUnits() = default;
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  /// Constructs and initialize an empty LiveRegUnits set.
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364k
  LiveRegUnits(const TargetRegisterInfo &TRI) {
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    init(TRI);
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  }
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  /// For a machine instruction \p MI, adds all register units used in
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  /// \p UsedRegUnits and defined or clobbered in \p ModifiedRegUnits. This is
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  /// useful when walking over a range of instructions to track registers
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  /// used or defined seperately.
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  static void accumulateUsedDefed(const MachineInstr &MI,
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                                  LiveRegUnits &ModifiedRegUnits,
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                                  LiveRegUnits &UsedRegUnits,
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40.9M
                                  const TargetRegisterInfo *TRI) {
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187M
    for (ConstMIBundleOperands O(MI); O.isValid(); 
++O146M
) {
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146M
      if (O->isRegMask())
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1.30M
        ModifiedRegUnits.addRegsInMask(O->getRegMask());
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146M
      if (!O->isReg())
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        continue;
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100M
      unsigned Reg = O->getReg();
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100M
      if (!TargetRegisterInfo::isPhysicalRegister(Reg))
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520k
        continue;
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99.4M
      if (O->isDef()) {
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        // Some architectures (e.g. AArch64 XZR/WZR) have registers that are
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39.1M
        // constant and may be used as destinations to indicate the generated
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        // value is discarded. No need to track such case as a def.
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39.1M
        if (!TRI->isConstantPhysReg(Reg))
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36.2M
          ModifiedRegUnits.addReg(Reg);
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60.3M
      } else {
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60.3M
        assert(O->isUse() && "Reg operand not a def and not a use");
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60.3M
        UsedRegUnits.addReg(Reg);
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60.3M
      }
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99.4M
    }
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40.9M
    return;
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  }
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  /// Initialize and clear the set.
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  void init(const TargetRegisterInfo &TRI) {
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    this->TRI = &TRI;
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    Units.reset();
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    Units.resize(TRI.getNumRegUnits());
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  }
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  /// Clears the set.
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  void clear() { Units.reset(); }
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  /// Returns true if the set is empty.
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  bool empty() const { return Units.none(); }
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  /// Adds register units covered by physical register \p Reg.
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97.5M
  void addReg(MCPhysReg Reg) {
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    for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); 
++Unit99.1M
)
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      Units.set(*Unit);
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  }
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  /// Adds register units covered by physical register \p Reg that are
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  /// part of the lanemask \p Mask.
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  void addRegMasked(MCPhysReg Reg, LaneBitmask Mask) {
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    for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); 
++Unit2.18M
) {
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      LaneBitmask UnitMask = (*Unit).second;
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      if (UnitMask.none() || 
(UnitMask & Mask).any()1.81M
)
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        Units.set((*Unit).first);
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    }
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  }
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  /// Removes all register units covered by physical register \p Reg.
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  void removeReg(MCPhysReg Reg) {
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    for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); 
++Unit666k
)
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      Units.reset(*Unit);
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  }
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  /// Removes register units not preserved by the regmask \p RegMask.
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  /// The regmask has the same format as the one in the RegMask machine operand.
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  void removeRegsNotPreserved(const uint32_t *RegMask);
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  /// Adds register units not preserved by the regmask \p RegMask.
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  /// The regmask has the same format as the one in the RegMask machine operand.
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  void addRegsInMask(const uint32_t *RegMask);
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  /// Returns true if no part of physical register \p Reg is live.
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  bool available(MCPhysReg Reg) const {
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    for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); 
++Unit49.2M
) {
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      if (Units.test(*Unit))
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        return false;
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    }
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return true48.9M
;
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  }
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  /// Updates liveness when stepping backwards over the instruction \p MI.
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  /// This removes all register units defined or clobbered in \p MI and then
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  /// adds the units used (as in use operands) in \p MI.
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  void stepBackward(const MachineInstr &MI);
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  /// Adds all register units used, defined or clobbered in \p MI.
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  /// This is useful when walking over a range of instruction to find registers
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  /// unused over the whole range.
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  void accumulate(const MachineInstr &MI);
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  /// Adds registers living out of block \p MBB.
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  /// Live out registers are the union of the live-in registers of the successor
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  /// blocks and pristine registers. Live out registers of the end block are the
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  /// callee saved registers.
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  void addLiveOuts(const MachineBasicBlock &MBB);
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  /// Adds registers living into block \p MBB.
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  void addLiveIns(const MachineBasicBlock &MBB);
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  /// Adds all register units marked in the bitvector \p RegUnits.
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  void addUnits(const BitVector &RegUnits) {
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    Units |= RegUnits;
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  }
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  /// Removes all register units marked in the bitvector \p RegUnits.
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  void removeUnits(const BitVector &RegUnits) {
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    Units.reset(RegUnits);
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  }
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  /// Return the internal bitvector representation of the set.
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  const BitVector &getBitVector() const {
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    return Units;
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  }
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private:
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  /// Adds pristine registers. Pristine registers are callee saved registers
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  /// that are unused in the function.
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  void addPristines(const MachineFunction &MF);
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_LIVEREGUNITS_H