Coverage Report

Created: 2019-02-21 13:17

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/LiveStacks.h
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//===- LiveStacks.h - Live Stack Slot Analysis ------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the live stack slot analysis pass. It is analogous to
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// live interval analysis except it's analyzing liveness of stack slots rather
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// than registers.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVESTACKS_H
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#define LLVM_CODEGEN_LIVESTACKS_H
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/Pass.h"
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#include <cassert>
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#include <map>
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#include <unordered_map>
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namespace llvm {
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class LiveStacks : public MachineFunctionPass {
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  const TargetRegisterInfo *TRI;
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  /// Special pool allocator for VNInfo's (LiveInterval val#).
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  ///
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  VNInfo::Allocator VNInfoAllocator;
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  /// S2IMap - Stack slot indices to live interval mapping.
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  using SS2IntervalMap = std::unordered_map<int, LiveInterval>;
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  SS2IntervalMap S2IMap;
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  /// S2RCMap - Stack slot indices to register class mapping.
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  std::map<int, const TargetRegisterClass *> S2RCMap;
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public:
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  static char ID; // Pass identification, replacement for typeid
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  LiveStacks() : MachineFunctionPass(ID) {
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31.9k
    initializeLiveStacksPass(*PassRegistry::getPassRegistry());
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  }
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  using iterator = SS2IntervalMap::iterator;
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  using const_iterator = SS2IntervalMap::const_iterator;
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  const_iterator begin() const { return S2IMap.begin(); }
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  const_iterator end() const { return S2IMap.end(); }
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  iterator begin() { return S2IMap.begin(); }
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  iterator end() { return S2IMap.end(); }
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  unsigned getNumIntervals() const { return (unsigned)S2IMap.size(); }
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  LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
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  LiveInterval &getInterval(int Slot) {
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    assert(Slot >= 0 && "Spill slot indice must be >= 0");
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    SS2IntervalMap::iterator I = S2IMap.find(Slot);
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    assert(I != S2IMap.end() && "Interval does not exist for stack slot");
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    return I->second;
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  }
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  const LiveInterval &getInterval(int Slot) const {
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    assert(Slot >= 0 && "Spill slot indice must be >= 0");
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    SS2IntervalMap::const_iterator I = S2IMap.find(Slot);
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    assert(I != S2IMap.end() && "Interval does not exist for stack slot");
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    return I->second;
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  }
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  bool hasInterval(int Slot) const { return S2IMap.count(Slot); }
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  const TargetRegisterClass *getIntervalRegClass(int Slot) const {
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    assert(Slot >= 0 && "Spill slot indice must be >= 0");
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    std::map<int, const TargetRegisterClass *>::const_iterator I =
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        S2RCMap.find(Slot);
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    assert(I != S2RCMap.end() &&
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           "Register class info does not exist for stack slot");
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    return I->second;
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  }
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  VNInfo::Allocator &getVNInfoAllocator() { return VNInfoAllocator; }
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  void getAnalysisUsage(AnalysisUsage &AU) const override;
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  void releaseMemory() override;
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  /// runOnMachineFunction - pass entry point
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  bool runOnMachineFunction(MachineFunction &) override;
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  /// print - Implement the dump method.
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  void print(raw_ostream &O, const Module * = nullptr) const override;
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};
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} // end namespace llvm
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#endif