Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/MachineInstr.h
Line
Count
Source (jump to first uncovered line)
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//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the declaration of the MachineInstr class, which is the
10
// basic representation for all target dependent machine instructions used by
11
// the back end.
12
//
13
//===----------------------------------------------------------------------===//
14
15
#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16
#define LLVM_CODEGEN_MACHINEINSTR_H
17
18
#include "llvm/ADT/DenseMapInfo.h"
19
#include "llvm/ADT/PointerSumType.h"
20
#include "llvm/ADT/ilist.h"
21
#include "llvm/ADT/ilist_node.h"
22
#include "llvm/ADT/iterator_range.h"
23
#include "llvm/Analysis/AliasAnalysis.h"
24
#include "llvm/CodeGen/MachineMemOperand.h"
25
#include "llvm/CodeGen/MachineOperand.h"
26
#include "llvm/CodeGen/TargetOpcodes.h"
27
#include "llvm/IR/DebugInfoMetadata.h"
28
#include "llvm/IR/DebugLoc.h"
29
#include "llvm/IR/InlineAsm.h"
30
#include "llvm/MC/MCInstrDesc.h"
31
#include "llvm/MC/MCSymbol.h"
32
#include "llvm/Support/ArrayRecycler.h"
33
#include "llvm/Support/TrailingObjects.h"
34
#include <algorithm>
35
#include <cassert>
36
#include <cstdint>
37
#include <utility>
38
39
namespace llvm {
40
41
template <typename T> class ArrayRef;
42
class DIExpression;
43
class DILocalVariable;
44
class MachineBasicBlock;
45
class MachineFunction;
46
class MachineMemOperand;
47
class MachineRegisterInfo;
48
class ModuleSlotTracker;
49
class raw_ostream;
50
template <typename T> class SmallVectorImpl;
51
class SmallBitVector;
52
class StringRef;
53
class TargetInstrInfo;
54
class TargetRegisterClass;
55
class TargetRegisterInfo;
56
57
//===----------------------------------------------------------------------===//
58
/// Representation of each machine instruction.
59
///
60
/// This class isn't a POD type, but it must have a trivial destructor. When a
61
/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
62
/// without having their destructor called.
63
///
64
class MachineInstr
65
    : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
66
                                    ilist_sentinel_tracking<true>> {
67
public:
68
  using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;
69
70
  /// Flags to specify different kinds of comments to output in
71
  /// assembly code.  These flags carry semantic information not
72
  /// otherwise easily derivable from the IR text.
73
  ///
74
  enum CommentFlag {
75
    ReloadReuse = 0x1,    // higher bits are reserved for target dep comments.
76
    NoSchedComment = 0x2,
77
    TAsmComments = 0x4    // Target Asm comments should start from this value.
78
  };
79
80
  enum MIFlag {
81
    NoFlags      = 0,
82
    FrameSetup   = 1 << 0,              // Instruction is used as a part of
83
                                        // function frame setup code.
84
    FrameDestroy = 1 << 1,              // Instruction is used as a part of
85
                                        // function frame destruction code.
86
    BundledPred  = 1 << 2,              // Instruction has bundled predecessors.
87
    BundledSucc  = 1 << 3,              // Instruction has bundled successors.
88
    FmNoNans     = 1 << 4,              // Instruction does not support Fast
89
                                        // math nan values.
90
    FmNoInfs     = 1 << 5,              // Instruction does not support Fast
91
                                        // math infinity values.
92
    FmNsz        = 1 << 6,              // Instruction is not required to retain
93
                                        // signed zero values.
94
    FmArcp       = 1 << 7,              // Instruction supports Fast math
95
                                        // reciprocal approximations.
96
    FmContract   = 1 << 8,              // Instruction supports Fast math
97
                                        // contraction operations like fma.
98
    FmAfn        = 1 << 9,              // Instruction may map to Fast math
99
                                        // instrinsic approximation.
100
    FmReassoc    = 1 << 10,             // Instruction supports Fast math
101
                                        // reassociation of operand order.
102
    NoUWrap      = 1 << 11,             // Instruction supports binary operator
103
                                        // no unsigned wrap.
104
    NoSWrap      = 1 << 12,             // Instruction supports binary operator
105
                                        // no signed wrap.
106
    IsExact      = 1 << 13,             // Instruction supports division is
107
                                        // known to be exact.
108
    FPExcept     = 1 << 14,             // Instruction may raise floating-point
109
                                        // exceptions.
110
  };
111
112
private:
113
  const MCInstrDesc *MCID;              // Instruction descriptor.
114
  MachineBasicBlock *Parent = nullptr;  // Pointer to the owning basic block.
115
116
  // Operands are allocated by an ArrayRecycler.
117
  MachineOperand *Operands = nullptr;   // Pointer to the first operand.
118
  unsigned NumOperands = 0;             // Number of operands on instruction.
119
  using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
120
  OperandCapacity CapOperands;          // Capacity of the Operands array.
121
122
  uint16_t Flags = 0;                   // Various bits of additional
123
                                        // information about machine
124
                                        // instruction.
125
126
  uint8_t AsmPrinterFlags = 0;          // Various bits of information used by
127
                                        // the AsmPrinter to emit helpful
128
                                        // comments.  This is *not* semantic
129
                                        // information.  Do not use this for
130
                                        // anything other than to convey comment
131
                                        // information to AsmPrinter.
132
133
  /// Internal implementation detail class that provides out-of-line storage for
134
  /// extra info used by the machine instruction when this info cannot be stored
135
  /// in-line within the instruction itself.
136
  ///
137
  /// This has to be defined eagerly due to the implementation constraints of
138
  /// `PointerSumType` where it is used.
139
  class ExtraInfo final
140
      : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *> {
141
  public:
142
    static ExtraInfo *create(BumpPtrAllocator &Allocator,
143
                             ArrayRef<MachineMemOperand *> MMOs,
144
                             MCSymbol *PreInstrSymbol = nullptr,
145
2.19M
                             MCSymbol *PostInstrSymbol = nullptr) {
146
2.19M
      bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
147
2.19M
      bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
148
2.19M
      auto *Result = new (Allocator.Allocate(
149
2.19M
          totalSizeToAlloc<MachineMemOperand *, MCSymbol *>(
150
2.19M
              MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol),
151
2.19M
          alignof(ExtraInfo)))
152
2.19M
          ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol);
153
2.19M
154
2.19M
      // Copy the actual data into the trailing objects.
155
2.19M
      std::copy(MMOs.begin(), MMOs.end(),
156
2.19M
                Result->getTrailingObjects<MachineMemOperand *>());
157
2.19M
158
2.19M
      if (HasPreInstrSymbol)
159
7
        Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
160
2.19M
      if (HasPostInstrSymbol)
161
6
        Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
162
6
            PostInstrSymbol;
163
2.19M
164
2.19M
      return Result;
165
2.19M
    }
166
167
3.47M
    ArrayRef<MachineMemOperand *> getMMOs() const {
168
3.47M
      return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
169
3.47M
    }
170
171
1.72M
    MCSymbol *getPreInstrSymbol() const {
172
1.72M
      return HasPreInstrSymbol ? 
getTrailingObjects<MCSymbol *>()[0]7
:
nullptr1.72M
;
173
1.72M
    }
174
175
1.72M
    MCSymbol *getPostInstrSymbol() const {
176
1.72M
      return HasPostInstrSymbol
177
1.72M
                 ? 
getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]6
178
1.72M
                 : 
nullptr1.72M
;
179
1.72M
    }
180
181
  private:
182
    friend TrailingObjects;
183
184
    // Description of the extra info, used to interpret the actual optional
185
    // data appended.
186
    //
187
    // Note that this is not terribly space optimized. This leaves a great deal
188
    // of flexibility to fit more in here later.
189
    const int NumMMOs;
190
    const bool HasPreInstrSymbol;
191
    const bool HasPostInstrSymbol;
192
193
    // Implement the `TrailingObjects` internal API.
194
26
    size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
195
26
      return NumMMOs;
196
26
    }
197
0
    size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
198
0
      return HasPreInstrSymbol + HasPostInstrSymbol;
199
0
    }
200
201
    // Just a boring constructor to allow us to initialize the sizes. Always use
202
    // the `create` routine above.
203
    ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol)
204
        : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
205
2.19M
          HasPostInstrSymbol(HasPostInstrSymbol) {}
206
  };
207
208
  /// Enumeration of the kinds of inline extra info available. It is important
209
  /// that the `MachineMemOperand` inline kind has a tag value of zero to make
210
  /// it accessible as an `ArrayRef`.
211
  enum ExtraInfoInlineKinds {
212
    EIIK_MMO = 0,
213
    EIIK_PreInstrSymbol,
214
    EIIK_PostInstrSymbol,
215
    EIIK_OutOfLine
216
  };
217
218
  // We store extra information about the instruction here. The common case is
219
  // expected to be nothing or a single pointer (typically a MMO or a symbol).
220
  // We work to optimize this common case by storing it inline here rather than
221
  // requiring a separate allocation, but we fall back to an allocation when
222
  // multiple pointers are needed.
223
  PointerSumType<ExtraInfoInlineKinds,
224
                 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
225
                 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
226
                 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
227
                 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
228
      Info;
229
230
  DebugLoc debugLoc;                    // Source line information.
231
232
  // Intrusive list support
233
  friend struct ilist_traits<MachineInstr>;
234
  friend struct ilist_callback_traits<MachineBasicBlock>;
235
114M
  void setParent(MachineBasicBlock *P) { Parent = P; }
236
237
  /// This constructor creates a copy of the given
238
  /// MachineInstr in the given MachineFunction.
239
  MachineInstr(MachineFunction &, const MachineInstr &);
240
241
  /// This constructor create a MachineInstr and add the implicit operands.
242
  /// It reserves space for number of operands specified by
243
  /// MCInstrDesc.  An explicit DebugLoc is supplied.
244
  MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl,
245
               bool NoImp = false);
246
247
  // MachineInstrs are pool-allocated and owned by MachineFunction.
248
  friend class MachineFunction;
249
250
public:
251
  MachineInstr(const MachineInstr &) = delete;
252
  MachineInstr &operator=(const MachineInstr &) = delete;
253
  // Use MachineFunction::DeleteMachineInstr() instead.
254
  ~MachineInstr() = delete;
255
256
394M
  const MachineBasicBlock* getParent() const { return Parent; }
257
864M
  MachineBasicBlock* getParent() { return Parent; }
258
259
  /// Return the function that contains the basic block that this instruction
260
  /// belongs to.
261
  ///
262
  /// Note: this is undefined behaviour if the instruction does not have a
263
  /// parent.
264
  const MachineFunction *getMF() const;
265
55.6M
  MachineFunction *getMF() {
266
55.6M
    return const_cast<MachineFunction *>(
267
55.6M
        static_cast<const MachineInstr *>(this)->getMF());
268
55.6M
  }
269
270
  /// Return the asm printer flags bitvector.
271
53.8k
  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
272
273
  /// Clear the AsmPrinter bitvector.
274
0
  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
275
276
  /// Return whether an AsmPrinter flag is set.
277
2.02M
  bool getAsmPrinterFlag(CommentFlag Flag) const {
278
2.02M
    return AsmPrinterFlags & Flag;
279
2.02M
  }
280
281
  /// Set a flag for the AsmPrinter.
282
36.0k
  void setAsmPrinterFlag(uint8_t Flag) {
283
36.0k
    AsmPrinterFlags |= Flag;
284
36.0k
  }
285
286
  /// Clear specific AsmPrinter flags.
287
0
  void clearAsmPrinterFlag(CommentFlag Flag) {
288
0
    AsmPrinterFlags &= ~Flag;
289
0
  }
290
291
  /// Return the MI flags bitvector.
292
13.2M
  uint16_t getFlags() const {
293
13.2M
    return Flags;
294
13.2M
  }
295
296
  /// Return whether an MI flag is set.
297
7.23G
  bool getFlag(MIFlag Flag) const {
298
7.23G
    return Flags & Flag;
299
7.23G
  }
300
301
  /// Set a MI flag.
302
2.58M
  void setFlag(MIFlag Flag) {
303
2.58M
    Flags |= (uint16_t)Flag;
304
2.58M
  }
305
306
4.05M
  void setFlags(unsigned flags) {
307
4.05M
    // Filter out the automatically maintained flags.
308
4.05M
    unsigned Mask = BundledPred | BundledSucc;
309
4.05M
    Flags = (Flags & Mask) | (flags & ~Mask);
310
4.05M
  }
311
312
  /// clearFlag - Clear a MI flag.
313
151k
  void clearFlag(MIFlag Flag) {
314
151k
    Flags &= ~((uint16_t)Flag);
315
151k
  }
316
317
  /// Return true if MI is in a bundle (but not the first MI in a bundle).
318
  ///
319
  /// A bundle looks like this before it's finalized:
320
  ///   ----------------
321
  ///   |      MI      |
322
  ///   ----------------
323
  ///          |
324
  ///   ----------------
325
  ///   |      MI    * |
326
  ///   ----------------
327
  ///          |
328
  ///   ----------------
329
  ///   |      MI    * |
330
  ///   ----------------
331
  /// In this case, the first MI starts a bundle but is not inside a bundle, the
332
  /// next 2 MIs are considered "inside" the bundle.
333
  ///
334
  /// After a bundle is finalized, it looks like this:
335
  ///   ----------------
336
  ///   |    Bundle    |
337
  ///   ----------------
338
  ///          |
339
  ///   ----------------
340
  ///   |      MI    * |
341
  ///   ----------------
342
  ///          |
343
  ///   ----------------
344
  ///   |      MI    * |
345
  ///   ----------------
346
  ///          |
347
  ///   ----------------
348
  ///   |      MI    * |
349
  ///   ----------------
350
  /// The first instruction has the special opcode "BUNDLE". It's not "inside"
351
  /// a bundle, but the next three MIs are.
352
193M
  bool isInsideBundle() const {
353
193M
    return getFlag(BundledPred);
354
193M
  }
355
356
  /// Return true if this instruction part of a bundle. This is true
357
  /// if either itself or its following instruction is marked "InsideBundle".
358
2.34G
  bool isBundled() const {
359
2.34G
    return isBundledWithPred() || 
isBundledWithSucc()2.34G
;
360
2.34G
  }
361
362
  /// Return true if this instruction is part of a bundle, and it is not the
363
  /// first instruction in the bundle.
364
3.19G
  bool isBundledWithPred() const { return getFlag(BundledPred); }
365
366
  /// Return true if this instruction is part of a bundle, and it is not the
367
  /// last instruction in the bundle.
368
3.84G
  bool isBundledWithSucc() const { return getFlag(BundledSucc); }
369
370
  /// Bundle this instruction with its predecessor. This can be an unbundled
371
  /// instruction, or it can be the first instruction in a bundle.
372
  void bundleWithPred();
373
374
  /// Bundle this instruction with its successor. This can be an unbundled
375
  /// instruction, or it can be the last instruction in a bundle.
376
  void bundleWithSucc();
377
378
  /// Break bundle above this instruction.
379
  void unbundleFromPred();
380
381
  /// Break bundle below this instruction.
382
  void unbundleFromSucc();
383
384
  /// Returns the debug location id of this MachineInstr.
385
54.5M
  const DebugLoc &getDebugLoc() const { return debugLoc; }
386
387
  /// Return the debug variable referenced by
388
  /// this DBG_VALUE instruction.
389
  const DILocalVariable *getDebugVariable() const;
390
391
  /// Return the complex address expression referenced by
392
  /// this DBG_VALUE instruction.
393
  const DIExpression *getDebugExpression() const;
394
395
  /// Return the debug label referenced by
396
  /// this DBG_LABEL instruction.
397
  const DILabel *getDebugLabel() const;
398
399
  /// Emit an error referring to the source location of this instruction.
400
  /// This should only be used for inline assembly that is somehow
401
  /// impossible to compile. Other errors should have been handled much
402
  /// earlier.
403
  ///
404
  /// If this method returns, the caller should try to recover from the error.
405
  void emitError(StringRef Msg) const;
406
407
  /// Returns the target instruction descriptor of this MachineInstr.
408
3.71G
  const MCInstrDesc &getDesc() const { return *MCID; }
409
410
  /// Returns the opcode of this MachineInstr.
411
10.7G
  unsigned getOpcode() const { return MCID->Opcode; }
412
413
  /// Retuns the total number of operands.
414
1.14G
  unsigned getNumOperands() const { return NumOperands; }
415
416
1.95G
  const MachineOperand& getOperand(unsigned i) const {
417
1.95G
    assert(i < getNumOperands() && "getOperand() out of range!");
418
1.95G
    return Operands[i];
419
1.95G
  }
420
1.75G
  MachineOperand& getOperand(unsigned i) {
421
1.75G
    assert(i < getNumOperands() && "getOperand() out of range!");
422
1.75G
    return Operands[i];
423
1.75G
  }
424
425
  /// Returns the total number of definitions.
426
4.76M
  unsigned getNumDefs() const {
427
4.76M
    return getNumExplicitDefs() + MCID->getNumImplicitDefs();
428
4.76M
  }
429
430
  /// Return true if operand \p OpIdx is a subregister index.
431
158k
  bool isOperandSubregIdx(unsigned OpIdx) const {
432
158k
    assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&
433
158k
           "Expected MO_Immediate operand type.");
434
158k
    if (isExtractSubreg() && 
OpIdx == 27
)
435
7
      return true;
436
158k
    if (isInsertSubreg() && 
OpIdx == 3201
)
437
201
      return true;
438
158k
    if (isRegSequence() && 
OpIdx > 11.30k
&&
(OpIdx % 2) == 01.30k
)
439
1.30k
      return true;
440
157k
    if (isSubregToReg() && 
OpIdx == 32.54k
)
441
1.27k
      return true;
442
155k
    return false;
443
155k
  }
444
445
  /// Returns the number of non-implicit operands.
446
  unsigned getNumExplicitOperands() const;
447
448
  /// Returns the number of non-implicit definitions.
449
  unsigned getNumExplicitDefs() const;
450
451
  /// iterator/begin/end - Iterate over all operands of a machine instruction.
452
  using mop_iterator = MachineOperand *;
453
  using const_mop_iterator = const MachineOperand *;
454
455
410M
  mop_iterator operands_begin() { return Operands; }
456
392M
  mop_iterator operands_end() { return Operands + NumOperands; }
457
458
317M
  const_mop_iterator operands_begin() const { return Operands; }
459
260M
  const_mop_iterator operands_end() const { return Operands + NumOperands; }
460
461
268M
  iterator_range<mop_iterator> operands() {
462
268M
    return make_range(operands_begin(), operands_end());
463
268M
  }
464
210M
  iterator_range<const_mop_iterator> operands() const {
465
210M
    return make_range(operands_begin(), operands_end());
466
210M
  }
467
9.99M
  iterator_range<mop_iterator> explicit_operands() {
468
9.99M
    return make_range(operands_begin(),
469
9.99M
                      operands_begin() + getNumExplicitOperands());
470
9.99M
  }
471
6.02M
  iterator_range<const_mop_iterator> explicit_operands() const {
472
6.02M
    return make_range(operands_begin(),
473
6.02M
                      operands_begin() + getNumExplicitOperands());
474
6.02M
  }
475
9.97M
  iterator_range<mop_iterator> implicit_operands() {
476
9.97M
    return make_range(explicit_operands().end(), operands_end());
477
9.97M
  }
478
5.47M
  iterator_range<const_mop_iterator> implicit_operands() const {
479
5.47M
    return make_range(explicit_operands().end(), operands_end());
480
5.47M
  }
481
  /// Returns a range over all explicit operands that are register definitions.
482
  /// Implicit definition are not included!
483
3.27M
  iterator_range<mop_iterator> defs() {
484
3.27M
    return make_range(operands_begin(),
485
3.27M
                      operands_begin() + getNumExplicitDefs());
486
3.27M
  }
487
  /// \copydoc defs()
488
18.2M
  iterator_range<const_mop_iterator> defs() const {
489
18.2M
    return make_range(operands_begin(),
490
18.2M
                      operands_begin() + getNumExplicitDefs());
491
18.2M
  }
492
  /// Returns a range that includes all operands that are register uses.
493
  /// This may include unrelated operands which are not register uses.
494
3.33M
  iterator_range<mop_iterator> uses() {
495
3.33M
    return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
496
3.33M
  }
497
  /// \copydoc uses()
498
34.0M
  iterator_range<const_mop_iterator> uses() const {
499
34.0M
    return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
500
34.0M
  }
501
73.3k
  iterator_range<mop_iterator> explicit_uses() {
502
73.3k
    return make_range(operands_begin() + getNumExplicitDefs(),
503
73.3k
                      operands_begin() + getNumExplicitOperands());
504
73.3k
  }
505
39.3k
  iterator_range<const_mop_iterator> explicit_uses() const {
506
39.3k
    return make_range(operands_begin() + getNumExplicitDefs(),
507
39.3k
                      operands_begin() + getNumExplicitOperands());
508
39.3k
  }
509
510
  /// Returns the number of the operand iterator \p I points to.
511
13.9M
  unsigned getOperandNo(const_mop_iterator I) const {
512
13.9M
    return I - operands_begin();
513
13.9M
  }
514
515
  /// Access to memory operands of the instruction. If there are none, that does
516
  /// not imply anything about whether the function accesses memory. Instead,
517
  /// the caller must behave conservatively.
518
355M
  ArrayRef<MachineMemOperand *> memoperands() const {
519
355M
    if (!Info)
520
132M
      return {};
521
223M
522
223M
    if (Info.is<EIIK_MMO>())
523
219M
      return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
524
3.47M
525
3.47M
    if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
526
3.47M
      return EI->getMMOs();
527
1.32k
528
1.32k
    return {};
529
1.32k
  }
530
531
  /// Access to memory operands of the instruction.
532
  ///
533
  /// If `memoperands_begin() == memoperands_end()`, that does not imply
534
  /// anything about whether the function accesses memory. Instead, the caller
535
  /// must behave conservatively.
536
78.0M
  mmo_iterator memoperands_begin() const { return memoperands().begin(); }
537
538
  /// Access to memory operands of the instruction.
539
  ///
540
  /// If `memoperands_begin() == memoperands_end()`, that does not imply
541
  /// anything about whether the function accesses memory. Instead, the caller
542
  /// must behave conservatively.
543
62.7M
  mmo_iterator memoperands_end() const { return memoperands().end(); }
544
545
  /// Return true if we don't have any memory operands which described the
546
  /// memory access done by this instruction.  If this is true, calling code
547
  /// must be conservative.
548
83.3M
  bool memoperands_empty() const { return memoperands().empty(); }
549
550
  /// Return true if this instruction has exactly one MachineMemOperand.
551
15.0M
  bool hasOneMemOperand() const { return memoperands().size() == 1; }
552
553
  /// Return the number of memory operands.
554
671k
  unsigned getNumMemOperands() const { return memoperands().size(); }
555
556
  /// Helper to extract a pre-instruction symbol if one has been added.
557
29.0M
  MCSymbol *getPreInstrSymbol() const {
558
29.0M
    if (!Info)
559
22.4M
      return nullptr;
560
6.60M
    if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
561
33
      return S;
562
6.60M
    if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
563
1.72M
      return EI->getPreInstrSymbol();
564
4.87M
565
4.87M
    return nullptr;
566
4.87M
  }
567
568
  /// Helper to extract a post-instruction symbol if one has been added.
569
29.0M
  MCSymbol *getPostInstrSymbol() const {
570
29.0M
    if (!Info)
571
22.4M
      return nullptr;
572
6.60M
    if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
573
55
      return S;
574
6.60M
    if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
575
1.72M
      return EI->getPostInstrSymbol();
576
4.87M
577
4.87M
    return nullptr;
578
4.87M
  }
579
580
  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
581
  /// queries but they are bundle aware.
582
583
  enum QueryType {
584
    IgnoreBundle,    // Ignore bundles
585
    AnyInBundle,     // Return true if any instruction in bundle has property
586
    AllInBundle      // Return true if all instructions in bundle have property
587
  };
588
589
  /// Return true if the instruction (or in the case of a bundle,
590
  /// the instructions inside the bundle) has the specified property.
591
  /// The first argument is the property being queried.
592
  /// The second argument indicates whether the query should look inside
593
  /// instruction bundles.
594
2.82G
  bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
595
2.82G
    assert(MCFlag < 64 &&
596
2.82G
           "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
597
2.82G
    // Inline the fast path for unbundled or bundle-internal instructions.
598
2.82G
    if (Type == IgnoreBundle || 
!isBundled()2.33G
||
isBundledWithPred()582k
)
599
2.82G
      return getDesc().getFlags() & (1ULL << MCFlag);
600
377k
601
377k
    // If this is the first instruction in a bundle, take the slow path.
602
377k
    return hasPropertyInBundle(1ULL << MCFlag, Type);
603
377k
  }
604
605
  /// Return true if this instruction can have a variable number of operands.
606
  /// In this case, the variable operands will be after the normal
607
  /// operands but before the implicit definitions and uses (if any are
608
  /// present).
609
53.9M
  bool isVariadic(QueryType Type = IgnoreBundle) const {
610
53.9M
    return hasProperty(MCID::Variadic, Type);
611
53.9M
  }
612
613
  /// Set if this instruction has an optional definition, e.g.
614
  /// ARM instructions which can set condition code if 's' bit is set.
615
14.2k
  bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
616
14.2k
    return hasProperty(MCID::HasOptionalDef, Type);
617
14.2k
  }
618
619
  /// Return true if this is a pseudo instruction that doesn't
620
  /// correspond to a real machine instruction.
621
36.3M
  bool isPseudo(QueryType Type = IgnoreBundle) const {
622
36.3M
    return hasProperty(MCID::Pseudo, Type);
623
36.3M
  }
624
625
16.4M
  bool isReturn(QueryType Type = AnyInBundle) const {
626
16.4M
    return hasProperty(MCID::Return, Type);
627
16.4M
  }
628
629
  /// Return true if this is an instruction that marks the end of an EH scope,
630
  /// i.e., a catchpad or a cleanuppad instruction.
631
2.47k
  bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
632
2.47k
    return hasProperty(MCID::EHScopeReturn, Type);
633
2.47k
  }
634
635
336M
  bool isCall(QueryType Type = AnyInBundle) const {
636
336M
    return hasProperty(MCID::Call, Type);
637
336M
  }
638
639
  /// Returns true if the specified instruction stops control flow
640
  /// from executing the instruction immediately following it.  Examples include
641
  /// unconditional branches and return instructions.
642
86.2M
  bool isBarrier(QueryType Type = AnyInBundle) const {
643
86.2M
    return hasProperty(MCID::Barrier, Type);
644
86.2M
  }
645
646
  /// Returns true if this instruction part of the terminator for a basic block.
647
  /// Typically this is things like return and branch instructions.
648
  ///
649
  /// Various passes use this to insert code into the bottom of a basic block,
650
  /// but before control flow occurs.
651
455M
  bool isTerminator(QueryType Type = AnyInBundle) const {
652
455M
    return hasProperty(MCID::Terminator, Type);
653
455M
  }
654
655
  /// Returns true if this is a conditional, unconditional, or indirect branch.
656
  /// Predicates below can be used to discriminate between
657
  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
658
  /// get more information.
659
111M
  bool isBranch(QueryType Type = AnyInBundle) const {
660
111M
    return hasProperty(MCID::Branch, Type);
661
111M
  }
662
663
  /// Return true if this is an indirect branch, such as a
664
  /// branch through a register.
665
39.2M
  bool isIndirectBranch(QueryType Type = AnyInBundle) const {
666
39.2M
    return hasProperty(MCID::IndirectBranch, Type);
667
39.2M
  }
668
669
  /// Return true if this is a branch which may fall
670
  /// through to the next instruction or may transfer control flow to some other
671
  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
672
  /// information about this branch.
673
26.1M
  bool isConditionalBranch(QueryType Type = AnyInBundle) const {
674
26.1M
    return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
675
26.1M
  }
676
677
  /// Return true if this is a branch which always
678
  /// transfers control flow to some other block.  The
679
  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
680
  /// about this branch.
681
5.19M
  bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
682
5.19M
    return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
683
5.19M
  }
684
685
  /// Return true if this instruction has a predicate operand that
686
  /// controls execution.  It may be set to 'always', or may be set to other
687
  /// values.   There are various methods in TargetInstrInfo that can be used to
688
  /// control and modify the predicate in this instruction.
689
18.7M
  bool isPredicable(QueryType Type = AllInBundle) const {
690
18.7M
    // If it's a bundle than all bundled instructions must be predicable for this
691
18.7M
    // to return true.
692
18.7M
    return hasProperty(MCID::Predicable, Type);
693
18.7M
  }
694
695
  /// Return true if this instruction is a comparison.
696
25.1M
  bool isCompare(QueryType Type = IgnoreBundle) const {
697
25.1M
    return hasProperty(MCID::Compare, Type);
698
25.1M
  }
699
700
  /// Return true if this instruction is a move immediate
701
  /// (including conditional moves) instruction.
702
132M
  bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
703
132M
    return hasProperty(MCID::MoveImm, Type);
704
132M
  }
705
706
  /// Return true if this instruction is a register move.
707
  /// (including moving values from subreg to reg)
708
2.46k
  bool isMoveReg(QueryType Type = IgnoreBundle) const {
709
2.46k
    return hasProperty(MCID::MoveReg, Type);
710
2.46k
  }
711
712
  /// Return true if this instruction is a bitcast instruction.
713
28.1M
  bool isBitcast(QueryType Type = IgnoreBundle) const {
714
28.1M
    return hasProperty(MCID::Bitcast, Type);
715
28.1M
  }
716
717
  /// Return true if this instruction is a select instruction.
718
24.0M
  bool isSelect(QueryType Type = IgnoreBundle) const {
719
24.0M
    return hasProperty(MCID::Select, Type);
720
24.0M
  }
721
722
  /// Return true if this instruction cannot be safely duplicated.
723
  /// For example, if the instruction has a unique labels attached
724
  /// to it, duplicating it would cause multiple definition errors.
725
26.6M
  bool isNotDuplicable(QueryType Type = AnyInBundle) const {
726
26.6M
    return hasProperty(MCID::NotDuplicable, Type);
727
26.6M
  }
728
729
  /// Return true if this instruction is convergent.
730
  /// Convergent instructions can not be made control-dependent on any
731
  /// additional values.
732
32.1M
  bool isConvergent(QueryType Type = AnyInBundle) const {
733
32.1M
    if (isInlineAsm()) {
734
10.5k
      unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
735
10.5k
      if (ExtraInfo & InlineAsm::Extra_IsConvergent)
736
2
        return true;
737
32.1M
    }
738
32.1M
    return hasProperty(MCID::Convergent, Type);
739
32.1M
  }
740
741
  /// Returns true if the specified instruction has a delay slot
742
  /// which must be filled by the code generator.
743
147k
  bool hasDelaySlot(QueryType Type = AnyInBundle) const {
744
147k
    return hasProperty(MCID::DelaySlot, Type);
745
147k
  }
746
747
  /// Return true for instructions that can be folded as
748
  /// memory operands in other instructions. The most common use for this
749
  /// is instructions that are simple loads from memory that don't modify
750
  /// the loaded value in any way, but it can also be used for instructions
751
  /// that can be expressed as constant-pool loads, such as V_SETALLONES
752
  /// on x86, to allow them to be folded when it is beneficial.
753
  /// This should only be set on instructions that return a value in their
754
  /// only virtual register definition.
755
29.7M
  bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
756
29.7M
    return hasProperty(MCID::FoldableAsLoad, Type);
757
29.7M
  }
758
759
  /// Return true if this instruction behaves
760
  /// the same way as the generic REG_SEQUENCE instructions.
761
  /// E.g., on ARM,
762
  /// dX VMOVDRR rY, rZ
763
  /// is equivalent to
764
  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
765
  ///
766
  /// Note that for the optimizers to be able to take advantage of
767
  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
768
  /// override accordingly.
769
27.8M
  bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
770
27.8M
    return hasProperty(MCID::RegSequence, Type);
771
27.8M
  }
772
773
  /// Return true if this instruction behaves
774
  /// the same way as the generic EXTRACT_SUBREG instructions.
775
  /// E.g., on ARM,
776
  /// rX, rY VMOVRRD dZ
777
  /// is equivalent to two EXTRACT_SUBREG:
778
  /// rX = EXTRACT_SUBREG dZ, ssub_0
779
  /// rY = EXTRACT_SUBREG dZ, ssub_1
780
  ///
781
  /// Note that for the optimizers to be able to take advantage of
782
  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
783
  /// override accordingly.
784
27.6M
  bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
785
27.6M
    return hasProperty(MCID::ExtractSubreg, Type);
786
27.6M
  }
787
788
  /// Return true if this instruction behaves
789
  /// the same way as the generic INSERT_SUBREG instructions.
790
  /// E.g., on ARM,
791
  /// dX = VSETLNi32 dY, rZ, Imm
792
  /// is equivalent to a INSERT_SUBREG:
793
  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
794
  ///
795
  /// Note that for the optimizers to be able to take advantage of
796
  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
797
  /// override accordingly.
798
27.6M
  bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
799
27.6M
    return hasProperty(MCID::InsertSubreg, Type);
800
27.6M
  }
801
802
  //===--------------------------------------------------------------------===//
803
  // Side Effect Analysis
804
  //===--------------------------------------------------------------------===//
805
806
  /// Return true if this instruction could possibly read memory.
807
  /// Instructions with this flag set are not necessarily simple load
808
  /// instructions, they may load a value and modify it, for example.
809
400M
  bool mayLoad(QueryType Type = AnyInBundle) const {
810
400M
    if (isInlineAsm()) {
811
66.0k
      unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
812
66.0k
      if (ExtraInfo & InlineAsm::Extra_MayLoad)
813
30.8k
        return true;
814
400M
    }
815
400M
    return hasProperty(MCID::MayLoad, Type);
816
400M
  }
817
818
  /// Return true if this instruction could possibly modify memory.
819
  /// Instructions with this flag set are not necessarily simple store
820
  /// instructions, they may store a modified value based on their operands, or
821
  /// may not actually modify anything, for example.
822
381M
  bool mayStore(QueryType Type = AnyInBundle) const {
823
381M
    if (isInlineAsm()) {
824
90.9k
      unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
825
90.9k
      if (ExtraInfo & InlineAsm::Extra_MayStore)
826
41.8k
        return true;
827
381M
    }
828
381M
    return hasProperty(MCID::MayStore, Type);
829
381M
  }
830
831
  /// Return true if this instruction could possibly read or modify memory.
832
12.3M
  bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
833
12.3M
    return mayLoad(Type) || 
mayStore(Type)9.58M
;
834
12.3M
  }
835
836
  /// Return true if this instruction could possibly raise a floating-point
837
  /// exception.  This is the case if the instruction is a floating-point
838
  /// instruction that can in principle raise an exception, as indicated
839
  /// by the MCID::MayRaiseFPException property, *and* at the same time,
840
  /// the instruction is used in a context where we expect floating-point
841
  /// exceptions might be enabled, as indicated by the FPExcept MI flag.
842
164M
  bool mayRaiseFPException() const {
843
164M
    return hasProperty(MCID::MayRaiseFPException) &&
844
164M
           
getFlag(MachineInstr::MIFlag::FPExcept)18.3k
;
845
164M
  }
846
847
  //===--------------------------------------------------------------------===//
848
  // Flags that indicate whether an instruction can be modified by a method.
849
  //===--------------------------------------------------------------------===//
850
851
  /// Return true if this may be a 2- or 3-address
852
  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
853
  /// result if Y and Z are exchanged.  If this flag is set, then the
854
  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
855
  /// instruction.
856
  ///
857
  /// Note that this flag may be set on instructions that are only commutable
858
  /// sometimes.  In these cases, the call to commuteInstruction will fail.
859
  /// Also note that some instructions require non-trivial modification to
860
  /// commute them.
861
20.2M
  bool isCommutable(QueryType Type = IgnoreBundle) const {
862
20.2M
    return hasProperty(MCID::Commutable, Type);
863
20.2M
  }
864
865
  /// Return true if this is a 2-address instruction
866
  /// which can be changed into a 3-address instruction if needed.  Doing this
867
  /// transformation can be profitable in the register allocator, because it
868
  /// means that the instruction can use a 2-address form if possible, but
869
  /// degrade into a less efficient form if the source and dest register cannot
870
  /// be assigned to the same register.  For example, this allows the x86
871
  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
872
  /// is the same speed as the shift but has bigger code size.
873
  ///
874
  /// If this returns true, then the target must implement the
875
  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
876
  /// is allowed to fail if the transformation isn't valid for this specific
877
  /// instruction (e.g. shl reg, 4 on x86).
878
  ///
879
426k
  bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
880
426k
    return hasProperty(MCID::ConvertibleTo3Addr, Type);
881
426k
  }
882
883
  /// Return true if this instruction requires
884
  /// custom insertion support when the DAG scheduler is inserting it into a
885
  /// machine basic block.  If this is true for the instruction, it basically
886
  /// means that it is a pseudo instruction used at SelectionDAG time that is
887
  /// expanded out into magic code by the target when MachineInstrs are formed.
888
  ///
889
  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
890
  /// is used to insert this into the MachineBasicBlock.
891
25.2M
  bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
892
25.2M
    return hasProperty(MCID::UsesCustomInserter, Type);
893
25.2M
  }
894
895
  /// Return true if this instruction requires *adjustment*
896
  /// after instruction selection by calling a target hook. For example, this
897
  /// can be used to fill in ARM 's' optional operand depending on whether
898
  /// the conditional flag register is used.
899
0
  bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
900
0
    return hasProperty(MCID::HasPostISelHook, Type);
901
0
  }
902
903
  /// Returns true if this instruction is a candidate for remat.
904
  /// This flag is deprecated, please don't use it anymore.  If this
905
  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
906
  /// verify the instruction is really rematable.
907
0
  bool isRematerializable(QueryType Type = AllInBundle) const {
908
0
    // It's only possible to re-mat a bundle if all bundled instructions are
909
0
    // re-materializable.
910
0
    return hasProperty(MCID::Rematerializable, Type);
911
0
  }
912
913
  /// Returns true if this instruction has the same cost (or less) than a move
914
  /// instruction. This is useful during certain types of optimizations
915
  /// (e.g., remat during two-address conversion or machine licm)
916
  /// where we would like to remat or hoist the instruction, but not if it costs
917
  /// more than moving the instruction into the appropriate register. Note, we
918
  /// are not marking copies from and to the same register class with this flag.
919
10.4M
  bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
920
10.4M
    // Only returns true for a bundle if all bundled instructions are cheap.
921
10.4M
    return hasProperty(MCID::CheapAsAMove, Type);
922
10.4M
  }
923
924
  /// Returns true if this instruction source operands
925
  /// have special register allocation requirements that are not captured by the
926
  /// operand register classes. e.g. ARM::STRD's two source registers must be an
927
  /// even / odd pair, ARM::STM registers have to be in ascending order.
928
  /// Post-register allocation passes should not attempt to change allocations
929
  /// for sources of instructions with this flag.
930
18.5M
  bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
931
18.5M
    return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
932
18.5M
  }
933
934
  /// Returns true if this instruction def operands
935
  /// have special register allocation requirements that are not captured by the
936
  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
937
  /// even / odd pair, ARM::LDM registers have to be in ascending order.
938
  /// Post-register allocation passes should not attempt to change allocations
939
  /// for definitions of instructions with this flag.
940
8.36M
  bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
941
8.36M
    return hasProperty(MCID::ExtraDefRegAllocReq, Type);
942
8.36M
  }
943
944
  enum MICheckType {
945
    CheckDefs,      // Check all operands for equality
946
    CheckKillDead,  // Check all operands including kill / dead markers
947
    IgnoreDefs,     // Ignore all definitions
948
    IgnoreVRegDefs  // Ignore virtual register definitions
949
  };
950
951
  /// Return true if this instruction is identical to \p Other.
952
  /// Two instructions are identical if they have the same opcode and all their
953
  /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
954
  /// Note that this means liveness related flags (dead, undef, kill) do not
955
  /// affect the notion of identical.
956
  bool isIdenticalTo(const MachineInstr &Other,
957
                     MICheckType Check = CheckDefs) const;
958
959
  /// Unlink 'this' from the containing basic block, and return it without
960
  /// deleting it.
961
  ///
962
  /// This function can not be used on bundled instructions, use
963
  /// removeFromBundle() to remove individual instructions from a bundle.
964
  MachineInstr *removeFromParent();
965
966
  /// Unlink this instruction from its basic block and return it without
967
  /// deleting it.
968
  ///
969
  /// If the instruction is part of a bundle, the other instructions in the
970
  /// bundle remain bundled.
971
  MachineInstr *removeFromBundle();
972
973
  /// Unlink 'this' from the containing basic block and delete it.
974
  ///
975
  /// If this instruction is the header of a bundle, the whole bundle is erased.
976
  /// This function can not be used for instructions inside a bundle, use
977
  /// eraseFromBundle() to erase individual bundled instructions.
978
  void eraseFromParent();
979
980
  /// Unlink 'this' from the containing basic block and delete it.
981
  ///
982
  /// For all definitions mark their uses in DBG_VALUE nodes
983
  /// as undefined. Otherwise like eraseFromParent().
984
  void eraseFromParentAndMarkDBGValuesForRemoval();
985
986
  /// Unlink 'this' form its basic block and delete it.
987
  ///
988
  /// If the instruction is part of a bundle, the other instructions in the
989
  /// bundle remain bundled.
990
  void eraseFromBundle();
991
992
293M
  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
993
291M
  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
994
291M
  bool isAnnotationLabel() const {
995
291M
    return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
996
291M
  }
997
998
  /// Returns true if the MachineInstr represents a label.
999
292M
  bool isLabel() const {
1000
292M
    return isEHLabel() || 
isGCLabel()291M
||
isAnnotationLabel()291M
;
1001
292M
  }
1002
1003
347M
  bool isCFIInstruction() const {
1004
347M
    return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1005
347M
  }
1006
1007
  // True if the instruction represents a position in the function.
1008
292M
  bool isPosition() const { return isLabel() || 
isCFIInstruction()291M
; }
1009
1010
1.18G
  bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
1011
1.00G
  bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1012
992M
  bool isDebugInstr() const { return isDebugValue() || 
isDebugLabel()984M
; }
1013
1014
  /// A DBG_VALUE is indirect iff the first operand is a register and
1015
  /// the second operand is an immediate.
1016
5.33k
  bool isIndirectDebugValue() const {
1017
5.33k
    return isDebugValue()
1018
5.33k
      && 
getOperand(0).isReg()3.52k
1019
5.33k
      && 
getOperand(1).isImm()2.94k
;
1020
5.33k
  }
1021
1022
  /// A DBG_VALUE is an entry value iff its debug expression contains the
1023
  /// DW_OP_entry_value DWARF operation.
1024
2.14k
  bool isDebugEntryValue() const {
1025
2.14k
    return isDebugValue() && getDebugExpression()->isEntryValue();
1026
2.14k
  }
1027
1028
  /// Return true if the instruction is a debug value which describes a part of
1029
  /// a variable as unavailable.
1030
5.44k
  bool isUndefDebugValue() const {
1031
5.44k
    return isDebugValue() && getOperand(0).isReg() && 
!getOperand(0).getReg()1.31k
;
1032
5.44k
  }
1033
1034
470M
  bool isPHI() const {
1035
470M
    return getOpcode() == TargetOpcode::PHI ||
1036
470M
           
getOpcode() == TargetOpcode::G_PHI451M
;
1037
470M
  }
1038
93.3M
  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1039
202M
  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1040
1.49G
  bool isInlineAsm() const {
1041
1.49G
    return getOpcode() == TargetOpcode::INLINEASM ||
1042
1.49G
           
getOpcode() == TargetOpcode::INLINEASM_BR1.49G
;
1043
1.49G
  }
1044
1045
  /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1046
  /// specific, be attached to a generic MachineInstr.
1047
0
  bool isMSInlineAsm() const {
1048
0
    return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel;
1049
0
  }
1050
1051
  bool isStackAligningInlineAsm() const;
1052
  InlineAsm::AsmDialect getInlineAsmDialect() const;
1053
1054
37.9M
  bool isInsertSubreg() const {
1055
37.9M
    return getOpcode() == TargetOpcode::INSERT_SUBREG;
1056
37.9M
  }
1057
1058
79.3M
  bool isSubregToReg() const {
1059
79.3M
    return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1060
79.3M
  }
1061
1062
46.5M
  bool isRegSequence() const {
1063
46.5M
    return getOpcode() == TargetOpcode::REG_SEQUENCE;
1064
46.5M
  }
1065
1066
61.7M
  bool isBundle() const {
1067
61.7M
    return getOpcode() == TargetOpcode::BUNDLE;
1068
61.7M
  }
1069
1070
567M
  bool isCopy() const {
1071
567M
    return getOpcode() == TargetOpcode::COPY;
1072
567M
  }
1073
1074
13.6M
  bool isFullCopy() const {
1075
13.6M
    return isCopy() && 
!getOperand(0).getSubReg()6.18M
&&
!getOperand(1).getSubReg()5.89M
;
1076
13.6M
  }
1077
1078
17.7M
  bool isExtractSubreg() const {
1079
17.7M
    return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1080
17.7M
  }
1081
1082
  /// Return true if the instruction behaves like a copy.
1083
  /// This does not include native copy instructions.
1084
84.9M
  bool isCopyLike() const {
1085
84.9M
    return isCopy() || 
isSubregToReg()57.0M
;
1086
84.9M
  }
1087
1088
  /// Return true is the instruction is an identity copy.
1089
47.2M
  bool isIdentityCopy() const {
1090
47.2M
    return isCopy() && 
getOperand(0).getReg() == getOperand(1).getReg()11.6M
&&
1091
47.2M
      
getOperand(0).getSubReg() == getOperand(1).getSubReg()2.69M
;
1092
47.2M
  }
1093
1094
  /// Return true if this instruction doesn't produce any output in the form of
1095
  /// executable instructions.
1096
79.3M
  bool isMetaInstruction() const {
1097
79.3M
    switch (getOpcode()) {
1098
79.3M
    default:
1099
76.8M
      return false;
1100
79.3M
    case TargetOpcode::IMPLICIT_DEF:
1101
2.52M
    case TargetOpcode::KILL:
1102
2.52M
    case TargetOpcode::CFI_INSTRUCTION:
1103
2.52M
    case TargetOpcode::EH_LABEL:
1104
2.52M
    case TargetOpcode::GC_LABEL:
1105
2.52M
    case TargetOpcode::DBG_VALUE:
1106
2.52M
    case TargetOpcode::DBG_LABEL:
1107
2.52M
    case TargetOpcode::LIFETIME_START:
1108
2.52M
    case TargetOpcode::LIFETIME_END:
1109
2.52M
      return true;
1110
79.3M
    }
1111
79.3M
  }
1112
1113
  /// Return true if this is a transient instruction that is either very likely
1114
  /// to be eliminated during register allocation (such as copy-like
1115
  /// instructions), or if this instruction doesn't have an execution-time cost.
1116
63.6M
  bool isTransient() const {
1117
63.6M
    switch (getOpcode()) {
1118
63.6M
    default:
1119
55.9M
      return isMetaInstruction();
1120
63.6M
    // Copy-like instructions are usually eliminated during register allocation.
1121
63.6M
    case TargetOpcode::PHI:
1122
7.73M
    case TargetOpcode::G_PHI:
1123
7.73M
    case TargetOpcode::COPY:
1124
7.73M
    case TargetOpcode::INSERT_SUBREG:
1125
7.73M
    case TargetOpcode::SUBREG_TO_REG:
1126
7.73M
    case TargetOpcode::REG_SEQUENCE:
1127
7.73M
      return true;
1128
63.6M
    }
1129
63.6M
  }
1130
1131
  /// Return the number of instructions inside the MI bundle, excluding the
1132
  /// bundle header.
1133
  ///
1134
  /// This is the number of instructions that MachineBasicBlock::iterator
1135
  /// skips, 0 for unbundled instructions.
1136
  unsigned getBundleSize() const;
1137
1138
  /// Return true if the MachineInstr reads the specified register.
1139
  /// If TargetRegisterInfo is passed, then it also checks if there
1140
  /// is a read of a super-register.
1141
  /// This does not count partial redefines of virtual registers as reads:
1142
  ///   %reg1024:6 = OP.
1143
  bool readsRegister(unsigned Reg,
1144
2.83M
                     const TargetRegisterInfo *TRI = nullptr) const {
1145
2.83M
    return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1146
2.83M
  }
1147
1148
  /// Return true if the MachineInstr reads the specified virtual register.
1149
  /// Take into account that a partial define is a
1150
  /// read-modify-write operation.
1151
4.07M
  bool readsVirtualRegister(unsigned Reg) const {
1152
4.07M
    return readsWritesVirtualRegister(Reg).first;
1153
4.07M
  }
1154
1155
  /// Return a pair of bools (reads, writes) indicating if this instruction
1156
  /// reads or writes Reg. This also considers partial defines.
1157
  /// If Ops is not null, all operand indices for Reg are added.
1158
  std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
1159
                                SmallVectorImpl<unsigned> *Ops = nullptr) const;
1160
1161
  /// Return true if the MachineInstr kills the specified register.
1162
  /// If TargetRegisterInfo is passed, then it also checks if there is
1163
  /// a kill of a super-register.
1164
  bool killsRegister(unsigned Reg,
1165
1.03M
                     const TargetRegisterInfo *TRI = nullptr) const {
1166
1.03M
    return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1167
1.03M
  }
1168
1169
  /// Return true if the MachineInstr fully defines the specified register.
1170
  /// If TargetRegisterInfo is passed, then it also checks
1171
  /// if there is a def of a super-register.
1172
  /// NOTE: It's ignoring subreg indices on virtual registers.
1173
  bool definesRegister(unsigned Reg,
1174
38.2M
                       const TargetRegisterInfo *TRI = nullptr) const {
1175
38.2M
    return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1176
38.2M
  }
1177
1178
  /// Return true if the MachineInstr modifies (fully define or partially
1179
  /// define) the specified register.
1180
  /// NOTE: It's ignoring subreg indices on virtual registers.
1181
24.4M
  bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
1182
24.4M
    return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1183
24.4M
  }
1184
1185
  /// Returns true if the register is dead in this machine instruction.
1186
  /// If TargetRegisterInfo is passed, then it also checks
1187
  /// if there is a dead def of a super-register.
1188
  bool registerDefIsDead(unsigned Reg,
1189
1.57M
                         const TargetRegisterInfo *TRI = nullptr) const {
1190
1.57M
    return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1191
1.57M
  }
1192
1193
  /// Returns true if the MachineInstr has an implicit-use operand of exactly
1194
  /// the given register (not considering sub/super-registers).
1195
  bool hasRegisterImplicitUseOperand(unsigned Reg) const;
1196
1197
  /// Returns the operand index that is a use of the specific register or -1
1198
  /// if it is not found. It further tightens the search criteria to a use
1199
  /// that kills the register if isKill is true.
1200
  int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
1201
                                const TargetRegisterInfo *TRI = nullptr) const;
1202
1203
  /// Wrapper for findRegisterUseOperandIdx, it returns
1204
  /// a pointer to the MachineOperand rather than an index.
1205
  MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
1206
4.26M
                                      const TargetRegisterInfo *TRI = nullptr) {
1207
4.26M
    int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1208
4.26M
    return (Idx == -1) ? 
nullptr27.1k
:
&getOperand(Idx)4.23M
;
1209
4.26M
  }
1210
1211
  const MachineOperand *findRegisterUseOperand(
1212
    unsigned Reg, bool isKill = false,
1213
0
    const TargetRegisterInfo *TRI = nullptr) const {
1214
0
    return const_cast<MachineInstr *>(this)->
1215
0
      findRegisterUseOperand(Reg, isKill, TRI);
1216
0
  }
1217
1218
  /// Returns the operand index that is a def of the specified register or
1219
  /// -1 if it is not found. If isDead is true, defs that are not dead are
1220
  /// skipped. If Overlap is true, then it also looks for defs that merely
1221
  /// overlap the specified register. If TargetRegisterInfo is non-null,
1222
  /// then it also checks if there is a def of a super-register.
1223
  /// This may also return a register mask operand when Overlap is true.
1224
  int findRegisterDefOperandIdx(unsigned Reg,
1225
                                bool isDead = false, bool Overlap = false,
1226
                                const TargetRegisterInfo *TRI = nullptr) const;
1227
1228
  /// Wrapper for findRegisterDefOperandIdx, it returns
1229
  /// a pointer to the MachineOperand rather than an index.
1230
  MachineOperand *
1231
  findRegisterDefOperand(unsigned Reg, bool isDead = false,
1232
                         bool Overlap = false,
1233
6.54M
                         const TargetRegisterInfo *TRI = nullptr) {
1234
6.54M
    int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1235
6.54M
    return (Idx == -1) ? 
nullptr1.18M
:
&getOperand(Idx)5.36M
;
1236
6.54M
  }
1237
1238
  const MachineOperand *
1239
  findRegisterDefOperand(unsigned Reg, bool isDead = false,
1240
                         bool Overlap = false,
1241
0
                         const TargetRegisterInfo *TRI = nullptr) const {
1242
0
    return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1243
0
        Reg, isDead, Overlap, TRI);
1244
0
  }
1245
1246
  /// Find the index of the first operand in the
1247
  /// operand list that is used to represent the predicate. It returns -1 if
1248
  /// none is found.
1249
  int findFirstPredOperandIdx() const;
1250
1251
  /// Find the index of the flag word operand that
1252
  /// corresponds to operand OpIdx on an inline asm instruction.  Returns -1 if
1253
  /// getOperand(OpIdx) does not belong to an inline asm operand group.
1254
  ///
1255
  /// If GroupNo is not NULL, it will receive the number of the operand group
1256
  /// containing OpIdx.
1257
  ///
1258
  /// The flag operand is an immediate that can be decoded with methods like
1259
  /// InlineAsm::hasRegClassConstraint().
1260
  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1261
1262
  /// Compute the static register class constraint for operand OpIdx.
1263
  /// For normal instructions, this is derived from the MCInstrDesc.
1264
  /// For inline assembly it is derived from the flag words.
1265
  ///
1266
  /// Returns NULL if the static register class constraint cannot be
1267
  /// determined.
1268
  const TargetRegisterClass*
1269
  getRegClassConstraint(unsigned OpIdx,
1270
                        const TargetInstrInfo *TII,
1271
                        const TargetRegisterInfo *TRI) const;
1272
1273
  /// Applies the constraints (def/use) implied by this MI on \p Reg to
1274
  /// the given \p CurRC.
1275
  /// If \p ExploreBundle is set and MI is part of a bundle, all the
1276
  /// instructions inside the bundle will be taken into account. In other words,
1277
  /// this method accumulates all the constraints of the operand of this MI and
1278
  /// the related bundle if MI is a bundle or inside a bundle.
1279
  ///
1280
  /// Returns the register class that satisfies both \p CurRC and the
1281
  /// constraints set by MI. Returns NULL if such a register class does not
1282
  /// exist.
1283
  ///
1284
  /// \pre CurRC must not be NULL.
1285
  const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1286
      unsigned Reg, const TargetRegisterClass *CurRC,
1287
      const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1288
      bool ExploreBundle = false) const;
1289
1290
  /// Applies the constraints (def/use) implied by the \p OpIdx operand
1291
  /// to the given \p CurRC.
1292
  ///
1293
  /// Returns the register class that satisfies both \p CurRC and the
1294
  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1295
  /// does not exist.
1296
  ///
1297
  /// \pre CurRC must not be NULL.
1298
  /// \pre The operand at \p OpIdx must be a register.
1299
  const TargetRegisterClass *
1300
  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1301
                              const TargetInstrInfo *TII,
1302
                              const TargetRegisterInfo *TRI) const;
1303
1304
  /// Add a tie between the register operands at DefIdx and UseIdx.
1305
  /// The tie will cause the register allocator to ensure that the two
1306
  /// operands are assigned the same physical register.
1307
  ///
1308
  /// Tied operands are managed automatically for explicit operands in the
1309
  /// MCInstrDesc. This method is for exceptional cases like inline asm.
1310
  void tieOperands(unsigned DefIdx, unsigned UseIdx);
1311
1312
  /// Given the index of a tied register operand, find the
1313
  /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1314
  /// index of the tied operand which must exist.
1315
  unsigned findTiedOperandIdx(unsigned OpIdx) const;
1316
1317
  /// Given the index of a register def operand,
1318
  /// check if the register def is tied to a source operand, due to either
1319
  /// two-address elimination or inline assembly constraints. Returns the
1320
  /// first tied use operand index by reference if UseOpIdx is not null.
1321
  bool isRegTiedToUseOperand(unsigned DefOpIdx,
1322
439k
                             unsigned *UseOpIdx = nullptr) const {
1323
439k
    const MachineOperand &MO = getOperand(DefOpIdx);
1324
439k
    if (!MO.isReg() || 
!MO.isDef()437k
||
!MO.isTied()425k
)
1325
319k
      return false;
1326
119k
    if (UseOpIdx)
1327
25.3k
      *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1328
119k
    return true;
1329
119k
  }
1330
1331
  /// Return true if the use operand of the specified index is tied to a def
1332
  /// operand. It also returns the def operand index by reference if DefOpIdx
1333
  /// is not null.
1334
  bool isRegTiedToDefOperand(unsigned UseOpIdx,
1335
148M
                             unsigned *DefOpIdx = nullptr) const {
1336
148M
    const MachineOperand &MO = getOperand(UseOpIdx);
1337
148M
    if (!MO.isReg() || 
!MO.isUse()123M
||
!MO.isTied()99.2M
)
1338
146M
      return false;
1339
1.81M
    if (DefOpIdx)
1340
1.80M
      *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1341
1.81M
    return true;
1342
1.81M
  }
1343
1344
  /// Clears kill flags on all operands.
1345
  void clearKillInfo();
1346
1347
  /// Replace all occurrences of FromReg with ToReg:SubIdx,
1348
  /// properly composing subreg indices where necessary.
1349
  void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1350
                          const TargetRegisterInfo &RegInfo);
1351
1352
  /// We have determined MI kills a register. Look for the
1353
  /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1354
  /// add a implicit operand if it's not found. Returns true if the operand
1355
  /// exists / is added.
1356
  bool addRegisterKilled(unsigned IncomingReg,
1357
                         const TargetRegisterInfo *RegInfo,
1358
                         bool AddIfNotFound = false);
1359
1360
  /// Clear all kill flags affecting Reg.  If RegInfo is provided, this includes
1361
  /// all aliasing registers.
1362
  void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1363
1364
  /// We have determined MI defined a register without a use.
1365
  /// Look for the operand that defines it and mark it as IsDead. If
1366
  /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1367
  /// true if the operand exists / is added.
1368
  bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1369
                       bool AddIfNotFound = false);
1370
1371
  /// Clear all dead flags on operands defining register @p Reg.
1372
  void clearRegisterDeads(unsigned Reg);
1373
1374
  /// Mark all subregister defs of register @p Reg with the undef flag.
1375
  /// This function is used when we determined to have a subregister def in an
1376
  /// otherwise undefined super register.
1377
  void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true);
1378
1379
  /// We have determined MI defines a register. Make sure there is an operand
1380
  /// defining Reg.
1381
  void addRegisterDefined(unsigned Reg,
1382
                          const TargetRegisterInfo *RegInfo = nullptr);
1383
1384
  /// Mark every physreg used by this instruction as
1385
  /// dead except those in the UsedRegs list.
1386
  ///
1387
  /// On instructions with register mask operands, also add implicit-def
1388
  /// operands for all registers in UsedRegs.
1389
  void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1390
                             const TargetRegisterInfo &TRI);
1391
1392
  /// Return true if it is safe to move this instruction. If
1393
  /// SawStore is set to true, it means that there is a store (or call) between
1394
  /// the instruction's location and its intended destination.
1395
  bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1396
1397
  /// Returns true if this instruction's memory access aliases the memory
1398
  /// access of Other.
1399
  //
1400
  /// Assumes any physical registers used to compute addresses
1401
  /// have the same value for both instructions.  Returns false if neither
1402
  /// instruction writes to memory.
1403
  ///
1404
  /// @param AA Optional alias analysis, used to compare memory operands.
1405
  /// @param Other MachineInstr to check aliasing against.
1406
  /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1407
  bool mayAlias(AliasAnalysis *AA, const MachineInstr &Other, bool UseTBAA) const;
1408
1409
  /// Return true if this instruction may have an ordered
1410
  /// or volatile memory reference, or if the information describing the memory
1411
  /// reference is not available. Return false if it is known to have no
1412
  /// ordered or volatile memory references.
1413
  bool hasOrderedMemoryRef() const;
1414
1415
  /// Return true if this load instruction never traps and points to a memory
1416
  /// location whose value doesn't change during the execution of this function.
1417
  ///
1418
  /// Examples include loading a value from the constant pool or from the
1419
  /// argument area of a function (if it does not change).  If the instruction
1420
  /// does multiple loads, this returns true only if all of the loads are
1421
  /// dereferenceable and invariant.
1422
  bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const;
1423
1424
  /// If the specified instruction is a PHI that always merges together the
1425
  /// same virtual register, return the register, otherwise return 0.
1426
  unsigned isConstantValuePHI() const;
1427
1428
  /// Return true if this instruction has side effects that are not modeled
1429
  /// by mayLoad / mayStore, etc.
1430
  /// For all instructions, the property is encoded in MCInstrDesc::Flags
1431
  /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1432
  /// INLINEASM instruction, in which case the side effect property is encoded
1433
  /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1434
  ///
1435
  bool hasUnmodeledSideEffects() const;
1436
1437
  /// Returns true if it is illegal to fold a load across this instruction.
1438
  bool isLoadFoldBarrier() const;
1439
1440
  /// Return true if all the defs of this instruction are dead.
1441
  bool allDefsAreDead() const;
1442
1443
  /// Return a valid size if the instruction is a spill instruction.
1444
  Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;
1445
1446
  /// Return a valid size if the instruction is a folded spill instruction.
1447
  Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;
1448
1449
  /// Return a valid size if the instruction is a restore instruction.
1450
  Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;
1451
1452
  /// Return a valid size if the instruction is a folded restore instruction.
1453
  Optional<unsigned>
1454
  getFoldedRestoreSize(const TargetInstrInfo *TII) const;
1455
1456
  /// Copy implicit register operands from specified
1457
  /// instruction to this instruction.
1458
  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1459
1460
  /// Debugging support
1461
  /// @{
1462
  /// Determine the generic type to be printed (if needed) on uses and defs.
1463
  LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1464
                     const MachineRegisterInfo &MRI) const;
1465
1466
  /// Return true when an instruction has tied register that can't be determined
1467
  /// by the instruction's descriptor. This is useful for MIR printing, to
1468
  /// determine whether we need to print the ties or not.
1469
  bool hasComplexRegisterTies() const;
1470
1471
  /// Print this MI to \p OS.
1472
  /// Don't print information that can be inferred from other instructions if
1473
  /// \p IsStandalone is false. It is usually true when only a fragment of the
1474
  /// function is printed.
1475
  /// Only print the defs and the opcode if \p SkipOpers is true.
1476
  /// Otherwise, also print operands if \p SkipDebugLoc is true.
1477
  /// Otherwise, also print the debug loc, with a terminating newline.
1478
  /// \p TII is used to print the opcode name.  If it's not present, but the
1479
  /// MI is in a function, the opcode will be printed using the function's TII.
1480
  void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1481
             bool SkipDebugLoc = false, bool AddNewLine = true,
1482
             const TargetInstrInfo *TII = nullptr) const;
1483
  void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1484
             bool SkipOpers = false, bool SkipDebugLoc = false,
1485
             bool AddNewLine = true,
1486
             const TargetInstrInfo *TII = nullptr) const;
1487
  void dump() const;
1488
  /// @}
1489
1490
  //===--------------------------------------------------------------------===//
1491
  // Accessors used to build up machine instructions.
1492
1493
  /// Add the specified operand to the instruction.  If it is an implicit
1494
  /// operand, it is added to the end of the operand list.  If it is an
1495
  /// explicit operand it is added at the end of the explicit operand list
1496
  /// (before the first implicit operand).
1497
  ///
1498
  /// MF must be the machine function that was used to allocate this
1499
  /// instruction.
1500
  ///
1501
  /// MachineInstrBuilder provides a more convenient interface for creating
1502
  /// instructions and adding operands.
1503
  void addOperand(MachineFunction &MF, const MachineOperand &Op);
1504
1505
  /// Add an operand without providing an MF reference. This only works for
1506
  /// instructions that are inserted in a basic block.
1507
  ///
1508
  /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1509
  /// preferred.
1510
  void addOperand(const MachineOperand &Op);
1511
1512
  /// Replace the instruction descriptor (thus opcode) of
1513
  /// the current instruction with a new one.
1514
5.87M
  void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1515
1516
  /// Replace current source information with new such.
1517
  /// Avoid using this, the constructor argument is preferable.
1518
4.48M
  void setDebugLoc(DebugLoc dl) {
1519
4.48M
    debugLoc = std::move(dl);
1520
4.48M
    assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1521
4.48M
  }
1522
1523
  /// Erase an operand from an instruction, leaving it with one
1524
  /// fewer operand than it started with.
1525
  void RemoveOperand(unsigned OpNo);
1526
1527
  /// Clear this MachineInstr's memory reference descriptor list.  This resets
1528
  /// the memrefs to their most conservative state.  This should be used only
1529
  /// as a last resort since it greatly pessimizes our knowledge of the memory
1530
  /// access performed by the instruction.
1531
  void dropMemRefs(MachineFunction &MF);
1532
1533
  /// Assign this MachineInstr's memory reference descriptor list.
1534
  ///
1535
  /// Unlike other methods, this *will* allocate them into a new array
1536
  /// associated with the provided `MachineFunction`.
1537
  void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs);
1538
1539
  /// Add a MachineMemOperand to the machine instruction.
1540
  /// This function should be used only occasionally. The setMemRefs function
1541
  /// is the primary method for setting up a MachineInstr's MemRefs list.
1542
  void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1543
1544
  /// Clone another MachineInstr's memory reference descriptor list and replace
1545
  /// ours with it.
1546
  ///
1547
  /// Note that `*this` may be the incoming MI!
1548
  ///
1549
  /// Prefer this API whenever possible as it can avoid allocations in common
1550
  /// cases.
1551
  void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1552
1553
  /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1554
  /// list and replace ours with it.
1555
  ///
1556
  /// Note that `*this` may be one of the incoming MIs!
1557
  ///
1558
  /// Prefer this API whenever possible as it can avoid allocations in common
1559
  /// cases.
1560
  void cloneMergedMemRefs(MachineFunction &MF,
1561
                          ArrayRef<const MachineInstr *> MIs);
1562
1563
  /// Set a symbol that will be emitted just prior to the instruction itself.
1564
  ///
1565
  /// Setting this to a null pointer will remove any such symbol.
1566
  ///
1567
  /// FIXME: This is not fully implemented yet.
1568
  void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1569
1570
  /// Set a symbol that will be emitted just after the instruction itself.
1571
  ///
1572
  /// Setting this to a null pointer will remove any such symbol.
1573
  ///
1574
  /// FIXME: This is not fully implemented yet.
1575
  void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1576
1577
  /// Clone another MachineInstr's pre- and post- instruction symbols and
1578
  /// replace ours with it.
1579
  void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);
1580
1581
  /// Return the MIFlags which represent both MachineInstrs. This
1582
  /// should be used when merging two MachineInstrs into one. This routine does
1583
  /// not modify the MIFlags of this MachineInstr.
1584
  uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1585
1586
  static uint16_t copyFlagsFromInstruction(const Instruction &I);
1587
1588
  /// Copy all flags to MachineInst MIFlags
1589
  void copyIRFlags(const Instruction &I);
1590
1591
  /// Break any tie involving OpIdx.
1592
1.49M
  void untieRegOperand(unsigned OpIdx) {
1593
1.49M
    MachineOperand &MO = getOperand(OpIdx);
1594
1.49M
    if (MO.isReg() && 
MO.isTied()1.33M
) {
1595
192k
      getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1596
192k
      MO.TiedTo = 0;
1597
192k
    }
1598
1.49M
  }
1599
1600
  /// Add all implicit def and use operands to this instruction.
1601
  void addImplicitDefUseOperands(MachineFunction &MF);
1602
1603
  /// Scan instructions following MI and collect any matching DBG_VALUEs.
1604
  void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);
1605
1606
  /// Find all DBG_VALUEs immediately following this instruction that point
1607
  /// to a register def in this instruction and point them to \p Reg instead.
1608
  void changeDebugValuesDefReg(unsigned Reg);
1609
1610
  /// Returns the Intrinsic::ID for this instruction.
1611
  /// \pre Must have an intrinsic ID operand.
1612
91.9k
  unsigned getIntrinsicID() const {
1613
91.9k
    return getOperand(getNumExplicitDefs()).getIntrinsicID();
1614
91.9k
  }
1615
1616
private:
1617
  /// If this instruction is embedded into a MachineFunction, return the
1618
  /// MachineRegisterInfo object for the current function, otherwise
1619
  /// return null.
1620
  MachineRegisterInfo *getRegInfo();
1621
1622
  /// Unlink all of the register operands in this instruction from their
1623
  /// respective use lists.  This requires that the operands already be on their
1624
  /// use lists.
1625
  void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1626
1627
  /// Add all of the register operands in this instruction from their
1628
  /// respective use lists.  This requires that the operands not be on their
1629
  /// use lists yet.
1630
  void AddRegOperandsToUseLists(MachineRegisterInfo&);
1631
1632
  /// Slow path for hasProperty when we're dealing with a bundle.
1633
  bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1634
1635
  /// Implements the logic of getRegClassConstraintEffectForVReg for the
1636
  /// this MI and the given operand index \p OpIdx.
1637
  /// If the related operand does not constrained Reg, this returns CurRC.
1638
  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1639
      unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1640
      const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1641
};
1642
1643
/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1644
/// instruction rather than by pointer value.
1645
/// The hashing and equality testing functions ignore definitions so this is
1646
/// useful for CSE, etc.
1647
struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1648
270M
  static inline MachineInstr *getEmptyKey() {
1649
270M
    return nullptr;
1650
270M
  }
1651
1652
148M
  static inline MachineInstr *getTombstoneKey() {
1653
148M
    return reinterpret_cast<MachineInstr*>(-1);
1654
148M
  }
1655
1656
  static unsigned getHashValue(const MachineInstr* const &MI);
1657
1658
  static bool isEqual(const MachineInstr* const &LHS,
1659
209M
                      const MachineInstr* const &RHS) {
1660
209M
    if (RHS == getEmptyKey() || 
RHS == getTombstoneKey()90.1M
||
1661
209M
        
LHS == getEmptyKey()21.9M
||
LHS == getTombstoneKey()21.9M
)
1662
187M
      return LHS == RHS;
1663
21.9M
    return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1664
21.9M
  }
1665
};
1666
1667
//===----------------------------------------------------------------------===//
1668
// Debugging Support
1669
1670
1
inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1671
1
  MI.print(OS);
1672
1
  return OS;
1673
1
}
1674
1675
} // end namespace llvm
1676
1677
#endif // LLVM_CODEGEN_MACHINEINSTR_H