Coverage Report

Created: 2019-02-20 00:17

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/MachineInstr.h
Line
Count
Source (jump to first uncovered line)
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//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the declaration of the MachineInstr class, which is the
10
// basic representation for all target dependent machine instructions used by
11
// the back end.
12
//
13
//===----------------------------------------------------------------------===//
14
15
#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16
#define LLVM_CODEGEN_MACHINEINSTR_H
17
18
#include "llvm/ADT/DenseMapInfo.h"
19
#include "llvm/ADT/PointerSumType.h"
20
#include "llvm/ADT/ilist.h"
21
#include "llvm/ADT/ilist_node.h"
22
#include "llvm/ADT/iterator_range.h"
23
#include "llvm/Analysis/AliasAnalysis.h"
24
#include "llvm/CodeGen/MachineMemOperand.h"
25
#include "llvm/CodeGen/MachineOperand.h"
26
#include "llvm/CodeGen/TargetOpcodes.h"
27
#include "llvm/IR/DebugLoc.h"
28
#include "llvm/IR/InlineAsm.h"
29
#include "llvm/MC/MCInstrDesc.h"
30
#include "llvm/MC/MCSymbol.h"
31
#include "llvm/Support/ArrayRecycler.h"
32
#include "llvm/Support/TrailingObjects.h"
33
#include <algorithm>
34
#include <cassert>
35
#include <cstdint>
36
#include <utility>
37
38
namespace llvm {
39
40
template <typename T> class ArrayRef;
41
class DIExpression;
42
class DILocalVariable;
43
class MachineBasicBlock;
44
class MachineFunction;
45
class MachineMemOperand;
46
class MachineRegisterInfo;
47
class ModuleSlotTracker;
48
class raw_ostream;
49
template <typename T> class SmallVectorImpl;
50
class SmallBitVector;
51
class StringRef;
52
class TargetInstrInfo;
53
class TargetRegisterClass;
54
class TargetRegisterInfo;
55
56
//===----------------------------------------------------------------------===//
57
/// Representation of each machine instruction.
58
///
59
/// This class isn't a POD type, but it must have a trivial destructor. When a
60
/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
61
/// without having their destructor called.
62
///
63
class MachineInstr
64
    : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
65
                                    ilist_sentinel_tracking<true>> {
66
public:
67
  using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;
68
69
  /// Flags to specify different kinds of comments to output in
70
  /// assembly code.  These flags carry semantic information not
71
  /// otherwise easily derivable from the IR text.
72
  ///
73
  enum CommentFlag {
74
    ReloadReuse = 0x1,    // higher bits are reserved for target dep comments.
75
    NoSchedComment = 0x2,
76
    TAsmComments = 0x4    // Target Asm comments should start from this value.
77
  };
78
79
  enum MIFlag {
80
    NoFlags      = 0,
81
    FrameSetup   = 1 << 0,              // Instruction is used as a part of
82
                                        // function frame setup code.
83
    FrameDestroy = 1 << 1,              // Instruction is used as a part of
84
                                        // function frame destruction code.
85
    BundledPred  = 1 << 2,              // Instruction has bundled predecessors.
86
    BundledSucc  = 1 << 3,              // Instruction has bundled successors.
87
    FmNoNans     = 1 << 4,              // Instruction does not support Fast
88
                                        // math nan values.
89
    FmNoInfs     = 1 << 5,              // Instruction does not support Fast
90
                                        // math infinity values.
91
    FmNsz        = 1 << 6,              // Instruction is not required to retain
92
                                        // signed zero values.
93
    FmArcp       = 1 << 7,              // Instruction supports Fast math
94
                                        // reciprocal approximations.
95
    FmContract   = 1 << 8,              // Instruction supports Fast math
96
                                        // contraction operations like fma.
97
    FmAfn        = 1 << 9,              // Instruction may map to Fast math
98
                                        // instrinsic approximation.
99
    FmReassoc    = 1 << 10,             // Instruction supports Fast math
100
                                        // reassociation of operand order.
101
    NoUWrap      = 1 << 11,             // Instruction supports binary operator
102
                                        // no unsigned wrap.
103
    NoSWrap      = 1 << 12,             // Instruction supports binary operator
104
                                        // no signed wrap.
105
    IsExact      = 1 << 13              // Instruction supports division is
106
                                        // known to be exact.
107
  };
108
109
private:
110
  const MCInstrDesc *MCID;              // Instruction descriptor.
111
  MachineBasicBlock *Parent = nullptr;  // Pointer to the owning basic block.
112
113
  // Operands are allocated by an ArrayRecycler.
114
  MachineOperand *Operands = nullptr;   // Pointer to the first operand.
115
  unsigned NumOperands = 0;             // Number of operands on instruction.
116
  using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
117
  OperandCapacity CapOperands;          // Capacity of the Operands array.
118
119
  uint16_t Flags = 0;                   // Various bits of additional
120
                                        // information about machine
121
                                        // instruction.
122
123
  uint8_t AsmPrinterFlags = 0;          // Various bits of information used by
124
                                        // the AsmPrinter to emit helpful
125
                                        // comments.  This is *not* semantic
126
                                        // information.  Do not use this for
127
                                        // anything other than to convey comment
128
                                        // information to AsmPrinter.
129
130
  /// Internal implementation detail class that provides out-of-line storage for
131
  /// extra info used by the machine instruction when this info cannot be stored
132
  /// in-line within the instruction itself.
133
  ///
134
  /// This has to be defined eagerly due to the implementation constraints of
135
  /// `PointerSumType` where it is used.
136
  class ExtraInfo final
137
      : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *> {
138
  public:
139
    static ExtraInfo *create(BumpPtrAllocator &Allocator,
140
                             ArrayRef<MachineMemOperand *> MMOs,
141
                             MCSymbol *PreInstrSymbol = nullptr,
142
2.10M
                             MCSymbol *PostInstrSymbol = nullptr) {
143
2.10M
      bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
144
2.10M
      bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
145
2.10M
      auto *Result = new (Allocator.Allocate(
146
2.10M
          totalSizeToAlloc<MachineMemOperand *, MCSymbol *>(
147
2.10M
              MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol),
148
2.10M
          alignof(ExtraInfo)))
149
2.10M
          ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol);
150
2.10M
151
2.10M
      // Copy the actual data into the trailing objects.
152
2.10M
      std::copy(MMOs.begin(), MMOs.end(),
153
2.10M
                Result->getTrailingObjects<MachineMemOperand *>());
154
2.10M
155
2.10M
      if (HasPreInstrSymbol)
156
2
        Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
157
2.10M
      if (HasPostInstrSymbol)
158
2
        Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
159
2
            PostInstrSymbol;
160
2.10M
161
2.10M
      return Result;
162
2.10M
    }
163
164
2.93M
    ArrayRef<MachineMemOperand *> getMMOs() const {
165
2.93M
      return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
166
2.93M
    }
167
168
1.70M
    MCSymbol *getPreInstrSymbol() const {
169
1.70M
      return HasPreInstrSymbol ? 
getTrailingObjects<MCSymbol *>()[0]2
:
nullptr1.70M
;
170
1.70M
    }
171
172
1.70M
    MCSymbol *getPostInstrSymbol() const {
173
1.70M
      return HasPostInstrSymbol
174
1.70M
                 ? 
getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]2
175
1.70M
                 : 
nullptr1.70M
;
176
1.70M
    }
177
178
  private:
179
    friend TrailingObjects;
180
181
    // Description of the extra info, used to interpret the actual optional
182
    // data appended.
183
    //
184
    // Note that this is not terribly space optimized. This leaves a great deal
185
    // of flexibility to fit more in here later.
186
    const int NumMMOs;
187
    const bool HasPreInstrSymbol;
188
    const bool HasPostInstrSymbol;
189
190
    // Implement the `TrailingObjects` internal API.
191
8
    size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
192
8
      return NumMMOs;
193
8
    }
194
0
    size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
195
0
      return HasPreInstrSymbol + HasPostInstrSymbol;
196
0
    }
197
198
    // Just a boring constructor to allow us to initialize the sizes. Always use
199
    // the `create` routine above.
200
    ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol)
201
        : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
202
2.10M
          HasPostInstrSymbol(HasPostInstrSymbol) {}
203
  };
204
205
  /// Enumeration of the kinds of inline extra info available. It is important
206
  /// that the `MachineMemOperand` inline kind has a tag value of zero to make
207
  /// it accessible as an `ArrayRef`.
208
  enum ExtraInfoInlineKinds {
209
    EIIK_MMO = 0,
210
    EIIK_PreInstrSymbol,
211
    EIIK_PostInstrSymbol,
212
    EIIK_OutOfLine
213
  };
214
215
  // We store extra information about the instruction here. The common case is
216
  // expected to be nothing or a single pointer (typically a MMO or a symbol).
217
  // We work to optimize this common case by storing it inline here rather than
218
  // requiring a separate allocation, but we fall back to an allocation when
219
  // multiple pointers are needed.
220
  PointerSumType<ExtraInfoInlineKinds,
221
                 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
222
                 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
223
                 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
224
                 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
225
      Info;
226
227
  DebugLoc debugLoc;                    // Source line information.
228
229
  // Intrusive list support
230
  friend struct ilist_traits<MachineInstr>;
231
  friend struct ilist_callback_traits<MachineBasicBlock>;
232
118M
  void setParent(MachineBasicBlock *P) { Parent = P; }
233
234
  /// This constructor creates a copy of the given
235
  /// MachineInstr in the given MachineFunction.
236
  MachineInstr(MachineFunction &, const MachineInstr &);
237
238
  /// This constructor create a MachineInstr and add the implicit operands.
239
  /// It reserves space for number of operands specified by
240
  /// MCInstrDesc.  An explicit DebugLoc is supplied.
241
  MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl,
242
               bool NoImp = false);
243
244
  // MachineInstrs are pool-allocated and owned by MachineFunction.
245
  friend class MachineFunction;
246
247
public:
248
  MachineInstr(const MachineInstr &) = delete;
249
  MachineInstr &operator=(const MachineInstr &) = delete;
250
  // Use MachineFunction::DeleteMachineInstr() instead.
251
  ~MachineInstr() = delete;
252
253
375M
  const MachineBasicBlock* getParent() const { return Parent; }
254
845M
  MachineBasicBlock* getParent() { return Parent; }
255
256
  /// Return the function that contains the basic block that this instruction
257
  /// belongs to.
258
  ///
259
  /// Note: this is undefined behaviour if the instruction does not have a
260
  /// parent.
261
  const MachineFunction *getMF() const;
262
68.6M
  MachineFunction *getMF() {
263
68.6M
    return const_cast<MachineFunction *>(
264
68.6M
        static_cast<const MachineInstr *>(this)->getMF());
265
68.6M
  }
266
267
  /// Return the asm printer flags bitvector.
268
52.9k
  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
269
270
  /// Clear the AsmPrinter bitvector.
271
0
  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
272
273
  /// Return whether an AsmPrinter flag is set.
274
1.77M
  bool getAsmPrinterFlag(CommentFlag Flag) const {
275
1.77M
    return AsmPrinterFlags & Flag;
276
1.77M
  }
277
278
  /// Set a flag for the AsmPrinter.
279
33.2k
  void setAsmPrinterFlag(uint8_t Flag) {
280
33.2k
    AsmPrinterFlags |= Flag;
281
33.2k
  }
282
283
  /// Clear specific AsmPrinter flags.
284
0
  void clearAsmPrinterFlag(CommentFlag Flag) {
285
0
    AsmPrinterFlags &= ~Flag;
286
0
  }
287
288
  /// Return the MI flags bitvector.
289
11.0M
  uint16_t getFlags() const {
290
11.0M
    return Flags;
291
11.0M
  }
292
293
  /// Return whether an MI flag is set.
294
6.67G
  bool getFlag(MIFlag Flag) const {
295
6.67G
    return Flags & Flag;
296
6.67G
  }
297
298
  /// Set a MI flag.
299
2.60M
  void setFlag(MIFlag Flag) {
300
2.60M
    Flags |= (uint16_t)Flag;
301
2.60M
  }
302
303
3.98M
  void setFlags(unsigned flags) {
304
3.98M
    // Filter out the automatically maintained flags.
305
3.98M
    unsigned Mask = BundledPred | BundledSucc;
306
3.98M
    Flags = (Flags & Mask) | (flags & ~Mask);
307
3.98M
  }
308
309
  /// clearFlag - Clear a MI flag.
310
146k
  void clearFlag(MIFlag Flag) {
311
146k
    Flags &= ~((uint16_t)Flag);
312
146k
  }
313
314
  /// Return true if MI is in a bundle (but not the first MI in a bundle).
315
  ///
316
  /// A bundle looks like this before it's finalized:
317
  ///   ----------------
318
  ///   |      MI      |
319
  ///   ----------------
320
  ///          |
321
  ///   ----------------
322
  ///   |      MI    * |
323
  ///   ----------------
324
  ///          |
325
  ///   ----------------
326
  ///   |      MI    * |
327
  ///   ----------------
328
  /// In this case, the first MI starts a bundle but is not inside a bundle, the
329
  /// next 2 MIs are considered "inside" the bundle.
330
  ///
331
  /// After a bundle is finalized, it looks like this:
332
  ///   ----------------
333
  ///   |    Bundle    |
334
  ///   ----------------
335
  ///          |
336
  ///   ----------------
337
  ///   |      MI    * |
338
  ///   ----------------
339
  ///          |
340
  ///   ----------------
341
  ///   |      MI    * |
342
  ///   ----------------
343
  ///          |
344
  ///   ----------------
345
  ///   |      MI    * |
346
  ///   ----------------
347
  /// The first instruction has the special opcode "BUNDLE". It's not "inside"
348
  /// a bundle, but the next three MIs are.
349
188M
  bool isInsideBundle() const {
350
188M
    return getFlag(BundledPred);
351
188M
  }
352
353
  /// Return true if this instruction part of a bundle. This is true
354
  /// if either itself or its following instruction is marked "InsideBundle".
355
2.08G
  bool isBundled() const {
356
2.08G
    return isBundledWithPred() || 
isBundledWithSucc()2.08G
;
357
2.08G
  }
358
359
  /// Return true if this instruction is part of a bundle, and it is not the
360
  /// first instruction in the bundle.
361
2.92G
  bool isBundledWithPred() const { return getFlag(BundledPred); }
362
363
  /// Return true if this instruction is part of a bundle, and it is not the
364
  /// last instruction in the bundle.
365
3.54G
  bool isBundledWithSucc() const { return getFlag(BundledSucc); }
366
367
  /// Bundle this instruction with its predecessor. This can be an unbundled
368
  /// instruction, or it can be the first instruction in a bundle.
369
  void bundleWithPred();
370
371
  /// Bundle this instruction with its successor. This can be an unbundled
372
  /// instruction, or it can be the last instruction in a bundle.
373
  void bundleWithSucc();
374
375
  /// Break bundle above this instruction.
376
  void unbundleFromPred();
377
378
  /// Break bundle below this instruction.
379
  void unbundleFromSucc();
380
381
  /// Returns the debug location id of this MachineInstr.
382
59.0M
  const DebugLoc &getDebugLoc() const { return debugLoc; }
383
384
  /// Return the debug variable referenced by
385
  /// this DBG_VALUE instruction.
386
  const DILocalVariable *getDebugVariable() const;
387
388
  /// Return the complex address expression referenced by
389
  /// this DBG_VALUE instruction.
390
  const DIExpression *getDebugExpression() const;
391
392
  /// Return the debug label referenced by
393
  /// this DBG_LABEL instruction.
394
  const DILabel *getDebugLabel() const;
395
396
  /// Emit an error referring to the source location of this instruction.
397
  /// This should only be used for inline assembly that is somehow
398
  /// impossible to compile. Other errors should have been handled much
399
  /// earlier.
400
  ///
401
  /// If this method returns, the caller should try to recover from the error.
402
  void emitError(StringRef Msg) const;
403
404
  /// Returns the target instruction descriptor of this MachineInstr.
405
3.35G
  const MCInstrDesc &getDesc() const { return *MCID; }
406
407
  /// Returns the opcode of this MachineInstr.
408
10.0G
  unsigned getOpcode() const { return MCID->Opcode; }
409
410
  /// Retuns the total number of operands.
411
1.15G
  unsigned getNumOperands() const { return NumOperands; }
412
413
1.68G
  const MachineOperand& getOperand(unsigned i) const {
414
1.68G
    assert(i < getNumOperands() && "getOperand() out of range!");
415
1.68G
    return Operands[i];
416
1.68G
  }
417
1.88G
  MachineOperand& getOperand(unsigned i) {
418
1.88G
    assert(i < getNumOperands() && "getOperand() out of range!");
419
1.88G
    return Operands[i];
420
1.88G
  }
421
422
  /// Returns the total number of definitions.
423
335k
  unsigned getNumDefs() const {
424
335k
    return getNumExplicitDefs() + MCID->getNumImplicitDefs();
425
335k
  }
426
427
  /// Return true if operand \p OpIdx is a subregister index.
428
75.2k
  bool isOperandSubregIdx(unsigned OpIdx) const {
429
75.2k
    assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&
430
75.2k
           "Expected MO_Immediate operand type.");
431
75.2k
    if (isExtractSubreg() && 
OpIdx == 27
)
432
7
      return true;
433
75.2k
    if (isInsertSubreg() && 
OpIdx == 3121
)
434
121
      return true;
435
75.1k
    if (isRegSequence() && 
OpIdx > 1568
&&
(OpIdx % 2) == 0568
)
436
568
      return true;
437
74.5k
    if (isSubregToReg() && 
OpIdx == 31.33k
)
438
668
      return true;
439
73.9k
    return false;
440
73.9k
  }
441
442
  /// Returns the number of non-implicit operands.
443
  unsigned getNumExplicitOperands() const;
444
445
  /// Returns the number of non-implicit definitions.
446
  unsigned getNumExplicitDefs() const;
447
448
  /// iterator/begin/end - Iterate over all operands of a machine instruction.
449
  using mop_iterator = MachineOperand *;
450
  using const_mop_iterator = const MachineOperand *;
451
452
410M
  mop_iterator operands_begin() { return Operands; }
453
397M
  mop_iterator operands_end() { return Operands + NumOperands; }
454
455
312M
  const_mop_iterator operands_begin() const { return Operands; }
456
258M
  const_mop_iterator operands_end() const { return Operands + NumOperands; }
457
458
278M
  iterator_range<mop_iterator> operands() {
459
278M
    return make_range(operands_begin(), operands_end());
460
278M
  }
461
206M
  iterator_range<const_mop_iterator> operands() const {
462
206M
    return make_range(operands_begin(), operands_end());
463
206M
  }
464
9.82M
  iterator_range<mop_iterator> explicit_operands() {
465
9.82M
    return make_range(operands_begin(),
466
9.82M
                      operands_begin() + getNumExplicitOperands());
467
9.82M
  }
468
5.19M
  iterator_range<const_mop_iterator> explicit_operands() const {
469
5.19M
    return make_range(operands_begin(),
470
5.19M
                      operands_begin() + getNumExplicitOperands());
471
5.19M
  }
472
9.82M
  iterator_range<mop_iterator> implicit_operands() {
473
9.82M
    return make_range(explicit_operands().end(), operands_end());
474
9.82M
  }
475
4.70M
  iterator_range<const_mop_iterator> implicit_operands() const {
476
4.70M
    return make_range(explicit_operands().end(), operands_end());
477
4.70M
  }
478
  /// Returns a range over all explicit operands that are register definitions.
479
  /// Implicit definition are not included!
480
857k
  iterator_range<mop_iterator> defs() {
481
857k
    return make_range(operands_begin(),
482
857k
                      operands_begin() + getNumExplicitDefs());
483
857k
  }
484
  /// \copydoc defs()
485
16.4M
  iterator_range<const_mop_iterator> defs() const {
486
16.4M
    return make_range(operands_begin(),
487
16.4M
                      operands_begin() + getNumExplicitDefs());
488
16.4M
  }
489
  /// Returns a range that includes all operands that are register uses.
490
  /// This may include unrelated operands which are not register uses.
491
430k
  iterator_range<mop_iterator> uses() {
492
430k
    return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
493
430k
  }
494
  /// \copydoc uses()
495
35.5M
  iterator_range<const_mop_iterator> uses() const {
496
35.5M
    return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
497
35.5M
  }
498
52.6k
  iterator_range<mop_iterator> explicit_uses() {
499
52.6k
    return make_range(operands_begin() + getNumExplicitDefs(),
500
52.6k
                      operands_begin() + getNumExplicitOperands());
501
52.6k
  }
502
37
  iterator_range<const_mop_iterator> explicit_uses() const {
503
37
    return make_range(operands_begin() + getNumExplicitDefs(),
504
37
                      operands_begin() + getNumExplicitOperands());
505
37
  }
506
507
  /// Returns the number of the operand iterator \p I points to.
508
15.2M
  unsigned getOperandNo(const_mop_iterator I) const {
509
15.2M
    return I - operands_begin();
510
15.2M
  }
511
512
  /// Access to memory operands of the instruction. If there are none, that does
513
  /// not imply anything about whether the function accesses memory. Instead,
514
  /// the caller must behave conservatively.
515
335M
  ArrayRef<MachineMemOperand *> memoperands() const {
516
335M
    if (!Info)
517
128M
      return {};
518
206M
519
206M
    if (Info.is<EIIK_MMO>())
520
203M
      return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
521
2.93M
522
2.93M
    if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
523
2.93M
      return EI->getMMOs();
524
1.35k
525
1.35k
    return {};
526
1.35k
  }
527
528
  /// Access to memory operands of the instruction.
529
  ///
530
  /// If `memoperands_begin() == memoperands_end()`, that does not imply
531
  /// anything about whether the function accesses memory. Instead, the caller
532
  /// must behave conservatively.
533
72.0M
  mmo_iterator memoperands_begin() const { return memoperands().begin(); }
534
535
  /// Access to memory operands of the instruction.
536
  ///
537
  /// If `memoperands_begin() == memoperands_end()`, that does not imply
538
  /// anything about whether the function accesses memory. Instead, the caller
539
  /// must behave conservatively.
540
58.2M
  mmo_iterator memoperands_end() const { return memoperands().end(); }
541
542
  /// Return true if we don't have any memory operands which described the
543
  /// memory access done by this instruction.  If this is true, calling code
544
  /// must be conservative.
545
77.8M
  bool memoperands_empty() const { return memoperands().empty(); }
546
547
  /// Return true if this instruction has exactly one MachineMemOperand.
548
14.3M
  bool hasOneMemOperand() const { return memoperands().size() == 1; }
549
550
  /// Return the number of memory operands.
551
515k
  unsigned getNumMemOperands() const { return memoperands().size(); }
552
553
  /// Helper to extract a pre-instruction symbol if one has been added.
554
29.6M
  MCSymbol *getPreInstrSymbol() const {
555
29.6M
    if (!Info)
556
22.9M
      return nullptr;
557
6.67M
    if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
558
30
      return S;
559
6.67M
    if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
560
1.70M
      return EI->getPreInstrSymbol();
561
4.97M
562
4.97M
    return nullptr;
563
4.97M
  }
564
565
  /// Helper to extract a post-instruction symbol if one has been added.
566
29.6M
  MCSymbol *getPostInstrSymbol() const {
567
29.6M
    if (!Info)
568
22.9M
      return nullptr;
569
6.67M
    if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
570
55
      return S;
571
6.67M
    if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
572
1.70M
      return EI->getPostInstrSymbol();
573
4.97M
574
4.97M
    return nullptr;
575
4.97M
  }
576
577
  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
578
  /// queries but they are bundle aware.
579
580
  enum QueryType {
581
    IgnoreBundle,    // Ignore bundles
582
    AnyInBundle,     // Return true if any instruction in bundle has property
583
    AllInBundle      // Return true if all instructions in bundle have property
584
  };
585
586
  /// Return true if the instruction (or in the case of a bundle,
587
  /// the instructions inside the bundle) has the specified property.
588
  /// The first argument is the property being queried.
589
  /// The second argument indicates whether the query should look inside
590
  /// instruction bundles.
591
2.56G
  bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
592
2.56G
    assert(MCFlag < 64 &&
593
2.56G
           "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
594
2.56G
    // Inline the fast path for unbundled or bundle-internal instructions.
595
2.56G
    if (Type == IgnoreBundle || 
!isBundled()2.07G
||
isBundledWithPred()339k
)
596
2.56G
      return getDesc().getFlags() & (1ULL << MCFlag);
597
299k
598
299k
    // If this is the first instruction in a bundle, take the slow path.
599
299k
    return hasPropertyInBundle(1ULL << MCFlag, Type);
600
299k
  }
601
602
  /// Return true if this instruction can have a variable number of operands.
603
  /// In this case, the variable operands will be after the normal
604
  /// operands but before the implicit definitions and uses (if any are
605
  /// present).
606
47.4M
  bool isVariadic(QueryType Type = IgnoreBundle) const {
607
47.4M
    return hasProperty(MCID::Variadic, Type);
608
47.4M
  }
609
610
  /// Set if this instruction has an optional definition, e.g.
611
  /// ARM instructions which can set condition code if 's' bit is set.
612
16.4k
  bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
613
16.4k
    return hasProperty(MCID::HasOptionalDef, Type);
614
16.4k
  }
615
616
  /// Return true if this is a pseudo instruction that doesn't
617
  /// correspond to a real machine instruction.
618
38.9M
  bool isPseudo(QueryType Type = IgnoreBundle) const {
619
38.9M
    return hasProperty(MCID::Pseudo, Type);
620
38.9M
  }
621
622
15.3M
  bool isReturn(QueryType Type = AnyInBundle) const {
623
15.3M
    return hasProperty(MCID::Return, Type);
624
15.3M
  }
625
626
  /// Return true if this is an instruction that marks the end of an EH scope,
627
  /// i.e., a catchpad or a cleanuppad instruction.
628
2.20k
  bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
629
2.20k
    return hasProperty(MCID::EHScopeReturn, Type);
630
2.20k
  }
631
632
313M
  bool isCall(QueryType Type = AnyInBundle) const {
633
313M
    return hasProperty(MCID::Call, Type);
634
313M
  }
635
636
  /// Returns true if the specified instruction stops control flow
637
  /// from executing the instruction immediately following it.  Examples include
638
  /// unconditional branches and return instructions.
639
91.3M
  bool isBarrier(QueryType Type = AnyInBundle) const {
640
91.3M
    return hasProperty(MCID::Barrier, Type);
641
91.3M
  }
642
643
  /// Returns true if this instruction part of the terminator for a basic block.
644
  /// Typically this is things like return and branch instructions.
645
  ///
646
  /// Various passes use this to insert code into the bottom of a basic block,
647
  /// but before control flow occurs.
648
444M
  bool isTerminator(QueryType Type = AnyInBundle) const {
649
444M
    return hasProperty(MCID::Terminator, Type);
650
444M
  }
651
652
  /// Returns true if this is a conditional, unconditional, or indirect branch.
653
  /// Predicates below can be used to discriminate between
654
  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
655
  /// get more information.
656
117M
  bool isBranch(QueryType Type = AnyInBundle) const {
657
117M
    return hasProperty(MCID::Branch, Type);
658
117M
  }
659
660
  /// Return true if this is an indirect branch, such as a
661
  /// branch through a register.
662
40.8M
  bool isIndirectBranch(QueryType Type = AnyInBundle) const {
663
40.8M
    return hasProperty(MCID::IndirectBranch, Type);
664
40.8M
  }
665
666
  /// Return true if this is a branch which may fall
667
  /// through to the next instruction or may transfer control flow to some other
668
  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
669
  /// information about this branch.
670
27.7M
  bool isConditionalBranch(QueryType Type = AnyInBundle) const {
671
27.7M
    return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
672
27.7M
  }
673
674
  /// Return true if this is a branch which always
675
  /// transfers control flow to some other block.  The
676
  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
677
  /// about this branch.
678
5.18M
  bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
679
5.18M
    return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
680
5.18M
  }
681
682
  /// Return true if this instruction has a predicate operand that
683
  /// controls execution.  It may be set to 'always', or may be set to other
684
  /// values.   There are various methods in TargetInstrInfo that can be used to
685
  /// control and modify the predicate in this instruction.
686
20.4M
  bool isPredicable(QueryType Type = AllInBundle) const {
687
20.4M
    // If it's a bundle than all bundled instructions must be predicable for this
688
20.4M
    // to return true.
689
20.4M
    return hasProperty(MCID::Predicable, Type);
690
20.4M
  }
691
692
  /// Return true if this instruction is a comparison.
693
26.5M
  bool isCompare(QueryType Type = IgnoreBundle) const {
694
26.5M
    return hasProperty(MCID::Compare, Type);
695
26.5M
  }
696
697
  /// Return true if this instruction is a move immediate
698
  /// (including conditional moves) instruction.
699
126M
  bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
700
126M
    return hasProperty(MCID::MoveImm, Type);
701
126M
  }
702
703
  /// Return true if this instruction is a register move.
704
  /// (including moving values from subreg to reg)
705
2.07k
  bool isMoveReg(QueryType Type = IgnoreBundle) const {
706
2.07k
    return hasProperty(MCID::MoveReg, Type);
707
2.07k
  }
708
709
  /// Return true if this instruction is a bitcast instruction.
710
30.0M
  bool isBitcast(QueryType Type = IgnoreBundle) const {
711
30.0M
    return hasProperty(MCID::Bitcast, Type);
712
30.0M
  }
713
714
  /// Return true if this instruction is a select instruction.
715
25.6M
  bool isSelect(QueryType Type = IgnoreBundle) const {
716
25.6M
    return hasProperty(MCID::Select, Type);
717
25.6M
  }
718
719
  /// Return true if this instruction cannot be safely duplicated.
720
  /// For example, if the instruction has a unique labels attached
721
  /// to it, duplicating it would cause multiple definition errors.
722
19.8M
  bool isNotDuplicable(QueryType Type = AnyInBundle) const {
723
19.8M
    return hasProperty(MCID::NotDuplicable, Type);
724
19.8M
  }
725
726
  /// Return true if this instruction is convergent.
727
  /// Convergent instructions can not be made control-dependent on any
728
  /// additional values.
729
35.2M
  bool isConvergent(QueryType Type = AnyInBundle) const {
730
35.2M
    if (isInlineAsm()) {
731
10.5k
      unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
732
10.5k
      if (ExtraInfo & InlineAsm::Extra_IsConvergent)
733
2
        return true;
734
35.2M
    }
735
35.2M
    return hasProperty(MCID::Convergent, Type);
736
35.2M
  }
737
738
  /// Returns true if the specified instruction has a delay slot
739
  /// which must be filled by the code generator.
740
137k
  bool hasDelaySlot(QueryType Type = AnyInBundle) const {
741
137k
    return hasProperty(MCID::DelaySlot, Type);
742
137k
  }
743
744
  /// Return true for instructions that can be folded as
745
  /// memory operands in other instructions. The most common use for this
746
  /// is instructions that are simple loads from memory that don't modify
747
  /// the loaded value in any way, but it can also be used for instructions
748
  /// that can be expressed as constant-pool loads, such as V_SETALLONES
749
  /// on x86, to allow them to be folded when it is beneficial.
750
  /// This should only be set on instructions that return a value in their
751
  /// only virtual register definition.
752
31.4M
  bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
753
31.4M
    return hasProperty(MCID::FoldableAsLoad, Type);
754
31.4M
  }
755
756
  /// Return true if this instruction behaves
757
  /// the same way as the generic REG_SEQUENCE instructions.
758
  /// E.g., on ARM,
759
  /// dX VMOVDRR rY, rZ
760
  /// is equivalent to
761
  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
762
  ///
763
  /// Note that for the optimizers to be able to take advantage of
764
  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
765
  /// override accordingly.
766
29.7M
  bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
767
29.7M
    return hasProperty(MCID::RegSequence, Type);
768
29.7M
  }
769
770
  /// Return true if this instruction behaves
771
  /// the same way as the generic EXTRACT_SUBREG instructions.
772
  /// E.g., on ARM,
773
  /// rX, rY VMOVRRD dZ
774
  /// is equivalent to two EXTRACT_SUBREG:
775
  /// rX = EXTRACT_SUBREG dZ, ssub_0
776
  /// rY = EXTRACT_SUBREG dZ, ssub_1
777
  ///
778
  /// Note that for the optimizers to be able to take advantage of
779
  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
780
  /// override accordingly.
781
29.6M
  bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
782
29.6M
    return hasProperty(MCID::ExtractSubreg, Type);
783
29.6M
  }
784
785
  /// Return true if this instruction behaves
786
  /// the same way as the generic INSERT_SUBREG instructions.
787
  /// E.g., on ARM,
788
  /// dX = VSETLNi32 dY, rZ, Imm
789
  /// is equivalent to a INSERT_SUBREG:
790
  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
791
  ///
792
  /// Note that for the optimizers to be able to take advantage of
793
  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
794
  /// override accordingly.
795
29.6M
  bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
796
29.6M
    return hasProperty(MCID::InsertSubreg, Type);
797
29.6M
  }
798
799
  //===--------------------------------------------------------------------===//
800
  // Side Effect Analysis
801
  //===--------------------------------------------------------------------===//
802
803
  /// Return true if this instruction could possibly read memory.
804
  /// Instructions with this flag set are not necessarily simple load
805
  /// instructions, they may load a value and modify it, for example.
806
376M
  bool mayLoad(QueryType Type = AnyInBundle) const {
807
376M
    if (isInlineAsm()) {
808
61.4k
      unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
809
61.4k
      if (ExtraInfo & InlineAsm::Extra_MayLoad)
810
30.3k
        return true;
811
376M
    }
812
376M
    return hasProperty(MCID::MayLoad, Type);
813
376M
  }
814
815
  /// Return true if this instruction could possibly modify memory.
816
  /// Instructions with this flag set are not necessarily simple store
817
  /// instructions, they may store a modified value based on their operands, or
818
  /// may not actually modify anything, for example.
819
355M
  bool mayStore(QueryType Type = AnyInBundle) const {
820
355M
    if (isInlineAsm()) {
821
85.2k
      unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
822
85.2k
      if (ExtraInfo & InlineAsm::Extra_MayStore)
823
42.1k
        return true;
824
355M
    }
825
355M
    return hasProperty(MCID::MayStore, Type);
826
355M
  }
827
828
  /// Return true if this instruction could possibly read or modify memory.
829
11.4M
  bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
830
11.4M
    return mayLoad(Type) || 
mayStore(Type)8.70M
;
831
11.4M
  }
832
833
  //===--------------------------------------------------------------------===//
834
  // Flags that indicate whether an instruction can be modified by a method.
835
  //===--------------------------------------------------------------------===//
836
837
  /// Return true if this may be a 2- or 3-address
838
  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
839
  /// result if Y and Z are exchanged.  If this flag is set, then the
840
  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
841
  /// instruction.
842
  ///
843
  /// Note that this flag may be set on instructions that are only commutable
844
  /// sometimes.  In these cases, the call to commuteInstruction will fail.
845
  /// Also note that some instructions require non-trivial modification to
846
  /// commute them.
847
20.6M
  bool isCommutable(QueryType Type = IgnoreBundle) const {
848
20.6M
    return hasProperty(MCID::Commutable, Type);
849
20.6M
  }
850
851
  /// Return true if this is a 2-address instruction
852
  /// which can be changed into a 3-address instruction if needed.  Doing this
853
  /// transformation can be profitable in the register allocator, because it
854
  /// means that the instruction can use a 2-address form if possible, but
855
  /// degrade into a less efficient form if the source and dest register cannot
856
  /// be assigned to the same register.  For example, this allows the x86
857
  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
858
  /// is the same speed as the shift but has bigger code size.
859
  ///
860
  /// If this returns true, then the target must implement the
861
  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
862
  /// is allowed to fail if the transformation isn't valid for this specific
863
  /// instruction (e.g. shl reg, 4 on x86).
864
  ///
865
382k
  bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
866
382k
    return hasProperty(MCID::ConvertibleTo3Addr, Type);
867
382k
  }
868
869
  /// Return true if this instruction requires
870
  /// custom insertion support when the DAG scheduler is inserting it into a
871
  /// machine basic block.  If this is true for the instruction, it basically
872
  /// means that it is a pseudo instruction used at SelectionDAG time that is
873
  /// expanded out into magic code by the target when MachineInstrs are formed.
874
  ///
875
  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
876
  /// is used to insert this into the MachineBasicBlock.
877
26.7M
  bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
878
26.7M
    return hasProperty(MCID::UsesCustomInserter, Type);
879
26.7M
  }
880
881
  /// Return true if this instruction requires *adjustment*
882
  /// after instruction selection by calling a target hook. For example, this
883
  /// can be used to fill in ARM 's' optional operand depending on whether
884
  /// the conditional flag register is used.
885
0
  bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
886
0
    return hasProperty(MCID::HasPostISelHook, Type);
887
0
  }
888
889
  /// Returns true if this instruction is a candidate for remat.
890
  /// This flag is deprecated, please don't use it anymore.  If this
891
  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
892
  /// verify the instruction is really rematable.
893
0
  bool isRematerializable(QueryType Type = AllInBundle) const {
894
0
    // It's only possible to re-mat a bundle if all bundled instructions are
895
0
    // re-materializable.
896
0
    return hasProperty(MCID::Rematerializable, Type);
897
0
  }
898
899
  /// Returns true if this instruction has the same cost (or less) than a move
900
  /// instruction. This is useful during certain types of optimizations
901
  /// (e.g., remat during two-address conversion or machine licm)
902
  /// where we would like to remat or hoist the instruction, but not if it costs
903
  /// more than moving the instruction into the appropriate register. Note, we
904
  /// are not marking copies from and to the same register class with this flag.
905
3.57M
  bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
906
3.57M
    // Only returns true for a bundle if all bundled instructions are cheap.
907
3.57M
    return hasProperty(MCID::CheapAsAMove, Type);
908
3.57M
  }
909
910
  /// Returns true if this instruction source operands
911
  /// have special register allocation requirements that are not captured by the
912
  /// operand register classes. e.g. ARM::STRD's two source registers must be an
913
  /// even / odd pair, ARM::STM registers have to be in ascending order.
914
  /// Post-register allocation passes should not attempt to change allocations
915
  /// for sources of instructions with this flag.
916
16.7M
  bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
917
16.7M
    return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
918
16.7M
  }
919
920
  /// Returns true if this instruction def operands
921
  /// have special register allocation requirements that are not captured by the
922
  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
923
  /// even / odd pair, ARM::LDM registers have to be in ascending order.
924
  /// Post-register allocation passes should not attempt to change allocations
925
  /// for definitions of instructions with this flag.
926
7.24M
  bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
927
7.24M
    return hasProperty(MCID::ExtraDefRegAllocReq, Type);
928
7.24M
  }
929
930
  enum MICheckType {
931
    CheckDefs,      // Check all operands for equality
932
    CheckKillDead,  // Check all operands including kill / dead markers
933
    IgnoreDefs,     // Ignore all definitions
934
    IgnoreVRegDefs  // Ignore virtual register definitions
935
  };
936
937
  /// Return true if this instruction is identical to \p Other.
938
  /// Two instructions are identical if they have the same opcode and all their
939
  /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
940
  /// Note that this means liveness related flags (dead, undef, kill) do not
941
  /// affect the notion of identical.
942
  bool isIdenticalTo(const MachineInstr &Other,
943
                     MICheckType Check = CheckDefs) const;
944
945
  /// Unlink 'this' from the containing basic block, and return it without
946
  /// deleting it.
947
  ///
948
  /// This function can not be used on bundled instructions, use
949
  /// removeFromBundle() to remove individual instructions from a bundle.
950
  MachineInstr *removeFromParent();
951
952
  /// Unlink this instruction from its basic block and return it without
953
  /// deleting it.
954
  ///
955
  /// If the instruction is part of a bundle, the other instructions in the
956
  /// bundle remain bundled.
957
  MachineInstr *removeFromBundle();
958
959
  /// Unlink 'this' from the containing basic block and delete it.
960
  ///
961
  /// If this instruction is the header of a bundle, the whole bundle is erased.
962
  /// This function can not be used for instructions inside a bundle, use
963
  /// eraseFromBundle() to erase individual bundled instructions.
964
  void eraseFromParent();
965
966
  /// Unlink 'this' from the containing basic block and delete it.
967
  ///
968
  /// For all definitions mark their uses in DBG_VALUE nodes
969
  /// as undefined. Otherwise like eraseFromParent().
970
  void eraseFromParentAndMarkDBGValuesForRemoval();
971
972
  /// Unlink 'this' form its basic block and delete it.
973
  ///
974
  /// If the instruction is part of a bundle, the other instructions in the
975
  /// bundle remain bundled.
976
  void eraseFromBundle();
977
978
266M
  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
979
263M
  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
980
263M
  bool isAnnotationLabel() const {
981
263M
    return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
982
263M
  }
983
984
  /// Returns true if the MachineInstr represents a label.
985
264M
  bool isLabel() const {
986
264M
    return isEHLabel() || 
isGCLabel()263M
||
isAnnotationLabel()263M
;
987
264M
  }
988
989
310M
  bool isCFIInstruction() const {
990
310M
    return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
991
310M
  }
992
993
  // True if the instruction represents a position in the function.
994
264M
  bool isPosition() const { return isLabel() || 
isCFIInstruction()263M
; }
995
996
1.15G
  bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
997
987M
  bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
998
973M
  bool isDebugInstr() const { return isDebugValue() || 
isDebugLabel()973M
; }
999
1000
  /// A DBG_VALUE is indirect iff the first operand is a register and
1001
  /// the second operand is an immediate.
1002
4.83k
  bool isIndirectDebugValue() const {
1003
4.83k
    return isDebugValue()
1004
4.83k
      && 
getOperand(0).isReg()3.02k
1005
4.83k
      && 
getOperand(1).isImm()2.42k
;
1006
4.83k
  }
1007
1008
428M
  bool isPHI() const {
1009
428M
    return getOpcode() == TargetOpcode::PHI ||
1010
428M
           
getOpcode() == TargetOpcode::G_PHI410M
;
1011
428M
  }
1012
71.5M
  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1013
189M
  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1014
1.39G
  bool isInlineAsm() const {
1015
1.39G
    return getOpcode() == TargetOpcode::INLINEASM ||
1016
1.39G
           
getOpcode() == TargetOpcode::INLINEASM_BR1.39G
;
1017
1.39G
  }
1018
1019
0
  bool isMSInlineAsm() const {
1020
0
    return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel;
1021
0
  }
1022
1023
  bool isStackAligningInlineAsm() const;
1024
  InlineAsm::AsmDialect getInlineAsmDialect() const;
1025
1026
39.0M
  bool isInsertSubreg() const {
1027
39.0M
    return getOpcode() == TargetOpcode::INSERT_SUBREG;
1028
39.0M
  }
1029
1030
65.3M
  bool isSubregToReg() const {
1031
65.3M
    return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1032
65.3M
  }
1033
1034
47.6M
  bool isRegSequence() const {
1035
47.6M
    return getOpcode() == TargetOpcode::REG_SEQUENCE;
1036
47.6M
  }
1037
1038
57.9M
  bool isBundle() const {
1039
57.9M
    return getOpcode() == TargetOpcode::BUNDLE;
1040
57.9M
  }
1041
1042
555M
  bool isCopy() const {
1043
555M
    return getOpcode() == TargetOpcode::COPY;
1044
555M
  }
1045
1046
13.6M
  bool isFullCopy() const {
1047
13.6M
    return isCopy() && 
!getOperand(0).getSubReg()6.10M
&&
!getOperand(1).getSubReg()5.84M
;
1048
13.6M
  }
1049
1050
18.2M
  bool isExtractSubreg() const {
1051
18.2M
    return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1052
18.2M
  }
1053
1054
  /// Return true if the instruction behaves like a copy.
1055
  /// This does not include native copy instructions.
1056
64.0M
  bool isCopyLike() const {
1057
64.0M
    return isCopy() || 
isSubregToReg()42.4M
;
1058
64.0M
  }
1059
1060
  /// Return true is the instruction is an identity copy.
1061
48.4M
  bool isIdentityCopy() const {
1062
48.4M
    return isCopy() && 
getOperand(0).getReg() == getOperand(1).getReg()11.4M
&&
1063
48.4M
      
getOperand(0).getSubReg() == getOperand(1).getSubReg()2.62M
;
1064
48.4M
  }
1065
1066
  /// Return true if this instruction doesn't produce any output in the form of
1067
  /// executable instructions.
1068
82.7M
  bool isMetaInstruction() const {
1069
82.7M
    switch (getOpcode()) {
1070
82.7M
    default:
1071
80.1M
      return false;
1072
82.7M
    case TargetOpcode::IMPLICIT_DEF:
1073
2.53M
    case TargetOpcode::KILL:
1074
2.53M
    case TargetOpcode::CFI_INSTRUCTION:
1075
2.53M
    case TargetOpcode::EH_LABEL:
1076
2.53M
    case TargetOpcode::GC_LABEL:
1077
2.53M
    case TargetOpcode::DBG_VALUE:
1078
2.53M
    case TargetOpcode::DBG_LABEL:
1079
2.53M
    case TargetOpcode::LIFETIME_START:
1080
2.53M
    case TargetOpcode::LIFETIME_END:
1081
2.53M
      return true;
1082
82.7M
    }
1083
82.7M
  }
1084
1085
  /// Return true if this is a transient instruction that is either very likely
1086
  /// to be eliminated during register allocation (such as copy-like
1087
  /// instructions), or if this instruction doesn't have an execution-time cost.
1088
67.3M
  bool isTransient() const {
1089
67.3M
    switch (getOpcode()) {
1090
67.3M
    default:
1091
58.7M
      return isMetaInstruction();
1092
67.3M
    // Copy-like instructions are usually eliminated during register allocation.
1093
67.3M
    case TargetOpcode::PHI:
1094
8.54M
    case TargetOpcode::G_PHI:
1095
8.54M
    case TargetOpcode::COPY:
1096
8.54M
    case TargetOpcode::INSERT_SUBREG:
1097
8.54M
    case TargetOpcode::SUBREG_TO_REG:
1098
8.54M
    case TargetOpcode::REG_SEQUENCE:
1099
8.54M
      return true;
1100
67.3M
    }
1101
67.3M
  }
1102
1103
  /// Return the number of instructions inside the MI bundle, excluding the
1104
  /// bundle header.
1105
  ///
1106
  /// This is the number of instructions that MachineBasicBlock::iterator
1107
  /// skips, 0 for unbundled instructions.
1108
  unsigned getBundleSize() const;
1109
1110
  /// Return true if the MachineInstr reads the specified register.
1111
  /// If TargetRegisterInfo is passed, then it also checks if there
1112
  /// is a read of a super-register.
1113
  /// This does not count partial redefines of virtual registers as reads:
1114
  ///   %reg1024:6 = OP.
1115
  bool readsRegister(unsigned Reg,
1116
2.63M
                     const TargetRegisterInfo *TRI = nullptr) const {
1117
2.63M
    return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1118
2.63M
  }
1119
1120
  /// Return true if the MachineInstr reads the specified virtual register.
1121
  /// Take into account that a partial define is a
1122
  /// read-modify-write operation.
1123
4.58M
  bool readsVirtualRegister(unsigned Reg) const {
1124
4.58M
    return readsWritesVirtualRegister(Reg).first;
1125
4.58M
  }
1126
1127
  /// Return a pair of bools (reads, writes) indicating if this instruction
1128
  /// reads or writes Reg. This also considers partial defines.
1129
  /// If Ops is not null, all operand indices for Reg are added.
1130
  std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
1131
                                SmallVectorImpl<unsigned> *Ops = nullptr) const;
1132
1133
  /// Return true if the MachineInstr kills the specified register.
1134
  /// If TargetRegisterInfo is passed, then it also checks if there is
1135
  /// a kill of a super-register.
1136
  bool killsRegister(unsigned Reg,
1137
1.01M
                     const TargetRegisterInfo *TRI = nullptr) const {
1138
1.01M
    return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1139
1.01M
  }
1140
1141
  /// Return true if the MachineInstr fully defines the specified register.
1142
  /// If TargetRegisterInfo is passed, then it also checks
1143
  /// if there is a def of a super-register.
1144
  /// NOTE: It's ignoring subreg indices on virtual registers.
1145
  bool definesRegister(unsigned Reg,
1146
40.4M
                       const TargetRegisterInfo *TRI = nullptr) const {
1147
40.4M
    return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1148
40.4M
  }
1149
1150
  /// Return true if the MachineInstr modifies (fully define or partially
1151
  /// define) the specified register.
1152
  /// NOTE: It's ignoring subreg indices on virtual registers.
1153
24.0M
  bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
1154
24.0M
    return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1155
24.0M
  }
1156
1157
  /// Returns true if the register is dead in this machine instruction.
1158
  /// If TargetRegisterInfo is passed, then it also checks
1159
  /// if there is a dead def of a super-register.
1160
  bool registerDefIsDead(unsigned Reg,
1161
1.50M
                         const TargetRegisterInfo *TRI = nullptr) const {
1162
1.50M
    return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1163
1.50M
  }
1164
1165
  /// Returns true if the MachineInstr has an implicit-use operand of exactly
1166
  /// the given register (not considering sub/super-registers).
1167
  bool hasRegisterImplicitUseOperand(unsigned Reg) const;
1168
1169
  /// Returns the operand index that is a use of the specific register or -1
1170
  /// if it is not found. It further tightens the search criteria to a use
1171
  /// that kills the register if isKill is true.
1172
  int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
1173
                                const TargetRegisterInfo *TRI = nullptr) const;
1174
1175
  /// Wrapper for findRegisterUseOperandIdx, it returns
1176
  /// a pointer to the MachineOperand rather than an index.
1177
  MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
1178
71.1k
                                      const TargetRegisterInfo *TRI = nullptr) {
1179
71.1k
    int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1180
71.1k
    return (Idx == -1) ? 
nullptr24.4k
:
&getOperand(Idx)46.7k
;
1181
71.1k
  }
1182
1183
  const MachineOperand *findRegisterUseOperand(
1184
    unsigned Reg, bool isKill = false,
1185
5
    const TargetRegisterInfo *TRI = nullptr) const {
1186
5
    return const_cast<MachineInstr *>(this)->
1187
5
      findRegisterUseOperand(Reg, isKill, TRI);
1188
5
  }
1189
1190
  /// Returns the operand index that is a def of the specified register or
1191
  /// -1 if it is not found. If isDead is true, defs that are not dead are
1192
  /// skipped. If Overlap is true, then it also looks for defs that merely
1193
  /// overlap the specified register. If TargetRegisterInfo is non-null,
1194
  /// then it also checks if there is a def of a super-register.
1195
  /// This may also return a register mask operand when Overlap is true.
1196
  int findRegisterDefOperandIdx(unsigned Reg,
1197
                                bool isDead = false, bool Overlap = false,
1198
                                const TargetRegisterInfo *TRI = nullptr) const;
1199
1200
  /// Wrapper for findRegisterDefOperandIdx, it returns
1201
  /// a pointer to the MachineOperand rather than an index.
1202
  MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
1203
6.91M
                                      const TargetRegisterInfo *TRI = nullptr) {
1204
6.91M
    int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
1205
6.91M
    return (Idx == -1) ? 
nullptr1.31M
:
&getOperand(Idx)5.59M
;
1206
6.91M
  }
1207
1208
  /// Find the index of the first operand in the
1209
  /// operand list that is used to represent the predicate. It returns -1 if
1210
  /// none is found.
1211
  int findFirstPredOperandIdx() const;
1212
1213
  /// Find the index of the flag word operand that
1214
  /// corresponds to operand OpIdx on an inline asm instruction.  Returns -1 if
1215
  /// getOperand(OpIdx) does not belong to an inline asm operand group.
1216
  ///
1217
  /// If GroupNo is not NULL, it will receive the number of the operand group
1218
  /// containing OpIdx.
1219
  ///
1220
  /// The flag operand is an immediate that can be decoded with methods like
1221
  /// InlineAsm::hasRegClassConstraint().
1222
  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1223
1224
  /// Compute the static register class constraint for operand OpIdx.
1225
  /// For normal instructions, this is derived from the MCInstrDesc.
1226
  /// For inline assembly it is derived from the flag words.
1227
  ///
1228
  /// Returns NULL if the static register class constraint cannot be
1229
  /// determined.
1230
  const TargetRegisterClass*
1231
  getRegClassConstraint(unsigned OpIdx,
1232
                        const TargetInstrInfo *TII,
1233
                        const TargetRegisterInfo *TRI) const;
1234
1235
  /// Applies the constraints (def/use) implied by this MI on \p Reg to
1236
  /// the given \p CurRC.
1237
  /// If \p ExploreBundle is set and MI is part of a bundle, all the
1238
  /// instructions inside the bundle will be taken into account. In other words,
1239
  /// this method accumulates all the constraints of the operand of this MI and
1240
  /// the related bundle if MI is a bundle or inside a bundle.
1241
  ///
1242
  /// Returns the register class that satisfies both \p CurRC and the
1243
  /// constraints set by MI. Returns NULL if such a register class does not
1244
  /// exist.
1245
  ///
1246
  /// \pre CurRC must not be NULL.
1247
  const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1248
      unsigned Reg, const TargetRegisterClass *CurRC,
1249
      const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1250
      bool ExploreBundle = false) const;
1251
1252
  /// Applies the constraints (def/use) implied by the \p OpIdx operand
1253
  /// to the given \p CurRC.
1254
  ///
1255
  /// Returns the register class that satisfies both \p CurRC and the
1256
  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1257
  /// does not exist.
1258
  ///
1259
  /// \pre CurRC must not be NULL.
1260
  /// \pre The operand at \p OpIdx must be a register.
1261
  const TargetRegisterClass *
1262
  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1263
                              const TargetInstrInfo *TII,
1264
                              const TargetRegisterInfo *TRI) const;
1265
1266
  /// Add a tie between the register operands at DefIdx and UseIdx.
1267
  /// The tie will cause the register allocator to ensure that the two
1268
  /// operands are assigned the same physical register.
1269
  ///
1270
  /// Tied operands are managed automatically for explicit operands in the
1271
  /// MCInstrDesc. This method is for exceptional cases like inline asm.
1272
  void tieOperands(unsigned DefIdx, unsigned UseIdx);
1273
1274
  /// Given the index of a tied register operand, find the
1275
  /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1276
  /// index of the tied operand which must exist.
1277
  unsigned findTiedOperandIdx(unsigned OpIdx) const;
1278
1279
  /// Given the index of a register def operand,
1280
  /// check if the register def is tied to a source operand, due to either
1281
  /// two-address elimination or inline assembly constraints. Returns the
1282
  /// first tied use operand index by reference if UseOpIdx is not null.
1283
  bool isRegTiedToUseOperand(unsigned DefOpIdx,
1284
435k
                             unsigned *UseOpIdx = nullptr) const {
1285
435k
    const MachineOperand &MO = getOperand(DefOpIdx);
1286
435k
    if (!MO.isReg() || 
!MO.isDef()434k
||
!MO.isTied()422k
)
1287
375k
      return false;
1288
59.7k
    if (UseOpIdx)
1289
25.2k
      *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1290
59.7k
    return true;
1291
59.7k
  }
1292
1293
  /// Return true if the use operand of the specified index is tied to a def
1294
  /// operand. It also returns the def operand index by reference if DefOpIdx
1295
  /// is not null.
1296
  bool isRegTiedToDefOperand(unsigned UseOpIdx,
1297
144M
                             unsigned *DefOpIdx = nullptr) const {
1298
144M
    const MachineOperand &MO = getOperand(UseOpIdx);
1299
144M
    if (!MO.isReg() || 
!MO.isUse()120M
||
!MO.isTied()94.4M
)
1300
142M
      return false;
1301
1.57M
    if (DefOpIdx)
1302
1.56M
      *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1303
1.57M
    return true;
1304
1.57M
  }
1305
1306
  /// Clears kill flags on all operands.
1307
  void clearKillInfo();
1308
1309
  /// Replace all occurrences of FromReg with ToReg:SubIdx,
1310
  /// properly composing subreg indices where necessary.
1311
  void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1312
                          const TargetRegisterInfo &RegInfo);
1313
1314
  /// We have determined MI kills a register. Look for the
1315
  /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1316
  /// add a implicit operand if it's not found. Returns true if the operand
1317
  /// exists / is added.
1318
  bool addRegisterKilled(unsigned IncomingReg,
1319
                         const TargetRegisterInfo *RegInfo,
1320
                         bool AddIfNotFound = false);
1321
1322
  /// Clear all kill flags affecting Reg.  If RegInfo is provided, this includes
1323
  /// all aliasing registers.
1324
  void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1325
1326
  /// We have determined MI defined a register without a use.
1327
  /// Look for the operand that defines it and mark it as IsDead. If
1328
  /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1329
  /// true if the operand exists / is added.
1330
  bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1331
                       bool AddIfNotFound = false);
1332
1333
  /// Clear all dead flags on operands defining register @p Reg.
1334
  void clearRegisterDeads(unsigned Reg);
1335
1336
  /// Mark all subregister defs of register @p Reg with the undef flag.
1337
  /// This function is used when we determined to have a subregister def in an
1338
  /// otherwise undefined super register.
1339
  void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true);
1340
1341
  /// We have determined MI defines a register. Make sure there is an operand
1342
  /// defining Reg.
1343
  void addRegisterDefined(unsigned Reg,
1344
                          const TargetRegisterInfo *RegInfo = nullptr);
1345
1346
  /// Mark every physreg used by this instruction as
1347
  /// dead except those in the UsedRegs list.
1348
  ///
1349
  /// On instructions with register mask operands, also add implicit-def
1350
  /// operands for all registers in UsedRegs.
1351
  void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1352
                             const TargetRegisterInfo &TRI);
1353
1354
  /// Return true if it is safe to move this instruction. If
1355
  /// SawStore is set to true, it means that there is a store (or call) between
1356
  /// the instruction's location and its intended destination.
1357
  bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1358
1359
  /// Returns true if this instruction's memory access aliases the memory
1360
  /// access of Other.
1361
  //
1362
  /// Assumes any physical registers used to compute addresses
1363
  /// have the same value for both instructions.  Returns false if neither
1364
  /// instruction writes to memory.
1365
  ///
1366
  /// @param AA Optional alias analysis, used to compare memory operands.
1367
  /// @param Other MachineInstr to check aliasing against.
1368
  /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1369
  bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA);
1370
1371
  /// Return true if this instruction may have an ordered
1372
  /// or volatile memory reference, or if the information describing the memory
1373
  /// reference is not available. Return false if it is known to have no
1374
  /// ordered or volatile memory references.
1375
  bool hasOrderedMemoryRef() const;
1376
1377
  /// Return true if this load instruction never traps and points to a memory
1378
  /// location whose value doesn't change during the execution of this function.
1379
  ///
1380
  /// Examples include loading a value from the constant pool or from the
1381
  /// argument area of a function (if it does not change).  If the instruction
1382
  /// does multiple loads, this returns true only if all of the loads are
1383
  /// dereferenceable and invariant.
1384
  bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const;
1385
1386
  /// If the specified instruction is a PHI that always merges together the
1387
  /// same virtual register, return the register, otherwise return 0.
1388
  unsigned isConstantValuePHI() const;
1389
1390
  /// Return true if this instruction has side effects that are not modeled
1391
  /// by mayLoad / mayStore, etc.
1392
  /// For all instructions, the property is encoded in MCInstrDesc::Flags
1393
  /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1394
  /// INLINEASM instruction, in which case the side effect property is encoded
1395
  /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1396
  ///
1397
  bool hasUnmodeledSideEffects() const;
1398
1399
  /// Returns true if it is illegal to fold a load across this instruction.
1400
  bool isLoadFoldBarrier() const;
1401
1402
  /// Return true if all the defs of this instruction are dead.
1403
  bool allDefsAreDead() const;
1404
1405
  /// Return a valid size if the instruction is a spill instruction.
1406
  Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;
1407
1408
  /// Return a valid size if the instruction is a folded spill instruction.
1409
  Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;
1410
1411
  /// Return a valid size if the instruction is a restore instruction.
1412
  Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;
1413
1414
  /// Return a valid size if the instruction is a folded restore instruction.
1415
  Optional<unsigned>
1416
  getFoldedRestoreSize(const TargetInstrInfo *TII) const;
1417
1418
  /// Copy implicit register operands from specified
1419
  /// instruction to this instruction.
1420
  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1421
1422
  /// Debugging support
1423
  /// @{
1424
  /// Determine the generic type to be printed (if needed) on uses and defs.
1425
  LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1426
                     const MachineRegisterInfo &MRI) const;
1427
1428
  /// Return true when an instruction has tied register that can't be determined
1429
  /// by the instruction's descriptor. This is useful for MIR printing, to
1430
  /// determine whether we need to print the ties or not.
1431
  bool hasComplexRegisterTies() const;
1432
1433
  /// Print this MI to \p OS.
1434
  /// Don't print information that can be inferred from other instructions if
1435
  /// \p IsStandalone is false. It is usually true when only a fragment of the
1436
  /// function is printed.
1437
  /// Only print the defs and the opcode if \p SkipOpers is true.
1438
  /// Otherwise, also print operands if \p SkipDebugLoc is true.
1439
  /// Otherwise, also print the debug loc, with a terminating newline.
1440
  /// \p TII is used to print the opcode name.  If it's not present, but the
1441
  /// MI is in a function, the opcode will be printed using the function's TII.
1442
  void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1443
             bool SkipDebugLoc = false, bool AddNewLine = true,
1444
             const TargetInstrInfo *TII = nullptr) const;
1445
  void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1446
             bool SkipOpers = false, bool SkipDebugLoc = false,
1447
             bool AddNewLine = true,
1448
             const TargetInstrInfo *TII = nullptr) const;
1449
  void dump() const;
1450
  /// @}
1451
1452
  //===--------------------------------------------------------------------===//
1453
  // Accessors used to build up machine instructions.
1454
1455
  /// Add the specified operand to the instruction.  If it is an implicit
1456
  /// operand, it is added to the end of the operand list.  If it is an
1457
  /// explicit operand it is added at the end of the explicit operand list
1458
  /// (before the first implicit operand).
1459
  ///
1460
  /// MF must be the machine function that was used to allocate this
1461
  /// instruction.
1462
  ///
1463
  /// MachineInstrBuilder provides a more convenient interface for creating
1464
  /// instructions and adding operands.
1465
  void addOperand(MachineFunction &MF, const MachineOperand &Op);
1466
1467
  /// Add an operand without providing an MF reference. This only works for
1468
  /// instructions that are inserted in a basic block.
1469
  ///
1470
  /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1471
  /// preferred.
1472
  void addOperand(const MachineOperand &Op);
1473
1474
  /// Replace the instruction descriptor (thus opcode) of
1475
  /// the current instruction with a new one.
1476
6.84M
  void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1477
1478
  /// Replace current source information with new such.
1479
  /// Avoid using this, the constructor argument is preferable.
1480
5.04M
  void setDebugLoc(DebugLoc dl) {
1481
5.04M
    debugLoc = std::move(dl);
1482
5.04M
    assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1483
5.04M
  }
1484
1485
  /// Erase an operand from an instruction, leaving it with one
1486
  /// fewer operand than it started with.
1487
  void RemoveOperand(unsigned OpNo);
1488
1489
  /// Clear this MachineInstr's memory reference descriptor list.  This resets
1490
  /// the memrefs to their most conservative state.  This should be used only
1491
  /// as a last resort since it greatly pessimizes our knowledge of the memory
1492
  /// access performed by the instruction.
1493
  void dropMemRefs(MachineFunction &MF);
1494
1495
  /// Assign this MachineInstr's memory reference descriptor list.
1496
  ///
1497
  /// Unlike other methods, this *will* allocate them into a new array
1498
  /// associated with the provided `MachineFunction`.
1499
  void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs);
1500
1501
  /// Add a MachineMemOperand to the machine instruction.
1502
  /// This function should be used only occasionally. The setMemRefs function
1503
  /// is the primary method for setting up a MachineInstr's MemRefs list.
1504
  void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1505
1506
  /// Clone another MachineInstr's memory reference descriptor list and replace
1507
  /// ours with it.
1508
  ///
1509
  /// Note that `*this` may be the incoming MI!
1510
  ///
1511
  /// Prefer this API whenever possible as it can avoid allocations in common
1512
  /// cases.
1513
  void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1514
1515
  /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1516
  /// list and replace ours with it.
1517
  ///
1518
  /// Note that `*this` may be one of the incoming MIs!
1519
  ///
1520
  /// Prefer this API whenever possible as it can avoid allocations in common
1521
  /// cases.
1522
  void cloneMergedMemRefs(MachineFunction &MF,
1523
                          ArrayRef<const MachineInstr *> MIs);
1524
1525
  /// Set a symbol that will be emitted just prior to the instruction itself.
1526
  ///
1527
  /// Setting this to a null pointer will remove any such symbol.
1528
  ///
1529
  /// FIXME: This is not fully implemented yet.
1530
  void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1531
1532
  /// Set a symbol that will be emitted just after the instruction itself.
1533
  ///
1534
  /// Setting this to a null pointer will remove any such symbol.
1535
  ///
1536
  /// FIXME: This is not fully implemented yet.
1537
  void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1538
1539
  /// Return the MIFlags which represent both MachineInstrs. This
1540
  /// should be used when merging two MachineInstrs into one. This routine does
1541
  /// not modify the MIFlags of this MachineInstr.
1542
  uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1543
1544
  static uint16_t copyFlagsFromInstruction(const Instruction &I);
1545
1546
  /// Copy all flags to MachineInst MIFlags
1547
  void copyIRFlags(const Instruction &I);
1548
1549
  /// Break any tie involving OpIdx.
1550
1.42M
  void untieRegOperand(unsigned OpIdx) {
1551
1.42M
    MachineOperand &MO = getOperand(OpIdx);
1552
1.42M
    if (MO.isReg() && 
MO.isTied()1.29M
) {
1553
172k
      getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1554
172k
      MO.TiedTo = 0;
1555
172k
    }
1556
1.42M
  }
1557
1558
  /// Add all implicit def and use operands to this instruction.
1559
  void addImplicitDefUseOperands(MachineFunction &MF);
1560
1561
  /// Scan instructions following MI and collect any matching DBG_VALUEs.
1562
  void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);
1563
1564
  /// Find all DBG_VALUEs immediately following this instruction that point
1565
  /// to a register def in this instruction and point them to \p Reg instead.
1566
  void changeDebugValuesDefReg(unsigned Reg);
1567
1568
private:
1569
  /// If this instruction is embedded into a MachineFunction, return the
1570
  /// MachineRegisterInfo object for the current function, otherwise
1571
  /// return null.
1572
  MachineRegisterInfo *getRegInfo();
1573
1574
  /// Unlink all of the register operands in this instruction from their
1575
  /// respective use lists.  This requires that the operands already be on their
1576
  /// use lists.
1577
  void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1578
1579
  /// Add all of the register operands in this instruction from their
1580
  /// respective use lists.  This requires that the operands not be on their
1581
  /// use lists yet.
1582
  void AddRegOperandsToUseLists(MachineRegisterInfo&);
1583
1584
  /// Slow path for hasProperty when we're dealing with a bundle.
1585
  bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1586
1587
  /// Implements the logic of getRegClassConstraintEffectForVReg for the
1588
  /// this MI and the given operand index \p OpIdx.
1589
  /// If the related operand does not constrained Reg, this returns CurRC.
1590
  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1591
      unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1592
      const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1593
};
1594
1595
/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1596
/// instruction rather than by pointer value.
1597
/// The hashing and equality testing functions ignore definitions so this is
1598
/// useful for CSE, etc.
1599
struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1600
245M
  static inline MachineInstr *getEmptyKey() {
1601
245M
    return nullptr;
1602
245M
  }
1603
1604
149M
  static inline MachineInstr *getTombstoneKey() {
1605
149M
    return reinterpret_cast<MachineInstr*>(-1);
1606
149M
  }
1607
1608
  static unsigned getHashValue(const MachineInstr* const &MI);
1609
1610
  static bool isEqual(const MachineInstr* const &LHS,
1611
187M
                      const MachineInstr* const &RHS) {
1612
187M
    if (RHS == getEmptyKey() || 
RHS == getTombstoneKey()93.1M
||
1613
187M
        
LHS == getEmptyKey()22.8M
||
LHS == getTombstoneKey()22.8M
)
1614
164M
      return LHS == RHS;
1615
22.8M
    return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1616
22.8M
  }
1617
};
1618
1619
//===----------------------------------------------------------------------===//
1620
// Debugging Support
1621
1622
1
inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1623
1
  MI.print(OS);
1624
1
  return OS;
1625
1
}
1626
1627
} // end namespace llvm
1628
1629
#endif // LLVM_CODEGEN_MACHINEINSTR_H