Coverage Report

Created: 2019-02-21 13:17

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/MachineOperand.h
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//===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the declaration of the MachineOperand class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEOPERAND_H
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#define LLVM_CODEGEN_MACHINEOPERAND_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/LowLevelTypeImpl.h"
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#include <cassert>
21
22
namespace llvm {
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24
class BlockAddress;
25
class ConstantFP;
26
class ConstantInt;
27
class GlobalValue;
28
class MachineBasicBlock;
29
class MachineInstr;
30
class MachineRegisterInfo;
31
class MCCFIInstruction;
32
class MDNode;
33
class ModuleSlotTracker;
34
class TargetMachine;
35
class TargetIntrinsicInfo;
36
class TargetRegisterInfo;
37
class hash_code;
38
class raw_ostream;
39
class MCSymbol;
40
41
/// MachineOperand class - Representation of each machine instruction operand.
42
///
43
/// This class isn't a POD type because it has a private constructor, but its
44
/// destructor must be trivial. Functions like MachineInstr::addOperand(),
45
/// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
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/// not having to call the MachineOperand destructor.
47
///
48
class MachineOperand {
49
public:
50
  enum MachineOperandType : unsigned char {
51
    MO_Register,          ///< Register operand.
52
    MO_Immediate,         ///< Immediate operand
53
    MO_CImmediate,        ///< Immediate >64bit operand
54
    MO_FPImmediate,       ///< Floating-point immediate operand
55
    MO_MachineBasicBlock, ///< MachineBasicBlock reference
56
    MO_FrameIndex,        ///< Abstract Stack Frame Index
57
    MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
58
    MO_TargetIndex,       ///< Target-dependent index+offset operand.
59
    MO_JumpTableIndex,    ///< Address of indexed Jump Table for switch
60
    MO_ExternalSymbol,    ///< Name of external global symbol
61
    MO_GlobalAddress,     ///< Address of a global value
62
    MO_BlockAddress,      ///< Address of a basic block
63
    MO_RegisterMask,      ///< Mask of preserved registers.
64
    MO_RegisterLiveOut,   ///< Mask of live-out registers.
65
    MO_Metadata,          ///< Metadata reference (for debug info)
66
    MO_MCSymbol,          ///< MCSymbol reference (for debug/eh info)
67
    MO_CFIIndex,          ///< MCCFIInstruction index.
68
    MO_IntrinsicID,       ///< Intrinsic ID for ISel
69
    MO_Predicate,         ///< Generic predicate for ISel
70
    MO_Last = MO_Predicate,
71
  };
72
73
private:
74
  /// OpKind - Specify what kind of operand this is.  This discriminates the
75
  /// union.
76
  unsigned OpKind : 8;
77
78
  /// Subregister number for MO_Register.  A value of 0 indicates the
79
  /// MO_Register has no subReg.
80
  ///
81
  /// For all other kinds of operands, this field holds target-specific flags.
82
  unsigned SubReg_TargetFlags : 12;
83
84
  /// TiedTo - Non-zero when this register operand is tied to another register
85
  /// operand. The encoding of this field is described in the block comment
86
  /// before MachineInstr::tieOperands().
87
  unsigned TiedTo : 4;
88
89
  /// IsDef - True if this is a def, false if this is a use of the register.
90
  /// This is only valid on register operands.
91
  ///
92
  unsigned IsDef : 1;
93
94
  /// IsImp - True if this is an implicit def or use, false if it is explicit.
95
  /// This is only valid on register opderands.
96
  ///
97
  unsigned IsImp : 1;
98
99
  /// IsDeadOrKill
100
  /// For uses: IsKill - True if this instruction is the last use of the
101
  /// register on this path through the function.
102
  /// For defs: IsDead - True if this register is never used by a subsequent
103
  /// instruction.
104
  /// This is only valid on register operands.
105
  unsigned IsDeadOrKill : 1;
106
107
  /// See isRenamable().
108
  unsigned IsRenamable : 1;
109
110
  /// IsUndef - True if this register operand reads an "undef" value, i.e. the
111
  /// read value doesn't matter.  This flag can be set on both use and def
112
  /// operands.  On a sub-register def operand, it refers to the part of the
113
  /// register that isn't written.  On a full-register def operand, it is a
114
  /// noop.  See readsReg().
115
  ///
116
  /// This is only valid on registers.
117
  ///
118
  /// Note that an instruction may have multiple <undef> operands referring to
119
  /// the same register.  In that case, the instruction may depend on those
120
  /// operands reading the same dont-care value.  For example:
121
  ///
122
  ///   %1 = XOR undef %2, undef %2
123
  ///
124
  /// Any register can be used for %2, and its value doesn't matter, but
125
  /// the two operands must be the same register.
126
  ///
127
  unsigned IsUndef : 1;
128
129
  /// IsInternalRead - True if this operand reads a value that was defined
130
  /// inside the same instruction or bundle.  This flag can be set on both use
131
  /// and def operands.  On a sub-register def operand, it refers to the part
132
  /// of the register that isn't written.  On a full-register def operand, it
133
  /// is a noop.
134
  ///
135
  /// When this flag is set, the instruction bundle must contain at least one
136
  /// other def of the register.  If multiple instructions in the bundle define
137
  /// the register, the meaning is target-defined.
138
  unsigned IsInternalRead : 1;
139
140
  /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
141
  /// by the MachineInstr before all input registers are read.  This is used to
142
  /// model the GCC inline asm '&' constraint modifier.
143
  unsigned IsEarlyClobber : 1;
144
145
  /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
146
  /// not a real instruction.  Such uses should be ignored during codegen.
147
  unsigned IsDebug : 1;
148
149
  /// SmallContents - This really should be part of the Contents union, but
150
  /// lives out here so we can get a better packed struct.
151
  /// MO_Register: Register number.
152
  /// OffsetedInfo: Low bits of offset.
153
  union {
154
    unsigned RegNo;           // For MO_Register.
155
    unsigned OffsetLo;        // Matches Contents.OffsetedInfo.OffsetHi.
156
  } SmallContents;
157
158
  /// ParentMI - This is the instruction that this operand is embedded into.
159
  /// This is valid for all operand types, when the operand is in an instr.
160
  MachineInstr *ParentMI;
161
162
  /// Contents union - This contains the payload for the various operand types.
163
  union {
164
    MachineBasicBlock *MBB;  // For MO_MachineBasicBlock.
165
    const ConstantFP *CFP;   // For MO_FPImmediate.
166
    const ConstantInt *CI;   // For MO_CImmediate. Integers > 64bit.
167
    int64_t ImmVal;          // For MO_Immediate.
168
    const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
169
    const MDNode *MD;        // For MO_Metadata.
170
    MCSymbol *Sym;           // For MO_MCSymbol.
171
    unsigned CFIIndex;       // For MO_CFI.
172
    Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
173
    unsigned Pred;           // For MO_Predicate
174
175
    struct {                  // For MO_Register.
176
      // Register number is in SmallContents.RegNo.
177
      MachineOperand *Prev;   // Access list for register. See MRI.
178
      MachineOperand *Next;
179
    } Reg;
180
181
    /// OffsetedInfo - This struct contains the offset and an object identifier.
182
    /// this represent the object as with an optional offset from it.
183
    struct {
184
      union {
185
        int Index;                // For MO_*Index - The index itself.
186
        const char *SymbolName;   // For MO_ExternalSymbol.
187
        const GlobalValue *GV;    // For MO_GlobalAddress.
188
        const BlockAddress *BA;   // For MO_BlockAddress.
189
      } Val;
190
      // Low bits of offset are in SmallContents.OffsetLo.
191
      int OffsetHi;               // An offset from the object, high 32 bits.
192
    } OffsetedInfo;
193
  } Contents;
194
195
  explicit MachineOperand(MachineOperandType K)
196
223M
    : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {
197
223M
    // Assert that the layout is what we expect. It's easy to grow this object.
198
223M
    static_assert(alignof(MachineOperand) <= alignof(int64_t),
199
223M
                  "MachineOperand shouldn't be more than 8 byte aligned");
200
223M
    static_assert(sizeof(Contents) <= 2 * sizeof(void *),
201
223M
                  "Contents should be at most two pointers");
202
223M
    static_assert(sizeof(MachineOperand) <=
203
223M
                      alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
204
223M
                                                3 * sizeof(void *)),
205
223M
                  "MachineOperand too big. Should be Kind, SmallContents, "
206
223M
                  "ParentMI, and Contents");
207
223M
  }
208
209
public:
210
  /// getType - Returns the MachineOperandType for this operand.
211
  ///
212
693M
  MachineOperandType getType() const { return (MachineOperandType)OpKind; }
213
214
241M
  unsigned getTargetFlags() const {
215
241M
    return isReg() ? 
0132M
:
SubReg_TargetFlags109M
;
216
241M
  }
217
19.7M
  void setTargetFlags(unsigned F) {
218
19.7M
    assert(!isReg() && "Register operands can't have target flags");
219
19.7M
    SubReg_TargetFlags = F;
220
19.7M
    assert(SubReg_TargetFlags == F && "Target flags out of range");
221
19.7M
  }
222
1
  void addTargetFlag(unsigned F) {
223
1
    assert(!isReg() && "Register operands can't have target flags");
224
1
    SubReg_TargetFlags |= F;
225
1
    assert((SubReg_TargetFlags & F) && "Target flags out of range");
226
1
  }
227
228
229
  /// getParent - Return the instruction that this operand belongs to.
230
  ///
231
349M
  MachineInstr *getParent() { return ParentMI; }
232
388M
  const MachineInstr *getParent() const { return ParentMI; }
233
234
  /// clearParent - Reset the parent pointer.
235
  ///
236
  /// The MachineOperand copy constructor also copies ParentMI, expecting the
237
  /// original to be deleted. If a MachineOperand is ever stored outside a
238
  /// MachineInstr, the parent pointer must be cleared.
239
  ///
240
  /// Never call clearParent() on an operand in a MachineInstr.
241
  ///
242
800
  void clearParent() { ParentMI = nullptr; }
243
244
  /// Print a subreg index operand.
245
  /// MO_Immediate operands can also be subreg idices. If it's the case, the
246
  /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
247
  /// called to check this.
248
  static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
249
                             const TargetRegisterInfo *TRI);
250
251
  /// Print operand target flags.
252
  static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
253
254
  /// Print a MCSymbol as an operand.
255
  static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
256
257
  /// Print a stack object reference.
258
  static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
259
                                        bool IsFixed, StringRef Name);
260
261
  /// Print the offset with explicit +/- signs.
262
  static void printOperandOffset(raw_ostream &OS, int64_t Offset);
263
264
  /// Print an IRSlotNumber.
265
  static void printIRSlotNumber(raw_ostream &OS, int Slot);
266
267
  /// Print the MachineOperand to \p os.
268
  /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
269
  /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
270
  /// function will try to pick it up from the parent.
271
  void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
272
             const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
273
274
  /// More complex way of printing a MachineOperand.
275
  /// \param TypeToPrint specifies the generic type to be printed on uses and
276
  /// defs. It can be determined using MachineInstr::getTypeToPrint.
277
  /// \param PrintDef - whether we want to print `def` on an operand which
278
  /// isDef. Sometimes, if the operand is printed before '=', we don't print
279
  /// `def`.
280
  /// \param IsStandalone - whether we want a verbose output of the MO. This
281
  /// prints extra information that can be easily inferred when printing the
282
  /// whole function, but not when printing only a fragment of it.
283
  /// \param ShouldPrintRegisterTies - whether we want to print register ties.
284
  /// Sometimes they are easily determined by the instruction's descriptor
285
  /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
286
  /// \param TiedOperandIdx - if we need to print register ties this needs to
287
  /// provide the index of the tied register. If not, it will be ignored.
288
  /// \param TRI - provide more target-specific information to the printer.
289
  /// Unlike the previous function, this one will not try and get the
290
  /// information from it's parent.
291
  /// \param IntrinsicInfo - same as \p TRI.
292
  void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
293
             bool PrintDef, bool IsStandalone, bool ShouldPrintRegisterTies,
294
             unsigned TiedOperandIdx, const TargetRegisterInfo *TRI,
295
             const TargetIntrinsicInfo *IntrinsicInfo) const;
296
297
  /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level
298
  /// type to be printed the same way the full version of print(...) does it.
299
  void print(raw_ostream &os, LLT TypeToPrint,
300
             const TargetRegisterInfo *TRI = nullptr,
301
             const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
302
303
  void dump() const;
304
305
  //===--------------------------------------------------------------------===//
306
  // Accessors that tell you what kind of MachineOperand you're looking at.
307
  //===--------------------------------------------------------------------===//
308
309
  /// isReg - Tests if this is a MO_Register operand.
310
4.43G
  bool isReg() const { return OpKind == MO_Register; }
311
  /// isImm - Tests if this is a MO_Immediate operand.
312
103M
  bool isImm() const { return OpKind == MO_Immediate; }
313
  /// isCImm - Test if this is a MO_CImmediate operand.
314
10.0M
  bool isCImm() const { return OpKind == MO_CImmediate; }
315
  /// isFPImm - Tests if this is a MO_FPImmediate operand.
316
44.7M
  bool isFPImm() const { return OpKind == MO_FPImmediate; }
317
  /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
318
11.2M
  bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
319
  /// isFI - Tests if this is a MO_FrameIndex operand.
320
369M
  bool isFI() const { return OpKind == MO_FrameIndex; }
321
  /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
322
4.99M
  bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
323
  /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
324
5.02k
  bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
325
  /// isJTI - Tests if this is a MO_JumpTableIndex operand.
326
24.5M
  bool isJTI() const { return OpKind == MO_JumpTableIndex; }
327
  /// isGlobal - Tests if this is a MO_GlobalAddress operand.
328
2.01M
  bool isGlobal() const { return OpKind == MO_GlobalAddress; }
329
  /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
330
1.00M
  bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
331
  /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
332
569k
  bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
333
  /// isRegMask - Tests if this is a MO_RegisterMask operand.
334
882M
  bool isRegMask() const { return OpKind == MO_RegisterMask; }
335
  /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
336
446
  bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
337
  /// isMetadata - Tests if this is a MO_Metadata operand.
338
125k
  bool isMetadata() const { return OpKind == MO_Metadata; }
339
24.0k
  bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
340
5.06k
  bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
341
171k
  bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
342
1
  bool isPredicate() const { return OpKind == MO_Predicate; }
343
  //===--------------------------------------------------------------------===//
344
  // Accessors for Register Operands
345
  //===--------------------------------------------------------------------===//
346
347
  /// getReg - Returns the register number.
348
3.10G
  unsigned getReg() const {
349
3.10G
    assert(isReg() && "This is not a register operand!");
350
3.10G
    return SmallContents.RegNo;
351
3.10G
  }
352
353
608M
  unsigned getSubReg() const {
354
608M
    assert(isReg() && "Wrong MachineOperand accessor");
355
608M
    return SubReg_TargetFlags;
356
608M
  }
357
358
1.45G
  bool isUse() const {
359
1.45G
    assert(isReg() && "Wrong MachineOperand accessor");
360
1.45G
    return !IsDef;
361
1.45G
  }
362
363
2.12G
  bool isDef() const {
364
2.12G
    assert(isReg() && "Wrong MachineOperand accessor");
365
2.12G
    return IsDef;
366
2.12G
  }
367
368
483M
  bool isImplicit() const {
369
483M
    assert(isReg() && "Wrong MachineOperand accessor");
370
483M
    return IsImp;
371
483M
  }
372
373
119M
  bool isDead() const {
374
119M
    assert(isReg() && "Wrong MachineOperand accessor");
375
119M
    return IsDeadOrKill & IsDef;
376
119M
  }
377
378
170M
  bool isKill() const {
379
170M
    assert(isReg() && "Wrong MachineOperand accessor");
380
170M
    return IsDeadOrKill & !IsDef;
381
170M
  }
382
383
601M
  bool isUndef() const {
384
601M
    assert(isReg() && "Wrong MachineOperand accessor");
385
601M
    return IsUndef;
386
601M
  }
387
388
  /// isRenamable - Returns true if this register may be renamed, i.e. it does
389
  /// not generate a value that is somehow read in a way that is not represented
390
  /// by the Machine IR (e.g. to meet an ABI or ISA requirement).  This is only
391
  /// valid on physical register operands.  Virtual registers are assumed to
392
  /// always be renamable regardless of the value of this field.
393
  ///
394
  /// Operands that are renamable can freely be changed to any other register
395
  /// that is a member of the register class returned by
396
  /// MI->getRegClassConstraint().
397
  ///
398
  /// isRenamable can return false for several different reasons:
399
  ///
400
  /// - ABI constraints (since liveness is not always precisely modeled).  We
401
  ///   conservatively handle these cases by setting all physical register
402
  ///   operands that didn’t start out as virtual regs to not be renamable.
403
  ///   Also any physical register operands created after register allocation or
404
  ///   whose register is changed after register allocation will not be
405
  ///   renamable.  This state is tracked in the MachineOperand::IsRenamable
406
  ///   bit.
407
  ///
408
  /// - Opcode/target constraints: for opcodes that have complex register class
409
  ///   requirements (e.g. that depend on other operands/instructions), we set
410
  ///   hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
411
  ///   description.  Operands belonging to instructions with opcodes that are
412
  ///   marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
413
  ///   isRenamable().  Additionally, the AllowRegisterRenaming target property
414
  ///   prevents any operands from being marked renamable for targets that don't
415
  ///   have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
416
  ///   values.
417
  bool isRenamable() const;
418
419
377M
  bool isInternalRead() const {
420
377M
    assert(isReg() && "Wrong MachineOperand accessor");
421
377M
    return IsInternalRead;
422
377M
  }
423
424
144M
  bool isEarlyClobber() const {
425
144M
    assert(isReg() && "Wrong MachineOperand accessor");
426
144M
    return IsEarlyClobber;
427
144M
  }
428
429
241M
  bool isTied() const {
430
241M
    assert(isReg() && "Wrong MachineOperand accessor");
431
241M
    return TiedTo;
432
241M
  }
433
434
512M
  bool isDebug() const {
435
512M
    assert(isReg() && "Wrong MachineOperand accessor");
436
512M
    return IsDebug;
437
512M
  }
438
439
  /// readsReg - Returns true if this operand reads the previous value of its
440
  /// register.  A use operand with the <undef> flag set doesn't read its
441
  /// register.  A sub-register def implicitly reads the other parts of the
442
  /// register being redefined unless the <undef> flag is set.
443
  ///
444
  /// This refers to reading the register value from before the current
445
  /// instruction or bundle. Internal bundle reads are not included.
446
352M
  bool readsReg() const {
447
352M
    assert(isReg() && "Wrong MachineOperand accessor");
448
352M
    return !isUndef() && 
!isInternalRead()347M
&&
(347M
isUse()347M
||
getSubReg()103M
);
449
352M
  }
450
451
  //===--------------------------------------------------------------------===//
452
  // Mutators for Register Operands
453
  //===--------------------------------------------------------------------===//
454
455
  /// Change the register this operand corresponds to.
456
  ///
457
  void setReg(unsigned Reg);
458
459
134M
  void setSubReg(unsigned subReg) {
460
134M
    assert(isReg() && "Wrong MachineOperand mutator");
461
134M
    SubReg_TargetFlags = subReg;
462
134M
    assert(SubReg_TargetFlags == subReg && "SubReg out of range");
463
134M
  }
464
465
  /// substVirtReg - Substitute the current register with the virtual
466
  /// subregister Reg:SubReg. Take any existing SubReg index into account,
467
  /// using TargetRegisterInfo to compose the subreg indices if necessary.
468
  /// Reg must be a virtual register, SubIdx can be 0.
469
  ///
470
  void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&);
471
472
  /// substPhysReg - Substitute the current register with the physical register
473
  /// Reg, taking any existing SubReg into account. For instance,
474
  /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
475
  ///
476
  void substPhysReg(unsigned Reg, const TargetRegisterInfo&);
477
478
660
  void setIsUse(bool Val = true) { setIsDef(!Val); }
479
480
  /// Change a def to a use, or a use to a def.
481
  void setIsDef(bool Val = true);
482
483
14.2k
  void setImplicit(bool Val = true) {
484
14.2k
    assert(isReg() && "Wrong MachineOperand mutator");
485
14.2k
    IsImp = Val;
486
14.2k
  }
487
488
107M
  void setIsKill(bool Val = true) {
489
107M
    assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
490
107M
    assert((!Val || !isDebug()) && "Marking a debug operation as kill");
491
107M
    IsDeadOrKill = Val;
492
107M
  }
493
494
14.5M
  void setIsDead(bool Val = true) {
495
14.5M
    assert(isReg() && IsDef && "Wrong MachineOperand mutator");
496
14.5M
    IsDeadOrKill = Val;
497
14.5M
  }
498
499
3.71M
  void setIsUndef(bool Val = true) {
500
3.71M
    assert(isReg() && "Wrong MachineOperand mutator");
501
3.71M
    IsUndef = Val;
502
3.71M
  }
503
504
  void setIsRenamable(bool Val = true);
505
506
2.08M
  void setIsInternalRead(bool Val = true) {
507
2.08M
    assert(isReg() && "Wrong MachineOperand mutator");
508
2.08M
    IsInternalRead = Val;
509
2.08M
  }
510
511
402k
  void setIsEarlyClobber(bool Val = true) {
512
402k
    assert(isReg() && IsDef && "Wrong MachineOperand mutator");
513
402k
    IsEarlyClobber = Val;
514
402k
  }
515
516
731
  void setIsDebug(bool Val = true) {
517
731
    assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
518
731
    IsDebug = Val;
519
731
  }
520
521
  //===--------------------------------------------------------------------===//
522
  // Accessors for various operand types.
523
  //===--------------------------------------------------------------------===//
524
525
222M
  int64_t getImm() const {
526
222M
    assert(isImm() && "Wrong MachineOperand accessor");
527
222M
    return Contents.ImmVal;
528
222M
  }
529
530
12.0M
  const ConstantInt *getCImm() const {
531
12.0M
    assert(isCImm() && "Wrong MachineOperand accessor");
532
12.0M
    return Contents.CI;
533
12.0M
  }
534
535
186k
  const ConstantFP *getFPImm() const {
536
186k
    assert(isFPImm() && "Wrong MachineOperand accessor");
537
186k
    return Contents.CFP;
538
186k
  }
539
540
100M
  MachineBasicBlock *getMBB() const {
541
100M
    assert(isMBB() && "Wrong MachineOperand accessor");
542
100M
    return Contents.MBB;
543
100M
  }
544
545
10.6M
  int getIndex() const {
546
10.6M
    assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
547
10.6M
           "Wrong MachineOperand accessor");
548
10.6M
    return Contents.OffsetedInfo.Val.Index;
549
10.6M
  }
550
551
16.9M
  const GlobalValue *getGlobal() const {
552
16.9M
    assert(isGlobal() && "Wrong MachineOperand accessor");
553
16.9M
    return Contents.OffsetedInfo.Val.GV;
554
16.9M
  }
555
556
927
  const BlockAddress *getBlockAddress() const {
557
927
    assert(isBlockAddress() && "Wrong MachineOperand accessor");
558
927
    return Contents.OffsetedInfo.Val.BA;
559
927
  }
560
561
460k
  MCSymbol *getMCSymbol() const {
562
460k
    assert(isMCSymbol() && "Wrong MachineOperand accessor");
563
460k
    return Contents.Sym;
564
460k
  }
565
566
447k
  unsigned getCFIIndex() const {
567
447k
    assert(isCFIIndex() && "Wrong MachineOperand accessor");
568
447k
    return Contents.CFIIndex;
569
447k
  }
570
571
163k
  Intrinsic::ID getIntrinsicID() const {
572
163k
    assert(isIntrinsicID() && "Wrong MachineOperand accessor");
573
163k
    return Contents.IntrinsicID;
574
163k
  }
575
576
869k
  unsigned getPredicate() const {
577
869k
    assert(isPredicate() && "Wrong MachineOperand accessor");
578
869k
    return Contents.Pred;
579
869k
  }
580
581
  /// Return the offset from the symbol in this operand. This always returns 0
582
  /// for ExternalSymbol operands.
583
14.8M
  int64_t getOffset() const {
584
14.8M
    assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
585
14.8M
            isTargetIndex() || isBlockAddress()) &&
586
14.8M
           "Wrong MachineOperand accessor");
587
14.8M
    return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
588
14.8M
           SmallContents.OffsetLo;
589
14.8M
  }
590
591
282k
  const char *getSymbolName() const {
592
282k
    assert(isSymbol() && "Wrong MachineOperand accessor");
593
282k
    return Contents.OffsetedInfo.Val.SymbolName;
594
282k
  }
595
596
  /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
597
  /// It is sometimes necessary to detach the register mask pointer from its
598
  /// machine operand. This static method can be used for such detached bit
599
  /// mask pointers.
600
410M
  static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
601
410M
    // See TargetRegisterInfo.h.
602
410M
    assert(PhysReg < (1u << 30) && "Not a physical register");
603
410M
    return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
604
410M
  }
605
606
  /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
607
100M
  bool clobbersPhysReg(unsigned PhysReg) const {
608
100M
     return clobbersPhysReg(getRegMask(), PhysReg);
609
100M
  }
610
611
  /// getRegMask - Returns a bit mask of registers preserved by this RegMask
612
  /// operand.
613
118M
  const uint32_t *getRegMask() const {
614
118M
    assert(isRegMask() && "Wrong MachineOperand accessor");
615
118M
    return Contents.RegMask;
616
118M
  }
617
618
  /// Returns number of elements needed for a regmask array.
619
21.3k
  static unsigned getRegMaskSize(unsigned NumRegs) {
620
21.3k
    return (NumRegs + 31) / 32;
621
21.3k
  }
622
623
  /// getRegLiveOut - Returns a bit mask of live-out registers.
624
181
  const uint32_t *getRegLiveOut() const {
625
181
    assert(isRegLiveOut() && "Wrong MachineOperand accessor");
626
181
    return Contents.RegMask;
627
181
  }
628
629
26.0k
  const MDNode *getMetadata() const {
630
26.0k
    assert(isMetadata() && "Wrong MachineOperand accessor");
631
26.0k
    return Contents.MD;
632
26.0k
  }
633
634
  //===--------------------------------------------------------------------===//
635
  // Mutators for various operand types.
636
  //===--------------------------------------------------------------------===//
637
638
73.0M
  void setImm(int64_t immVal) {
639
73.0M
    assert(isImm() && "Wrong MachineOperand mutator");
640
73.0M
    Contents.ImmVal = immVal;
641
73.0M
  }
642
643
180k
  void setCImm(const ConstantInt *CI) {
644
180k
    assert(isCImm() && "Wrong MachineOperand mutator");
645
180k
    Contents.CI = CI;
646
180k
  }
647
648
6
  void setFPImm(const ConstantFP *CFP) {
649
6
    assert(isFPImm() && "Wrong MachineOperand mutator");
650
6
    Contents.CFP = CFP;
651
6
  }
652
653
3.74M
  void setOffset(int64_t Offset) {
654
3.74M
    assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
655
3.74M
            isTargetIndex() || isBlockAddress()) &&
656
3.74M
           "Wrong MachineOperand mutator");
657
3.74M
    SmallContents.OffsetLo = unsigned(Offset);
658
3.74M
    Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
659
3.74M
  }
660
661
1.82M
  void setIndex(int Idx) {
662
1.82M
    assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
663
1.82M
           "Wrong MachineOperand mutator");
664
1.82M
    Contents.OffsetedInfo.Val.Index = Idx;
665
1.82M
  }
666
667
125
  void setMetadata(const MDNode *MD) {
668
125
    assert(isMetadata() && "Wrong MachineOperand mutator");
669
125
    Contents.MD = MD;
670
125
  }
671
672
16.5M
  void setMBB(MachineBasicBlock *MBB) {
673
16.5M
    assert(isMBB() && "Wrong MachineOperand mutator");
674
16.5M
    Contents.MBB = MBB;
675
16.5M
  }
676
677
  /// Sets value of register mask operand referencing Mask.  The
678
  /// operand does not take ownership of the memory referenced by Mask, it must
679
  /// remain valid for the lifetime of the operand. See CreateRegMask().
680
  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
681
54
  void setRegMask(const uint32_t *RegMaskPtr) {
682
54
    assert(isRegMask() && "Wrong MachineOperand mutator");
683
54
    Contents.RegMask = RegMaskPtr;
684
54
  }
685
686
  //===--------------------------------------------------------------------===//
687
  // Other methods.
688
  //===--------------------------------------------------------------------===//
689
690
  /// Returns true if this operand is identical to the specified operand except
691
  /// for liveness related flags (isKill, isUndef and isDead). Note that this
692
  /// should stay in sync with the hash_value overload below.
693
  bool isIdenticalTo(const MachineOperand &Other) const;
694
695
  /// MachineOperand hash_value overload.
696
  ///
697
  /// Note that this includes the same information in the hash that
698
  /// isIdenticalTo uses for comparison. It is thus suited for use in hash
699
  /// tables which use that function for equality comparisons only. This must
700
  /// stay exactly in sync with isIdenticalTo above.
701
  friend hash_code hash_value(const MachineOperand &MO);
702
703
  /// ChangeToImmediate - Replace this operand with a new immediate operand of
704
  /// the specified value.  If an operand is known to be an immediate already,
705
  /// the setImm method should be used.
706
  void ChangeToImmediate(int64_t ImmVal);
707
708
  /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
709
  /// of the specified value.  If an operand is known to be an FP immediate
710
  /// already, the setFPImm method should be used.
711
  void ChangeToFPImmediate(const ConstantFP *FPImm);
712
713
  /// ChangeToES - Replace this operand with a new external symbol operand.
714
  void ChangeToES(const char *SymName, unsigned char TargetFlags = 0);
715
716
  /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
717
  void ChangeToMCSymbol(MCSymbol *Sym);
718
719
  /// Replace this operand with a frame index.
720
  void ChangeToFrameIndex(int Idx);
721
722
  /// Replace this operand with a target index.
723
  void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
724
                           unsigned char TargetFlags = 0);
725
726
  /// ChangeToRegister - Replace this operand with a new register operand of
727
  /// the specified value.  If an operand is known to be an register already,
728
  /// the setReg method should be used.
729
  void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
730
                        bool isKill = false, bool isDead = false,
731
                        bool isUndef = false, bool isDebug = false);
732
733
  //===--------------------------------------------------------------------===//
734
  // Construction methods.
735
  //===--------------------------------------------------------------------===//
736
737
66.6M
  static MachineOperand CreateImm(int64_t Val) {
738
66.6M
    MachineOperand Op(MachineOperand::MO_Immediate);
739
66.6M
    Op.setImm(Val);
740
66.6M
    return Op;
741
66.6M
  }
742
743
3.87M
  static MachineOperand CreateCImm(const ConstantInt *CI) {
744
3.87M
    MachineOperand Op(MachineOperand::MO_CImmediate);
745
3.87M
    Op.Contents.CI = CI;
746
3.87M
    return Op;
747
3.87M
  }
748
749
57.2k
  static MachineOperand CreateFPImm(const ConstantFP *CFP) {
750
57.2k
    MachineOperand Op(MachineOperand::MO_FPImmediate);
751
57.2k
    Op.Contents.CFP = CFP;
752
57.2k
    return Op;
753
57.2k
  }
754
755
  static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
756
                                  bool isKill = false, bool isDead = false,
757
                                  bool isUndef = false,
758
                                  bool isEarlyClobber = false,
759
                                  unsigned SubReg = 0, bool isDebug = false,
760
                                  bool isInternalRead = false,
761
128M
                                  bool isRenamable = false) {
762
128M
    assert(!(isDead && !isDef) && "Dead flag on non-def");
763
128M
    assert(!(isKill && isDef) && "Kill flag on def");
764
128M
    MachineOperand Op(MachineOperand::MO_Register);
765
128M
    Op.IsDef = isDef;
766
128M
    Op.IsImp = isImp;
767
128M
    Op.IsDeadOrKill = isKill | isDead;
768
128M
    Op.IsRenamable = isRenamable;
769
128M
    Op.IsUndef = isUndef;
770
128M
    Op.IsInternalRead = isInternalRead;
771
128M
    Op.IsEarlyClobber = isEarlyClobber;
772
128M
    Op.TiedTo = 0;
773
128M
    Op.IsDebug = isDebug;
774
128M
    Op.SmallContents.RegNo = Reg;
775
128M
    Op.Contents.Reg.Prev = nullptr;
776
128M
    Op.Contents.Reg.Next = nullptr;
777
128M
    Op.setSubReg(SubReg);
778
128M
    return Op;
779
128M
  }
780
  static MachineOperand CreateMBB(MachineBasicBlock *MBB,
781
15.6M
                                  unsigned char TargetFlags = 0) {
782
15.6M
    MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
783
15.6M
    Op.setMBB(MBB);
784
15.6M
    Op.setTargetFlags(TargetFlags);
785
15.6M
    return Op;
786
15.6M
  }
787
1.27M
  static MachineOperand CreateFI(int Idx) {
788
1.27M
    MachineOperand Op(MachineOperand::MO_FrameIndex);
789
1.27M
    Op.setIndex(Idx);
790
1.27M
    return Op;
791
1.27M
  }
792
  static MachineOperand CreateCPI(unsigned Idx, int Offset,
793
125k
                                  unsigned char TargetFlags = 0) {
794
125k
    MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
795
125k
    Op.setIndex(Idx);
796
125k
    Op.setOffset(Offset);
797
125k
    Op.setTargetFlags(TargetFlags);
798
125k
    return Op;
799
125k
  }
800
  static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
801
3
                                          unsigned char TargetFlags = 0) {
802
3
    MachineOperand Op(MachineOperand::MO_TargetIndex);
803
3
    Op.setIndex(Idx);
804
3
    Op.setOffset(Offset);
805
3
    Op.setTargetFlags(TargetFlags);
806
3
    return Op;
807
3
  }
808
6.55k
  static MachineOperand CreateJTI(unsigned Idx, unsigned char TargetFlags = 0) {
809
6.55k
    MachineOperand Op(MachineOperand::MO_JumpTableIndex);
810
6.55k
    Op.setIndex(Idx);
811
6.55k
    Op.setTargetFlags(TargetFlags);
812
6.55k
    return Op;
813
6.55k
  }
814
  static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
815
3.43M
                                 unsigned char TargetFlags = 0) {
816
3.43M
    MachineOperand Op(MachineOperand::MO_GlobalAddress);
817
3.43M
    Op.Contents.OffsetedInfo.Val.GV = GV;
818
3.43M
    Op.setOffset(Offset);
819
3.43M
    Op.setTargetFlags(TargetFlags);
820
3.43M
    return Op;
821
3.43M
  }
822
  static MachineOperand CreateES(const char *SymName,
823
84.7k
                                 unsigned char TargetFlags = 0) {
824
84.7k
    MachineOperand Op(MachineOperand::MO_ExternalSymbol);
825
84.7k
    Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
826
84.7k
    Op.setOffset(0); // Offset is always 0.
827
84.7k
    Op.setTargetFlags(TargetFlags);
828
84.7k
    return Op;
829
84.7k
  }
830
  static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
831
182
                                 unsigned char TargetFlags = 0) {
832
182
    MachineOperand Op(MachineOperand::MO_BlockAddress);
833
182
    Op.Contents.OffsetedInfo.Val.BA = BA;
834
182
    Op.setOffset(Offset);
835
182
    Op.setTargetFlags(TargetFlags);
836
182
    return Op;
837
182
  }
838
  /// CreateRegMask - Creates a register mask operand referencing Mask.  The
839
  /// operand does not take ownership of the memory referenced by Mask, it
840
  /// must remain valid for the lifetime of the operand.
841
  ///
842
  /// A RegMask operand represents a set of non-clobbered physical registers
843
  /// on an instruction that clobbers many registers, typically a call.  The
844
  /// bit mask has a bit set for each physreg that is preserved by this
845
  /// instruction, as described in the documentation for
846
  /// TargetRegisterInfo::getCallPreservedMask().
847
  ///
848
  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
849
  ///
850
1.80M
  static MachineOperand CreateRegMask(const uint32_t *Mask) {
851
1.80M
    assert(Mask && "Missing register mask");
852
1.80M
    MachineOperand Op(MachineOperand::MO_RegisterMask);
853
1.80M
    Op.Contents.RegMask = Mask;
854
1.80M
    return Op;
855
1.80M
  }
856
180
  static MachineOperand CreateRegLiveOut(const uint32_t *Mask) {
857
180
    assert(Mask && "Missing live-out register mask");
858
180
    MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
859
180
    Op.Contents.RegMask = Mask;
860
180
    return Op;
861
180
  }
862
13.8k
  static MachineOperand CreateMetadata(const MDNode *Meta) {
863
13.8k
    MachineOperand Op(MachineOperand::MO_Metadata);
864
13.8k
    Op.Contents.MD = Meta;
865
13.8k
    return Op;
866
13.8k
  }
867
868
  static MachineOperand CreateMCSymbol(MCSymbol *Sym,
869
90.0k
                                       unsigned char TargetFlags = 0) {
870
90.0k
    MachineOperand Op(MachineOperand::MO_MCSymbol);
871
90.0k
    Op.Contents.Sym = Sym;
872
90.0k
    Op.setOffset(0);
873
90.0k
    Op.setTargetFlags(TargetFlags);
874
90.0k
    return Op;
875
90.0k
  }
876
877
491k
  static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
878
491k
    MachineOperand Op(MachineOperand::MO_CFIIndex);
879
491k
    Op.Contents.CFIIndex = CFIIndex;
880
491k
    return Op;
881
491k
  }
882
883
66.8k
  static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) {
884
66.8k
    MachineOperand Op(MachineOperand::MO_IntrinsicID);
885
66.8k
    Op.Contents.IntrinsicID = ID;
886
66.8k
    return Op;
887
66.8k
  }
888
889
1.10M
  static MachineOperand CreatePredicate(unsigned Pred) {
890
1.10M
    MachineOperand Op(MachineOperand::MO_Predicate);
891
1.10M
    Op.Contents.Pred = Pred;
892
1.10M
    return Op;
893
1.10M
  }
894
895
  friend class MachineInstr;
896
  friend class MachineRegisterInfo;
897
898
private:
899
  // If this operand is currently a register operand, and if this is in a
900
  // function, deregister the operand from the register's use/def list.
901
  void removeRegFromUses();
902
903
  /// Artificial kinds for DenseMap usage.
904
  enum : unsigned char {
905
    MO_Empty = MO_Last + 1,
906
    MO_Tombstone,
907
  };
908
909
  friend struct DenseMapInfo<MachineOperand>;
910
911
  //===--------------------------------------------------------------------===//
912
  // Methods for handling register use/def lists.
913
  //===--------------------------------------------------------------------===//
914
915
  /// isOnRegUseList - Return true if this operand is on a register use/def
916
  /// list or false if not.  This can only be called for register operands
917
  /// that are part of a machine instruction.
918
140k
  bool isOnRegUseList() const {
919
140k
    assert(isReg() && "Can only add reg operand to use lists");
920
140k
    return Contents.Reg.Prev != nullptr;
921
140k
  }
922
};
923
924
template <> struct DenseMapInfo<MachineOperand> {
925
2.55k
  static MachineOperand getEmptyKey() {
926
2.55k
    return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
927
2.55k
        MachineOperand::MO_Empty));
928
2.55k
  }
929
1.33k
  static MachineOperand getTombstoneKey() {
930
1.33k
    return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
931
1.33k
        MachineOperand::MO_Tombstone));
932
1.33k
  }
933
785
  static unsigned getHashValue(const MachineOperand &MO) {
934
785
    return hash_value(MO);
935
785
  }
936
38.1k
  static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
937
38.1k
    if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
938
38.1k
                             MachineOperand::MO_Empty) ||
939
38.1k
        LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
940
2.11k
                             MachineOperand::MO_Tombstone))
941
35.9k
      return LHS.getType() == RHS.getType();
942
2.11k
    return LHS.isIdenticalTo(RHS);
943
2.11k
  }
944
};
945
946
0
inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) {
947
0
  MO.print(OS);
948
0
  return OS;
949
0
}
950
951
// See friend declaration above. This additional declaration is required in
952
// order to compile LLVM with IBM xlC compiler.
953
hash_code hash_value(const MachineOperand &MO);
954
} // namespace llvm
955
956
#endif