Coverage Report

Created: 2018-07-19 03:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/MachineOperand.h
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//===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the declaration of the MachineOperand class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEOPERAND_H
15
#define LLVM_CODEGEN_MACHINEOPERAND_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/LowLevelTypeImpl.h"
21
#include <cassert>
22
23
namespace llvm {
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25
class BlockAddress;
26
class ConstantFP;
27
class ConstantInt;
28
class GlobalValue;
29
class MachineBasicBlock;
30
class MachineInstr;
31
class MachineRegisterInfo;
32
class MCCFIInstruction;
33
class MDNode;
34
class ModuleSlotTracker;
35
class TargetMachine;
36
class TargetIntrinsicInfo;
37
class TargetRegisterInfo;
38
class hash_code;
39
class raw_ostream;
40
class MCSymbol;
41
42
/// MachineOperand class - Representation of each machine instruction operand.
43
///
44
/// This class isn't a POD type because it has a private constructor, but its
45
/// destructor must be trivial. Functions like MachineInstr::addOperand(),
46
/// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
47
/// not having to call the MachineOperand destructor.
48
///
49
class MachineOperand {
50
public:
51
  enum MachineOperandType : unsigned char {
52
    MO_Register,          ///< Register operand.
53
    MO_Immediate,         ///< Immediate operand
54
    MO_CImmediate,        ///< Immediate >64bit operand
55
    MO_FPImmediate,       ///< Floating-point immediate operand
56
    MO_MachineBasicBlock, ///< MachineBasicBlock reference
57
    MO_FrameIndex,        ///< Abstract Stack Frame Index
58
    MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
59
    MO_TargetIndex,       ///< Target-dependent index+offset operand.
60
    MO_JumpTableIndex,    ///< Address of indexed Jump Table for switch
61
    MO_ExternalSymbol,    ///< Name of external global symbol
62
    MO_GlobalAddress,     ///< Address of a global value
63
    MO_BlockAddress,      ///< Address of a basic block
64
    MO_RegisterMask,      ///< Mask of preserved registers.
65
    MO_RegisterLiveOut,   ///< Mask of live-out registers.
66
    MO_Metadata,          ///< Metadata reference (for debug info)
67
    MO_MCSymbol,          ///< MCSymbol reference (for debug/eh info)
68
    MO_CFIIndex,          ///< MCCFIInstruction index.
69
    MO_IntrinsicID,       ///< Intrinsic ID for ISel
70
    MO_Predicate,         ///< Generic predicate for ISel
71
    MO_Last = MO_Predicate,
72
  };
73
74
private:
75
  /// OpKind - Specify what kind of operand this is.  This discriminates the
76
  /// union.
77
  unsigned OpKind : 8;
78
79
  /// Subregister number for MO_Register.  A value of 0 indicates the
80
  /// MO_Register has no subReg.
81
  ///
82
  /// For all other kinds of operands, this field holds target-specific flags.
83
  unsigned SubReg_TargetFlags : 12;
84
85
  /// TiedTo - Non-zero when this register operand is tied to another register
86
  /// operand. The encoding of this field is described in the block comment
87
  /// before MachineInstr::tieOperands().
88
  unsigned TiedTo : 4;
89
90
  /// IsDef - True if this is a def, false if this is a use of the register.
91
  /// This is only valid on register operands.
92
  ///
93
  unsigned IsDef : 1;
94
95
  /// IsImp - True if this is an implicit def or use, false if it is explicit.
96
  /// This is only valid on register opderands.
97
  ///
98
  unsigned IsImp : 1;
99
100
  /// IsDeadOrKill
101
  /// For uses: IsKill - True if this instruction is the last use of the
102
  /// register on this path through the function.
103
  /// For defs: IsDead - True if this register is never used by a subsequent
104
  /// instruction.
105
  /// This is only valid on register operands.
106
  unsigned IsDeadOrKill : 1;
107
108
  /// See isRenamable().
109
  unsigned IsRenamable : 1;
110
111
  /// IsUndef - True if this register operand reads an "undef" value, i.e. the
112
  /// read value doesn't matter.  This flag can be set on both use and def
113
  /// operands.  On a sub-register def operand, it refers to the part of the
114
  /// register that isn't written.  On a full-register def operand, it is a
115
  /// noop.  See readsReg().
116
  ///
117
  /// This is only valid on registers.
118
  ///
119
  /// Note that an instruction may have multiple <undef> operands referring to
120
  /// the same register.  In that case, the instruction may depend on those
121
  /// operands reading the same dont-care value.  For example:
122
  ///
123
  ///   %1 = XOR undef %2, undef %2
124
  ///
125
  /// Any register can be used for %2, and its value doesn't matter, but
126
  /// the two operands must be the same register.
127
  ///
128
  unsigned IsUndef : 1;
129
130
  /// IsInternalRead - True if this operand reads a value that was defined
131
  /// inside the same instruction or bundle.  This flag can be set on both use
132
  /// and def operands.  On a sub-register def operand, it refers to the part
133
  /// of the register that isn't written.  On a full-register def operand, it
134
  /// is a noop.
135
  ///
136
  /// When this flag is set, the instruction bundle must contain at least one
137
  /// other def of the register.  If multiple instructions in the bundle define
138
  /// the register, the meaning is target-defined.
139
  unsigned IsInternalRead : 1;
140
141
  /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
142
  /// by the MachineInstr before all input registers are read.  This is used to
143
  /// model the GCC inline asm '&' constraint modifier.
144
  unsigned IsEarlyClobber : 1;
145
146
  /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
147
  /// not a real instruction.  Such uses should be ignored during codegen.
148
  unsigned IsDebug : 1;
149
150
  /// SmallContents - This really should be part of the Contents union, but
151
  /// lives out here so we can get a better packed struct.
152
  /// MO_Register: Register number.
153
  /// OffsetedInfo: Low bits of offset.
154
  union {
155
    unsigned RegNo;           // For MO_Register.
156
    unsigned OffsetLo;        // Matches Contents.OffsetedInfo.OffsetHi.
157
  } SmallContents;
158
159
  /// ParentMI - This is the instruction that this operand is embedded into.
160
  /// This is valid for all operand types, when the operand is in an instr.
161
  MachineInstr *ParentMI;
162
163
  /// Contents union - This contains the payload for the various operand types.
164
  union {
165
    MachineBasicBlock *MBB;  // For MO_MachineBasicBlock.
166
    const ConstantFP *CFP;   // For MO_FPImmediate.
167
    const ConstantInt *CI;   // For MO_CImmediate. Integers > 64bit.
168
    int64_t ImmVal;          // For MO_Immediate.
169
    const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
170
    const MDNode *MD;        // For MO_Metadata.
171
    MCSymbol *Sym;           // For MO_MCSymbol.
172
    unsigned CFIIndex;       // For MO_CFI.
173
    Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
174
    unsigned Pred;           // For MO_Predicate
175
176
    struct {                  // For MO_Register.
177
      // Register number is in SmallContents.RegNo.
178
      MachineOperand *Prev;   // Access list for register. See MRI.
179
      MachineOperand *Next;
180
    } Reg;
181
182
    /// OffsetedInfo - This struct contains the offset and an object identifier.
183
    /// this represent the object as with an optional offset from it.
184
    struct {
185
      union {
186
        int Index;                // For MO_*Index - The index itself.
187
        const char *SymbolName;   // For MO_ExternalSymbol.
188
        const GlobalValue *GV;    // For MO_GlobalAddress.
189
        const BlockAddress *BA;   // For MO_BlockAddress.
190
      } Val;
191
      // Low bits of offset are in SmallContents.OffsetLo.
192
      int OffsetHi;               // An offset from the object, high 32 bits.
193
    } OffsetedInfo;
194
  } Contents;
195
196
  explicit MachineOperand(MachineOperandType K)
197
218M
    : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {
198
218M
    // Assert that the layout is what we expect. It's easy to grow this object.
199
218M
    static_assert(alignof(MachineOperand) <= alignof(int64_t),
200
218M
                  "MachineOperand shouldn't be more than 8 byte aligned");
201
218M
    static_assert(sizeof(Contents) <= 2 * sizeof(void *),
202
218M
                  "Contents should be at most two pointers");
203
218M
    static_assert(sizeof(MachineOperand) <=
204
218M
                      alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
205
218M
                                                3 * sizeof(void *)),
206
218M
                  "MachineOperand too big. Should be Kind, SmallContents, "
207
218M
                  "ParentMI, and Contents");
208
218M
  }
209
210
public:
211
  /// getType - Returns the MachineOperandType for this operand.
212
  ///
213
589M
  MachineOperandType getType() const { return (MachineOperandType)OpKind; }
214
215
200M
  unsigned getTargetFlags() const {
216
200M
    return isReg() ? 
099.0M
:
SubReg_TargetFlags101M
;
217
200M
  }
218
20.2M
  void setTargetFlags(unsigned F) {
219
20.2M
    assert(!isReg() && "Register operands can't have target flags");
220
20.2M
    SubReg_TargetFlags = F;
221
20.2M
    assert(SubReg_TargetFlags == F && "Target flags out of range");
222
20.2M
  }
223
1
  void addTargetFlag(unsigned F) {
224
1
    assert(!isReg() && "Register operands can't have target flags");
225
1
    SubReg_TargetFlags |= F;
226
1
    assert((SubReg_TargetFlags & F) && "Target flags out of range");
227
1
  }
228
229
230
  /// getParent - Return the instruction that this operand belongs to.
231
  ///
232
292M
  MachineInstr *getParent() { return ParentMI; }
233
322M
  const MachineInstr *getParent() const { return ParentMI; }
234
235
  /// clearParent - Reset the parent pointer.
236
  ///
237
  /// The MachineOperand copy constructor also copies ParentMI, expecting the
238
  /// original to be deleted. If a MachineOperand is ever stored outside a
239
  /// MachineInstr, the parent pointer must be cleared.
240
  ///
241
  /// Never call clearParent() on an operand in a MachineInstr.
242
  ///
243
758
  void clearParent() { ParentMI = nullptr; }
244
245
  /// Print a subreg index operand.
246
  /// MO_Immediate operands can also be subreg idices. If it's the case, the
247
  /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
248
  /// called to check this.
249
  static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
250
                             const TargetRegisterInfo *TRI);
251
252
  /// Print operand target flags.
253
  static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
254
255
  /// Print a MCSymbol as an operand.
256
  static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
257
258
  /// Print a stack object reference.
259
  static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
260
                                        bool IsFixed, StringRef Name);
261
262
  /// Print the offset with explicit +/- signs.
263
  static void printOperandOffset(raw_ostream &OS, int64_t Offset);
264
265
  /// Print an IRSlotNumber.
266
  static void printIRSlotNumber(raw_ostream &OS, int Slot);
267
268
  /// Print the MachineOperand to \p os.
269
  /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
270
  /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
271
  /// function will try to pick it up from the parent.
272
  void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
273
             const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
274
275
  /// More complex way of printing a MachineOperand.
276
  /// \param TypeToPrint specifies the generic type to be printed on uses and
277
  /// defs. It can be determined using MachineInstr::getTypeToPrint.
278
  /// \param PrintDef - whether we want to print `def` on an operand which
279
  /// isDef. Sometimes, if the operand is printed before '=', we don't print
280
  /// `def`.
281
  /// \param IsStandalone - whether we want a verbose output of the MO. This
282
  /// prints extra information that can be easily inferred when printing the
283
  /// whole function, but not when printing only a fragment of it.
284
  /// \param ShouldPrintRegisterTies - whether we want to print register ties.
285
  /// Sometimes they are easily determined by the instruction's descriptor
286
  /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
287
  /// \param TiedOperandIdx - if we need to print register ties this needs to
288
  /// provide the index of the tied register. If not, it will be ignored.
289
  /// \param TRI - provide more target-specific information to the printer.
290
  /// Unlike the previous function, this one will not try and get the
291
  /// information from it's parent.
292
  /// \param IntrinsicInfo - same as \p TRI.
293
  void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
294
             bool PrintDef, bool IsStandalone, bool ShouldPrintRegisterTies,
295
             unsigned TiedOperandIdx, const TargetRegisterInfo *TRI,
296
             const TargetIntrinsicInfo *IntrinsicInfo) const;
297
298
  /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level
299
  /// type to be printed the same way the full version of print(...) does it.
300
  void print(raw_ostream &os, LLT TypeToPrint,
301
             const TargetRegisterInfo *TRI = nullptr,
302
             const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
303
304
  void dump() const;
305
306
  //===--------------------------------------------------------------------===//
307
  // Accessors that tell you what kind of MachineOperand you're looking at.
308
  //===--------------------------------------------------------------------===//
309
310
  /// isReg - Tests if this is a MO_Register operand.
311
3.99G
  bool isReg() const { return OpKind == MO_Register; }
312
  /// isImm - Tests if this is a MO_Immediate operand.
313
75.6M
  bool isImm() const { return OpKind == MO_Immediate; }
314
  /// isCImm - Test if this is a MO_CImmediate operand.
315
1.60M
  bool isCImm() const { return OpKind == MO_CImmediate; }
316
  /// isFPImm - Tests if this is a MO_FPImmediate operand.
317
37.4M
  bool isFPImm() const { return OpKind == MO_FPImmediate; }
318
  /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
319
10.5M
  bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
320
  /// isFI - Tests if this is a MO_FrameIndex operand.
321
382M
  bool isFI() const { return OpKind == MO_FrameIndex; }
322
  /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
323
4.81M
  bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
324
  /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
325
1.91k
  bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
326
  /// isJTI - Tests if this is a MO_JumpTableIndex operand.
327
25.1M
  bool isJTI() const { return OpKind == MO_JumpTableIndex; }
328
  /// isGlobal - Tests if this is a MO_GlobalAddress operand.
329
1.96M
  bool isGlobal() const { return OpKind == MO_GlobalAddress; }
330
  /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
331
1.00M
  bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
332
  /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
333
570k
  bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
334
  /// isRegMask - Tests if this is a MO_RegisterMask operand.
335
766M
  bool isRegMask() const { return OpKind == MO_RegisterMask; }
336
  /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
337
431
  bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
338
  /// isMetadata - Tests if this is a MO_Metadata operand.
339
172k
  bool isMetadata() const { return OpKind == MO_Metadata; }
340
1.86k
  bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
341
1.93k
  bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
342
709k
  bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
343
  bool isPredicate() const { return OpKind == MO_Predicate; }
344
  //===--------------------------------------------------------------------===//
345
  // Accessors for Register Operands
346
  //===--------------------------------------------------------------------===//
347
348
  /// getReg - Returns the register number.
349
2.69G
  unsigned getReg() const {
350
2.69G
    assert(isReg() && "This is not a register operand!");
351
2.69G
    return SmallContents.RegNo;
352
2.69G
  }
353
354
534M
  unsigned getSubReg() const {
355
534M
    assert(isReg() && "Wrong MachineOperand accessor");
356
534M
    return SubReg_TargetFlags;
357
534M
  }
358
359
1.33G
  bool isUse() const {
360
1.33G
    assert(isReg() && "Wrong MachineOperand accessor");
361
1.33G
    return !IsDef;
362
1.33G
  }
363
364
1.80G
  bool isDef() const {
365
1.80G
    assert(isReg() && "Wrong MachineOperand accessor");
366
1.80G
    return IsDef;
367
1.80G
  }
368
369
445M
  bool isImplicit() const {
370
445M
    assert(isReg() && "Wrong MachineOperand accessor");
371
445M
    return IsImp;
372
445M
  }
373
374
108M
  bool isDead() const {
375
108M
    assert(isReg() && "Wrong MachineOperand accessor");
376
108M
    return IsDeadOrKill & IsDef;
377
108M
  }
378
379
156M
  bool isKill() const {
380
156M
    assert(isReg() && "Wrong MachineOperand accessor");
381
156M
    return IsDeadOrKill & !IsDef;
382
156M
  }
383
384
540M
  bool isUndef() const {
385
540M
    assert(isReg() && "Wrong MachineOperand accessor");
386
540M
    return IsUndef;
387
540M
  }
388
389
  /// isRenamable - Returns true if this register may be renamed, i.e. it does
390
  /// not generate a value that is somehow read in a way that is not represented
391
  /// by the Machine IR (e.g. to meet an ABI or ISA requirement).  This is only
392
  /// valid on physical register operands.  Virtual registers are assumed to
393
  /// always be renamable regardless of the value of this field.
394
  ///
395
  /// Operands that are renamable can freely be changed to any other register
396
  /// that is a member of the register class returned by
397
  /// MI->getRegClassConstraint().
398
  ///
399
  /// isRenamable can return false for several different reasons:
400
  ///
401
  /// - ABI constraints (since liveness is not always precisely modeled).  We
402
  ///   conservatively handle these cases by setting all physical register
403
  ///   operands that didn’t start out as virtual regs to not be renamable.
404
  ///   Also any physical register operands created after register allocation or
405
  ///   whose register is changed after register allocation will not be
406
  ///   renamable.  This state is tracked in the MachineOperand::IsRenamable
407
  ///   bit.
408
  ///
409
  /// - Opcode/target constraints: for opcodes that have complex register class
410
  ///   requirements (e.g. that depend on other operands/instructions), we set
411
  ///   hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
412
  ///   description.  Operands belonging to instructions with opcodes that are
413
  ///   marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
414
  ///   isRenamable().  Additionally, the AllowRegisterRenaming target property
415
  ///   prevents any operands from being marked renamable for targets that don't
416
  ///   have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
417
  ///   values.
418
  bool isRenamable() const;
419
420
346M
  bool isInternalRead() const {
421
346M
    assert(isReg() && "Wrong MachineOperand accessor");
422
346M
    return IsInternalRead;
423
346M
  }
424
425
136M
  bool isEarlyClobber() const {
426
136M
    assert(isReg() && "Wrong MachineOperand accessor");
427
136M
    return IsEarlyClobber;
428
136M
  }
429
430
195M
  bool isTied() const {
431
195M
    assert(isReg() && "Wrong MachineOperand accessor");
432
195M
    return TiedTo;
433
195M
  }
434
435
455M
  bool isDebug() const {
436
455M
    assert(isReg() && "Wrong MachineOperand accessor");
437
455M
    return IsDebug;
438
455M
  }
439
440
  /// readsReg - Returns true if this operand reads the previous value of its
441
  /// register.  A use operand with the <undef> flag set doesn't read its
442
  /// register.  A sub-register def implicitly reads the other parts of the
443
  /// register being redefined unless the <undef> flag is set.
444
  ///
445
  /// This refers to reading the register value from before the current
446
  /// instruction or bundle. Internal bundle reads are not included.
447
322M
  bool readsReg() const {
448
322M
    assert(isReg() && "Wrong MachineOperand accessor");
449
322M
    return !isUndef() && 
!isInternalRead()318M
&&
(318M
isUse()318M
||
getSubReg()92.7M
);
450
322M
  }
451
452
  //===--------------------------------------------------------------------===//
453
  // Mutators for Register Operands
454
  //===--------------------------------------------------------------------===//
455
456
  /// Change the register this operand corresponds to.
457
  ///
458
  void setReg(unsigned Reg);
459
460
129M
  void setSubReg(unsigned subReg) {
461
129M
    assert(isReg() && "Wrong MachineOperand mutator");
462
129M
    SubReg_TargetFlags = subReg;
463
129M
    assert(SubReg_TargetFlags == subReg && "SubReg out of range");
464
129M
  }
465
466
  /// substVirtReg - Substitute the current register with the virtual
467
  /// subregister Reg:SubReg. Take any existing SubReg index into account,
468
  /// using TargetRegisterInfo to compose the subreg indices if necessary.
469
  /// Reg must be a virtual register, SubIdx can be 0.
470
  ///
471
  void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&);
472
473
  /// substPhysReg - Substitute the current register with the physical register
474
  /// Reg, taking any existing SubReg into account. For instance,
475
  /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
476
  ///
477
  void substPhysReg(unsigned Reg, const TargetRegisterInfo&);
478
479
631
  void setIsUse(bool Val = true) { setIsDef(!Val); }
480
481
  /// Change a def to a use, or a use to a def.
482
  void setIsDef(bool Val = true);
483
484
14.4k
  void setImplicit(bool Val = true) {
485
14.4k
    assert(isReg() && "Wrong MachineOperand mutator");
486
14.4k
    IsImp = Val;
487
14.4k
  }
488
489
103M
  void setIsKill(bool Val = true) {
490
103M
    assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
491
103M
    assert((!Val || !isDebug()) && "Marking a debug operation as kill");
492
103M
    IsDeadOrKill = Val;
493
103M
  }
494
495
14.5M
  void setIsDead(bool Val = true) {
496
14.5M
    assert(isReg() && IsDef && "Wrong MachineOperand mutator");
497
14.5M
    IsDeadOrKill = Val;
498
14.5M
  }
499
500
3.38M
  void setIsUndef(bool Val = true) {
501
3.38M
    assert(isReg() && "Wrong MachineOperand mutator");
502
3.38M
    IsUndef = Val;
503
3.38M
  }
504
505
  void setIsRenamable(bool Val = true);
506
507
1.88M
  void setIsInternalRead(bool Val = true) {
508
1.88M
    assert(isReg() && "Wrong MachineOperand mutator");
509
1.88M
    IsInternalRead = Val;
510
1.88M
  }
511
512
413k
  void setIsEarlyClobber(bool Val = true) {
513
413k
    assert(isReg() && IsDef && "Wrong MachineOperand mutator");
514
413k
    IsEarlyClobber = Val;
515
413k
  }
516
517
135
  void setIsDebug(bool Val = true) {
518
135
    assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
519
135
    IsDebug = Val;
520
135
  }
521
522
  //===--------------------------------------------------------------------===//
523
  // Accessors for various operand types.
524
  //===--------------------------------------------------------------------===//
525
526
190M
  int64_t getImm() const {
527
190M
    assert(isImm() && "Wrong MachineOperand accessor");
528
190M
    return Contents.ImmVal;
529
190M
  }
530
531
2.47M
  const ConstantInt *getCImm() const {
532
2.47M
    assert(isCImm() && "Wrong MachineOperand accessor");
533
2.47M
    return Contents.CI;
534
2.47M
  }
535
536
5.86k
  const ConstantFP *getFPImm() const {
537
5.86k
    assert(isFPImm() && "Wrong MachineOperand accessor");
538
5.86k
    return Contents.CFP;
539
5.86k
  }
540
541
98.6M
  MachineBasicBlock *getMBB() const {
542
98.6M
    assert(isMBB() && "Wrong MachineOperand accessor");
543
98.6M
    return Contents.MBB;
544
98.6M
  }
545
546
8.86M
  int getIndex() const {
547
8.86M
    assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
548
8.86M
           "Wrong MachineOperand accessor");
549
8.86M
    return Contents.OffsetedInfo.Val.Index;
550
8.86M
  }
551
552
16.6M
  const GlobalValue *getGlobal() const {
553
16.6M
    assert(isGlobal() && "Wrong MachineOperand accessor");
554
16.6M
    return Contents.OffsetedInfo.Val.GV;
555
16.6M
  }
556
557
850
  const BlockAddress *getBlockAddress() const {
558
850
    assert(isBlockAddress() && "Wrong MachineOperand accessor");
559
850
    return Contents.OffsetedInfo.Val.BA;
560
850
  }
561
562
454k
  MCSymbol *getMCSymbol() const {
563
454k
    assert(isMCSymbol() && "Wrong MachineOperand accessor");
564
454k
    return Contents.Sym;
565
454k
  }
566
567
430k
  unsigned getCFIIndex() const {
568
430k
    assert(isCFIIndex() && "Wrong MachineOperand accessor");
569
430k
    return Contents.CFIIndex;
570
430k
  }
571
572
701k
  Intrinsic::ID getIntrinsicID() const {
573
701k
    assert(isIntrinsicID() && "Wrong MachineOperand accessor");
574
701k
    return Contents.IntrinsicID;
575
701k
  }
576
577
609k
  unsigned getPredicate() const {
578
609k
    assert(isPredicate() && "Wrong MachineOperand accessor");
579
609k
    return Contents.Pred;
580
609k
  }
581
582
  /// Return the offset from the symbol in this operand. This always returns 0
583
  /// for ExternalSymbol operands.
584
13.7M
  int64_t getOffset() const {
585
13.7M
    assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
586
13.7M
            isTargetIndex() || isBlockAddress()) &&
587
13.7M
           "Wrong MachineOperand accessor");
588
13.7M
    return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
589
13.7M
           SmallContents.OffsetLo;
590
13.7M
  }
591
592
263k
  const char *getSymbolName() const {
593
263k
    assert(isSymbol() && "Wrong MachineOperand accessor");
594
263k
    return Contents.OffsetedInfo.Val.SymbolName;
595
263k
  }
596
597
  /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
598
  /// It is sometimes necessary to detach the register mask pointer from its
599
  /// machine operand. This static method can be used for such detached bit
600
  /// mask pointers.
601
338M
  static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
602
338M
    // See TargetRegisterInfo.h.
603
338M
    assert(PhysReg < (1u << 30) && "Not a physical register");
604
338M
    return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
605
338M
  }
606
607
  /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
608
125M
  bool clobbersPhysReg(unsigned PhysReg) const {
609
125M
     return clobbersPhysReg(getRegMask(), PhysReg);
610
125M
  }
611
612
  /// getRegMask - Returns a bit mask of registers preserved by this RegMask
613
  /// operand.
614
141M
  const uint32_t *getRegMask() const {
615
141M
    assert(isRegMask() && "Wrong MachineOperand accessor");
616
141M
    return Contents.RegMask;
617
141M
  }
618
619
  /// getRegLiveOut - Returns a bit mask of live-out registers.
620
181
  const uint32_t *getRegLiveOut() const {
621
181
    assert(isRegLiveOut() && "Wrong MachineOperand accessor");
622
181
    return Contents.RegMask;
623
181
  }
624
625
19.0k
  const MDNode *getMetadata() const {
626
19.0k
    assert(isMetadata() && "Wrong MachineOperand accessor");
627
19.0k
    return Contents.MD;
628
19.0k
  }
629
630
  //===--------------------------------------------------------------------===//
631
  // Mutators for various operand types.
632
  //===--------------------------------------------------------------------===//
633
634
73.2M
  void setImm(int64_t immVal) {
635
73.2M
    assert(isImm() && "Wrong MachineOperand mutator");
636
73.2M
    Contents.ImmVal = immVal;
637
73.2M
  }
638
639
149k
  void setCImm(const ConstantInt *CI) {
640
149k
    assert(isCImm() && "Wrong MachineOperand mutator");
641
149k
    Contents.CI = CI;
642
149k
  }
643
644
1
  void setFPImm(const ConstantFP *CFP) {
645
1
    assert(isFPImm() && "Wrong MachineOperand mutator");
646
1
    Contents.CFP = CFP;
647
1
  }
648
649
4.11M
  void setOffset(int64_t Offset) {
650
4.11M
    assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
651
4.11M
            isTargetIndex() || isBlockAddress()) &&
652
4.11M
           "Wrong MachineOperand mutator");
653
4.11M
    SmallContents.OffsetLo = unsigned(Offset);
654
4.11M
    Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
655
4.11M
  }
656
657
1.87M
  void setIndex(int Idx) {
658
1.87M
    assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
659
1.87M
           "Wrong MachineOperand mutator");
660
1.87M
    Contents.OffsetedInfo.Val.Index = Idx;
661
1.87M
  }
662
663
119
  void setMetadata(const MDNode *MD) {
664
119
    assert(isMetadata() && "Wrong MachineOperand mutator");
665
119
    Contents.MD = MD;
666
119
  }
667
668
16.7M
  void setMBB(MachineBasicBlock *MBB) {
669
16.7M
    assert(isMBB() && "Wrong MachineOperand mutator");
670
16.7M
    Contents.MBB = MBB;
671
16.7M
  }
672
673
  /// Sets value of register mask operand referencing Mask.  The
674
  /// operand does not take ownership of the memory referenced by Mask, it must
675
  /// remain valid for the lifetime of the operand. See CreateRegMask().
676
  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
677
49
  void setRegMask(const uint32_t *RegMaskPtr) {
678
49
    assert(isRegMask() && "Wrong MachineOperand mutator");
679
49
    Contents.RegMask = RegMaskPtr;
680
49
  }
681
682
  //===--------------------------------------------------------------------===//
683
  // Other methods.
684
  //===--------------------------------------------------------------------===//
685
686
  /// Returns true if this operand is identical to the specified operand except
687
  /// for liveness related flags (isKill, isUndef and isDead). Note that this
688
  /// should stay in sync with the hash_value overload below.
689
  bool isIdenticalTo(const MachineOperand &Other) const;
690
691
  /// MachineOperand hash_value overload.
692
  ///
693
  /// Note that this includes the same information in the hash that
694
  /// isIdenticalTo uses for comparison. It is thus suited for use in hash
695
  /// tables which use that function for equality comparisons only. This must
696
  /// stay exactly in sync with isIdenticalTo above.
697
  friend hash_code hash_value(const MachineOperand &MO);
698
699
  /// ChangeToImmediate - Replace this operand with a new immediate operand of
700
  /// the specified value.  If an operand is known to be an immediate already,
701
  /// the setImm method should be used.
702
  void ChangeToImmediate(int64_t ImmVal);
703
704
  /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
705
  /// of the specified value.  If an operand is known to be an FP immediate
706
  /// already, the setFPImm method should be used.
707
  void ChangeToFPImmediate(const ConstantFP *FPImm);
708
709
  /// ChangeToES - Replace this operand with a new external symbol operand.
710
  void ChangeToES(const char *SymName, unsigned char TargetFlags = 0);
711
712
  /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
713
  void ChangeToMCSymbol(MCSymbol *Sym);
714
715
  /// Replace this operand with a frame index.
716
  void ChangeToFrameIndex(int Idx);
717
718
  /// Replace this operand with a target index.
719
  void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
720
                           unsigned char TargetFlags = 0);
721
722
  /// ChangeToRegister - Replace this operand with a new register operand of
723
  /// the specified value.  If an operand is known to be an register already,
724
  /// the setReg method should be used.
725
  void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
726
                        bool isKill = false, bool isDead = false,
727
                        bool isUndef = false, bool isDebug = false);
728
729
  //===--------------------------------------------------------------------===//
730
  // Construction methods.
731
  //===--------------------------------------------------------------------===//
732
733
66.9M
  static MachineOperand CreateImm(int64_t Val) {
734
66.9M
    MachineOperand Op(MachineOperand::MO_Immediate);
735
66.9M
    Op.setImm(Val);
736
66.9M
    return Op;
737
66.9M
  }
738
739
1.88M
  static MachineOperand CreateCImm(const ConstantInt *CI) {
740
1.88M
    MachineOperand Op(MachineOperand::MO_CImmediate);
741
1.88M
    Op.Contents.CI = CI;
742
1.88M
    return Op;
743
1.88M
  }
744
745
30.3k
  static MachineOperand CreateFPImm(const ConstantFP *CFP) {
746
30.3k
    MachineOperand Op(MachineOperand::MO_FPImmediate);
747
30.3k
    Op.Contents.CFP = CFP;
748
30.3k
    return Op;
749
30.3k
  }
750
751
  static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
752
                                  bool isKill = false, bool isDead = false,
753
                                  bool isUndef = false,
754
                                  bool isEarlyClobber = false,
755
                                  unsigned SubReg = 0, bool isDebug = false,
756
                                  bool isInternalRead = false,
757
124M
                                  bool isRenamable = false) {
758
124M
    assert(!(isDead && !isDef) && "Dead flag on non-def");
759
124M
    assert(!(isKill && isDef) && "Kill flag on def");
760
124M
    MachineOperand Op(MachineOperand::MO_Register);
761
124M
    Op.IsDef = isDef;
762
124M
    Op.IsImp = isImp;
763
124M
    Op.IsDeadOrKill = isKill | isDead;
764
124M
    Op.IsRenamable = isRenamable;
765
124M
    Op.IsUndef = isUndef;
766
124M
    Op.IsInternalRead = isInternalRead;
767
124M
    Op.IsEarlyClobber = isEarlyClobber;
768
124M
    Op.TiedTo = 0;
769
124M
    Op.IsDebug = isDebug;
770
124M
    Op.SmallContents.RegNo = Reg;
771
124M
    Op.Contents.Reg.Prev = nullptr;
772
124M
    Op.Contents.Reg.Next = nullptr;
773
124M
    Op.setSubReg(SubReg);
774
124M
    return Op;
775
124M
  }
776
  static MachineOperand CreateMBB(MachineBasicBlock *MBB,
777
15.8M
                                  unsigned char TargetFlags = 0) {
778
15.8M
    MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
779
15.8M
    Op.setMBB(MBB);
780
15.8M
    Op.setTargetFlags(TargetFlags);
781
15.8M
    return Op;
782
15.8M
  }
783
1.33M
  static MachineOperand CreateFI(int Idx) {
784
1.33M
    MachineOperand Op(MachineOperand::MO_FrameIndex);
785
1.33M
    Op.setIndex(Idx);
786
1.33M
    return Op;
787
1.33M
  }
788
  static MachineOperand CreateCPI(unsigned Idx, int Offset,
789
145k
                                  unsigned char TargetFlags = 0) {
790
145k
    MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
791
145k
    Op.setIndex(Idx);
792
145k
    Op.setOffset(Offset);
793
145k
    Op.setTargetFlags(TargetFlags);
794
145k
    return Op;
795
145k
  }
796
  static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
797
3
                                          unsigned char TargetFlags = 0) {
798
3
    MachineOperand Op(MachineOperand::MO_TargetIndex);
799
3
    Op.setIndex(Idx);
800
3
    Op.setOffset(Offset);
801
3
    Op.setTargetFlags(TargetFlags);
802
3
    return Op;
803
3
  }
804
5.27k
  static MachineOperand CreateJTI(unsigned Idx, unsigned char TargetFlags = 0) {
805
5.27k
    MachineOperand Op(MachineOperand::MO_JumpTableIndex);
806
5.27k
    Op.setIndex(Idx);
807
5.27k
    Op.setTargetFlags(TargetFlags);
808
5.27k
    return Op;
809
5.27k
  }
810
  static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
811
3.77M
                                 unsigned char TargetFlags = 0) {
812
3.77M
    MachineOperand Op(MachineOperand::MO_GlobalAddress);
813
3.77M
    Op.Contents.OffsetedInfo.Val.GV = GV;
814
3.77M
    Op.setOffset(Offset);
815
3.77M
    Op.setTargetFlags(TargetFlags);
816
3.77M
    return Op;
817
3.77M
  }
818
  static MachineOperand CreateES(const char *SymName,
819
84.3k
                                 unsigned char TargetFlags = 0) {
820
84.3k
    MachineOperand Op(MachineOperand::MO_ExternalSymbol);
821
84.3k
    Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
822
84.3k
    Op.setOffset(0); // Offset is always 0.
823
84.3k
    Op.setTargetFlags(TargetFlags);
824
84.3k
    return Op;
825
84.3k
  }
826
  static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
827
145
                                 unsigned char TargetFlags = 0) {
828
145
    MachineOperand Op(MachineOperand::MO_BlockAddress);
829
145
    Op.Contents.OffsetedInfo.Val.BA = BA;
830
145
    Op.setOffset(Offset);
831
145
    Op.setTargetFlags(TargetFlags);
832
145
    return Op;
833
145
  }
834
  /// CreateRegMask - Creates a register mask operand referencing Mask.  The
835
  /// operand does not take ownership of the memory referenced by Mask, it
836
  /// must remain valid for the lifetime of the operand.
837
  ///
838
  /// A RegMask operand represents a set of non-clobbered physical registers
839
  /// on an instruction that clobbers many registers, typically a call.  The
840
  /// bit mask has a bit set for each physreg that is preserved by this
841
  /// instruction, as described in the documentation for
842
  /// TargetRegisterInfo::getCallPreservedMask().
843
  ///
844
  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
845
  ///
846
1.98M
  static MachineOperand CreateRegMask(const uint32_t *Mask) {
847
1.98M
    assert(Mask && "Missing register mask");
848
1.98M
    MachineOperand Op(MachineOperand::MO_RegisterMask);
849
1.98M
    Op.Contents.RegMask = Mask;
850
1.98M
    return Op;
851
1.98M
  }
852
180
  static MachineOperand CreateRegLiveOut(const uint32_t *Mask) {
853
180
    assert(Mask && "Missing live-out register mask");
854
180
    MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
855
180
    Op.Contents.RegMask = Mask;
856
180
    return Op;
857
180
  }
858
13.4k
  static MachineOperand CreateMetadata(const MDNode *Meta) {
859
13.4k
    MachineOperand Op(MachineOperand::MO_Metadata);
860
13.4k
    Op.Contents.MD = Meta;
861
13.4k
    return Op;
862
13.4k
  }
863
864
  static MachineOperand CreateMCSymbol(MCSymbol *Sym,
865
101k
                                       unsigned char TargetFlags = 0) {
866
101k
    MachineOperand Op(MachineOperand::MO_MCSymbol);
867
101k
    Op.Contents.Sym = Sym;
868
101k
    Op.setOffset(0);
869
101k
    Op.setTargetFlags(TargetFlags);
870
101k
    return Op;
871
101k
  }
872
873
472k
  static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
874
472k
    MachineOperand Op(MachineOperand::MO_CFIIndex);
875
472k
    Op.Contents.CFIIndex = CFIIndex;
876
472k
    return Op;
877
472k
  }
878
879
161k
  static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) {
880
161k
    MachineOperand Op(MachineOperand::MO_IntrinsicID);
881
161k
    Op.Contents.IntrinsicID = ID;
882
161k
    return Op;
883
161k
  }
884
885
1.07M
  static MachineOperand CreatePredicate(unsigned Pred) {
886
1.07M
    MachineOperand Op(MachineOperand::MO_Predicate);
887
1.07M
    Op.Contents.Pred = Pred;
888
1.07M
    return Op;
889
1.07M
  }
890
891
  friend class MachineInstr;
892
  friend class MachineRegisterInfo;
893
894
private:
895
  // If this operand is currently a register operand, and if this is in a
896
  // function, deregister the operand from the register's use/def list.
897
  void removeRegFromUses();
898
899
  /// Artificial kinds for DenseMap usage.
900
  enum : unsigned char {
901
    MO_Empty = MO_Last + 1,
902
    MO_Tombstone,
903
  };
904
905
  friend struct DenseMapInfo<MachineOperand>;
906
907
  //===--------------------------------------------------------------------===//
908
  // Methods for handling register use/def lists.
909
  //===--------------------------------------------------------------------===//
910
911
  /// isOnRegUseList - Return true if this operand is on a register use/def
912
  /// list or false if not.  This can only be called for register operands
913
  /// that are part of a machine instruction.
914
103k
  bool isOnRegUseList() const {
915
103k
    assert(isReg() && "Can only add reg operand to use lists");
916
103k
    return Contents.Reg.Prev != nullptr;
917
103k
  }
918
};
919
920
template <> struct DenseMapInfo<MachineOperand> {
921
2.40k
  static MachineOperand getEmptyKey() {
922
2.40k
    return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
923
2.40k
        MachineOperand::MO_Empty));
924
2.40k
  }
925
1.26k
  static MachineOperand getTombstoneKey() {
926
1.26k
    return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
927
1.26k
        MachineOperand::MO_Tombstone));
928
1.26k
  }
929
743
  static unsigned getHashValue(const MachineOperand &MO) {
930
743
    return hash_value(MO);
931
743
  }
932
35.8k
  static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
933
35.8k
    if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
934
35.8k
                             MachineOperand::MO_Empty) ||
935
35.8k
        LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
936
1.98k
                             MachineOperand::MO_Tombstone))
937
33.8k
      return LHS.getType() == RHS.getType();
938
1.98k
    return LHS.isIdenticalTo(RHS);
939
1.98k
  }
940
};
941
942
0
inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) {
943
0
  MO.print(OS);
944
0
  return OS;
945
0
}
946
947
// See friend declaration above. This additional declaration is required in
948
// order to compile LLVM with IBM xlC compiler.
949
hash_code hash_value(const MachineOperand &MO);
950
} // namespace llvm
951
952
#endif