/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/MachineOperand.h
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1 | | //===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | // This file contains the declaration of the MachineOperand class. |
10 | | // |
11 | | //===----------------------------------------------------------------------===// |
12 | | |
13 | | #ifndef LLVM_CODEGEN_MACHINEOPERAND_H |
14 | | #define LLVM_CODEGEN_MACHINEOPERAND_H |
15 | | |
16 | | #include "llvm/ADT/DenseMap.h" |
17 | | #include "llvm/CodeGen/Register.h" |
18 | | #include "llvm/IR/Intrinsics.h" |
19 | | #include "llvm/Support/DataTypes.h" |
20 | | #include "llvm/Support/LowLevelTypeImpl.h" |
21 | | #include <cassert> |
22 | | |
23 | | namespace llvm { |
24 | | |
25 | | class BlockAddress; |
26 | | class ConstantFP; |
27 | | class ConstantInt; |
28 | | class GlobalValue; |
29 | | class MachineBasicBlock; |
30 | | class MachineInstr; |
31 | | class MachineRegisterInfo; |
32 | | class MCCFIInstruction; |
33 | | class MDNode; |
34 | | class ModuleSlotTracker; |
35 | | class TargetMachine; |
36 | | class TargetIntrinsicInfo; |
37 | | class TargetRegisterInfo; |
38 | | class hash_code; |
39 | | class raw_ostream; |
40 | | class MCSymbol; |
41 | | |
42 | | /// MachineOperand class - Representation of each machine instruction operand. |
43 | | /// |
44 | | /// This class isn't a POD type because it has a private constructor, but its |
45 | | /// destructor must be trivial. Functions like MachineInstr::addOperand(), |
46 | | /// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on |
47 | | /// not having to call the MachineOperand destructor. |
48 | | /// |
49 | | class MachineOperand { |
50 | | public: |
51 | | enum MachineOperandType : unsigned char { |
52 | | MO_Register, ///< Register operand. |
53 | | MO_Immediate, ///< Immediate operand |
54 | | MO_CImmediate, ///< Immediate >64bit operand |
55 | | MO_FPImmediate, ///< Floating-point immediate operand |
56 | | MO_MachineBasicBlock, ///< MachineBasicBlock reference |
57 | | MO_FrameIndex, ///< Abstract Stack Frame Index |
58 | | MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool |
59 | | MO_TargetIndex, ///< Target-dependent index+offset operand. |
60 | | MO_JumpTableIndex, ///< Address of indexed Jump Table for switch |
61 | | MO_ExternalSymbol, ///< Name of external global symbol |
62 | | MO_GlobalAddress, ///< Address of a global value |
63 | | MO_BlockAddress, ///< Address of a basic block |
64 | | MO_RegisterMask, ///< Mask of preserved registers. |
65 | | MO_RegisterLiveOut, ///< Mask of live-out registers. |
66 | | MO_Metadata, ///< Metadata reference (for debug info) |
67 | | MO_MCSymbol, ///< MCSymbol reference (for debug/eh info) |
68 | | MO_CFIIndex, ///< MCCFIInstruction index. |
69 | | MO_IntrinsicID, ///< Intrinsic ID for ISel |
70 | | MO_Predicate, ///< Generic predicate for ISel |
71 | | MO_Last = MO_Predicate, |
72 | | }; |
73 | | |
74 | | private: |
75 | | /// OpKind - Specify what kind of operand this is. This discriminates the |
76 | | /// union. |
77 | | unsigned OpKind : 8; |
78 | | |
79 | | /// Subregister number for MO_Register. A value of 0 indicates the |
80 | | /// MO_Register has no subReg. |
81 | | /// |
82 | | /// For all other kinds of operands, this field holds target-specific flags. |
83 | | unsigned SubReg_TargetFlags : 12; |
84 | | |
85 | | /// TiedTo - Non-zero when this register operand is tied to another register |
86 | | /// operand. The encoding of this field is described in the block comment |
87 | | /// before MachineInstr::tieOperands(). |
88 | | unsigned TiedTo : 4; |
89 | | |
90 | | /// IsDef - True if this is a def, false if this is a use of the register. |
91 | | /// This is only valid on register operands. |
92 | | /// |
93 | | unsigned IsDef : 1; |
94 | | |
95 | | /// IsImp - True if this is an implicit def or use, false if it is explicit. |
96 | | /// This is only valid on register opderands. |
97 | | /// |
98 | | unsigned IsImp : 1; |
99 | | |
100 | | /// IsDeadOrKill |
101 | | /// For uses: IsKill - True if this instruction is the last use of the |
102 | | /// register on this path through the function. |
103 | | /// For defs: IsDead - True if this register is never used by a subsequent |
104 | | /// instruction. |
105 | | /// This is only valid on register operands. |
106 | | unsigned IsDeadOrKill : 1; |
107 | | |
108 | | /// See isRenamable(). |
109 | | unsigned IsRenamable : 1; |
110 | | |
111 | | /// IsUndef - True if this register operand reads an "undef" value, i.e. the |
112 | | /// read value doesn't matter. This flag can be set on both use and def |
113 | | /// operands. On a sub-register def operand, it refers to the part of the |
114 | | /// register that isn't written. On a full-register def operand, it is a |
115 | | /// noop. See readsReg(). |
116 | | /// |
117 | | /// This is only valid on registers. |
118 | | /// |
119 | | /// Note that an instruction may have multiple <undef> operands referring to |
120 | | /// the same register. In that case, the instruction may depend on those |
121 | | /// operands reading the same dont-care value. For example: |
122 | | /// |
123 | | /// %1 = XOR undef %2, undef %2 |
124 | | /// |
125 | | /// Any register can be used for %2, and its value doesn't matter, but |
126 | | /// the two operands must be the same register. |
127 | | /// |
128 | | unsigned IsUndef : 1; |
129 | | |
130 | | /// IsInternalRead - True if this operand reads a value that was defined |
131 | | /// inside the same instruction or bundle. This flag can be set on both use |
132 | | /// and def operands. On a sub-register def operand, it refers to the part |
133 | | /// of the register that isn't written. On a full-register def operand, it |
134 | | /// is a noop. |
135 | | /// |
136 | | /// When this flag is set, the instruction bundle must contain at least one |
137 | | /// other def of the register. If multiple instructions in the bundle define |
138 | | /// the register, the meaning is target-defined. |
139 | | unsigned IsInternalRead : 1; |
140 | | |
141 | | /// IsEarlyClobber - True if this MO_Register 'def' operand is written to |
142 | | /// by the MachineInstr before all input registers are read. This is used to |
143 | | /// model the GCC inline asm '&' constraint modifier. |
144 | | unsigned IsEarlyClobber : 1; |
145 | | |
146 | | /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo, |
147 | | /// not a real instruction. Such uses should be ignored during codegen. |
148 | | unsigned IsDebug : 1; |
149 | | |
150 | | /// SmallContents - This really should be part of the Contents union, but |
151 | | /// lives out here so we can get a better packed struct. |
152 | | /// MO_Register: Register number. |
153 | | /// OffsetedInfo: Low bits of offset. |
154 | | union { |
155 | | unsigned RegNo; // For MO_Register. |
156 | | unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi. |
157 | | } SmallContents; |
158 | | |
159 | | /// ParentMI - This is the instruction that this operand is embedded into. |
160 | | /// This is valid for all operand types, when the operand is in an instr. |
161 | | MachineInstr *ParentMI; |
162 | | |
163 | | /// Contents union - This contains the payload for the various operand types. |
164 | | union { |
165 | | MachineBasicBlock *MBB; // For MO_MachineBasicBlock. |
166 | | const ConstantFP *CFP; // For MO_FPImmediate. |
167 | | const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit. |
168 | | int64_t ImmVal; // For MO_Immediate. |
169 | | const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut. |
170 | | const MDNode *MD; // For MO_Metadata. |
171 | | MCSymbol *Sym; // For MO_MCSymbol. |
172 | | unsigned CFIIndex; // For MO_CFI. |
173 | | Intrinsic::ID IntrinsicID; // For MO_IntrinsicID. |
174 | | unsigned Pred; // For MO_Predicate |
175 | | |
176 | | struct { // For MO_Register. |
177 | | // Register number is in SmallContents.RegNo. |
178 | | MachineOperand *Prev; // Access list for register. See MRI. |
179 | | MachineOperand *Next; |
180 | | } Reg; |
181 | | |
182 | | /// OffsetedInfo - This struct contains the offset and an object identifier. |
183 | | /// this represent the object as with an optional offset from it. |
184 | | struct { |
185 | | union { |
186 | | int Index; // For MO_*Index - The index itself. |
187 | | const char *SymbolName; // For MO_ExternalSymbol. |
188 | | const GlobalValue *GV; // For MO_GlobalAddress. |
189 | | const BlockAddress *BA; // For MO_BlockAddress. |
190 | | } Val; |
191 | | // Low bits of offset are in SmallContents.OffsetLo. |
192 | | int OffsetHi; // An offset from the object, high 32 bits. |
193 | | } OffsetedInfo; |
194 | | } Contents; |
195 | | |
196 | | explicit MachineOperand(MachineOperandType K) |
197 | 221M | : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) { |
198 | 221M | // Assert that the layout is what we expect. It's easy to grow this object. |
199 | 221M | static_assert(alignof(MachineOperand) <= alignof(int64_t), |
200 | 221M | "MachineOperand shouldn't be more than 8 byte aligned"); |
201 | 221M | static_assert(sizeof(Contents) <= 2 * sizeof(void *), |
202 | 221M | "Contents should be at most two pointers"); |
203 | 221M | static_assert(sizeof(MachineOperand) <= |
204 | 221M | alignTo<alignof(int64_t)>(2 * sizeof(unsigned) + |
205 | 221M | 3 * sizeof(void *)), |
206 | 221M | "MachineOperand too big. Should be Kind, SmallContents, " |
207 | 221M | "ParentMI, and Contents"); |
208 | 221M | } |
209 | | |
210 | | public: |
211 | | /// getType - Returns the MachineOperandType for this operand. |
212 | | /// |
213 | 748M | MachineOperandType getType() const { return (MachineOperandType)OpKind; } |
214 | | |
215 | 264M | unsigned getTargetFlags() const { |
216 | 264M | return isReg() ? 0146M : SubReg_TargetFlags118M ; |
217 | 264M | } |
218 | 18.4M | void setTargetFlags(unsigned F) { |
219 | 18.4M | assert(!isReg() && "Register operands can't have target flags"); |
220 | 18.4M | SubReg_TargetFlags = F; |
221 | 18.4M | assert(SubReg_TargetFlags == F && "Target flags out of range"); |
222 | 18.4M | } |
223 | 0 | void addTargetFlag(unsigned F) { |
224 | 0 | assert(!isReg() && "Register operands can't have target flags"); |
225 | 0 | SubReg_TargetFlags |= F; |
226 | 0 | assert((SubReg_TargetFlags & F) && "Target flags out of range"); |
227 | 0 | } |
228 | | |
229 | | |
230 | | /// getParent - Return the instruction that this operand belongs to. |
231 | | /// |
232 | 401M | MachineInstr *getParent() { return ParentMI; } |
233 | 452M | const MachineInstr *getParent() const { return ParentMI; } |
234 | | |
235 | | /// clearParent - Reset the parent pointer. |
236 | | /// |
237 | | /// The MachineOperand copy constructor also copies ParentMI, expecting the |
238 | | /// original to be deleted. If a MachineOperand is ever stored outside a |
239 | | /// MachineInstr, the parent pointer must be cleared. |
240 | | /// |
241 | | /// Never call clearParent() on an operand in a MachineInstr. |
242 | | /// |
243 | 4.88k | void clearParent() { ParentMI = nullptr; } |
244 | | |
245 | | /// Print a subreg index operand. |
246 | | /// MO_Immediate operands can also be subreg idices. If it's the case, the |
247 | | /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be |
248 | | /// called to check this. |
249 | | static void printSubRegIdx(raw_ostream &OS, uint64_t Index, |
250 | | const TargetRegisterInfo *TRI); |
251 | | |
252 | | /// Print operand target flags. |
253 | | static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op); |
254 | | |
255 | | /// Print a MCSymbol as an operand. |
256 | | static void printSymbol(raw_ostream &OS, MCSymbol &Sym); |
257 | | |
258 | | /// Print a stack object reference. |
259 | | static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, |
260 | | bool IsFixed, StringRef Name); |
261 | | |
262 | | /// Print the offset with explicit +/- signs. |
263 | | static void printOperandOffset(raw_ostream &OS, int64_t Offset); |
264 | | |
265 | | /// Print an IRSlotNumber. |
266 | | static void printIRSlotNumber(raw_ostream &OS, int Slot); |
267 | | |
268 | | /// Print the MachineOperand to \p os. |
269 | | /// Providing a valid \p TRI and \p IntrinsicInfo results in a more |
270 | | /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the |
271 | | /// function will try to pick it up from the parent. |
272 | | void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr, |
273 | | const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const; |
274 | | |
275 | | /// More complex way of printing a MachineOperand. |
276 | | /// \param TypeToPrint specifies the generic type to be printed on uses and |
277 | | /// defs. It can be determined using MachineInstr::getTypeToPrint. |
278 | | /// \param PrintDef - whether we want to print `def` on an operand which |
279 | | /// isDef. Sometimes, if the operand is printed before '=', we don't print |
280 | | /// `def`. |
281 | | /// \param IsStandalone - whether we want a verbose output of the MO. This |
282 | | /// prints extra information that can be easily inferred when printing the |
283 | | /// whole function, but not when printing only a fragment of it. |
284 | | /// \param ShouldPrintRegisterTies - whether we want to print register ties. |
285 | | /// Sometimes they are easily determined by the instruction's descriptor |
286 | | /// (MachineInstr::hasComplexRegiterTies can determine if it's needed). |
287 | | /// \param TiedOperandIdx - if we need to print register ties this needs to |
288 | | /// provide the index of the tied register. If not, it will be ignored. |
289 | | /// \param TRI - provide more target-specific information to the printer. |
290 | | /// Unlike the previous function, this one will not try and get the |
291 | | /// information from it's parent. |
292 | | /// \param IntrinsicInfo - same as \p TRI. |
293 | | void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint, |
294 | | bool PrintDef, bool IsStandalone, bool ShouldPrintRegisterTies, |
295 | | unsigned TiedOperandIdx, const TargetRegisterInfo *TRI, |
296 | | const TargetIntrinsicInfo *IntrinsicInfo) const; |
297 | | |
298 | | /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level |
299 | | /// type to be printed the same way the full version of print(...) does it. |
300 | | void print(raw_ostream &os, LLT TypeToPrint, |
301 | | const TargetRegisterInfo *TRI = nullptr, |
302 | | const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const; |
303 | | |
304 | | void dump() const; |
305 | | |
306 | | //===--------------------------------------------------------------------===// |
307 | | // Accessors that tell you what kind of MachineOperand you're looking at. |
308 | | //===--------------------------------------------------------------------===// |
309 | | |
310 | | /// isReg - Tests if this is a MO_Register operand. |
311 | 4.47G | bool isReg() const { return OpKind == MO_Register; } |
312 | | /// isImm - Tests if this is a MO_Immediate operand. |
313 | 126M | bool isImm() const { return OpKind == MO_Immediate; } |
314 | | /// isCImm - Test if this is a MO_CImmediate operand. |
315 | 15.6M | bool isCImm() const { return OpKind == MO_CImmediate; } |
316 | | /// isFPImm - Tests if this is a MO_FPImmediate operand. |
317 | 58.3M | bool isFPImm() const { return OpKind == MO_FPImmediate; } |
318 | | /// isMBB - Tests if this is a MO_MachineBasicBlock operand. |
319 | 10.7M | bool isMBB() const { return OpKind == MO_MachineBasicBlock; } |
320 | | /// isFI - Tests if this is a MO_FrameIndex operand. |
321 | 328M | bool isFI() const { return OpKind == MO_FrameIndex; } |
322 | | /// isCPI - Tests if this is a MO_ConstantPoolIndex operand. |
323 | 4.62M | bool isCPI() const { return OpKind == MO_ConstantPoolIndex; } |
324 | | /// isTargetIndex - Tests if this is a MO_TargetIndex operand. |
325 | 5.08k | bool isTargetIndex() const { return OpKind == MO_TargetIndex; } |
326 | | /// isJTI - Tests if this is a MO_JumpTableIndex operand. |
327 | 25.8M | bool isJTI() const { return OpKind == MO_JumpTableIndex; } |
328 | | /// isGlobal - Tests if this is a MO_GlobalAddress operand. |
329 | 24.0M | bool isGlobal() const { return OpKind == MO_GlobalAddress; } |
330 | | /// isSymbol - Tests if this is a MO_ExternalSymbol operand. |
331 | 1.01M | bool isSymbol() const { return OpKind == MO_ExternalSymbol; } |
332 | | /// isBlockAddress - Tests if this is a MO_BlockAddress operand. |
333 | 564k | bool isBlockAddress() const { return OpKind == MO_BlockAddress; } |
334 | | /// isRegMask - Tests if this is a MO_RegisterMask operand. |
335 | 847M | bool isRegMask() const { return OpKind == MO_RegisterMask; } |
336 | | /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand. |
337 | 455 | bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; } |
338 | | /// isMetadata - Tests if this is a MO_Metadata operand. |
339 | 149k | bool isMetadata() const { return OpKind == MO_Metadata; } |
340 | 24.7k | bool isMCSymbol() const { return OpKind == MO_MCSymbol; } |
341 | 5.12k | bool isCFIIndex() const { return OpKind == MO_CFIIndex; } |
342 | 262k | bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; } |
343 | 1 | bool isPredicate() const { return OpKind == MO_Predicate; } |
344 | | //===--------------------------------------------------------------------===// |
345 | | // Accessors for Register Operands |
346 | | //===--------------------------------------------------------------------===// |
347 | | |
348 | | /// getReg - Returns the register number. |
349 | 3.13G | Register getReg() const { |
350 | 3.13G | assert(isReg() && "This is not a register operand!"); |
351 | 3.13G | return Register(SmallContents.RegNo); |
352 | 3.13G | } |
353 | | |
354 | 636M | unsigned getSubReg() const { |
355 | 636M | assert(isReg() && "Wrong MachineOperand accessor"); |
356 | 636M | return SubReg_TargetFlags; |
357 | 636M | } |
358 | | |
359 | 1.45G | bool isUse() const { |
360 | 1.45G | assert(isReg() && "Wrong MachineOperand accessor"); |
361 | 1.45G | return !IsDef; |
362 | 1.45G | } |
363 | | |
364 | 2.14G | bool isDef() const { |
365 | 2.14G | assert(isReg() && "Wrong MachineOperand accessor"); |
366 | 2.14G | return IsDef; |
367 | 2.14G | } |
368 | | |
369 | 469M | bool isImplicit() const { |
370 | 469M | assert(isReg() && "Wrong MachineOperand accessor"); |
371 | 469M | return IsImp; |
372 | 469M | } |
373 | | |
374 | 126M | bool isDead() const { |
375 | 126M | assert(isReg() && "Wrong MachineOperand accessor"); |
376 | 126M | return IsDeadOrKill & IsDef; |
377 | 126M | } |
378 | | |
379 | 176M | bool isKill() const { |
380 | 176M | assert(isReg() && "Wrong MachineOperand accessor"); |
381 | 176M | return IsDeadOrKill & !IsDef; |
382 | 176M | } |
383 | | |
384 | 606M | bool isUndef() const { |
385 | 606M | assert(isReg() && "Wrong MachineOperand accessor"); |
386 | 606M | return IsUndef; |
387 | 606M | } |
388 | | |
389 | | /// isRenamable - Returns true if this register may be renamed, i.e. it does |
390 | | /// not generate a value that is somehow read in a way that is not represented |
391 | | /// by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only |
392 | | /// valid on physical register operands. Virtual registers are assumed to |
393 | | /// always be renamable regardless of the value of this field. |
394 | | /// |
395 | | /// Operands that are renamable can freely be changed to any other register |
396 | | /// that is a member of the register class returned by |
397 | | /// MI->getRegClassConstraint(). |
398 | | /// |
399 | | /// isRenamable can return false for several different reasons: |
400 | | /// |
401 | | /// - ABI constraints (since liveness is not always precisely modeled). We |
402 | | /// conservatively handle these cases by setting all physical register |
403 | | /// operands that didn’t start out as virtual regs to not be renamable. |
404 | | /// Also any physical register operands created after register allocation or |
405 | | /// whose register is changed after register allocation will not be |
406 | | /// renamable. This state is tracked in the MachineOperand::IsRenamable |
407 | | /// bit. |
408 | | /// |
409 | | /// - Opcode/target constraints: for opcodes that have complex register class |
410 | | /// requirements (e.g. that depend on other operands/instructions), we set |
411 | | /// hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode |
412 | | /// description. Operands belonging to instructions with opcodes that are |
413 | | /// marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from |
414 | | /// isRenamable(). Additionally, the AllowRegisterRenaming target property |
415 | | /// prevents any operands from being marked renamable for targets that don't |
416 | | /// have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq |
417 | | /// values. |
418 | | bool isRenamable() const; |
419 | | |
420 | 385M | bool isInternalRead() const { |
421 | 385M | assert(isReg() && "Wrong MachineOperand accessor"); |
422 | 385M | return IsInternalRead; |
423 | 385M | } |
424 | | |
425 | 142M | bool isEarlyClobber() const { |
426 | 142M | assert(isReg() && "Wrong MachineOperand accessor"); |
427 | 142M | return IsEarlyClobber; |
428 | 142M | } |
429 | | |
430 | 264M | bool isTied() const { |
431 | 264M | assert(isReg() && "Wrong MachineOperand accessor"); |
432 | 264M | return TiedTo; |
433 | 264M | } |
434 | | |
435 | 521M | bool isDebug() const { |
436 | 521M | assert(isReg() && "Wrong MachineOperand accessor"); |
437 | 521M | return IsDebug; |
438 | 521M | } |
439 | | |
440 | | /// readsReg - Returns true if this operand reads the previous value of its |
441 | | /// register. A use operand with the <undef> flag set doesn't read its |
442 | | /// register. A sub-register def implicitly reads the other parts of the |
443 | | /// register being redefined unless the <undef> flag is set. |
444 | | /// |
445 | | /// This refers to reading the register value from before the current |
446 | | /// instruction or bundle. Internal bundle reads are not included. |
447 | 359M | bool readsReg() const { |
448 | 359M | assert(isReg() && "Wrong MachineOperand accessor"); |
449 | 359M | return !isUndef() && !isInternalRead()354M && (354M isUse()354M || getSubReg()106M ); |
450 | 359M | } |
451 | | |
452 | | //===--------------------------------------------------------------------===// |
453 | | // Mutators for Register Operands |
454 | | //===--------------------------------------------------------------------===// |
455 | | |
456 | | /// Change the register this operand corresponds to. |
457 | | /// |
458 | | void setReg(unsigned Reg); |
459 | | |
460 | 127M | void setSubReg(unsigned subReg) { |
461 | 127M | assert(isReg() && "Wrong MachineOperand mutator"); |
462 | 127M | SubReg_TargetFlags = subReg; |
463 | 127M | assert(SubReg_TargetFlags == subReg && "SubReg out of range"); |
464 | 127M | } |
465 | | |
466 | | /// substVirtReg - Substitute the current register with the virtual |
467 | | /// subregister Reg:SubReg. Take any existing SubReg index into account, |
468 | | /// using TargetRegisterInfo to compose the subreg indices if necessary. |
469 | | /// Reg must be a virtual register, SubIdx can be 0. |
470 | | /// |
471 | | void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&); |
472 | | |
473 | | /// substPhysReg - Substitute the current register with the physical register |
474 | | /// Reg, taking any existing SubReg into account. For instance, |
475 | | /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al. |
476 | | /// |
477 | | void substPhysReg(unsigned Reg, const TargetRegisterInfo&); |
478 | | |
479 | 740 | void setIsUse(bool Val = true) { setIsDef(!Val); } |
480 | | |
481 | | /// Change a def to a use, or a use to a def. |
482 | | void setIsDef(bool Val = true); |
483 | | |
484 | 12.8k | void setImplicit(bool Val = true) { |
485 | 12.8k | assert(isReg() && "Wrong MachineOperand mutator"); |
486 | 12.8k | IsImp = Val; |
487 | 12.8k | } |
488 | | |
489 | 113M | void setIsKill(bool Val = true) { |
490 | 113M | assert(isReg() && !IsDef && "Wrong MachineOperand mutator"); |
491 | 113M | assert((!Val || !isDebug()) && "Marking a debug operation as kill"); |
492 | 113M | IsDeadOrKill = Val; |
493 | 113M | } |
494 | | |
495 | 13.9M | void setIsDead(bool Val = true) { |
496 | 13.9M | assert(isReg() && IsDef && "Wrong MachineOperand mutator"); |
497 | 13.9M | IsDeadOrKill = Val; |
498 | 13.9M | } |
499 | | |
500 | 3.95M | void setIsUndef(bool Val = true) { |
501 | 3.95M | assert(isReg() && "Wrong MachineOperand mutator"); |
502 | 3.95M | IsUndef = Val; |
503 | 3.95M | } |
504 | | |
505 | | void setIsRenamable(bool Val = true); |
506 | | |
507 | 2.21M | void setIsInternalRead(bool Val = true) { |
508 | 2.21M | assert(isReg() && "Wrong MachineOperand mutator"); |
509 | 2.21M | IsInternalRead = Val; |
510 | 2.21M | } |
511 | | |
512 | 416k | void setIsEarlyClobber(bool Val = true) { |
513 | 416k | assert(isReg() && IsDef && "Wrong MachineOperand mutator"); |
514 | 416k | IsEarlyClobber = Val; |
515 | 416k | } |
516 | | |
517 | 1.00k | void setIsDebug(bool Val = true) { |
518 | 1.00k | assert(isReg() && !IsDef && "Wrong MachineOperand mutator"); |
519 | 1.00k | IsDebug = Val; |
520 | 1.00k | } |
521 | | |
522 | | //===--------------------------------------------------------------------===// |
523 | | // Accessors for various operand types. |
524 | | //===--------------------------------------------------------------------===// |
525 | | |
526 | 236M | int64_t getImm() const { |
527 | 236M | assert(isImm() && "Wrong MachineOperand accessor"); |
528 | 236M | return Contents.ImmVal; |
529 | 236M | } |
530 | | |
531 | 15.3M | const ConstantInt *getCImm() const { |
532 | 15.3M | assert(isCImm() && "Wrong MachineOperand accessor"); |
533 | 15.3M | return Contents.CI; |
534 | 15.3M | } |
535 | | |
536 | 247k | const ConstantFP *getFPImm() const { |
537 | 247k | assert(isFPImm() && "Wrong MachineOperand accessor"); |
538 | 247k | return Contents.CFP; |
539 | 247k | } |
540 | | |
541 | 96.9M | MachineBasicBlock *getMBB() const { |
542 | 96.9M | assert(isMBB() && "Wrong MachineOperand accessor"); |
543 | 96.9M | return Contents.MBB; |
544 | 96.9M | } |
545 | | |
546 | 7.57M | int getIndex() const { |
547 | 7.57M | assert((isFI() || isCPI() || isTargetIndex() || isJTI()) && |
548 | 7.57M | "Wrong MachineOperand accessor"); |
549 | 7.57M | return Contents.OffsetedInfo.Val.Index; |
550 | 7.57M | } |
551 | | |
552 | 20.3M | const GlobalValue *getGlobal() const { |
553 | 20.3M | assert(isGlobal() && "Wrong MachineOperand accessor"); |
554 | 20.3M | return Contents.OffsetedInfo.Val.GV; |
555 | 20.3M | } |
556 | | |
557 | 1.06k | const BlockAddress *getBlockAddress() const { |
558 | 1.06k | assert(isBlockAddress() && "Wrong MachineOperand accessor"); |
559 | 1.06k | return Contents.OffsetedInfo.Val.BA; |
560 | 1.06k | } |
561 | | |
562 | 543k | MCSymbol *getMCSymbol() const { |
563 | 543k | assert(isMCSymbol() && "Wrong MachineOperand accessor"); |
564 | 543k | return Contents.Sym; |
565 | 543k | } |
566 | | |
567 | 446k | unsigned getCFIIndex() const { |
568 | 446k | assert(isCFIIndex() && "Wrong MachineOperand accessor"); |
569 | 446k | return Contents.CFIIndex; |
570 | 446k | } |
571 | | |
572 | 370k | Intrinsic::ID getIntrinsicID() const { |
573 | 370k | assert(isIntrinsicID() && "Wrong MachineOperand accessor"); |
574 | 370k | return Contents.IntrinsicID; |
575 | 370k | } |
576 | | |
577 | 1.76M | unsigned getPredicate() const { |
578 | 1.76M | assert(isPredicate() && "Wrong MachineOperand accessor"); |
579 | 1.76M | return Contents.Pred; |
580 | 1.76M | } |
581 | | |
582 | | /// Return the offset from the symbol in this operand. This always returns 0 |
583 | | /// for ExternalSymbol operands. |
584 | 17.4M | int64_t getOffset() const { |
585 | 17.4M | assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || |
586 | 17.4M | isTargetIndex() || isBlockAddress()) && |
587 | 17.4M | "Wrong MachineOperand accessor"); |
588 | 17.4M | return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) | |
589 | 17.4M | SmallContents.OffsetLo; |
590 | 17.4M | } |
591 | | |
592 | 277k | const char *getSymbolName() const { |
593 | 277k | assert(isSymbol() && "Wrong MachineOperand accessor"); |
594 | 277k | return Contents.OffsetedInfo.Val.SymbolName; |
595 | 277k | } |
596 | | |
597 | | /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg. |
598 | | /// It is sometimes necessary to detach the register mask pointer from its |
599 | | /// machine operand. This static method can be used for such detached bit |
600 | | /// mask pointers. |
601 | 293M | static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) { |
602 | 293M | // See TargetRegisterInfo.h. |
603 | 293M | assert(PhysReg < (1u << 30) && "Not a physical register"); |
604 | 293M | return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32)); |
605 | 293M | } |
606 | | |
607 | | /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg. |
608 | 34.2M | bool clobbersPhysReg(unsigned PhysReg) const { |
609 | 34.2M | return clobbersPhysReg(getRegMask(), PhysReg); |
610 | 34.2M | } |
611 | | |
612 | | /// getRegMask - Returns a bit mask of registers preserved by this RegMask |
613 | | /// operand. |
614 | 58.6M | const uint32_t *getRegMask() const { |
615 | 58.6M | assert(isRegMask() && "Wrong MachineOperand accessor"); |
616 | 58.6M | return Contents.RegMask; |
617 | 58.6M | } |
618 | | |
619 | | /// Returns number of elements needed for a regmask array. |
620 | 408 | static unsigned getRegMaskSize(unsigned NumRegs) { |
621 | 408 | return (NumRegs + 31) / 32; |
622 | 408 | } |
623 | | |
624 | | /// getRegLiveOut - Returns a bit mask of live-out registers. |
625 | 184 | const uint32_t *getRegLiveOut() const { |
626 | 184 | assert(isRegLiveOut() && "Wrong MachineOperand accessor"); |
627 | 184 | return Contents.RegMask; |
628 | 184 | } |
629 | | |
630 | 24.1M | const MDNode *getMetadata() const { |
631 | 24.1M | assert(isMetadata() && "Wrong MachineOperand accessor"); |
632 | 24.1M | return Contents.MD; |
633 | 24.1M | } |
634 | | |
635 | | //===--------------------------------------------------------------------===// |
636 | | // Mutators for various operand types. |
637 | | //===--------------------------------------------------------------------===// |
638 | | |
639 | 78.1M | void setImm(int64_t immVal) { |
640 | 78.1M | assert(isImm() && "Wrong MachineOperand mutator"); |
641 | 78.1M | Contents.ImmVal = immVal; |
642 | 78.1M | } |
643 | | |
644 | 24.2k | void setCImm(const ConstantInt *CI) { |
645 | 24.2k | assert(isCImm() && "Wrong MachineOperand mutator"); |
646 | 24.2k | Contents.CI = CI; |
647 | 24.2k | } |
648 | | |
649 | 6 | void setFPImm(const ConstantFP *CFP) { |
650 | 6 | assert(isFPImm() && "Wrong MachineOperand mutator"); |
651 | 6 | Contents.CFP = CFP; |
652 | 6 | } |
653 | | |
654 | 3.58M | void setOffset(int64_t Offset) { |
655 | 3.58M | assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || |
656 | 3.58M | isTargetIndex() || isBlockAddress()) && |
657 | 3.58M | "Wrong MachineOperand mutator"); |
658 | 3.58M | SmallContents.OffsetLo = unsigned(Offset); |
659 | 3.58M | Contents.OffsetedInfo.OffsetHi = int(Offset >> 32); |
660 | 3.58M | } |
661 | | |
662 | 1.51M | void setIndex(int Idx) { |
663 | 1.51M | assert((isFI() || isCPI() || isTargetIndex() || isJTI()) && |
664 | 1.51M | "Wrong MachineOperand mutator"); |
665 | 1.51M | Contents.OffsetedInfo.Val.Index = Idx; |
666 | 1.51M | } |
667 | | |
668 | 131 | void setMetadata(const MDNode *MD) { |
669 | 131 | assert(isMetadata() && "Wrong MachineOperand mutator"); |
670 | 131 | Contents.MD = MD; |
671 | 131 | } |
672 | | |
673 | 15.6M | void setMBB(MachineBasicBlock *MBB) { |
674 | 15.6M | assert(isMBB() && "Wrong MachineOperand mutator"); |
675 | 15.6M | Contents.MBB = MBB; |
676 | 15.6M | } |
677 | | |
678 | | /// Sets value of register mask operand referencing Mask. The |
679 | | /// operand does not take ownership of the memory referenced by Mask, it must |
680 | | /// remain valid for the lifetime of the operand. See CreateRegMask(). |
681 | | /// Any physreg with a 0 bit in the mask is clobbered by the instruction. |
682 | 82 | void setRegMask(const uint32_t *RegMaskPtr) { |
683 | 82 | assert(isRegMask() && "Wrong MachineOperand mutator"); |
684 | 82 | Contents.RegMask = RegMaskPtr; |
685 | 82 | } |
686 | | |
687 | 380k | void setPredicate(unsigned Predicate) { |
688 | 380k | assert(isPredicate() && "Wrong MachineOperand mutator"); |
689 | 380k | Contents.Pred = Predicate; |
690 | 380k | } |
691 | | |
692 | | //===--------------------------------------------------------------------===// |
693 | | // Other methods. |
694 | | //===--------------------------------------------------------------------===// |
695 | | |
696 | | /// Returns true if this operand is identical to the specified operand except |
697 | | /// for liveness related flags (isKill, isUndef and isDead). Note that this |
698 | | /// should stay in sync with the hash_value overload below. |
699 | | bool isIdenticalTo(const MachineOperand &Other) const; |
700 | | |
701 | | /// MachineOperand hash_value overload. |
702 | | /// |
703 | | /// Note that this includes the same information in the hash that |
704 | | /// isIdenticalTo uses for comparison. It is thus suited for use in hash |
705 | | /// tables which use that function for equality comparisons only. This must |
706 | | /// stay exactly in sync with isIdenticalTo above. |
707 | | friend hash_code hash_value(const MachineOperand &MO); |
708 | | |
709 | | /// ChangeToImmediate - Replace this operand with a new immediate operand of |
710 | | /// the specified value. If an operand is known to be an immediate already, |
711 | | /// the setImm method should be used. |
712 | | void ChangeToImmediate(int64_t ImmVal); |
713 | | |
714 | | /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand |
715 | | /// of the specified value. If an operand is known to be an FP immediate |
716 | | /// already, the setFPImm method should be used. |
717 | | void ChangeToFPImmediate(const ConstantFP *FPImm); |
718 | | |
719 | | /// ChangeToES - Replace this operand with a new external symbol operand. |
720 | | void ChangeToES(const char *SymName, unsigned char TargetFlags = 0); |
721 | | |
722 | | /// ChangeToGA - Replace this operand with a new global address operand. |
723 | | void ChangeToGA(const GlobalValue *GV, int64_t Offset, |
724 | | unsigned char TargetFlags = 0); |
725 | | |
726 | | /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand. |
727 | | void ChangeToMCSymbol(MCSymbol *Sym); |
728 | | |
729 | | /// Replace this operand with a frame index. |
730 | | void ChangeToFrameIndex(int Idx); |
731 | | |
732 | | /// Replace this operand with a target index. |
733 | | void ChangeToTargetIndex(unsigned Idx, int64_t Offset, |
734 | | unsigned char TargetFlags = 0); |
735 | | |
736 | | /// ChangeToRegister - Replace this operand with a new register operand of |
737 | | /// the specified value. If an operand is known to be an register already, |
738 | | /// the setReg method should be used. |
739 | | void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false, |
740 | | bool isKill = false, bool isDead = false, |
741 | | bool isUndef = false, bool isDebug = false); |
742 | | |
743 | | //===--------------------------------------------------------------------===// |
744 | | // Construction methods. |
745 | | //===--------------------------------------------------------------------===// |
746 | | |
747 | 72.0M | static MachineOperand CreateImm(int64_t Val) { |
748 | 72.0M | MachineOperand Op(MachineOperand::MO_Immediate); |
749 | 72.0M | Op.setImm(Val); |
750 | 72.0M | return Op; |
751 | 72.0M | } |
752 | | |
753 | 5.79M | static MachineOperand CreateCImm(const ConstantInt *CI) { |
754 | 5.79M | MachineOperand Op(MachineOperand::MO_CImmediate); |
755 | 5.79M | Op.Contents.CI = CI; |
756 | 5.79M | return Op; |
757 | 5.79M | } |
758 | | |
759 | 57.4k | static MachineOperand CreateFPImm(const ConstantFP *CFP) { |
760 | 57.4k | MachineOperand Op(MachineOperand::MO_FPImmediate); |
761 | 57.4k | Op.Contents.CFP = CFP; |
762 | 57.4k | return Op; |
763 | 57.4k | } |
764 | | |
765 | | static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false, |
766 | | bool isKill = false, bool isDead = false, |
767 | | bool isUndef = false, |
768 | | bool isEarlyClobber = false, |
769 | | unsigned SubReg = 0, bool isDebug = false, |
770 | | bool isInternalRead = false, |
771 | 121M | bool isRenamable = false) { |
772 | 121M | assert(!(isDead && !isDef) && "Dead flag on non-def"); |
773 | 121M | assert(!(isKill && isDef) && "Kill flag on def"); |
774 | 121M | MachineOperand Op(MachineOperand::MO_Register); |
775 | 121M | Op.IsDef = isDef; |
776 | 121M | Op.IsImp = isImp; |
777 | 121M | Op.IsDeadOrKill = isKill | isDead; |
778 | 121M | Op.IsRenamable = isRenamable; |
779 | 121M | Op.IsUndef = isUndef; |
780 | 121M | Op.IsInternalRead = isInternalRead; |
781 | 121M | Op.IsEarlyClobber = isEarlyClobber; |
782 | 121M | Op.TiedTo = 0; |
783 | 121M | Op.IsDebug = isDebug; |
784 | 121M | Op.SmallContents.RegNo = Reg; |
785 | 121M | Op.Contents.Reg.Prev = nullptr; |
786 | 121M | Op.Contents.Reg.Next = nullptr; |
787 | 121M | Op.setSubReg(SubReg); |
788 | 121M | return Op; |
789 | 121M | } |
790 | | static MachineOperand CreateMBB(MachineBasicBlock *MBB, |
791 | 14.4M | unsigned char TargetFlags = 0) { |
792 | 14.4M | MachineOperand Op(MachineOperand::MO_MachineBasicBlock); |
793 | 14.4M | Op.setMBB(MBB); |
794 | 14.4M | Op.setTargetFlags(TargetFlags); |
795 | 14.4M | return Op; |
796 | 14.4M | } |
797 | 1.07M | static MachineOperand CreateFI(int Idx) { |
798 | 1.07M | MachineOperand Op(MachineOperand::MO_FrameIndex); |
799 | 1.07M | Op.setIndex(Idx); |
800 | 1.07M | return Op; |
801 | 1.07M | } |
802 | | static MachineOperand CreateCPI(unsigned Idx, int Offset, |
803 | 114k | unsigned char TargetFlags = 0) { |
804 | 114k | MachineOperand Op(MachineOperand::MO_ConstantPoolIndex); |
805 | 114k | Op.setIndex(Idx); |
806 | 114k | Op.setOffset(Offset); |
807 | 114k | Op.setTargetFlags(TargetFlags); |
808 | 114k | return Op; |
809 | 114k | } |
810 | | static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, |
811 | 3 | unsigned char TargetFlags = 0) { |
812 | 3 | MachineOperand Op(MachineOperand::MO_TargetIndex); |
813 | 3 | Op.setIndex(Idx); |
814 | 3 | Op.setOffset(Offset); |
815 | 3 | Op.setTargetFlags(TargetFlags); |
816 | 3 | return Op; |
817 | 3 | } |
818 | 13.2k | static MachineOperand CreateJTI(unsigned Idx, unsigned char TargetFlags = 0) { |
819 | 13.2k | MachineOperand Op(MachineOperand::MO_JumpTableIndex); |
820 | 13.2k | Op.setIndex(Idx); |
821 | 13.2k | Op.setTargetFlags(TargetFlags); |
822 | 13.2k | return Op; |
823 | 13.2k | } |
824 | | static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, |
825 | 3.30M | unsigned char TargetFlags = 0) { |
826 | 3.30M | MachineOperand Op(MachineOperand::MO_GlobalAddress); |
827 | 3.30M | Op.Contents.OffsetedInfo.Val.GV = GV; |
828 | 3.30M | Op.setOffset(Offset); |
829 | 3.30M | Op.setTargetFlags(TargetFlags); |
830 | 3.30M | return Op; |
831 | 3.30M | } |
832 | | static MachineOperand CreateES(const char *SymName, |
833 | 85.7k | unsigned char TargetFlags = 0) { |
834 | 85.7k | MachineOperand Op(MachineOperand::MO_ExternalSymbol); |
835 | 85.7k | Op.Contents.OffsetedInfo.Val.SymbolName = SymName; |
836 | 85.7k | Op.setOffset(0); // Offset is always 0. |
837 | 85.7k | Op.setTargetFlags(TargetFlags); |
838 | 85.7k | return Op; |
839 | 85.7k | } |
840 | | static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, |
841 | 189 | unsigned char TargetFlags = 0) { |
842 | 189 | MachineOperand Op(MachineOperand::MO_BlockAddress); |
843 | 189 | Op.Contents.OffsetedInfo.Val.BA = BA; |
844 | 189 | Op.setOffset(Offset); |
845 | 189 | Op.setTargetFlags(TargetFlags); |
846 | 189 | return Op; |
847 | 189 | } |
848 | | /// CreateRegMask - Creates a register mask operand referencing Mask. The |
849 | | /// operand does not take ownership of the memory referenced by Mask, it |
850 | | /// must remain valid for the lifetime of the operand. |
851 | | /// |
852 | | /// A RegMask operand represents a set of non-clobbered physical registers |
853 | | /// on an instruction that clobbers many registers, typically a call. The |
854 | | /// bit mask has a bit set for each physreg that is preserved by this |
855 | | /// instruction, as described in the documentation for |
856 | | /// TargetRegisterInfo::getCallPreservedMask(). |
857 | | /// |
858 | | /// Any physreg with a 0 bit in the mask is clobbered by the instruction. |
859 | | /// |
860 | 1.71M | static MachineOperand CreateRegMask(const uint32_t *Mask) { |
861 | 1.71M | assert(Mask && "Missing register mask"); |
862 | 1.71M | MachineOperand Op(MachineOperand::MO_RegisterMask); |
863 | 1.71M | Op.Contents.RegMask = Mask; |
864 | 1.71M | return Op; |
865 | 1.71M | } |
866 | 183 | static MachineOperand CreateRegLiveOut(const uint32_t *Mask) { |
867 | 183 | assert(Mask && "Missing live-out register mask"); |
868 | 183 | MachineOperand Op(MachineOperand::MO_RegisterLiveOut); |
869 | 183 | Op.Contents.RegMask = Mask; |
870 | 183 | return Op; |
871 | 183 | } |
872 | 31.1k | static MachineOperand CreateMetadata(const MDNode *Meta) { |
873 | 31.1k | MachineOperand Op(MachineOperand::MO_Metadata); |
874 | 31.1k | Op.Contents.MD = Meta; |
875 | 31.1k | return Op; |
876 | 31.1k | } |
877 | | |
878 | | static MachineOperand CreateMCSymbol(MCSymbol *Sym, |
879 | 80.3k | unsigned char TargetFlags = 0) { |
880 | 80.3k | MachineOperand Op(MachineOperand::MO_MCSymbol); |
881 | 80.3k | Op.Contents.Sym = Sym; |
882 | 80.3k | Op.setOffset(0); |
883 | 80.3k | Op.setTargetFlags(TargetFlags); |
884 | 80.3k | return Op; |
885 | 80.3k | } |
886 | | |
887 | 501k | static MachineOperand CreateCFIIndex(unsigned CFIIndex) { |
888 | 501k | MachineOperand Op(MachineOperand::MO_CFIIndex); |
889 | 501k | Op.Contents.CFIIndex = CFIIndex; |
890 | 501k | return Op; |
891 | 501k | } |
892 | | |
893 | 102k | static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) { |
894 | 102k | MachineOperand Op(MachineOperand::MO_IntrinsicID); |
895 | 102k | Op.Contents.IntrinsicID = ID; |
896 | 102k | return Op; |
897 | 102k | } |
898 | | |
899 | 1.09M | static MachineOperand CreatePredicate(unsigned Pred) { |
900 | 1.09M | MachineOperand Op(MachineOperand::MO_Predicate); |
901 | 1.09M | Op.Contents.Pred = Pred; |
902 | 1.09M | return Op; |
903 | 1.09M | } |
904 | | |
905 | | friend class MachineInstr; |
906 | | friend class MachineRegisterInfo; |
907 | | |
908 | | private: |
909 | | // If this operand is currently a register operand, and if this is in a |
910 | | // function, deregister the operand from the register's use/def list. |
911 | | void removeRegFromUses(); |
912 | | |
913 | | /// Artificial kinds for DenseMap usage. |
914 | | enum : unsigned char { |
915 | | MO_Empty = MO_Last + 1, |
916 | | MO_Tombstone, |
917 | | }; |
918 | | |
919 | | friend struct DenseMapInfo<MachineOperand>; |
920 | | |
921 | | //===--------------------------------------------------------------------===// |
922 | | // Methods for handling register use/def lists. |
923 | | //===--------------------------------------------------------------------===// |
924 | | |
925 | | /// isOnRegUseList - Return true if this operand is on a register use/def |
926 | | /// list or false if not. This can only be called for register operands |
927 | | /// that are part of a machine instruction. |
928 | 158k | bool isOnRegUseList() const { |
929 | 158k | assert(isReg() && "Can only add reg operand to use lists"); |
930 | 158k | return Contents.Reg.Prev != nullptr; |
931 | 158k | } |
932 | | }; |
933 | | |
934 | | template <> struct DenseMapInfo<MachineOperand> { |
935 | 18.8k | static MachineOperand getEmptyKey() { |
936 | 18.8k | return MachineOperand(static_cast<MachineOperand::MachineOperandType>( |
937 | 18.8k | MachineOperand::MO_Empty)); |
938 | 18.8k | } |
939 | 9.49k | static MachineOperand getTombstoneKey() { |
940 | 9.49k | return MachineOperand(static_cast<MachineOperand::MachineOperandType>( |
941 | 9.49k | MachineOperand::MO_Tombstone)); |
942 | 9.49k | } |
943 | 4.87k | static unsigned getHashValue(const MachineOperand &MO) { |
944 | 4.87k | return hash_value(MO); |
945 | 4.87k | } |
946 | 314k | static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) { |
947 | 314k | if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>( |
948 | 314k | MachineOperand::MO_Empty) || |
949 | 314k | LHS.getType() == static_cast<MachineOperand::MachineOperandType>( |
950 | 14.3k | MachineOperand::MO_Tombstone)) |
951 | 300k | return LHS.getType() == RHS.getType(); |
952 | 14.3k | return LHS.isIdenticalTo(RHS); |
953 | 14.3k | } |
954 | | }; |
955 | | |
956 | 0 | inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) { |
957 | 0 | MO.print(OS); |
958 | 0 | return OS; |
959 | 0 | } |
960 | | |
961 | | // See friend declaration above. This additional declaration is required in |
962 | | // order to compile LLVM with IBM xlC compiler. |
963 | | hash_code hash_value(const MachineOperand &MO); |
964 | | } // namespace llvm |
965 | | |
966 | | #endif |